1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 ************************************************************/
29
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 const u16 phy_rate_table[] = {
34 /*@20M*/
35 1, 2, 5, 11,
36 6, 9, 12, 18, 24, 36, 48, 54,
37 6, 13, 19, 26, 39, 52, 58, 65, /*@MCS0~7*/
38 13, 26, 39, 52, 78, 104, 117, 130, /*@MCS8~15*/
39 19, 39, 58, 78, 117, 156, 175, 195, /*@MCS16~23*/
40 26, 52, 78, 104, 156, 208, 234, 260, /*@MCS24~31*/
41 6, 13, 19, 26, 39, 52, 58, 65, 78, 90, /*@1ss MCS0~9*/
42 13, 26, 39, 52, 78, 104, 117, 130, 156, 180, /*@2ss MCS0~9*/
43 19, 39, 58, 78, 117, 156, 175, 195, 234, 260, /*@3ss MCS0~9*/
44 26, 52, 78, 104, 156, 208, 234, 260, 312, 360 /*@4ss MCS0~9*/
45 };
46
phydm_traffic_load_decision(void * dm_void)47 void phydm_traffic_load_decision(void *dm_void)
48 {
49 struct dm_struct *dm = (struct dm_struct *)dm_void;
50 u8 shift = 0;
51
52 /*@---TP & Trafic-load calculation---*/
53
54 if (dm->last_tx_ok_cnt > *dm->num_tx_bytes_unicast)
55 dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
56
57 if (dm->last_rx_ok_cnt > *dm->num_rx_bytes_unicast)
58 dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
59
60 dm->cur_tx_ok_cnt = *dm->num_tx_bytes_unicast - dm->last_tx_ok_cnt;
61 dm->cur_rx_ok_cnt = *dm->num_rx_bytes_unicast - dm->last_rx_ok_cnt;
62 dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
63 dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
64
65 /*@AP: <<3(8bit), >>20(10^6,M), >>0(1sec)*/
66 shift = 17 + (PHYDM_WATCH_DOG_PERIOD - 1);
67 /*@WIN&CE: <<3(8bit), >>20(10^6,M), >>1(2sec)*/
68
69 dm->tx_tp = (dm->tx_tp >> 1) + (u32)((dm->cur_tx_ok_cnt >> shift) >> 1);
70 dm->rx_tp = (dm->rx_tp >> 1) + (u32)((dm->cur_rx_ok_cnt >> shift) >> 1);
71
72 dm->total_tp = dm->tx_tp + dm->rx_tp;
73
74 /*@[Calculate TX/RX state]*/
75 if (dm->tx_tp > (dm->rx_tp << 1))
76 dm->txrx_state_all = TX_STATE;
77 else if (dm->rx_tp > (dm->tx_tp << 1))
78 dm->txrx_state_all = RX_STATE;
79 else
80 dm->txrx_state_all = BI_DIRECTION_STATE;
81
82 /*@[Traffic load decision]*/
83 dm->pre_traffic_load = dm->traffic_load;
84
85 if (dm->cur_tx_ok_cnt > 1875000 || dm->cur_rx_ok_cnt > 1875000) {
86 /* @( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/
87 dm->traffic_load = TRAFFIC_HIGH;
88 } else if (dm->cur_tx_ok_cnt > 500000 || dm->cur_rx_ok_cnt > 500000) {
89 /*@( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/
90 dm->traffic_load = TRAFFIC_MID;
91 } else if (dm->cur_tx_ok_cnt > 100000 || dm->cur_rx_ok_cnt > 100000) {
92 /*@( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/
93 dm->traffic_load = TRAFFIC_LOW;
94 } else if (dm->cur_tx_ok_cnt > 25000 || dm->cur_rx_ok_cnt > 25000) {
95 /*@( 0.025M * 8bit ) / 2sec = 0.1M bits /sec )*/
96 dm->traffic_load = TRAFFIC_ULTRA_LOW;
97 } else {
98 dm->traffic_load = TRAFFIC_NO_TP;
99 }
100
101 /*@[Calculate consecutive idlel time]*/
102 if (dm->traffic_load == 0)
103 dm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD;
104 else
105 dm->consecutive_idlel_time = 0;
106
107 #if 0
108 PHYDM_DBG(dm, DBG_COMMON_FLOW,
109 "cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n",
110 dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt, dm->last_tx_ok_cnt,
111 dm->last_rx_ok_cnt);
112
113 PHYDM_DBG(dm, DBG_COMMON_FLOW, "tx_tp = %d, rx_tp = %d\n", dm->tx_tp,
114 dm->rx_tp);
115 #endif
116 }
117
phydm_cck_new_agc_chk(struct dm_struct * dm)118 void phydm_cck_new_agc_chk(struct dm_struct *dm)
119 {
120 u32 new_agc_addr = 0x0;
121
122 dm->cck_new_agc = false;
123 #if (RTL8723D_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT ||\
124 RTL8197F_SUPPORT || RTL8710B_SUPPORT || RTL8192F_SUPPORT ||\
125 RTL8195B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
126 RTL8721D_SUPPORT || RTL8710C_SUPPORT)
127 if (dm->support_ic_type & (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8821C |
128 ODM_RTL8197F | ODM_RTL8710B | ODM_RTL8192F | ODM_RTL8195B |
129 ODM_RTL8721D | ODM_RTL8710C)) {
130 new_agc_addr = R_0xa9c;
131 } else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C |
132 ODM_RTL8814B | ODM_RTL8197G)) {
133 new_agc_addr = R_0x1a9c;
134 }
135
136 /*@1: new agc 0: old agc*/
137 dm->cck_new_agc = (boolean)odm_get_bb_reg(dm, new_agc_addr, BIT(17));
138 #endif
139 }
140
141 /*select 3 or 4 bit LNA */
phydm_cck_lna_bit_num_chk(struct dm_struct * dm)142 void phydm_cck_lna_bit_num_chk(struct dm_struct *dm)
143 {
144 boolean report_type = 0;
145 #if (RTL8192E_SUPPORT)
146 u32 value_824, value_82c;
147 #endif
148
149 #if (RTL8192E_SUPPORT)
150 if (dm->support_ic_type & (ODM_RTL8192E)) {
151 /* @0x824[9] = 0x82C[9] = 0xA80[7] those registers setting
152 * should be equal or CCK RSSI report may be incorrect
153 */
154 value_824 = odm_get_bb_reg(dm, R_0x824, BIT(9));
155 value_82c = odm_get_bb_reg(dm, R_0x82c, BIT(9));
156
157 if (value_824 != value_82c)
158 odm_set_bb_reg(dm, R_0x82c, BIT(9), value_824);
159 odm_set_bb_reg(dm, R_0xa80, BIT(7), value_824);
160 report_type = (boolean)value_824;
161 }
162 #endif
163
164 #if (RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8710B_SUPPORT)
165 if (dm->support_ic_type &
166 (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
167 report_type = (boolean)odm_get_bb_reg(dm, R_0x950, BIT(11));
168
169 if (report_type != 1)
170 pr_debug("[Warning] CCK should be 4bit LNA\n");
171 }
172 #endif
173
174 #if (RTL8821C_SUPPORT)
175 if (dm->support_ic_type & ODM_RTL8821C) {
176 if (dm->default_rf_set_8821c == SWITCH_TO_BTG)
177 report_type = 1;
178 }
179 #endif
180
181 dm->cck_agc_report_type = report_type;
182
183 PHYDM_DBG(dm, ODM_COMP_INIT, "cck_agc_report_type=((%d))\n",
184 dm->cck_agc_report_type);
185 }
186
phydm_init_cck_setting(struct dm_struct * dm)187 void phydm_init_cck_setting(struct dm_struct *dm)
188 {
189 u32 reg_tmp = 0;
190 u32 mask_tmp = 0;
191
192 phydm_cck_new_agc_chk(dm);
193
194 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
195 return;
196
197 reg_tmp = ODM_REG(CCK_RPT_FORMAT, dm);
198 mask_tmp = ODM_BIT(CCK_RPT_FORMAT, dm);
199 dm->is_cck_high_power = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
200
201 PHYDM_DBG(dm, ODM_COMP_INIT, "ext_lna_gain=((%d))\n", dm->ext_lna_gain);
202
203 phydm_config_cck_rx_antenna_init(dm);
204
205 if (dm->support_ic_type & ODM_RTL8192F)
206 phydm_config_cck_rx_path(dm, BB_PATH_AB);
207 else if (dm->valid_path_set == BB_PATH_A)
208 phydm_config_cck_rx_path(dm, BB_PATH_A);
209 else if (dm->valid_path_set == BB_PATH_B)
210 phydm_config_cck_rx_path(dm, BB_PATH_B);
211
212 phydm_cck_lna_bit_num_chk(dm);
213 phydm_get_cck_rssi_table_from_reg(dm);
214 }
215
216 #ifdef CONFIG_RFE_BY_HW_INFO
phydm_init_hw_info_by_rfe(struct dm_struct * dm)217 void phydm_init_hw_info_by_rfe(struct dm_struct *dm)
218 {
219 #if (RTL8821C_SUPPORT)
220 if (dm->support_ic_type & ODM_RTL8821C)
221 phydm_init_hw_info_by_rfe_type_8821c(dm);
222 #endif
223 #if (RTL8197F_SUPPORT)
224 if (dm->support_ic_type & ODM_RTL8197F)
225 phydm_init_hw_info_by_rfe_type_8197f(dm);
226 #endif
227 #if (RTL8197G_SUPPORT)
228 if (dm->support_ic_type & ODM_RTL8197G)
229 phydm_init_hw_info_by_rfe_type_8197g(dm);
230 #endif
231 }
232 #endif
233
phydm_common_info_self_init(struct dm_struct * dm)234 void phydm_common_info_self_init(struct dm_struct *dm)
235 {
236 u32 reg_tmp = 0;
237 u32 mask_tmp = 0;
238
239 dm->run_in_drv_fw = RUN_IN_DRIVER;
240
241 /*@BB IP Generation*/
242 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
243 dm->ic_ip_series = PHYDM_IC_JGR3;
244 else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
245 dm->ic_ip_series = PHYDM_IC_AC;
246 else if (dm->support_ic_type & ODM_IC_11N_SERIES)
247 dm->ic_ip_series = PHYDM_IC_N;
248
249 /*@BB phy-status Generation*/
250 if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC)
251 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_3;
252 else if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC)
253 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_2;
254 else
255 dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_1;
256
257 phydm_init_cck_setting(dm);
258
259 reg_tmp = ODM_REG(BB_RX_PATH, dm);
260 mask_tmp = ODM_BIT(BB_RX_PATH, dm);
261 dm->rf_path_rx_enable = (u8)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
262 #if (DM_ODM_SUPPORT_TYPE != ODM_CE)
263 dm->is_net_closed = &dm->BOOLEAN_temp;
264
265 phydm_init_debug_setting(dm);
266 #endif
267 phydm_init_soft_ml_setting(dm);
268
269 dm->phydm_sys_up_time = 0;
270
271 if (dm->support_ic_type & ODM_IC_1SS)
272 dm->num_rf_path = 1;
273 else if (dm->support_ic_type & ODM_IC_2SS)
274 dm->num_rf_path = 2;
275 #if 0
276 /* @RTK do not has IC which is equipped with 3 RF paths,
277 * so ODM_IC_3SS is an enpty macro and result in coverity check errors
278 */
279 else if (dm->support_ic_type & ODM_IC_3SS)
280 dm->num_rf_path = 3;
281 #endif
282 else if (dm->support_ic_type & ODM_IC_4SS)
283 dm->num_rf_path = 4;
284 else
285 dm->num_rf_path = 1;
286
287 phydm_trx_antenna_setting_init(dm, dm->num_rf_path);
288
289 dm->tx_rate = 0xFF;
290 dm->rssi_min_by_path = 0xFF;
291
292 dm->number_linked_client = 0;
293 dm->pre_number_linked_client = 0;
294 dm->number_active_client = 0;
295 dm->pre_number_active_client = 0;
296
297 dm->last_tx_ok_cnt = 0;
298 dm->last_rx_ok_cnt = 0;
299 dm->tx_tp = 0;
300 dm->rx_tp = 0;
301 dm->total_tp = 0;
302 dm->traffic_load = TRAFFIC_LOW;
303
304 dm->nbi_set_result = 0;
305 dm->is_init_hw_info_by_rfe = false;
306 dm->pre_dbg_priority = DBGPORT_RELEASE;
307 dm->tp_active_th = 5;
308 dm->disable_phydm_watchdog = 0;
309
310 dm->u8_dummy = 0xf;
311 dm->u16_dummy = 0xffff;
312 dm->u32_dummy = 0xffffffff;
313 #if (RTL8814B_SUPPORT)
314 /*@------------For spur detection Default Mode------------@*/
315 dm->dsde_sel = DET_CSI;
316 dm->csi_wgt = 4;
317 /*@-------------------------------------------------------@*/
318 #endif
319 dm->pre_is_linked = false;
320 dm->is_linked = false;
321 /*dym bw thre and it can config by registry*/
322 if (dm->en_auto_bw_th == 0)
323 dm->en_auto_bw_th = 20;
324
325 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
326 if (!(dm->is_fcs_mode_enable)) {
327 dm->is_fcs_mode_enable = &dm->boolean_dummy;
328 pr_debug("[Warning] is_fcs_mode_enable=NULL\n");
329 }
330 #endif
331 /*init IOT table*/
332 odm_memory_set(dm, &dm->iot_table, 0, sizeof(struct phydm_iot_center));
333 }
334
phydm_iot_patch_id_update(void * dm_void,u32 iot_idx,boolean en)335 void phydm_iot_patch_id_update(void *dm_void, u32 iot_idx, boolean en)
336 {
337 struct dm_struct *dm = (struct dm_struct *)dm_void;
338 struct phydm_iot_center *iot_table = &dm->iot_table;
339
340 PHYDM_DBG(dm, DBG_CMN, "[IOT] 0x%x = %d\n", iot_idx, en);
341 switch (iot_idx) {
342 case 0x100f0401:
343 iot_table->patch_id_100f0401 = en;
344 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_100f0401 = %d\n",
345 iot_table->patch_id_100f0401);
346 break;
347 case 0x10120200:
348 iot_table->patch_id_10120200 = en;
349 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_10120200 = %d\n",
350 iot_table->patch_id_10120200);
351 break;
352 case 0x40010700:
353 iot_table->patch_id_40010700 = en;
354 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_40010700 = %d\n",
355 iot_table->patch_id_40010700);
356 break;
357 case 0x021f0800:
358 iot_table->patch_id_021f0800 = en;
359 PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_021f0800 = %d\n",
360 iot_table->patch_id_021f0800);
361 break;
362 default:
363 pr_debug("[%s] warning!\n", __func__);
364 break;
365 }
366 }
367
phydm_cmn_sta_info_update(void * dm_void,u8 macid)368 void phydm_cmn_sta_info_update(void *dm_void, u8 macid)
369 {
370 struct dm_struct *dm = (struct dm_struct *)dm_void;
371 struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
372 struct ra_sta_info *ra = NULL;
373
374 if (is_sta_active(sta)) {
375 ra = &sta->ra_info;
376 } else {
377 PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid sta_info\n",
378 __func__);
379 return;
380 }
381
382 PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
383 PHYDM_DBG(dm, DBG_RA_MASK, "MACID=%d\n", sta->mac_id);
384
385 /*@[Calculate TX/RX state]*/
386 if (sta->tx_moving_average_tp > (sta->rx_moving_average_tp << 1))
387 ra->txrx_state = TX_STATE;
388 else if (sta->rx_moving_average_tp > (sta->tx_moving_average_tp << 1))
389 ra->txrx_state = RX_STATE;
390 else
391 ra->txrx_state = BI_DIRECTION_STATE;
392
393 ra->is_noisy = dm->noisy_decision;
394 }
395
phydm_common_info_self_update(struct dm_struct * dm)396 void phydm_common_info_self_update(struct dm_struct *dm)
397 {
398 u8 sta_cnt = 0, num_active_client = 0;
399 u32 i, one_entry_macid = 0;
400 u32 ma_rx_tp = 0;
401 u32 tp_diff = 0;
402 struct cmn_sta_info *sta;
403 #ifdef RA_MASK_BY_RX_UTILITY
404 u8 rx_ss;
405 #endif
406 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
407 PADAPTER adapter = (PADAPTER)dm->adapter;
408 PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
409
410 sta = dm->phydm_sta_info[0];
411
412 /* STA mode is linked to AP */
413 if (is_sta_active(sta) && !ACTING_AS_AP(adapter))
414 dm->bsta_state = true;
415 else
416 dm->bsta_state = false;
417 #endif
418
419 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
420 sta = dm->phydm_sta_info[i];
421 if (is_sta_active(sta)) {
422 sta_cnt++;
423
424 if (sta_cnt == 1)
425 one_entry_macid = i;
426
427 phydm_cmn_sta_info_update(dm, (u8)i);
428 #ifdef PHYDM_BEAMFORMING_SUPPORT
429 /*@phydm_get_txbf_device_num(dm, (u8)i);*/
430 #endif
431
432 ma_rx_tp = sta->rx_moving_average_tp +
433 sta->tx_moving_average_tp;
434
435 PHYDM_DBG(dm, DBG_COMMON_FLOW,
436 "TP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp);
437
438 if (ma_rx_tp > ACTIVE_TP_THRESHOLD)
439 num_active_client++;
440 }
441 }
442
443 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
444 dm->is_linked = (sta_cnt != 0) ? true : false;
445 #endif
446
447 if (sta_cnt == 1) {
448 dm->is_one_entry_only = true;
449 dm->one_entry_macid = one_entry_macid;
450 dm->one_entry_tp = ma_rx_tp;
451
452 dm->tp_active_occur = 0;
453
454 PHYDM_DBG(dm, DBG_COMMON_FLOW,
455 "one_entry_tp=((%d)), pre_one_entry_tp=((%d))\n",
456 dm->one_entry_tp, dm->pre_one_entry_tp);
457
458 if (dm->one_entry_tp > dm->pre_one_entry_tp &&
459 dm->pre_one_entry_tp <= 2) {
460 tp_diff = dm->one_entry_tp - dm->pre_one_entry_tp;
461
462 if (tp_diff > dm->tp_active_th)
463 dm->tp_active_occur = 1;
464 }
465 dm->pre_one_entry_tp = dm->one_entry_tp;
466 } else {
467 dm->is_one_entry_only = false;
468 }
469
470 dm->pre_number_linked_client = dm->number_linked_client;
471 dm->pre_number_active_client = dm->number_active_client;
472
473 dm->number_linked_client = sta_cnt;
474 dm->number_active_client = num_active_client;
475
476 /*Traffic load information update*/
477 phydm_traffic_load_decision(dm);
478
479 dm->phydm_sys_up_time += PHYDM_WATCH_DOG_PERIOD;
480
481 dm->is_dfs_band = phydm_is_dfs_band(dm);
482 dm->phy_dbg_info.show_phy_sts_cnt = 0;
483
484 /*[Link Status Check]*/
485 dm->first_connect = dm->is_linked && !dm->pre_is_linked;
486 dm->first_disconnect = !dm->is_linked && dm->pre_is_linked;
487 dm->pre_is_linked = dm->is_linked;
488
489 #ifdef RA_MASK_BY_RX_UTILITY
490 dm->one_entry_avg_phy_rate = 500;
491 dm->one_entry_rx_utility = 500;
492 if (dm->is_one_entry_only) {
493 sta = dm->phydm_sta_info[one_entry_macid];
494 if (is_sta_active(sta)) {
495 dm->one_entry_avg_phy_rate = phydm_rx_avg_phy_rate(dm);
496 rx_ss = phydm_get_rx_stream_num(dm, sta->mimo_type);
497 dm->one_entry_rx_utility = phydm_rx_utility(dm, dm->one_entry_avg_phy_rate,
498 rx_ss, sta->bw_mode);
499 }
500 }
501
502 PHYDM_DBG(dm, DBG_RA_MASK, "[Uty]Avg_rx_rate = %d, rx_utility=( %d / 1000 )\n",
503 dm->one_entry_avg_phy_rate, dm->one_entry_rx_utility);
504 #endif
505 }
506
phydm_common_info_self_reset(struct dm_struct * dm)507 void phydm_common_info_self_reset(struct dm_struct *dm)
508 {
509 struct odm_phy_dbg_info *dbg_t = &dm->phy_dbg_info;
510
511 dbg_t->beacon_cnt_in_period = dbg_t->num_qry_beacon_pkt;
512 dbg_t->num_qry_beacon_pkt = 0;
513
514 dm->rxsc_l = 0xff;
515 dm->rxsc_20 = 0xff;
516 dm->rxsc_40 = 0xff;
517 dm->rxsc_80 = 0xff;
518 #ifdef RA_MASK_BY_RX_UTILITY
519 phydm_reset_rx_rate_distribution(dm);
520 #endif
521 }
522
523 void *
phydm_get_structure(struct dm_struct * dm,u8 structure_type)524 phydm_get_structure(struct dm_struct *dm, u8 structure_type)
525
526 {
527 void *structure = NULL;
528
529 switch (structure_type) {
530 case PHYDM_FALSEALMCNT:
531 structure = &dm->false_alm_cnt;
532 break;
533
534 case PHYDM_CFOTRACK:
535 structure = &dm->dm_cfo_track;
536 break;
537
538 case PHYDM_ADAPTIVITY:
539 structure = &dm->adaptivity;
540 break;
541 #ifdef CONFIG_PHYDM_DFS_MASTER
542 case PHYDM_DFS:
543 structure = &dm->dfs;
544 break;
545 #endif
546 default:
547 break;
548 }
549
550 return structure;
551 }
552
phydm_phy_info_update(struct dm_struct * dm)553 void phydm_phy_info_update(struct dm_struct *dm)
554 {
555 #if (RTL8822B_SUPPORT)
556 if (dm->support_ic_type == ODM_RTL8822B)
557 dm->phy_dbg_info.condi_num = phydm_get_condi_num_8822b(dm);
558 #endif
559 }
560
phydm_hw_setting(struct dm_struct * dm)561 void phydm_hw_setting(struct dm_struct *dm)
562 {
563 #if (RTL8188F_SUPPORT)
564 if (dm->support_ic_type & ODM_RTL8188F)
565 odm_hw_setting_8188F(dm);
566 #endif
567 #if (RTL8821A_SUPPORT)
568 if (dm->support_ic_type & ODM_RTL8821)
569 odm_hw_setting_8821a(dm);
570 #endif
571
572 #if (RTL8814A_SUPPORT)
573 if (dm->support_ic_type & ODM_RTL8814A)
574 phydm_hwsetting_8814a(dm);
575 #endif
576
577 #if (RTL8822B_SUPPORT)
578 if (dm->support_ic_type & ODM_RTL8822B)
579 phydm_hwsetting_8822b(dm);
580 #endif
581
582 #if (RTL8812A_SUPPORT)
583 if (dm->support_ic_type & ODM_RTL8812)
584 phydm_hwsetting_8812a(dm);
585 #endif
586
587 #if (RTL8197F_SUPPORT)
588 if (dm->support_ic_type & ODM_RTL8197F)
589 phydm_hwsetting_8197f(dm);
590 #endif
591
592 #if (RTL8192F_SUPPORT)
593 if (dm->support_ic_type & ODM_RTL8192F)
594 phydm_hwsetting_8192f(dm);
595 #endif
596
597 #if (RTL8822C_SUPPORT)
598 if (dm->support_ic_type & ODM_RTL8822C)
599 phydm_hwsetting_8822c(dm);
600 #endif
601
602 #if (RTL8197G_SUPPORT)
603 if (dm->support_ic_type & ODM_RTL8197G)
604 phydm_hwsetting_8197g(dm);
605 #endif
606
607 #if (RTL8821C_SUPPORT)
608 if (dm->support_ic_type & ODM_RTL8821C)
609 phydm_hwsetting_8821c(dm);
610 #endif
611
612 #if (RTL8812F_SUPPORT)
613 if (dm->support_ic_type & ODM_RTL8812F)
614 phydm_hwsetting_8812f(dm);
615 #endif
616
617 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
618 phydm_cck_rx_pathdiv_watchdog(dm);
619 #endif
620 }
621
622 __odm_func__
phydm_chk_bb_rf_pkg_set_valid(struct dm_struct * dm)623 boolean phydm_chk_bb_rf_pkg_set_valid(struct dm_struct *dm)
624 {
625 boolean valid = true;
626
627 if (dm->support_ic_type == ODM_RTL8822C) {
628 #if (RTL8822C_SUPPORT)
629 valid = phydm_chk_pkg_set_valid_8822c(dm,
630 RELEASE_VERSION_8822C,
631 RF_RELEASE_VERSION_8822C);
632 #else
633 valid = true; /*@Just for preventing compile warnings*/
634 #endif
635 #if (RTL8812F_SUPPORT)
636 } else if (dm->support_ic_type == ODM_RTL8812F) {
637 valid = phydm_chk_pkg_set_valid_8812f(dm,
638 RELEASE_VERSION_8812F,
639 RF_RELEASE_VERSION_8812F);
640 #endif
641 #if (RTL8197G_SUPPORT)
642 } else if (dm->support_ic_type == ODM_RTL8197G) {
643 valid = phydm_chk_pkg_set_valid_8197g(dm,
644 RELEASE_VERSION_8197G,
645 RF_RELEASE_VERSION_8197G);
646 #endif
647 #if (RTL8812F_SUPPORT)
648 } else if (dm->support_ic_type == ODM_RTL8812F) {
649 valid = phydm_chk_pkg_set_valid_8812f(dm,
650 RELEASE_VERSION_8812F,
651 RF_RELEASE_VERSION_8812F);
652 #endif
653 #if (RTL8198F_SUPPORT)
654 } else if (dm->support_ic_type == ODM_RTL8198F) {
655 valid = phydm_chk_pkg_set_valid_8198f(dm,
656 RELEASE_VERSION_8198F,
657 RF_RELEASE_VERSION_8198F);
658 #endif
659 #if (RTL8814B_SUPPORT)
660 } else if (dm->support_ic_type == ODM_RTL8814B) {
661 valid = phydm_chk_pkg_set_valid_8814b(dm,
662 RELEASE_VERSION_8814B,
663 RF_RELEASE_VERSION_8814B);
664 #endif
665 }
666
667 return valid;
668 }
669
670 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
phydm_supportability_init_win(void * dm_void)671 u64 phydm_supportability_init_win(
672 void *dm_void)
673 {
674 struct dm_struct *dm = (struct dm_struct *)dm_void;
675 u64 support_ability = 0;
676
677 switch (dm->support_ic_type) {
678 /*@---------------N Series--------------------*/
679 #if (RTL8188E_SUPPORT)
680 case ODM_RTL8188E:
681 support_ability |=
682 ODM_BB_DIG |
683 ODM_BB_RA_MASK |
684 /*ODM_BB_DYNAMIC_TXPWR |*/
685 ODM_BB_FA_CNT |
686 ODM_BB_RSSI_MONITOR |
687 ODM_BB_CCK_PD |
688 /*ODM_BB_PWR_TRAIN |*/
689 ODM_BB_RATE_ADAPTIVE |
690 ODM_BB_ADAPTIVITY |
691 ODM_BB_CFO_TRACKING |
692 ODM_BB_ENV_MONITOR |
693 ODM_BB_PRIMARY_CCA;
694 break;
695 #endif
696
697 #if (RTL8192E_SUPPORT)
698 case ODM_RTL8192E:
699 support_ability |=
700 ODM_BB_DIG |
701 ODM_BB_RA_MASK |
702 /*ODM_BB_DYNAMIC_TXPWR |*/
703 ODM_BB_FA_CNT |
704 ODM_BB_RSSI_MONITOR |
705 ODM_BB_CCK_PD |
706 /*ODM_BB_PWR_TRAIN |*/
707 ODM_BB_RATE_ADAPTIVE |
708 ODM_BB_ADAPTIVITY |
709 ODM_BB_CFO_TRACKING |
710 ODM_BB_ENV_MONITOR |
711 ODM_BB_PRIMARY_CCA;
712 break;
713 #endif
714
715 #if (RTL8723B_SUPPORT)
716 case ODM_RTL8723B:
717 support_ability |=
718 ODM_BB_DIG |
719 ODM_BB_RA_MASK |
720 /*ODM_BB_DYNAMIC_TXPWR |*/
721 ODM_BB_FA_CNT |
722 ODM_BB_RSSI_MONITOR |
723 ODM_BB_CCK_PD |
724 /*ODM_BB_PWR_TRAIN |*/
725 ODM_BB_RATE_ADAPTIVE |
726 ODM_BB_ADAPTIVITY |
727 ODM_BB_CFO_TRACKING |
728 ODM_BB_ENV_MONITOR |
729 ODM_BB_PRIMARY_CCA;
730 break;
731 #endif
732
733 #if (RTL8703B_SUPPORT)
734 case ODM_RTL8703B:
735 support_ability |=
736 ODM_BB_DIG |
737 ODM_BB_RA_MASK |
738 /*ODM_BB_DYNAMIC_TXPWR |*/
739 ODM_BB_FA_CNT |
740 ODM_BB_RSSI_MONITOR |
741 ODM_BB_CCK_PD |
742 /*ODM_BB_PWR_TRAIN |*/
743 ODM_BB_RATE_ADAPTIVE |
744 ODM_BB_ADAPTIVITY |
745 ODM_BB_CFO_TRACKING |
746 ODM_BB_ENV_MONITOR;
747 break;
748 #endif
749
750 #if (RTL8723D_SUPPORT)
751 case ODM_RTL8723D:
752 support_ability |=
753 ODM_BB_DIG |
754 ODM_BB_RA_MASK |
755 /*ODM_BB_DYNAMIC_TXPWR |*/
756 ODM_BB_FA_CNT |
757 ODM_BB_RSSI_MONITOR |
758 ODM_BB_CCK_PD |
759 ODM_BB_PWR_TRAIN |
760 ODM_BB_RATE_ADAPTIVE |
761 ODM_BB_ADAPTIVITY |
762 ODM_BB_CFO_TRACKING |
763 ODM_BB_ENV_MONITOR;
764 break;
765 #endif
766
767 #if (RTL8710B_SUPPORT)
768 case ODM_RTL8710B:
769 support_ability |=
770 ODM_BB_DIG |
771 ODM_BB_RA_MASK |
772 /*ODM_BB_DYNAMIC_TXPWR |*/
773 ODM_BB_FA_CNT |
774 ODM_BB_RSSI_MONITOR |
775 ODM_BB_CCK_PD |
776 ODM_BB_PWR_TRAIN |
777 ODM_BB_RATE_ADAPTIVE |
778 ODM_BB_ADAPTIVITY |
779 ODM_BB_CFO_TRACKING |
780 ODM_BB_ENV_MONITOR;
781 break;
782 #endif
783
784 #if (RTL8188F_SUPPORT)
785 case ODM_RTL8188F:
786 support_ability |=
787 ODM_BB_DIG |
788 ODM_BB_RA_MASK |
789 /*ODM_BB_DYNAMIC_TXPWR |*/
790 ODM_BB_FA_CNT |
791 ODM_BB_RSSI_MONITOR |
792 ODM_BB_CCK_PD |
793 /*ODM_BB_PWR_TRAIN |*/
794 ODM_BB_RATE_ADAPTIVE |
795 ODM_BB_ADAPTIVITY |
796 ODM_BB_CFO_TRACKING |
797 ODM_BB_ENV_MONITOR;
798 break;
799 #endif
800
801 #if (RTL8192F_SUPPORT)
802 case ODM_RTL8192F:
803 support_ability |=
804 ODM_BB_DIG |
805 ODM_BB_RA_MASK |
806 ODM_BB_FA_CNT |
807 ODM_BB_RSSI_MONITOR |
808 ODM_BB_CCK_PD |
809 ODM_BB_PWR_TRAIN |
810 ODM_BB_RATE_ADAPTIVE |
811 /*ODM_BB_PATH_DIV |*/
812 ODM_BB_ADAPTIVITY |
813 ODM_BB_CFO_TRACKING |
814 ODM_BB_ADAPTIVE_SOML |
815 ODM_BB_ENV_MONITOR;
816 /*ODM_BB_LNA_SAT_CHK |*/
817 /*ODM_BB_PRIMARY_CCA*/
818
819 break;
820 #endif
821
822 /*@---------------AC Series-------------------*/
823
824 #if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
825 case ODM_RTL8812:
826 case ODM_RTL8821:
827 support_ability |=
828 ODM_BB_DIG |
829 ODM_BB_RA_MASK |
830 ODM_BB_DYNAMIC_TXPWR |
831 ODM_BB_FA_CNT |
832 ODM_BB_RSSI_MONITOR |
833 ODM_BB_CCK_PD |
834 /*ODM_BB_PWR_TRAIN |*/
835 ODM_BB_RATE_ADAPTIVE |
836 ODM_BB_ADAPTIVITY |
837 ODM_BB_CFO_TRACKING |
838 ODM_BB_ENV_MONITOR;
839 break;
840 #endif
841
842 #if (RTL8814A_SUPPORT)
843 case ODM_RTL8814A:
844 support_ability |=
845 ODM_BB_DIG |
846 ODM_BB_RA_MASK |
847 ODM_BB_DYNAMIC_TXPWR |
848 ODM_BB_FA_CNT |
849 ODM_BB_RSSI_MONITOR |
850 ODM_BB_CCK_PD |
851 /*ODM_BB_PWR_TRAIN |*/
852 ODM_BB_RATE_ADAPTIVE |
853 ODM_BB_ADAPTIVITY |
854 ODM_BB_CFO_TRACKING |
855 ODM_BB_ENV_MONITOR;
856 break;
857 #endif
858
859 #if (RTL8822B_SUPPORT)
860 case ODM_RTL8822B:
861 support_ability |=
862 ODM_BB_DIG |
863 ODM_BB_RA_MASK |
864 /*ODM_BB_DYNAMIC_TXPWR |*/
865 ODM_BB_FA_CNT |
866 ODM_BB_RSSI_MONITOR |
867 ODM_BB_CCK_PD |
868 /*ODM_BB_PWR_TRAIN |*/
869 /*ODM_BB_ADAPTIVE_SOML |*/
870 ODM_BB_RATE_ADAPTIVE |
871 /*ODM_BB_PATH_DIV |*/
872 ODM_BB_ADAPTIVITY |
873 ODM_BB_CFO_TRACKING |
874 ODM_BB_ENV_MONITOR;
875 break;
876 #endif
877
878 #if (RTL8821C_SUPPORT)
879 case ODM_RTL8821C:
880 support_ability |=
881 ODM_BB_DIG |
882 ODM_BB_RA_MASK |
883 /*ODM_BB_DYNAMIC_TXPWR |*/
884 ODM_BB_FA_CNT |
885 ODM_BB_RSSI_MONITOR |
886 ODM_BB_CCK_PD |
887 /*ODM_BB_PWR_TRAIN |*/
888 ODM_BB_RATE_ADAPTIVE |
889 ODM_BB_ADAPTIVITY |
890 ODM_BB_CFO_TRACKING |
891 ODM_BB_ENV_MONITOR;
892 break;
893 #endif
894
895 /*@---------------JGR3 Series-------------------*/
896
897 #if (RTL8822C_SUPPORT)
898 case ODM_RTL8822C:
899 support_ability |=
900 ODM_BB_DIG |
901 ODM_BB_RA_MASK |
902 ODM_BB_DYNAMIC_TXPWR |
903 ODM_BB_FA_CNT |
904 ODM_BB_RSSI_MONITOR |
905 ODM_BB_CCK_PD |
906 ODM_BB_RATE_ADAPTIVE |
907 ODM_BB_PATH_DIV |
908 ODM_BB_ADAPTIVITY |
909 ODM_BB_CFO_TRACKING |
910 ODM_BB_ENV_MONITOR;
911 break;
912 #endif
913
914 #if (RTL8814B_SUPPORT)
915 case ODM_RTL8814B:
916 support_ability |=
917 ODM_BB_DIG |
918 ODM_BB_RA_MASK |
919 /*ODM_BB_DYNAMIC_TXPWR |*/
920 ODM_BB_FA_CNT |
921 ODM_BB_RSSI_MONITOR |
922 ODM_BB_CCK_PD |
923 /*ODM_BB_PWR_TRAIN |*/
924 ODM_BB_RATE_ADAPTIVE |
925 ODM_BB_ADAPTIVITY |
926 ODM_BB_CFO_TRACKING;
927 /*ODM_BB_ENV_MONITOR;*/
928 break;
929 #endif
930
931 default:
932 support_ability |=
933 ODM_BB_DIG |
934 ODM_BB_RA_MASK |
935 /*ODM_BB_DYNAMIC_TXPWR |*/
936 ODM_BB_FA_CNT |
937 ODM_BB_RSSI_MONITOR |
938 ODM_BB_CCK_PD |
939 /*ODM_BB_PWR_TRAIN |*/
940 ODM_BB_RATE_ADAPTIVE |
941 ODM_BB_ADAPTIVITY |
942 ODM_BB_CFO_TRACKING |
943 ODM_BB_ENV_MONITOR;
944
945 pr_debug("[Warning] Supportability Init Warning !!!\n");
946 break;
947 }
948
949 return support_ability;
950 }
951 #endif
952
953 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
phydm_supportability_init_ce(void * dm_void)954 u64 phydm_supportability_init_ce(void *dm_void)
955 {
956 struct dm_struct *dm = (struct dm_struct *)dm_void;
957 u64 support_ability = 0;
958
959 switch (dm->support_ic_type) {
960 /*@---------------N Series--------------------*/
961 #if (RTL8188E_SUPPORT)
962 case ODM_RTL8188E:
963 support_ability |=
964 ODM_BB_DIG |
965 ODM_BB_RA_MASK |
966 /*@ODM_BB_DYNAMIC_TXPWR |*/
967 ODM_BB_FA_CNT |
968 ODM_BB_RSSI_MONITOR |
969 ODM_BB_CCK_PD |
970 /*@ODM_BB_PWR_TRAIN |*/
971 ODM_BB_RATE_ADAPTIVE |
972 ODM_BB_ADAPTIVITY |
973 ODM_BB_CFO_TRACKING |
974 ODM_BB_ENV_MONITOR |
975 ODM_BB_PRIMARY_CCA;
976 break;
977 #endif
978
979 #if (RTL8192E_SUPPORT)
980 case ODM_RTL8192E:
981 support_ability |=
982 ODM_BB_DIG |
983 ODM_BB_RA_MASK |
984 /*@ODM_BB_DYNAMIC_TXPWR |*/
985 ODM_BB_FA_CNT |
986 ODM_BB_RSSI_MONITOR |
987 ODM_BB_CCK_PD |
988 /*@ODM_BB_PWR_TRAIN |*/
989 ODM_BB_RATE_ADAPTIVE |
990 ODM_BB_ADAPTIVITY |
991 ODM_BB_CFO_TRACKING |
992 ODM_BB_ENV_MONITOR |
993 ODM_BB_PRIMARY_CCA;
994 break;
995 #endif
996
997 #if (RTL8723B_SUPPORT)
998 case ODM_RTL8723B:
999 support_ability |=
1000 ODM_BB_DIG |
1001 ODM_BB_RA_MASK |
1002 /*@ODM_BB_DYNAMIC_TXPWR |*/
1003 ODM_BB_FA_CNT |
1004 ODM_BB_RSSI_MONITOR |
1005 ODM_BB_CCK_PD |
1006 /*@ODM_BB_PWR_TRAIN |*/
1007 ODM_BB_RATE_ADAPTIVE |
1008 ODM_BB_ADAPTIVITY |
1009 ODM_BB_CFO_TRACKING |
1010 ODM_BB_ENV_MONITOR |
1011 ODM_BB_PRIMARY_CCA;
1012 break;
1013 #endif
1014
1015 #if (RTL8703B_SUPPORT)
1016 case ODM_RTL8703B:
1017 support_ability |=
1018 ODM_BB_DIG |
1019 ODM_BB_RA_MASK |
1020 /*@ODM_BB_DYNAMIC_TXPWR |*/
1021 ODM_BB_FA_CNT |
1022 ODM_BB_RSSI_MONITOR |
1023 ODM_BB_CCK_PD |
1024 /*@ODM_BB_PWR_TRAIN |*/
1025 ODM_BB_RATE_ADAPTIVE |
1026 ODM_BB_ADAPTIVITY |
1027 ODM_BB_CFO_TRACKING |
1028 ODM_BB_ENV_MONITOR;
1029 break;
1030 #endif
1031
1032 #if (RTL8723D_SUPPORT)
1033 case ODM_RTL8723D:
1034 support_ability |=
1035 ODM_BB_DIG |
1036 ODM_BB_RA_MASK |
1037 /*@ODM_BB_DYNAMIC_TXPWR |*/
1038 ODM_BB_FA_CNT |
1039 ODM_BB_RSSI_MONITOR |
1040 ODM_BB_CCK_PD |
1041 ODM_BB_PWR_TRAIN |
1042 ODM_BB_RATE_ADAPTIVE |
1043 ODM_BB_ADAPTIVITY |
1044 ODM_BB_CFO_TRACKING |
1045 ODM_BB_ENV_MONITOR;
1046 break;
1047 #endif
1048
1049 #if (RTL8710B_SUPPORT)
1050 case ODM_RTL8710B:
1051 support_ability |=
1052 ODM_BB_DIG |
1053 ODM_BB_RA_MASK |
1054 /*@ODM_BB_DYNAMIC_TXPWR |*/
1055 ODM_BB_FA_CNT |
1056 ODM_BB_RSSI_MONITOR |
1057 ODM_BB_CCK_PD |
1058 /*@ODM_BB_PWR_TRAIN |*/
1059 ODM_BB_RATE_ADAPTIVE |
1060 ODM_BB_ADAPTIVITY |
1061 ODM_BB_CFO_TRACKING |
1062 ODM_BB_ENV_MONITOR;
1063 break;
1064 #endif
1065
1066 #if (RTL8188F_SUPPORT)
1067 case ODM_RTL8188F:
1068 support_ability |=
1069 ODM_BB_DIG |
1070 ODM_BB_RA_MASK |
1071 /*@ODM_BB_DYNAMIC_TXPWR |*/
1072 ODM_BB_FA_CNT |
1073 ODM_BB_RSSI_MONITOR |
1074 ODM_BB_CCK_PD |
1075 /*@ODM_BB_PWR_TRAIN |*/
1076 ODM_BB_RATE_ADAPTIVE |
1077 ODM_BB_ADAPTIVITY |
1078 ODM_BB_CFO_TRACKING |
1079 ODM_BB_ENV_MONITOR;
1080 break;
1081 #endif
1082
1083 #if (RTL8192F_SUPPORT)
1084 case ODM_RTL8192F:
1085 support_ability |=
1086 ODM_BB_DIG |
1087 ODM_BB_RA_MASK |
1088 ODM_BB_FA_CNT |
1089 ODM_BB_RSSI_MONITOR |
1090 ODM_BB_CCK_PD |
1091 ODM_BB_PWR_TRAIN |
1092 ODM_BB_RATE_ADAPTIVE |
1093 /*ODM_BB_PATH_DIV |*/
1094 ODM_BB_ADAPTIVITY |
1095 ODM_BB_CFO_TRACKING |
1096 /*@ODM_BB_ADAPTIVE_SOML |*/
1097 ODM_BB_ENV_MONITOR;
1098 /*@ODM_BB_LNA_SAT_CHK |*/
1099 /*@ODM_BB_PRIMARY_CCA*/
1100 break;
1101 #endif
1102 /*@---------------AC Series-------------------*/
1103
1104 #if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
1105 case ODM_RTL8812:
1106 case ODM_RTL8821:
1107 support_ability |=
1108 ODM_BB_DIG |
1109 ODM_BB_RA_MASK |
1110 /*@ODM_BB_DYNAMIC_TXPWR |*/
1111 ODM_BB_FA_CNT |
1112 ODM_BB_RSSI_MONITOR |
1113 ODM_BB_CCK_PD |
1114 /*@ODM_BB_PWR_TRAIN |*/
1115 ODM_BB_RATE_ADAPTIVE |
1116 ODM_BB_ADAPTIVITY |
1117 ODM_BB_CFO_TRACKING |
1118 ODM_BB_ENV_MONITOR;
1119 break;
1120 #endif
1121
1122 #if (RTL8814A_SUPPORT)
1123 case ODM_RTL8814A:
1124 support_ability |=
1125 ODM_BB_DIG |
1126 ODM_BB_RA_MASK |
1127 /*@ODM_BB_DYNAMIC_TXPWR |*/
1128 ODM_BB_FA_CNT |
1129 ODM_BB_RSSI_MONITOR |
1130 ODM_BB_CCK_PD |
1131 /*@ODM_BB_PWR_TRAIN |*/
1132 ODM_BB_RATE_ADAPTIVE |
1133 ODM_BB_ADAPTIVITY |
1134 ODM_BB_CFO_TRACKING |
1135 ODM_BB_ENV_MONITOR;
1136 break;
1137 #endif
1138
1139 #if (RTL8822B_SUPPORT)
1140 case ODM_RTL8822B:
1141 support_ability |=
1142 ODM_BB_DIG |
1143 ODM_BB_RA_MASK |
1144 ODM_BB_DYNAMIC_TXPWR |
1145 ODM_BB_FA_CNT |
1146 ODM_BB_RSSI_MONITOR |
1147 ODM_BB_CCK_PD |
1148 /*@ODM_BB_PWR_TRAIN |*/
1149 ODM_BB_RATE_ADAPTIVE |
1150 /*ODM_BB_PATH_DIV |*/
1151 ODM_BB_ADAPTIVITY |
1152 ODM_BB_CFO_TRACKING |
1153 ODM_BB_ENV_MONITOR;
1154 break;
1155 #endif
1156
1157 #if (RTL8821C_SUPPORT)
1158 case ODM_RTL8821C:
1159 support_ability |=
1160 ODM_BB_DIG |
1161 ODM_BB_RA_MASK |
1162 /*@ODM_BB_DYNAMIC_TXPWR |*/
1163 ODM_BB_FA_CNT |
1164 ODM_BB_RSSI_MONITOR |
1165 ODM_BB_CCK_PD |
1166 /*@ODM_BB_PWR_TRAIN |*/
1167 ODM_BB_RATE_ADAPTIVE |
1168 ODM_BB_ADAPTIVITY |
1169 ODM_BB_CFO_TRACKING |
1170 ODM_BB_ENV_MONITOR;
1171 break;
1172 #endif
1173
1174 /*@---------------JGR3 Series-------------------*/
1175
1176 #if (RTL8822C_SUPPORT)
1177 case ODM_RTL8822C:
1178 support_ability |=
1179 ODM_BB_DIG |
1180 ODM_BB_RA_MASK |
1181 ODM_BB_DYNAMIC_TXPWR |
1182 ODM_BB_FA_CNT |
1183 ODM_BB_RSSI_MONITOR |
1184 ODM_BB_CCK_PD |
1185 ODM_BB_RATE_ADAPTIVE |
1186 /* ODM_BB_PATH_DIV | */
1187 ODM_BB_ADAPTIVITY |
1188 ODM_BB_CFO_TRACKING |
1189 ODM_BB_ENV_MONITOR;
1190 break;
1191 #endif
1192
1193 #if (RTL8814B_SUPPORT)
1194 case ODM_RTL8814B:
1195 support_ability |=
1196 ODM_BB_DIG |
1197 ODM_BB_RA_MASK |
1198 /*@ODM_BB_DYNAMIC_TXPWR |*/
1199 ODM_BB_FA_CNT |
1200 ODM_BB_RSSI_MONITOR |
1201 ODM_BB_CCK_PD |
1202 /*@ODM_BB_PWR_TRAIN |*/
1203 /*ODM_BB_RATE_ADAPTIVE |*/
1204 ODM_BB_ADAPTIVITY |
1205 ODM_BB_CFO_TRACKING;
1206 /*ODM_BB_ENV_MONITOR;*/
1207 break;
1208 #endif
1209
1210 default:
1211 support_ability |=
1212 ODM_BB_DIG |
1213 ODM_BB_RA_MASK |
1214 /*@ODM_BB_DYNAMIC_TXPWR |*/
1215 ODM_BB_FA_CNT |
1216 ODM_BB_RSSI_MONITOR |
1217 ODM_BB_CCK_PD |
1218 /*@ODM_BB_PWR_TRAIN |*/
1219 ODM_BB_RATE_ADAPTIVE |
1220 ODM_BB_ADAPTIVITY |
1221 ODM_BB_CFO_TRACKING |
1222 ODM_BB_ENV_MONITOR;
1223
1224 pr_debug("[Warning] Supportability Init Warning !!!\n");
1225 break;
1226 }
1227
1228 return support_ability;
1229 }
1230 #endif
1231
1232 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
phydm_supportability_init_ap(void * dm_void)1233 u64 phydm_supportability_init_ap(
1234 void *dm_void)
1235 {
1236 struct dm_struct *dm = (struct dm_struct *)dm_void;
1237 u64 support_ability = 0;
1238
1239 switch (dm->support_ic_type) {
1240 /*@---------------N Series--------------------*/
1241 #if (RTL8188E_SUPPORT)
1242 case ODM_RTL8188E:
1243 support_ability |=
1244 ODM_BB_DIG |
1245 ODM_BB_RA_MASK |
1246 ODM_BB_FA_CNT |
1247 ODM_BB_RSSI_MONITOR |
1248 ODM_BB_CCK_PD |
1249 /*ODM_BB_PWR_TRAIN |*/
1250 ODM_BB_RATE_ADAPTIVE |
1251 ODM_BB_ADAPTIVITY |
1252 ODM_BB_CFO_TRACKING |
1253 ODM_BB_ENV_MONITOR |
1254 ODM_BB_PRIMARY_CCA;
1255 break;
1256 #endif
1257
1258 #if (RTL8192E_SUPPORT)
1259 case ODM_RTL8192E:
1260 support_ability |=
1261 ODM_BB_DIG |
1262 ODM_BB_RA_MASK |
1263 ODM_BB_FA_CNT |
1264 ODM_BB_RSSI_MONITOR |
1265 ODM_BB_CCK_PD |
1266 /*ODM_BB_PWR_TRAIN |*/
1267 ODM_BB_RATE_ADAPTIVE |
1268 ODM_BB_ADAPTIVITY |
1269 ODM_BB_CFO_TRACKING |
1270 ODM_BB_ENV_MONITOR |
1271 ODM_BB_PRIMARY_CCA;
1272 break;
1273 #endif
1274
1275 #if (RTL8723B_SUPPORT)
1276 case ODM_RTL8723B:
1277 support_ability |=
1278 ODM_BB_DIG |
1279 ODM_BB_RA_MASK |
1280 ODM_BB_FA_CNT |
1281 ODM_BB_RSSI_MONITOR |
1282 ODM_BB_CCK_PD |
1283 /*ODM_BB_PWR_TRAIN |*/
1284 ODM_BB_RATE_ADAPTIVE |
1285 ODM_BB_ADAPTIVITY |
1286 ODM_BB_CFO_TRACKING |
1287 ODM_BB_ENV_MONITOR;
1288 break;
1289 #endif
1290
1291 #if (RTL8198F_SUPPORT || RTL8197F_SUPPORT)
1292 case ODM_RTL8198F:
1293 support_ability |=
1294 ODM_BB_DIG |
1295 ODM_BB_RA_MASK |
1296 ODM_BB_FA_CNT |
1297 ODM_BB_RSSI_MONITOR |
1298 ODM_BB_CCK_PD |
1299 /*ODM_BB_PWR_TRAIN |*/
1300 /*ODM_BB_RATE_ADAPTIVE |*/
1301 ODM_BB_ADAPTIVITY |
1302 ODM_BB_CFO_TRACKING;
1303 /*ODM_BB_ADAPTIVE_SOML |*/
1304 /*ODM_BB_ENV_MONITOR |*/
1305 /*ODM_BB_LNA_SAT_CHK |*/
1306 /*ODM_BB_PRIMARY_CCA;*/
1307 break;
1308 case ODM_RTL8197F:
1309 support_ability |=
1310 ODM_BB_DIG |
1311 ODM_BB_RA_MASK |
1312 ODM_BB_FA_CNT |
1313 ODM_BB_RSSI_MONITOR |
1314 ODM_BB_CCK_PD |
1315 /*ODM_BB_PWR_TRAIN |*/
1316 ODM_BB_RATE_ADAPTIVE |
1317 ODM_BB_ADAPTIVITY |
1318 ODM_BB_CFO_TRACKING |
1319 ODM_BB_ADAPTIVE_SOML |
1320 ODM_BB_ENV_MONITOR |
1321 ODM_BB_LNA_SAT_CHK |
1322 ODM_BB_PRIMARY_CCA;
1323 break;
1324 #endif
1325
1326 #if (RTL8192F_SUPPORT)
1327 case ODM_RTL8192F:
1328 support_ability |=
1329 ODM_BB_DIG |
1330 ODM_BB_RA_MASK |
1331 ODM_BB_FA_CNT |
1332 ODM_BB_RSSI_MONITOR |
1333 ODM_BB_CCK_PD |
1334 /*ODM_BB_PWR_TRAIN |*/
1335 ODM_BB_RATE_ADAPTIVE |
1336 ODM_BB_ADAPTIVITY |
1337 /*ODM_BB_CFO_TRACKING |*/
1338 ODM_BB_ADAPTIVE_SOML |
1339 /*ODM_BB_PATH_DIV |*/
1340 ODM_BB_ENV_MONITOR |
1341 /*ODM_BB_LNA_SAT_CHK |*/
1342 /*ODM_BB_PRIMARY_CCA |*/
1343 0;
1344 break;
1345 #endif
1346
1347 /*@---------------AC Series-------------------*/
1348
1349 #if (RTL8881A_SUPPORT)
1350 case ODM_RTL8881A:
1351 support_ability |=
1352 ODM_BB_DIG |
1353 ODM_BB_RA_MASK |
1354 ODM_BB_FA_CNT |
1355 ODM_BB_RSSI_MONITOR |
1356 ODM_BB_CCK_PD |
1357 /*ODM_BB_PWR_TRAIN |*/
1358 ODM_BB_RATE_ADAPTIVE |
1359 ODM_BB_ADAPTIVITY |
1360 ODM_BB_CFO_TRACKING |
1361 ODM_BB_ENV_MONITOR;
1362 break;
1363 #endif
1364
1365 #if (RTL8814A_SUPPORT)
1366 case ODM_RTL8814A:
1367 support_ability |=
1368 ODM_BB_DIG |
1369 ODM_BB_RA_MASK |
1370 ODM_BB_FA_CNT |
1371 ODM_BB_RSSI_MONITOR |
1372 ODM_BB_CCK_PD |
1373 /*ODM_BB_PWR_TRAIN |*/
1374 ODM_BB_RATE_ADAPTIVE |
1375 ODM_BB_ADAPTIVITY |
1376 ODM_BB_CFO_TRACKING |
1377 ODM_BB_ENV_MONITOR;
1378 break;
1379 #endif
1380
1381 #if (RTL8822B_SUPPORT)
1382 case ODM_RTL8822B:
1383 support_ability |=
1384 ODM_BB_DIG |
1385 ODM_BB_RA_MASK |
1386 ODM_BB_FA_CNT |
1387 ODM_BB_RSSI_MONITOR |
1388 ODM_BB_CCK_PD |
1389 /*ODM_BB_PWR_TRAIN |*/
1390 /*ODM_BB_ADAPTIVE_SOML |*/
1391 ODM_BB_RATE_ADAPTIVE |
1392 ODM_BB_ADAPTIVITY |
1393 ODM_BB_CFO_TRACKING |
1394 ODM_BB_ENV_MONITOR;
1395 break;
1396 #endif
1397
1398 #if (RTL8821C_SUPPORT)
1399 case ODM_RTL8821C:
1400 support_ability |=
1401 ODM_BB_DIG |
1402 ODM_BB_RA_MASK |
1403 ODM_BB_FA_CNT |
1404 ODM_BB_RSSI_MONITOR |
1405 ODM_BB_CCK_PD |
1406 /*ODM_BB_PWR_TRAIN |*/
1407 ODM_BB_RATE_ADAPTIVE |
1408 ODM_BB_ADAPTIVITY |
1409 ODM_BB_CFO_TRACKING |
1410 ODM_BB_ENV_MONITOR;
1411
1412 break;
1413 #endif
1414
1415 /*@---------------JGR3 Series-------------------*/
1416
1417 #if (RTL8814B_SUPPORT)
1418 case ODM_RTL8814B:
1419 support_ability |=
1420 ODM_BB_DIG |
1421 ODM_BB_RA_MASK |
1422 ODM_BB_FA_CNT |
1423 ODM_BB_RSSI_MONITOR |
1424 ODM_BB_CCK_PD |
1425 /*ODM_BB_PWR_TRAIN |*/
1426 /*ODM_BB_RATE_ADAPTIVE |*/
1427 ODM_BB_ADAPTIVITY |
1428 ODM_BB_CFO_TRACKING |
1429 ODM_BB_ENV_MONITOR;
1430 break;
1431 #endif
1432
1433 #if (RTL8197G_SUPPORT)
1434 case ODM_RTL8197G:
1435 support_ability |=
1436 ODM_BB_DIG |
1437 ODM_BB_RA_MASK |
1438 ODM_BB_FA_CNT |
1439 ODM_BB_RSSI_MONITOR |
1440 ODM_BB_CCK_PD |
1441 /*ODM_BB_PWR_TRAIN |*/
1442 ODM_BB_RATE_ADAPTIVE |
1443 ODM_BB_ADAPTIVITY |
1444 ODM_BB_CFO_TRACKING |
1445 ODM_BB_ENV_MONITOR;
1446 break;
1447 #endif
1448
1449 #if (RTL8812F_SUPPORT)
1450 case ODM_RTL8812F:
1451 support_ability |=
1452 ODM_BB_DIG |
1453 ODM_BB_RA_MASK |
1454 ODM_BB_DYNAMIC_TXPWR |
1455 ODM_BB_FA_CNT |
1456 ODM_BB_RSSI_MONITOR |
1457 /*ODM_BB_CCK_PD |*/
1458 /*ODM_BB_PWR_TRAIN |*/
1459 ODM_BB_RATE_ADAPTIVE |
1460 ODM_BB_ADAPTIVITY |
1461 ODM_BB_CFO_TRACKING |
1462 ODM_BB_ENV_MONITOR;
1463 break;
1464 #endif
1465
1466 default:
1467 support_ability |=
1468 ODM_BB_DIG |
1469 ODM_BB_RA_MASK |
1470 ODM_BB_FA_CNT |
1471 ODM_BB_RSSI_MONITOR |
1472 ODM_BB_CCK_PD |
1473 /*ODM_BB_PWR_TRAIN |*/
1474 ODM_BB_RATE_ADAPTIVE |
1475 ODM_BB_ADAPTIVITY |
1476 ODM_BB_CFO_TRACKING |
1477 ODM_BB_ENV_MONITOR;
1478
1479 pr_debug("[Warning] Supportability Init Warning !!!\n");
1480 break;
1481 }
1482
1483 return support_ability;
1484 }
1485 #endif
1486
1487 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
phydm_supportability_init_iot(void * dm_void)1488 u64 phydm_supportability_init_iot(
1489 void *dm_void)
1490 {
1491 struct dm_struct *dm = (struct dm_struct *)dm_void;
1492 u64 support_ability = 0;
1493
1494 switch (dm->support_ic_type) {
1495 #if (RTL8710B_SUPPORT)
1496 case ODM_RTL8710B:
1497 support_ability |=
1498 ODM_BB_DIG |
1499 ODM_BB_RA_MASK |
1500 /*ODM_BB_DYNAMIC_TXPWR |*/
1501 ODM_BB_FA_CNT |
1502 ODM_BB_RSSI_MONITOR |
1503 ODM_BB_CCK_PD |
1504 /*ODM_BB_PWR_TRAIN |*/
1505 ODM_BB_RATE_ADAPTIVE |
1506 ODM_BB_CFO_TRACKING |
1507 ODM_BB_ENV_MONITOR;
1508 break;
1509 #endif
1510
1511 #if (RTL8195A_SUPPORT)
1512 case ODM_RTL8195A:
1513 support_ability |=
1514 ODM_BB_DIG |
1515 ODM_BB_RA_MASK |
1516 /*ODM_BB_DYNAMIC_TXPWR |*/
1517 ODM_BB_FA_CNT |
1518 ODM_BB_RSSI_MONITOR |
1519 ODM_BB_CCK_PD |
1520 /*ODM_BB_PWR_TRAIN |*/
1521 ODM_BB_RATE_ADAPTIVE |
1522 ODM_BB_CFO_TRACKING |
1523 ODM_BB_ENV_MONITOR;
1524 break;
1525 #endif
1526
1527 #if (RTL8195B_SUPPORT)
1528 case ODM_RTL8195B:
1529 support_ability |=
1530 ODM_BB_DIG |
1531 ODM_BB_RA_MASK |
1532 /*ODM_BB_DYNAMIC_TXPWR |*/
1533 ODM_BB_FA_CNT |
1534 ODM_BB_RSSI_MONITOR |
1535 ODM_BB_CCK_PD |
1536 /*ODM_BB_PWR_TRAIN |*/
1537 ODM_BB_RATE_ADAPTIVE |
1538 ODM_BB_ADAPTIVITY |
1539 ODM_BB_CFO_TRACKING |
1540 ODM_BB_ENV_MONITOR;
1541 break;
1542 #endif
1543
1544 #if (RTL8721D_SUPPORT)
1545 case ODM_RTL8721D:
1546 support_ability |=
1547 ODM_BB_DIG |
1548 ODM_BB_RA_MASK |
1549 /*ODM_BB_DYNAMIC_TXPWR |*/
1550 ODM_BB_FA_CNT |
1551 ODM_BB_RSSI_MONITOR |
1552 ODM_BB_CCK_PD |
1553 /*ODM_BB_PWR_TRAIN |*/
1554 ODM_BB_RATE_ADAPTIVE |
1555 ODM_BB_ADAPTIVITY |
1556 ODM_BB_CFO_TRACKING |
1557 ODM_BB_ENV_MONITOR;
1558 break;
1559 #endif
1560
1561 #if (RTL8710C_SUPPORT)
1562 case ODM_RTL8710C:
1563 support_ability |=
1564 ODM_BB_DIG |
1565 ODM_BB_RA_MASK |
1566 /*ODM_BB_DYNAMIC_TXPWR |*/
1567 ODM_BB_FA_CNT |
1568 ODM_BB_RSSI_MONITOR |
1569 ODM_BB_CCK_PD |
1570 /*ODM_BB_PWR_TRAIN |*/
1571 ODM_BB_RATE_ADAPTIVE |
1572 ODM_BB_ADAPTIVITY |
1573 ODM_BB_CFO_TRACKING |
1574 ODM_BB_ENV_MONITOR;
1575 break;
1576 #endif
1577 default:
1578 support_ability |=
1579 ODM_BB_DIG |
1580 ODM_BB_RA_MASK |
1581 /*ODM_BB_DYNAMIC_TXPWR |*/
1582 ODM_BB_FA_CNT |
1583 ODM_BB_RSSI_MONITOR |
1584 ODM_BB_CCK_PD |
1585 /*ODM_BB_PWR_TRAIN |*/
1586 ODM_BB_RATE_ADAPTIVE |
1587 ODM_BB_CFO_TRACKING |
1588 ODM_BB_ENV_MONITOR;
1589
1590 pr_debug("[Warning] Supportability Init Warning !!!\n");
1591 break;
1592 }
1593
1594 return support_ability;
1595 }
1596 #endif
1597
phydm_fwoffload_ability_init(struct dm_struct * dm,enum phydm_offload_ability offload_ability)1598 void phydm_fwoffload_ability_init(struct dm_struct *dm,
1599 enum phydm_offload_ability offload_ability)
1600 {
1601 switch (offload_ability) {
1602 case PHYDM_PHY_PARAM_OFFLOAD:
1603 if (dm->support_ic_type & PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD)
1604 dm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD;
1605 break;
1606
1607 case PHYDM_RF_IQK_OFFLOAD:
1608 dm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD;
1609 break;
1610
1611 case PHYDM_RF_DPK_OFFLOAD:
1612 dm->fw_offload_ability |= PHYDM_RF_DPK_OFFLOAD;
1613 break;
1614
1615 default:
1616 PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
1617 break;
1618 }
1619
1620 PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
1621 dm->fw_offload_ability);
1622 }
1623
phydm_fwoffload_ability_clear(struct dm_struct * dm,enum phydm_offload_ability offload_ability)1624 void phydm_fwoffload_ability_clear(struct dm_struct *dm,
1625 enum phydm_offload_ability offload_ability)
1626 {
1627 switch (offload_ability) {
1628 case PHYDM_PHY_PARAM_OFFLOAD:
1629 if (dm->support_ic_type & PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD)
1630 dm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD);
1631 break;
1632
1633 case PHYDM_RF_IQK_OFFLOAD:
1634 dm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD);
1635 break;
1636
1637 case PHYDM_RF_DPK_OFFLOAD:
1638 dm->fw_offload_ability &= (~PHYDM_RF_DPK_OFFLOAD);
1639 break;
1640
1641 default:
1642 PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
1643 break;
1644 }
1645
1646 PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
1647 dm->fw_offload_ability);
1648 }
1649
phydm_supportability_init(void * dm_void)1650 void phydm_supportability_init(void *dm_void)
1651 {
1652 struct dm_struct *dm = (struct dm_struct *)dm_void;
1653 u64 support_ability;
1654
1655 if (dm->manual_supportability &&
1656 *dm->manual_supportability != 0xffffffff) {
1657 support_ability = *dm->manual_supportability;
1658 } else if (*dm->mp_mode) {
1659 support_ability = 0;
1660 } else {
1661 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1662 support_ability = phydm_supportability_init_win(dm);
1663 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1664 support_ability = phydm_supportability_init_ap(dm);
1665 #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
1666 support_ability = phydm_supportability_init_ce(dm);
1667 #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
1668 support_ability = phydm_supportability_init_iot(dm);
1669 #endif
1670
1671 /*@[Config Antenna Diversity]*/
1672 if (IS_FUNC_EN(dm->enable_antdiv))
1673 support_ability |= ODM_BB_ANT_DIV;
1674
1675 /*@[Config TXpath Diversity]*/
1676 if (IS_FUNC_EN(dm->enable_pathdiv))
1677 support_ability |= ODM_BB_PATH_DIV;
1678
1679 /*@[Config Adaptive SOML]*/
1680 if (IS_FUNC_EN(dm->en_adap_soml))
1681 support_ability |= ODM_BB_ADAPTIVE_SOML;
1682
1683 }
1684 dm->support_ability = support_ability;
1685 PHYDM_DBG(dm, ODM_COMP_INIT, "IC=0x%x, mp=%d, Supportability=0x%llx\n",
1686 dm->support_ic_type, *dm->mp_mode, dm->support_ability);
1687 }
1688
phydm_rfe_init(void * dm_void)1689 void phydm_rfe_init(void *dm_void)
1690 {
1691 struct dm_struct *dm = (struct dm_struct *)dm_void;
1692
1693 PHYDM_DBG(dm, ODM_COMP_INIT, "RFE_Init\n");
1694 #if (RTL8822B_SUPPORT == 1)
1695 if (dm->support_ic_type == ODM_RTL8822B)
1696 phydm_rfe_8822b_init(dm);
1697 #endif
1698 }
1699
1700 #ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
phydm_tx_collsion_th_init(void * dm_void)1701 void phydm_tx_collsion_th_init(void *dm_void)
1702 {
1703
1704 struct dm_struct *dm = (struct dm_struct *)dm_void;
1705
1706 #if (RTL8197G_SUPPORT)
1707 if (dm->support_ic_type & ODM_RTL8197G)
1708 phydm_tx_collsion_th_init_8197g(dm);
1709 #endif
1710
1711 #if (RTL8812F_SUPPORT)
1712 if (dm->support_ic_type & ODM_RTL8812F)
1713 phydm_tx_collsion_th_init_8812f(dm);
1714 #endif
1715
1716 }
1717
phydm_tx_collsion_th_set(void * dm_void,u8 val_r2t,u8 val_t2r)1718 void phydm_tx_collsion_th_set(void *dm_void, u8 val_r2t, u8 val_t2r)
1719 {
1720 struct dm_struct *dm = (struct dm_struct *)dm_void;
1721
1722 #if (RTL8197G_SUPPORT)
1723 if (dm->support_ic_type & ODM_RTL8197G)
1724 phydm_tx_collsion_th_set_8197g(dm, val_r2t, val_t2r);
1725 #endif
1726
1727 #if (RTL8812F_SUPPORT)
1728 if (dm->support_ic_type & ODM_RTL8812F)
1729 phydm_tx_collsion_th_set_8812f(dm, val_r2t, val_t2r);
1730 #endif
1731
1732 }
1733 #endif
1734
phydm_dm_early_init(struct dm_struct * dm)1735 void phydm_dm_early_init(struct dm_struct *dm)
1736 {
1737 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1738 phydm_init_debug_setting(dm);
1739 #endif
1740 }
1741
odm_dm_init(struct dm_struct * dm)1742 enum phydm_init_result odm_dm_init(struct dm_struct *dm)
1743 {
1744 enum phydm_init_result result = PHYDM_INIT_SUCCESS;
1745
1746 if (!phydm_chk_bb_rf_pkg_set_valid(dm)) {
1747 pr_debug("[Warning][%s] Init fail\n", __func__);
1748 return PHYDM_INIT_FAIL_BBRF_REG_INVALID;
1749 }
1750
1751 halrf_init(dm);
1752 phydm_supportability_init(dm);
1753 phydm_pause_func_init(dm);
1754 phydm_rfe_init(dm);
1755 phydm_common_info_self_init(dm);
1756 phydm_rx_phy_status_init(dm);
1757 #ifdef PHYDM_AUTO_DEGBUG
1758 phydm_auto_dbg_engine_init(dm);
1759 #endif
1760 phydm_dig_init(dm);
1761 #ifdef PHYDM_SUPPORT_CCKPD
1762 #ifdef PHYDM_DCC_ENHANCE
1763 phydm_dig_cckpd_coex_init(dm);
1764 #endif
1765 phydm_cck_pd_init(dm);
1766 #endif
1767 phydm_env_monitor_init(dm);
1768 phydm_enhance_monitor_init(dm);
1769 phydm_adaptivity_init(dm);
1770 phydm_ra_info_init(dm);
1771 phydm_rssi_monitor_init(dm);
1772 phydm_cfo_tracking_init(dm);
1773 phydm_rf_init(dm);
1774 phydm_dc_cancellation(dm);
1775 #ifdef PHYDM_TXA_CALIBRATION
1776 phydm_txcurrentcalibration(dm);
1777 phydm_get_pa_bias_offset(dm);
1778 #endif
1779 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1780 odm_antenna_diversity_init(dm);
1781 #endif
1782 #ifdef CONFIG_ADAPTIVE_SOML
1783 phydm_adaptive_soml_init(dm);
1784 #endif
1785 #ifdef CONFIG_PATH_DIVERSITY
1786 phydm_tx_path_diversity_init(dm);
1787 #endif
1788 #ifdef CONFIG_DYNAMIC_TX_TWR
1789 phydm_dynamic_tx_power_init(dm);
1790 #endif
1791 #if (PHYDM_LA_MODE_SUPPORT)
1792 phydm_la_init(dm);
1793 #endif
1794
1795 #ifdef PHYDM_BEAMFORMING_VERSION1
1796 phydm_beamforming_init(dm);
1797 #endif
1798
1799 #if (RTL8188E_SUPPORT)
1800 odm_ra_info_init_all(dm);
1801 #endif
1802 #ifdef PHYDM_PRIMARY_CCA
1803 phydm_primary_cca_init(dm);
1804 #endif
1805 #ifdef CONFIG_PSD_TOOL
1806 phydm_psd_init(dm);
1807 #endif
1808
1809 #ifdef CONFIG_SMART_ANTENNA
1810 phydm_smt_ant_init(dm);
1811 #endif
1812 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
1813 phydm_lna_sat_check_init(dm);
1814 #endif
1815 #ifdef CONFIG_MCC_DM
1816 phydm_mcc_init(dm);
1817 #endif
1818
1819 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
1820 phydm_cck_rx_pathdiv_init(dm);
1821 #endif
1822
1823 #ifdef CONFIG_MU_RSOML
1824 phydm_mu_rsoml_init(dm);
1825 #endif
1826
1827 #ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
1828 phydm_tx_collsion_th_init(dm);
1829 #endif
1830
1831 return result;
1832 }
1833
odm_dm_reset(struct dm_struct * dm)1834 void odm_dm_reset(struct dm_struct *dm)
1835 {
1836 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1837 odm_ant_div_reset(dm);
1838 #endif
1839 phydm_set_edcca_threshold_api(dm);
1840 }
1841
phydm_supportability_en(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)1842 void phydm_supportability_en(void *dm_void, char input[][16], u32 *_used,
1843 char *output, u32 *_out_len)
1844 {
1845 struct dm_struct *dm = (struct dm_struct *)dm_void;
1846 u32 dm_value[10] = {0};
1847 u64 pre_support_ability, one = 1;
1848 u64 comp = 0;
1849 u32 used = *_used;
1850 u32 out_len = *_out_len;
1851 u8 i;
1852
1853 for (i = 0; i < 5; i++) {
1854 if (input[i + 1])
1855 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
1856 }
1857
1858 pre_support_ability = dm->support_ability;
1859 comp = dm->support_ability;
1860
1861 PDM_SNPF(out_len, used, output + used, out_len - used,
1862 "\n================================\n");
1863
1864 if (dm_value[0] == 100) {
1865 PDM_SNPF(out_len, used, output + used, out_len - used,
1866 "[Supportability] PhyDM Selection\n");
1867 PDM_SNPF(out_len, used, output + used, out_len - used,
1868 "================================\n");
1869 PDM_SNPF(out_len, used, output + used, out_len - used,
1870 "00. (( %s ))DIG\n",
1871 ((comp & ODM_BB_DIG) ? ("V") : (".")));
1872 PDM_SNPF(out_len, used, output + used, out_len - used,
1873 "01. (( %s ))RA_MASK\n",
1874 ((comp & ODM_BB_RA_MASK) ? ("V") : (".")));
1875 PDM_SNPF(out_len, used, output + used, out_len - used,
1876 "02. (( %s ))DYN_TXPWR\n",
1877 ((comp & ODM_BB_DYNAMIC_TXPWR) ? ("V") : (".")));
1878 PDM_SNPF(out_len, used, output + used, out_len - used,
1879 "03. (( %s ))FA_CNT\n",
1880 ((comp & ODM_BB_FA_CNT) ? ("V") : (".")));
1881 PDM_SNPF(out_len, used, output + used, out_len - used,
1882 "04. (( %s ))RSSI_MNTR\n",
1883 ((comp & ODM_BB_RSSI_MONITOR) ? ("V") : (".")));
1884 PDM_SNPF(out_len, used, output + used, out_len - used,
1885 "05. (( %s ))CCK_PD\n",
1886 ((comp & ODM_BB_CCK_PD) ? ("V") : (".")));
1887 PDM_SNPF(out_len, used, output + used, out_len - used,
1888 "06. (( %s ))ANT_DIV\n",
1889 ((comp & ODM_BB_ANT_DIV) ? ("V") : (".")));
1890 PDM_SNPF(out_len, used, output + used, out_len - used,
1891 "07. (( %s ))SMT_ANT\n",
1892 ((comp & ODM_BB_SMT_ANT) ? ("V") : (".")));
1893 PDM_SNPF(out_len, used, output + used, out_len - used,
1894 "08. (( %s ))PWR_TRAIN\n",
1895 ((comp & ODM_BB_PWR_TRAIN) ? ("V") : (".")));
1896 PDM_SNPF(out_len, used, output + used, out_len - used,
1897 "09. (( %s ))RA\n",
1898 ((comp & ODM_BB_RATE_ADAPTIVE) ? ("V") : (".")));
1899 PDM_SNPF(out_len, used, output + used, out_len - used,
1900 "10. (( %s ))PATH_DIV\n",
1901 ((comp & ODM_BB_PATH_DIV) ? ("V") : (".")));
1902 PDM_SNPF(out_len, used, output + used, out_len - used,
1903 "11. (( %s ))DFS\n",
1904 ((comp & ODM_BB_DFS) ? ("V") : (".")));
1905 PDM_SNPF(out_len, used, output + used, out_len - used,
1906 "12. (( %s ))DYN_ARFR\n",
1907 ((comp & ODM_BB_DYNAMIC_ARFR) ? ("V") : (".")));
1908 PDM_SNPF(out_len, used, output + used, out_len - used,
1909 "13. (( %s ))ADAPTIVITY\n",
1910 ((comp & ODM_BB_ADAPTIVITY) ? ("V") : (".")));
1911 PDM_SNPF(out_len, used, output + used, out_len - used,
1912 "14. (( %s ))CFO_TRACK\n",
1913 ((comp & ODM_BB_CFO_TRACKING) ? ("V") : (".")));
1914 PDM_SNPF(out_len, used, output + used, out_len - used,
1915 "15. (( %s ))ENV_MONITOR\n",
1916 ((comp & ODM_BB_ENV_MONITOR) ? ("V") : (".")));
1917 PDM_SNPF(out_len, used, output + used, out_len - used,
1918 "16. (( %s ))PRI_CCA\n",
1919 ((comp & ODM_BB_PRIMARY_CCA) ? ("V") : (".")));
1920 PDM_SNPF(out_len, used, output + used, out_len - used,
1921 "17. (( %s ))ADPTV_SOML\n",
1922 ((comp & ODM_BB_ADAPTIVE_SOML) ? ("V") : (".")));
1923 PDM_SNPF(out_len, used, output + used, out_len - used,
1924 "18. (( %s ))LNA_SAT_CHK\n",
1925 ((comp & ODM_BB_LNA_SAT_CHK) ? ("V") : (".")));
1926 PDM_SNPF(out_len, used, output + used, out_len - used,
1927 "================================\n");
1928 PDM_SNPF(out_len, used, output + used, out_len - used,
1929 "[Supportability] PhyDM offload ability\n");
1930 PDM_SNPF(out_len, used, output + used, out_len - used,
1931 "================================\n");
1932
1933 PDM_SNPF(out_len, used, output + used, out_len - used,
1934 "00. (( %s ))PHY PARAM OFFLOAD\n",
1935 ((dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) ?
1936 ("V") : (".")));
1937 PDM_SNPF(out_len, used, output + used, out_len - used,
1938 "01. (( %s ))RF IQK OFFLOAD\n",
1939 ((dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ?
1940 ("V") : (".")));
1941 PDM_SNPF(out_len, used, output + used, out_len - used,
1942 "================================\n");
1943
1944 } else if (dm_value[0] == 101) {
1945 dm->support_ability = 0;
1946 PDM_SNPF(out_len, used, output + used, out_len - used,
1947 "Disable all support_ability components\n");
1948 } else {
1949 if (dm_value[1] == 1) { /* @enable */
1950 dm->support_ability |= (one << dm_value[0]);
1951 } else if (dm_value[1] == 2) {/* @disable */
1952 dm->support_ability &= ~(one << dm_value[0]);
1953 } else {
1954 PDM_SNPF(out_len, used, output + used, out_len - used,
1955 "[Warning!!!] 1:enable, 2:disable\n");
1956 }
1957 }
1958 PDM_SNPF(out_len, used, output + used, out_len - used,
1959 "pre-supportability = 0x%llx\n", pre_support_ability);
1960 PDM_SNPF(out_len, used, output + used, out_len - used,
1961 "Cur-supportability = 0x%llx\n", dm->support_ability);
1962 PDM_SNPF(out_len, used, output + used, out_len - used,
1963 "================================\n");
1964
1965 *_used = used;
1966 *_out_len = out_len;
1967 }
1968
phydm_watchdog_lps_32k(struct dm_struct * dm)1969 void phydm_watchdog_lps_32k(struct dm_struct *dm)
1970 {
1971 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
1972
1973 phydm_common_info_self_update(dm);
1974 phydm_rssi_monitor_check(dm);
1975 phydm_dig_lps_32k(dm);
1976 phydm_common_info_self_reset(dm);
1977 }
1978
phydm_watchdog_lps(struct dm_struct * dm)1979 void phydm_watchdog_lps(struct dm_struct *dm)
1980 {
1981 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
1982 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
1983
1984 phydm_common_info_self_update(dm);
1985 phydm_rssi_monitor_check(dm);
1986 phydm_basic_dbg_message(dm);
1987 phydm_receiver_blocking(dm);
1988 phydm_false_alarm_counter_statistics(dm);
1989 phydm_dig_by_rssi_lps(dm);
1990 #ifdef PHYDM_SUPPORT_CCKPD
1991 phydm_cck_pd_th(dm);
1992 #endif
1993 phydm_adaptivity(dm);
1994 #ifdef CONFIG_BW_INDICATION
1995 phydm_dyn_bw_indication(dm);
1996 #endif
1997 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
1998 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
1999 /*@enable AntDiv in PS mode, request from SD4 Jeff*/
2000 odm_antenna_diversity(dm);
2001 #endif
2002 #endif
2003 phydm_common_info_self_reset(dm);
2004 #endif
2005 }
2006
phydm_watchdog_mp(struct dm_struct * dm)2007 void phydm_watchdog_mp(struct dm_struct *dm)
2008 {
2009 }
2010
phydm_pause_dm_watchdog(void * dm_void,enum phydm_pause_type pause_type)2011 void phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type)
2012 {
2013 struct dm_struct *dm = (struct dm_struct *)dm_void;
2014
2015 if (pause_type == PHYDM_PAUSE) {
2016 dm->disable_phydm_watchdog = 1;
2017 PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Stop\n");
2018 } else {
2019 dm->disable_phydm_watchdog = 0;
2020 PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Start\n");
2021 }
2022 }
2023
phydm_pause_func_init(void * dm_void)2024 void phydm_pause_func_init(void *dm_void)
2025 {
2026 struct dm_struct *dm = (struct dm_struct *)dm_void;
2027
2028 dm->pause_lv_table.lv_cckpd = PHYDM_PAUSE_RELEASE;
2029 dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
2030 dm->pause_lv_table.lv_antdiv = PHYDM_PAUSE_RELEASE;
2031 dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
2032 dm->pause_lv_table.lv_adapt = PHYDM_PAUSE_RELEASE;
2033 dm->pause_lv_table.lv_adsl = PHYDM_PAUSE_RELEASE;
2034 }
2035
phydm_pause_func(void * dm_void,enum phydm_func_idx pause_func,enum phydm_pause_type pause_type,enum phydm_pause_level pause_lv,u8 val_lehgth,u32 * val_buf)2036 u8 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func,
2037 enum phydm_pause_type pause_type,
2038 enum phydm_pause_level pause_lv, u8 val_lehgth,
2039 u32 *val_buf)
2040 {
2041 struct dm_struct *dm = (struct dm_struct *)dm_void;
2042 struct phydm_func_poiner *func_t = &dm->phydm_func_handler;
2043 s8 *pause_lv_pre = &dm->s8_dummy;
2044 u32 *bkp_val = &dm->u32_dummy;
2045 u32 ori_val[5] = {0};
2046 u64 pause_func_bitmap = (u64)BIT(pause_func);
2047 u8 i = 0;
2048 u8 en_2rcca = 0;
2049 u8 en_bw40m = 0;
2050 u8 pause_result = PAUSE_FAIL;
2051
2052 PHYDM_DBG(dm, ODM_COMP_API, "\n");
2053 PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] LV=%d, Len=%d\n", __func__,
2054 ((pause_type == PHYDM_PAUSE) ? "Pause" :
2055 ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
2056 pause_lv, val_lehgth);
2057
2058 if (pause_lv >= PHYDM_PAUSE_MAX_NUM) {
2059 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING]Wrong LV=%d\n", pause_lv);
2060 return PAUSE_FAIL;
2061 }
2062
2063 if (pause_func == F00_DIG) {
2064 PHYDM_DBG(dm, ODM_COMP_API, "[DIG]\n");
2065
2066 if (val_lehgth != 1) {
2067 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2068 return PAUSE_FAIL;
2069 }
2070
2071 ori_val[0] = (u32)(dm->dm_dig_table.cur_ig_value);
2072 pause_lv_pre = &dm->pause_lv_table.lv_dig;
2073 bkp_val = (u32 *)(&dm->dm_dig_table.rvrt_val);
2074 /*@function pointer hook*/
2075 func_t->pause_phydm_handler = phydm_set_dig_val;
2076
2077 #ifdef PHYDM_SUPPORT_CCKPD
2078 } else if (pause_func == F05_CCK_PD) {
2079 PHYDM_DBG(dm, ODM_COMP_API, "[CCK_PD]\n");
2080
2081 if (val_lehgth != 1) {
2082 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2083 return PAUSE_FAIL;
2084 }
2085
2086 ori_val[0] = (u32)dm->dm_cckpd_table.cck_pd_lv;
2087 pause_lv_pre = &dm->pause_lv_table.lv_cckpd;
2088 bkp_val = (u32 *)(&dm->dm_cckpd_table.rvrt_val);
2089 /*@function pointer hook*/
2090 func_t->pause_phydm_handler = phydm_set_cckpd_val;
2091 #endif
2092
2093 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2094 } else if (pause_func == F06_ANT_DIV) {
2095 PHYDM_DBG(dm, ODM_COMP_API, "[AntDiv]\n");
2096
2097 if (val_lehgth != 1) {
2098 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2099 return PAUSE_FAIL;
2100 }
2101 /*@default antenna*/
2102 ori_val[0] = (u32)(dm->dm_fat_table.rx_idle_ant);
2103 pause_lv_pre = &dm->pause_lv_table.lv_antdiv;
2104 bkp_val = (u32 *)(&dm->dm_fat_table.rvrt_val);
2105 /*@function pointer hook*/
2106 func_t->pause_phydm_handler = phydm_set_antdiv_val;
2107
2108 #endif
2109 #ifdef PHYDM_SUPPORT_ADAPTIVITY
2110 } else if (pause_func == F13_ADPTVTY) {
2111 PHYDM_DBG(dm, ODM_COMP_API, "[Adaptivity]\n");
2112
2113 if (val_lehgth != 2) {
2114 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 2\n");
2115 return PAUSE_FAIL;
2116 }
2117
2118 ori_val[0] = (u32)(dm->adaptivity.th_l2h); /*th_l2h*/
2119 ori_val[1] = (u32)(dm->adaptivity.th_h2l); /*th_h2l*/
2120 pause_lv_pre = &dm->pause_lv_table.lv_adapt;
2121 bkp_val = (u32 *)(&dm->adaptivity.rvrt_val);
2122 /*@function pointer hook*/
2123 func_t->pause_phydm_handler = phydm_set_edcca_val;
2124
2125 #endif
2126 #ifdef CONFIG_ADAPTIVE_SOML
2127 } else if (pause_func == F17_ADPTV_SOML) {
2128 PHYDM_DBG(dm, ODM_COMP_API, "[AD-SOML]\n");
2129
2130 if (val_lehgth != 1) {
2131 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
2132 return PAUSE_FAIL;
2133 }
2134 /*SOML_ON/OFF*/
2135 ori_val[0] = (u32)(dm->dm_soml_table.soml_on_off);
2136
2137 pause_lv_pre = &dm->pause_lv_table.lv_adsl;
2138 bkp_val = (u32 *)(&dm->dm_soml_table.rvrt_val);
2139 /*@function pointer hook*/
2140 func_t->pause_phydm_handler = phydm_set_adsl_val;
2141
2142 #endif
2143 } else {
2144 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error func idx\n");
2145 return PAUSE_FAIL;
2146 }
2147
2148 PHYDM_DBG(dm, ODM_COMP_API, "Pause_LV{new , pre} = {%d ,%d}\n",
2149 pause_lv, *pause_lv_pre);
2150
2151 if (pause_type == PHYDM_PAUSE || pause_type == PHYDM_PAUSE_NO_SET) {
2152 if (pause_lv <= *pause_lv_pre) {
2153 PHYDM_DBG(dm, ODM_COMP_API,
2154 "[PAUSE FAIL] Pre_LV >= Curr_LV\n");
2155 return PAUSE_FAIL;
2156 }
2157
2158 if (!(dm->pause_ability & pause_func_bitmap)) {
2159 for (i = 0; i < val_lehgth; i++)
2160 bkp_val[i] = ori_val[i];
2161 }
2162
2163 dm->pause_ability |= pause_func_bitmap;
2164 PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
2165 dm->pause_ability);
2166
2167 if (pause_type == PHYDM_PAUSE) {
2168 for (i = 0; i < val_lehgth; i++)
2169 PHYDM_DBG(dm, ODM_COMP_API,
2170 "[PAUSE SUCCESS] val_idx[%d]{New, Ori}={0x%x, 0x%x}\n",
2171 i, val_buf[i], bkp_val[i]);
2172 func_t->pause_phydm_handler(dm, val_buf, val_lehgth);
2173 } else {
2174 for (i = 0; i < val_lehgth; i++)
2175 PHYDM_DBG(dm, ODM_COMP_API,
2176 "[PAUSE NO Set: SUCCESS] val_idx[%d]{Ori}={0x%x}\n",
2177 i, bkp_val[i]);
2178 }
2179
2180 *pause_lv_pre = pause_lv;
2181 pause_result = PAUSE_SUCCESS;
2182
2183 } else if (pause_type == PHYDM_RESUME) {
2184 if (pause_lv < *pause_lv_pre) {
2185 PHYDM_DBG(dm, ODM_COMP_API,
2186 "[Resume FAIL] Pre_LV >= Curr_LV\n");
2187 return PAUSE_FAIL;
2188 }
2189
2190 if ((dm->pause_ability & pause_func_bitmap) == 0) {
2191 PHYDM_DBG(dm, ODM_COMP_API,
2192 "[RESUME] No Need to Revert\n");
2193 return PAUSE_SUCCESS;
2194 }
2195
2196 dm->pause_ability &= ~pause_func_bitmap;
2197 PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
2198 dm->pause_ability);
2199
2200 *pause_lv_pre = PHYDM_PAUSE_RELEASE;
2201
2202 for (i = 0; i < val_lehgth; i++) {
2203 PHYDM_DBG(dm, ODM_COMP_API,
2204 "[RESUME] val_idx[%d]={0x%x}\n", i,
2205 bkp_val[i]);
2206 }
2207
2208 func_t->pause_phydm_handler(dm, bkp_val, val_lehgth);
2209
2210 pause_result = PAUSE_SUCCESS;
2211 } else {
2212 PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error pause_type\n");
2213 pause_result = PAUSE_FAIL;
2214 }
2215 return pause_result;
2216 }
2217
phydm_pause_func_console(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)2218 void phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,
2219 char *output, u32 *_out_len)
2220 {
2221 struct dm_struct *dm = (struct dm_struct *)dm_void;
2222 char help[] = "-h";
2223 u32 var1[10] = {0};
2224 u32 used = *_used;
2225 u32 out_len = *_out_len;
2226 u32 i;
2227 u8 length = 0;
2228 u32 buf[5] = {0};
2229 u8 set_result = 0;
2230 enum phydm_func_idx func = 0;
2231 enum phydm_pause_type type = 0;
2232 enum phydm_pause_level lv = 0;
2233
2234 if ((strcmp(input[1], help) == 0)) {
2235 PDM_SNPF(out_len, used, output + used, out_len - used,
2236 "{Func} {1:pause,2:pause no set 3:Resume} {lv:0~3} Val[5:0]\n");
2237
2238 goto out;
2239 }
2240
2241 for (i = 0; i < 10; i++) {
2242 if (input[i + 1])
2243 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
2244 }
2245
2246 func = (enum phydm_func_idx)var1[0];
2247 type = (enum phydm_pause_type)var1[1];
2248 lv = (enum phydm_pause_level)var1[2];
2249
2250 for (i = 0; i < 5; i++)
2251 buf[i] = var1[3 + i];
2252
2253 if (func == F00_DIG) {
2254 PDM_SNPF(out_len, used, output + used, out_len - used,
2255 "[DIG]\n");
2256 length = 1;
2257
2258 } else if (func == F05_CCK_PD) {
2259 PDM_SNPF(out_len, used, output + used, out_len - used,
2260 "[CCK_PD]\n");
2261 length = 1;
2262 } else if (func == F06_ANT_DIV) {
2263 PDM_SNPF(out_len, used, output + used, out_len - used,
2264 "[Ant_Div]\n");
2265 length = 1;
2266 } else if (func == F13_ADPTVTY) {
2267 PDM_SNPF(out_len, used, output + used, out_len - used,
2268 "[Adaptivity]\n");
2269 length = 2;
2270 } else if (func == F17_ADPTV_SOML) {
2271 PDM_SNPF(out_len, used, output + used, out_len - used,
2272 "[ADSL]\n");
2273 length = 1;
2274 } else {
2275 PDM_SNPF(out_len, used, output + used, out_len - used,
2276 "[Set Function Error]\n");
2277 length = 0;
2278 }
2279
2280 if (length != 0) {
2281 PDM_SNPF(out_len, used, output + used, out_len - used,
2282 "{%s, lv=%d} val = %d, %d}\n",
2283 ((type == PHYDM_PAUSE) ? "Pause" :
2284 ((type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
2285 lv, var1[3], var1[4]);
2286
2287 set_result = phydm_pause_func(dm, func, type, lv, length, buf);
2288 }
2289
2290 PDM_SNPF(out_len, used, output + used, out_len - used,
2291 "set_result = %d\n", set_result);
2292
2293 out:
2294 *_used = used;
2295 *_out_len = out_len;
2296 }
2297
phydm_pause_dm_by_asso_pkt(struct dm_struct * dm,enum phydm_pause_type pause_type,u8 rssi)2298 void phydm_pause_dm_by_asso_pkt(struct dm_struct *dm,
2299 enum phydm_pause_type pause_type, u8 rssi)
2300 {
2301 u32 igi_val = rssi + 10;
2302 u32 th_buf[2];
2303
2304 PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] rssi=%d\n", __func__,
2305 ((pause_type == PHYDM_PAUSE) ? "Pause" :
2306 ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
2307 rssi);
2308
2309 if (pause_type == PHYDM_RESUME) {
2310 phydm_pause_func(dm, F00_DIG, PHYDM_RESUME,
2311 PHYDM_PAUSE_LEVEL_1, 1, &igi_val);
2312
2313 phydm_pause_func(dm, F13_ADPTVTY, PHYDM_RESUME,
2314 PHYDM_PAUSE_LEVEL_1, 2, th_buf);
2315 } else {
2316 odm_write_dig(dm, (u8)igi_val);
2317 phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE,
2318 PHYDM_PAUSE_LEVEL_1, 1, &igi_val);
2319
2320 th_buf[0] = 0xff;
2321 th_buf[1] = 0xff;
2322
2323 phydm_pause_func(dm, F13_ADPTVTY, PHYDM_PAUSE,
2324 PHYDM_PAUSE_LEVEL_1, 2, th_buf);
2325 }
2326 }
2327
phydm_stop_dm_watchdog_check(void * dm_void)2328 u8 phydm_stop_dm_watchdog_check(void *dm_void)
2329 {
2330 struct dm_struct *dm = (struct dm_struct *)dm_void;
2331
2332 if (dm->disable_phydm_watchdog == 1) {
2333 PHYDM_DBG(dm, DBG_COMMON_FLOW, "Disable phydm\n");
2334 return true;
2335 } else {
2336 return false;
2337 }
2338 }
2339
phydm_watchdog(struct dm_struct * dm)2340 void phydm_watchdog(struct dm_struct *dm)
2341 {
2342 PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
2343
2344 phydm_common_info_self_update(dm);
2345 phydm_phy_info_update(dm);
2346 phydm_rssi_monitor_check(dm);
2347 phydm_basic_dbg_message(dm);
2348 phydm_dm_summary(dm, FIRST_MACID);
2349 #ifdef PHYDM_AUTO_DEGBUG
2350 phydm_auto_dbg_engine(dm);
2351 #endif
2352 phydm_receiver_blocking(dm);
2353
2354 if (phydm_stop_dm_watchdog_check(dm) == true)
2355 return;
2356
2357 phydm_hw_setting(dm);
2358
2359 #ifdef PHYDM_TDMA_DIG_SUPPORT
2360 if (dm->original_dig_restore == 0) {
2361 phydm_tdma_dig_timer_check(dm);
2362 } else
2363 #endif
2364 {
2365 phydm_false_alarm_counter_statistics(dm);
2366 phydm_noisy_detection(dm);
2367
2368 #if defined(PHYDM_DCC_ENHANCE) && defined(PHYDM_SUPPORT_CCKPD)
2369 phydm_dig_cckpd_coex(dm);
2370 #else
2371 phydm_dig(dm);
2372 #ifdef PHYDM_SUPPORT_CCKPD
2373 phydm_cck_pd_th(dm);
2374 #endif
2375 #endif
2376 }
2377
2378 #ifdef PHYDM_HW_IGI
2379 phydm_hwigi(dm);
2380 #endif
2381 #ifdef PHYDM_POWER_TRAINING_SUPPORT
2382 phydm_update_power_training_state(dm);
2383 #endif
2384 phydm_adaptivity(dm);
2385 phydm_ra_info_watchdog(dm);
2386 #ifdef CONFIG_PATH_DIVERSITY
2387 phydm_tx_path_diversity(dm);
2388 #endif
2389 phydm_cfo_tracking(dm);
2390 #ifdef CONFIG_DYNAMIC_TX_TWR
2391 phydm_dynamic_tx_power(dm);
2392 #endif
2393 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2394 odm_antenna_diversity(dm);
2395 #endif
2396 #ifdef CONFIG_ADAPTIVE_SOML
2397 phydm_adaptive_soml(dm);
2398 #endif
2399
2400 #ifdef PHYDM_BEAMFORMING_VERSION1
2401 phydm_beamforming_watchdog(dm);
2402 #endif
2403
2404 halrf_watchdog(dm);
2405 #ifdef PHYDM_PRIMARY_CCA
2406 phydm_primary_cca(dm);
2407 #endif
2408 #ifdef CONFIG_BW_INDICATION
2409 phydm_dyn_bw_indication(dm);
2410 #endif
2411 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2412 odm_dtc(dm);
2413 #endif
2414
2415 phydm_env_mntr_watchdog(dm);
2416 phydm_enhance_mntr_watchdog(dm);
2417
2418 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
2419 phydm_lna_sat_chk_watchdog(dm);
2420 #endif
2421
2422 #ifdef CONFIG_MCC_DM
2423 phydm_mcc_switch(dm);
2424 #endif
2425
2426 #ifdef CONFIG_MU_RSOML
2427 phydm_mu_rsoml_decision(dm);
2428 #endif
2429
2430 phydm_common_info_self_reset(dm);
2431 }
2432
phydm_fw_dm_ctrl_en(void * dm_void,enum phydm_func_idx fun_idx,boolean enable)2433 void phydm_fw_dm_ctrl_en(void *dm_void, enum phydm_func_idx fun_idx,
2434 boolean enable)
2435 {
2436 struct dm_struct *dm = (struct dm_struct *)dm_void;
2437 u8 h2c_val[H2C_MAX_LENGTH] = {0};
2438 u8 para4[4]; /*4 bit*/
2439 u8 para8[4]; /*8 bit*/
2440 u8 i = 0;
2441
2442 for (i = 0; i < 4; i++) {
2443 para4[i] = 0;
2444 para8[i] = 0;
2445 }
2446
2447 switch (fun_idx) {
2448 case F00_DIG:
2449 phydm_fill_fw_dig_info(dm, &enable, para4, para8);
2450 break;
2451 default:
2452 pr_debug("[Warning] %s\n", __func__);
2453 return;
2454 }
2455
2456 h2c_val[0] = (u8)((fun_idx & 0x3f) | (enable << 6));
2457 h2c_val[1] = para8[0];
2458 h2c_val[2] = para8[1];
2459 h2c_val[3] = para8[2];
2460 h2c_val[4] = para8[3];
2461 h2c_val[5] = (para4[0] & 0xf) | ((para4[1] & 0xf) << 3);
2462 h2c_val[6] = (para4[2] & 0xf) | ((para4[3] & 0xf) << 3);
2463
2464 PHYDM_DBG(dm, DBG_FW_DM,
2465 "H2C[0x59] fun_idx=%d,en=%d,para8={%x %x %x %x},para4={%x %x %x %x}\n",
2466 fun_idx, enable,
2467 para8[0], para8[1], para8[2], para8[3],
2468 para4[0], para4[1], para4[2], para4[3]);
2469
2470 odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_DM_CTRL, H2C_MAX_LENGTH, h2c_val);
2471 }
2472
2473 /*@
2474 * Init /.. Fixed HW value. Only init time.
2475 */
odm_cmn_info_init(struct dm_struct * dm,enum odm_cmninfo cmn_info,u64 value)2476 void odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info,
2477 u64 value)
2478 {
2479 /* This section is used for init value */
2480 switch (cmn_info) {
2481 /* @Fixed ODM value. */
2482 case ODM_CMNINFO_ABILITY:
2483 dm->support_ability = (u64)value;
2484 break;
2485
2486 case ODM_CMNINFO_RF_TYPE:
2487 dm->rf_type = (u8)value;
2488 break;
2489
2490 case ODM_CMNINFO_PLATFORM:
2491 dm->support_platform = (u8)value;
2492 break;
2493
2494 case ODM_CMNINFO_INTERFACE:
2495 dm->support_interface = (u8)value;
2496 break;
2497
2498 case ODM_CMNINFO_MP_TEST_CHIP:
2499 dm->is_mp_chip = (u8)value;
2500 break;
2501
2502 case ODM_CMNINFO_IC_TYPE:
2503 dm->support_ic_type = (u32)value;
2504 break;
2505
2506 case ODM_CMNINFO_CUT_VER:
2507 dm->cut_version = (u8)value;
2508 break;
2509
2510 case ODM_CMNINFO_FAB_VER:
2511 dm->fab_version = (u8)value;
2512 break;
2513 case ODM_CMNINFO_FW_VER:
2514 dm->fw_version = (u8)value;
2515 break;
2516 case ODM_CMNINFO_FW_SUB_VER:
2517 dm->fw_sub_version = (u8)value;
2518 break;
2519 case ODM_CMNINFO_RFE_TYPE:
2520 #if (RTL8821C_SUPPORT)
2521 if (dm->support_ic_type & ODM_RTL8821C)
2522 dm->rfe_type_expand = (u8)value;
2523 else
2524 #endif
2525 dm->rfe_type = (u8)value;
2526
2527 #ifdef CONFIG_RFE_BY_HW_INFO
2528 phydm_init_hw_info_by_rfe(dm);
2529 #endif
2530 break;
2531
2532 case ODM_CMNINFO_RF_ANTENNA_TYPE:
2533 dm->ant_div_type = (u8)value;
2534 break;
2535
2536 case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH:
2537 dm->with_extenal_ant_switch = (u8)value;
2538 break;
2539
2540 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2541 case ODM_CMNINFO_BE_FIX_TX_ANT:
2542 dm->dm_fat_table.b_fix_tx_ant = (u8)value;
2543 break;
2544 #endif
2545
2546 case ODM_CMNINFO_BOARD_TYPE:
2547 if (!dm->is_init_hw_info_by_rfe)
2548 dm->board_type = (u8)value;
2549 break;
2550
2551 case ODM_CMNINFO_PACKAGE_TYPE:
2552 if (!dm->is_init_hw_info_by_rfe)
2553 dm->package_type = (u8)value;
2554 break;
2555
2556 case ODM_CMNINFO_EXT_LNA:
2557 if (!dm->is_init_hw_info_by_rfe)
2558 dm->ext_lna = (u8)value;
2559 break;
2560
2561 case ODM_CMNINFO_5G_EXT_LNA:
2562 if (!dm->is_init_hw_info_by_rfe)
2563 dm->ext_lna_5g = (u8)value;
2564 break;
2565
2566 case ODM_CMNINFO_EXT_PA:
2567 if (!dm->is_init_hw_info_by_rfe)
2568 dm->ext_pa = (u8)value;
2569 break;
2570
2571 case ODM_CMNINFO_5G_EXT_PA:
2572 if (!dm->is_init_hw_info_by_rfe)
2573 dm->ext_pa_5g = (u8)value;
2574 break;
2575
2576 case ODM_CMNINFO_GPA:
2577 if (!dm->is_init_hw_info_by_rfe)
2578 dm->type_gpa = (u16)value;
2579 break;
2580
2581 case ODM_CMNINFO_APA:
2582 if (!dm->is_init_hw_info_by_rfe)
2583 dm->type_apa = (u16)value;
2584 break;
2585
2586 case ODM_CMNINFO_GLNA:
2587 if (!dm->is_init_hw_info_by_rfe)
2588 dm->type_glna = (u16)value;
2589 break;
2590
2591 case ODM_CMNINFO_ALNA:
2592 if (!dm->is_init_hw_info_by_rfe)
2593 dm->type_alna = (u16)value;
2594 break;
2595
2596 case ODM_CMNINFO_EXT_TRSW:
2597 if (!dm->is_init_hw_info_by_rfe)
2598 dm->ext_trsw = (u8)value;
2599 break;
2600 case ODM_CMNINFO_EXT_LNA_GAIN:
2601 dm->ext_lna_gain = (u8)value;
2602 break;
2603 case ODM_CMNINFO_PATCH_ID:
2604 dm->iot_table.win_patch_id = (u8)value;
2605 break;
2606 case ODM_CMNINFO_BINHCT_TEST:
2607 dm->is_in_hct_test = (boolean)value;
2608 break;
2609 case ODM_CMNINFO_BWIFI_TEST:
2610 dm->wifi_test = (u8)value;
2611 break;
2612 case ODM_CMNINFO_SMART_CONCURRENT:
2613 dm->is_dual_mac_smart_concurrent = (boolean)value;
2614 break;
2615 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2616 case ODM_CMNINFO_CONFIG_BB_RF:
2617 dm->config_bbrf = (boolean)value;
2618 break;
2619 #endif
2620 case ODM_CMNINFO_IQKPAOFF:
2621 dm->rf_calibrate_info.is_iqk_pa_off = (boolean)value;
2622 break;
2623 case ODM_CMNINFO_REGRFKFREEENABLE:
2624 dm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value;
2625 break;
2626 case ODM_CMNINFO_RFKFREEENABLE:
2627 dm->rf_calibrate_info.rf_kfree_enable = (u8)value;
2628 break;
2629 case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE:
2630 dm->normal_rx_path = (u8)value;
2631 break;
2632 case ODM_CMNINFO_VALID_PATH_SET:
2633 dm->valid_path_set = (u8)value;
2634 break;
2635 case ODM_CMNINFO_EFUSE0X3D8:
2636 dm->efuse0x3d8 = (u8)value;
2637 break;
2638 case ODM_CMNINFO_EFUSE0X3D7:
2639 dm->efuse0x3d7 = (u8)value;
2640 break;
2641 case ODM_CMNINFO_ADVANCE_OTA:
2642 dm->p_advance_ota = (u8)value;
2643 break;
2644
2645 #ifdef CONFIG_PHYDM_DFS_MASTER
2646 case ODM_CMNINFO_DFS_REGION_DOMAIN:
2647 dm->dfs_region_domain = (u8)value;
2648 break;
2649 #endif
2650 case ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING:
2651 dm->soft_ap_special_setting = (u32)value;
2652 break;
2653
2654 case ODM_CMNINFO_X_CAP_SETTING:
2655 dm->dm_cfo_track.crystal_cap_default = (u8)value;
2656 break;
2657
2658 case ODM_CMNINFO_DPK_EN:
2659 /*@dm->dpk_en = (u1Byte)value;*/
2660 halrf_cmn_info_set(dm, HALRF_CMNINFO_DPK_EN, (u64)value);
2661 break;
2662
2663 case ODM_CMNINFO_HP_HWID:
2664 dm->hp_hw_id = (boolean)value;
2665 break;
2666 case ODM_CMNINFO_TSSI_ENABLE:
2667 dm->en_tssi_mode = (u8)value;
2668 break;
2669 case ODM_CMNINFO_DIS_DPD:
2670 dm->en_dis_dpd = (boolean)value;
2671 break;
2672 case ODM_CMNINFO_EN_AUTO_BW_TH:
2673 dm->en_auto_bw_th = (u8)value;
2674 break;
2675 #if (RTL8721D_SUPPORT)
2676 case ODM_CMNINFO_POWER_VOLTAGE:
2677 dm->power_voltage = (u8)value;
2678 break;
2679 case ODM_CMNINFO_ANTDIV_GPIO:
2680 dm->antdiv_gpio = (u8)value;
2681 break;
2682 case ODM_CMNINFO_PEAK_DETECT_MODE:
2683 dm->peak_detect_mode = (u8)value;
2684 break;
2685 #endif
2686 default:
2687 break;
2688 }
2689 }
2690
odm_cmn_info_hook(struct dm_struct * dm,enum odm_cmninfo cmn_info,void * value)2691 void odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info,
2692 void *value)
2693 {
2694 /* @Hook call by reference pointer. */
2695 switch (cmn_info) {
2696 /* @Dynamic call by reference pointer. */
2697 case ODM_CMNINFO_TX_UNI:
2698 dm->num_tx_bytes_unicast = (u64 *)value;
2699 break;
2700
2701 case ODM_CMNINFO_RX_UNI:
2702 dm->num_rx_bytes_unicast = (u64 *)value;
2703 break;
2704
2705 case ODM_CMNINFO_BAND:
2706 dm->band_type = (u8 *)value;
2707 break;
2708
2709 case ODM_CMNINFO_SEC_CHNL_OFFSET:
2710 dm->sec_ch_offset = (u8 *)value;
2711 break;
2712
2713 case ODM_CMNINFO_SEC_MODE:
2714 dm->security = (u8 *)value;
2715 break;
2716
2717 case ODM_CMNINFO_BW:
2718 dm->band_width = (u8 *)value;
2719 break;
2720
2721 case ODM_CMNINFO_CHNL:
2722 dm->channel = (u8 *)value;
2723 break;
2724
2725 case ODM_CMNINFO_SCAN:
2726 dm->is_scan_in_process = (boolean *)value;
2727 break;
2728
2729 case ODM_CMNINFO_POWER_SAVING:
2730 dm->is_power_saving = (boolean *)value;
2731 break;
2732
2733 case ODM_CMNINFO_TDMA:
2734 dm->is_tdma = (boolean *)value;
2735 break;
2736
2737 case ODM_CMNINFO_ONE_PATH_CCA:
2738 dm->one_path_cca = (u8 *)value;
2739 break;
2740
2741 case ODM_CMNINFO_DRV_STOP:
2742 dm->is_driver_stopped = (boolean *)value;
2743 break;
2744 case ODM_CMNINFO_INIT_ON:
2745 dm->pinit_adpt_in_progress = (boolean *)value;
2746 break;
2747
2748 case ODM_CMNINFO_ANT_TEST:
2749 dm->antenna_test = (u8 *)value;
2750 break;
2751
2752 case ODM_CMNINFO_NET_CLOSED:
2753 dm->is_net_closed = (boolean *)value;
2754 break;
2755
2756 case ODM_CMNINFO_FORCED_RATE:
2757 dm->forced_data_rate = (u16 *)value;
2758 break;
2759 case ODM_CMNINFO_ANT_DIV:
2760 dm->enable_antdiv = (u8 *)value;
2761 break;
2762 case ODM_CMNINFO_PATH_DIV:
2763 dm->enable_pathdiv = (u8 *)value;
2764 break;
2765 case ODM_CMNINFO_ADAPTIVE_SOML:
2766 dm->en_adap_soml = (u8 *)value;
2767 break;
2768 case ODM_CMNINFO_ADAPTIVITY:
2769 dm->edcca_mode = (u8 *)value;
2770 break;
2771
2772 case ODM_CMNINFO_P2P_LINK:
2773 dm->dm_dig_table.is_p2p_in_process = (u8 *)value;
2774 break;
2775
2776 case ODM_CMNINFO_IS1ANTENNA:
2777 dm->is_1_antenna = (boolean *)value;
2778 break;
2779
2780 case ODM_CMNINFO_RFDEFAULTPATH:
2781 dm->rf_default_path = (u8 *)value;
2782 break;
2783
2784 case ODM_CMNINFO_FCS_MODE: /* @fast channel switch (= MCC mode)*/
2785 dm->is_fcs_mode_enable = (boolean *)value;
2786 break;
2787
2788 case ODM_CMNINFO_HUBUSBMODE:
2789 dm->hub_usb_mode = (u8 *)value;
2790 break;
2791 case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS:
2792 dm->is_fw_dw_rsvd_page_in_progress = (boolean *)value;
2793 break;
2794 case ODM_CMNINFO_TX_TP:
2795 dm->current_tx_tp = (u32 *)value;
2796 break;
2797 case ODM_CMNINFO_RX_TP:
2798 dm->current_rx_tp = (u32 *)value;
2799 break;
2800 case ODM_CMNINFO_SOUNDING_SEQ:
2801 dm->sounding_seq = (u8 *)value;
2802 break;
2803 #ifdef CONFIG_PHYDM_DFS_MASTER
2804 case ODM_CMNINFO_DFS_MASTER_ENABLE:
2805 dm->dfs_master_enabled = (u8 *)value;
2806 break;
2807 #endif
2808
2809 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
2810 case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC:
2811 dm->dm_fat_table.p_force_tx_by_desc = (u8 *)value;
2812 break;
2813 case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA:
2814 dm->dm_fat_table.p_default_s0_s1 = (u8 *)value;
2815 break;
2816 case ODM_CMNINFO_BF_ANTDIV_DECISION:
2817 dm->dm_fat_table.is_no_csi_feedback = (boolean *)value;
2818 break;
2819 #endif
2820
2821 case ODM_CMNINFO_SOFT_AP_MODE:
2822 dm->soft_ap_mode = (u32 *)value;
2823 break;
2824 case ODM_CMNINFO_MP_MODE:
2825 dm->mp_mode = (u8 *)value;
2826 break;
2827 case ODM_CMNINFO_INTERRUPT_MASK:
2828 dm->interrupt_mask = (u32 *)value;
2829 break;
2830 case ODM_CMNINFO_BB_OPERATION_MODE:
2831 dm->bb_op_mode = (u8 *)value;
2832 break;
2833 case ODM_CMNINFO_MANUAL_SUPPORTABILITY:
2834 dm->manual_supportability = (u32 *)value;
2835 break;
2836 case ODM_CMNINFO_EN_DYM_BW_INDICATION:
2837 dm->dis_dym_bw_indication = (u8 *)value;
2838 default:
2839 /*do nothing*/
2840 break;
2841 }
2842 }
2843
2844 /*@
2845 * Update band/CHannel/.. The values are dynamic but non-per-packet.
2846 */
odm_cmn_info_update(struct dm_struct * dm,u32 cmn_info,u64 value)2847 void odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value)
2848 {
2849 /* This init variable may be changed in run time. */
2850 switch (cmn_info) {
2851 case ODM_CMNINFO_LINK_IN_PROGRESS:
2852 dm->is_link_in_process = (boolean)value;
2853 break;
2854
2855 case ODM_CMNINFO_ABILITY:
2856 dm->support_ability = (u64)value;
2857 break;
2858
2859 case ODM_CMNINFO_RF_TYPE:
2860 dm->rf_type = (u8)value;
2861 break;
2862
2863 case ODM_CMNINFO_WIFI_DIRECT:
2864 dm->is_wifi_direct = (boolean)value;
2865 break;
2866
2867 case ODM_CMNINFO_WIFI_DISPLAY:
2868 dm->is_wifi_display = (boolean)value;
2869 break;
2870
2871 case ODM_CMNINFO_LINK:
2872 dm->is_linked = (boolean)value;
2873 break;
2874
2875 case ODM_CMNINFO_CMW500LINK:
2876 dm->iot_table.is_linked_cmw500 = (boolean)value;
2877 break;
2878
2879 case ODM_CMNINFO_STATION_STATE:
2880 dm->bsta_state = (boolean)value;
2881 break;
2882
2883 case ODM_CMNINFO_RSSI_MIN:
2884 #if 0
2885 dm->rssi_min = (u8)value;
2886 #endif
2887 break;
2888
2889 case ODM_CMNINFO_RSSI_MIN_BY_PATH:
2890 dm->rssi_min_by_path = (u8)value;
2891 break;
2892
2893 case ODM_CMNINFO_DBG_COMP:
2894 dm->debug_components = (u64)value;
2895 break;
2896
2897 #ifdef ODM_CONFIG_BT_COEXIST
2898 /* The following is for BT HS mode and BT coexist mechanism. */
2899 case ODM_CMNINFO_BT_ENABLED:
2900 dm->bt_info_table.is_bt_enabled = (boolean)value;
2901 break;
2902
2903 case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
2904 dm->bt_info_table.is_bt_connect_process = (boolean)value;
2905 break;
2906
2907 case ODM_CMNINFO_BT_HS_RSSI:
2908 dm->bt_info_table.bt_hs_rssi = (u8)value;
2909 break;
2910
2911 case ODM_CMNINFO_BT_OPERATION:
2912 dm->bt_info_table.is_bt_hs_operation = (boolean)value;
2913 break;
2914
2915 case ODM_CMNINFO_BT_LIMITED_DIG:
2916 dm->bt_info_table.is_bt_limited_dig = (boolean)value;
2917 break;
2918 #endif
2919
2920 case ODM_CMNINFO_AP_TOTAL_NUM:
2921 dm->ap_total_num = (u8)value;
2922 break;
2923
2924 #ifdef CONFIG_PHYDM_DFS_MASTER
2925 case ODM_CMNINFO_DFS_REGION_DOMAIN:
2926 dm->dfs_region_domain = (u8)value;
2927 break;
2928 #endif
2929
2930 case ODM_CMNINFO_BT_CONTINUOUS_TURN:
2931 dm->is_bt_continuous_turn = (boolean)value;
2932 break;
2933 case ODM_CMNINFO_IS_DOWNLOAD_FW:
2934 dm->is_download_fw = (boolean)value;
2935 break;
2936 case ODM_CMNINFO_PHYDM_PATCH_ID:
2937 dm->iot_table.phydm_patch_id = (u32)value;
2938 break;
2939 case ODM_CMNINFO_RRSR_VAL:
2940 dm->dm_ra_table.rrsr_val_init = (u32)value;
2941 break;
2942 case ODM_CMNINFO_LINKED_BF_SUPPORT:
2943 dm->linked_bf_support = (u8)value;
2944 break;
2945 case ODM_CMNINFO_FLATNESS_TYPE:
2946 dm->flatness_type = (u8)value;
2947 break;
2948 case ODM_CMNINFO_TSSI_ENABLE:
2949 dm->en_tssi_mode = (u8)value;
2950 break;
2951 case ODM_CMNINFO_HUAWEI_HWID:
2952 dm->is_dig_low_bond = (boolean)value;
2953 break;
2954 case ODM_CMNINFO_ATHEROS_HWID:
2955 dm->is_R2R_CCA_MASKT_TIME_SHORT = (boolean)value;
2956 break;
2957 default:
2958 break;
2959 }
2960 }
2961
phydm_cmn_info_query(struct dm_struct * dm,enum phydm_info_query info_type)2962 u32 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type)
2963 {
2964 struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
2965 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2966 struct ccx_info *ccx_info = &dm->dm_ccx_info;
2967
2968 switch (info_type) {
2969 /*@=== [FA Relative] ===========================================*/
2970 case PHYDM_INFO_FA_OFDM:
2971 return fa_t->cnt_ofdm_fail;
2972
2973 case PHYDM_INFO_FA_CCK:
2974 return fa_t->cnt_cck_fail;
2975
2976 case PHYDM_INFO_FA_TOTAL:
2977 return fa_t->cnt_all;
2978
2979 case PHYDM_INFO_CCA_OFDM:
2980 return fa_t->cnt_ofdm_cca;
2981
2982 case PHYDM_INFO_CCA_CCK:
2983 return fa_t->cnt_cck_cca;
2984
2985 case PHYDM_INFO_CCA_ALL:
2986 return fa_t->cnt_cca_all;
2987
2988 case PHYDM_INFO_CRC32_OK_VHT:
2989 return fa_t->cnt_vht_crc32_ok;
2990
2991 case PHYDM_INFO_CRC32_OK_HT:
2992 return fa_t->cnt_ht_crc32_ok;
2993
2994 case PHYDM_INFO_CRC32_OK_LEGACY:
2995 return fa_t->cnt_ofdm_crc32_ok;
2996
2997 case PHYDM_INFO_CRC32_OK_CCK:
2998 return fa_t->cnt_cck_crc32_ok;
2999
3000 case PHYDM_INFO_CRC32_ERROR_VHT:
3001 return fa_t->cnt_vht_crc32_error;
3002
3003 case PHYDM_INFO_CRC32_ERROR_HT:
3004 return fa_t->cnt_ht_crc32_error;
3005
3006 case PHYDM_INFO_CRC32_ERROR_LEGACY:
3007 return fa_t->cnt_ofdm_crc32_error;
3008
3009 case PHYDM_INFO_CRC32_ERROR_CCK:
3010 return fa_t->cnt_cck_crc32_error;
3011
3012 case PHYDM_INFO_EDCCA_FLAG:
3013 return fa_t->edcca_flag;
3014
3015 case PHYDM_INFO_OFDM_ENABLE:
3016 return fa_t->ofdm_block_enable;
3017
3018 case PHYDM_INFO_CCK_ENABLE:
3019 return fa_t->cck_block_enable;
3020
3021 case PHYDM_INFO_DBG_PORT_0:
3022 return fa_t->dbg_port0;
3023
3024 case PHYDM_INFO_CRC32_OK_HT_AGG:
3025 return fa_t->cnt_ht_crc32_ok_agg;
3026
3027 case PHYDM_INFO_CRC32_ERROR_HT_AGG:
3028 return fa_t->cnt_ht_crc32_error_agg;
3029
3030 /*@=== [DIG] ================================================*/
3031
3032 case PHYDM_INFO_CURR_IGI:
3033 return dig_t->cur_ig_value;
3034
3035 /*@=== [RSSI] ===============================================*/
3036 case PHYDM_INFO_RSSI_MIN:
3037 return (u32)dm->rssi_min;
3038
3039 case PHYDM_INFO_RSSI_MAX:
3040 return (u32)dm->rssi_max;
3041
3042 case PHYDM_INFO_CLM_RATIO:
3043 return (u32)ccx_info->clm_ratio;
3044 case PHYDM_INFO_NHM_RATIO:
3045 return (u32)ccx_info->nhm_ratio;
3046 case PHYDM_INFO_NHM_NOISE_PWR:
3047 return (u32)ccx_info->nhm_level;
3048 case PHYDM_INFO_NHM_PWR:
3049 return (u32)ccx_info->nhm_pwr;
3050
3051 default:
3052 return 0xffffffff;
3053 }
3054 }
3055
3056 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
odm_init_all_work_items(struct dm_struct * dm)3057 void odm_init_all_work_items(struct dm_struct *dm)
3058 {
3059 void *adapter = dm->adapter;
3060 #if USE_WORKITEM
3061
3062 #ifdef CONFIG_ADAPTIVE_SOML
3063 odm_initialize_work_item(dm,
3064 &dm->dm_soml_table.phydm_adaptive_soml_workitem,
3065 (RT_WORKITEM_CALL_BACK)phydm_adaptive_soml_workitem_callback,
3066 (void *)adapter,
3067 "AdaptiveSOMLWorkitem");
3068 #endif
3069
3070 #ifdef ODM_EVM_ENHANCE_ANTDIV
3071 odm_initialize_work_item(dm,
3072 &dm->phydm_evm_antdiv_workitem,
3073 (RT_WORKITEM_CALL_BACK)phydm_evm_antdiv_workitem_callback,
3074 (void *)adapter,
3075 "EvmAntdivWorkitem");
3076 #endif
3077
3078 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
3079 odm_initialize_work_item(dm,
3080 &dm->dm_swat_table.phydm_sw_antenna_switch_workitem,
3081 (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback,
3082 (void *)adapter,
3083 "AntennaSwitchWorkitem");
3084 #endif
3085 #if (defined(CONFIG_HL_SMART_ANTENNA))
3086 odm_initialize_work_item(dm,
3087 &dm->dm_sat_table.hl_smart_antenna_workitem,
3088 (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback,
3089 (void *)adapter,
3090 "hl_smart_ant_workitem");
3091
3092 odm_initialize_work_item(dm,
3093 &dm->dm_sat_table.hl_smart_antenna_decision_workitem,
3094 (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback,
3095 (void *)adapter,
3096 "hl_smart_ant_decision_workitem");
3097 #endif
3098
3099 odm_initialize_work_item(
3100 dm,
3101 &dm->ra_rpt_workitem,
3102 (RT_WORKITEM_CALL_BACK)halrf_update_init_rate_work_item_callback,
3103 (void *)adapter,
3104 "ra_rpt_workitem");
3105
3106 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
3107 odm_initialize_work_item(
3108 dm,
3109 &dm->fast_ant_training_workitem,
3110 (RT_WORKITEM_CALL_BACK)odm_fast_ant_training_work_item_callback,
3111 (void *)adapter,
3112 "fast_ant_training_workitem");
3113 #endif
3114
3115 #endif /*#if USE_WORKITEM*/
3116
3117 #ifdef PHYDM_BEAMFORMING_SUPPORT
3118 odm_initialize_work_item(
3119 dm,
3120 &dm->beamforming_info.txbf_info.txbf_enter_work_item,
3121 (RT_WORKITEM_CALL_BACK)hal_com_txbf_enter_work_item_callback,
3122 (void *)adapter,
3123 "txbf_enter_work_item");
3124
3125 odm_initialize_work_item(
3126 dm,
3127 &dm->beamforming_info.txbf_info.txbf_leave_work_item,
3128 (RT_WORKITEM_CALL_BACK)hal_com_txbf_leave_work_item_callback,
3129 (void *)adapter,
3130 "txbf_leave_work_item");
3131
3132 odm_initialize_work_item(
3133 dm,
3134 &dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item,
3135 (RT_WORKITEM_CALL_BACK)hal_com_txbf_fw_ndpa_work_item_callback,
3136 (void *)adapter,
3137 "txbf_fw_ndpa_work_item");
3138
3139 odm_initialize_work_item(
3140 dm,
3141 &dm->beamforming_info.txbf_info.txbf_clk_work_item,
3142 (RT_WORKITEM_CALL_BACK)hal_com_txbf_clk_work_item_callback,
3143 (void *)adapter,
3144 "txbf_clk_work_item");
3145
3146 odm_initialize_work_item(
3147 dm,
3148 &dm->beamforming_info.txbf_info.txbf_rate_work_item,
3149 (RT_WORKITEM_CALL_BACK)hal_com_txbf_rate_work_item_callback,
3150 (void *)adapter,
3151 "txbf_rate_work_item");
3152
3153 odm_initialize_work_item(
3154 dm,
3155 &dm->beamforming_info.txbf_info.txbf_status_work_item,
3156 (RT_WORKITEM_CALL_BACK)hal_com_txbf_status_work_item_callback,
3157 (void *)adapter,
3158 "txbf_status_work_item");
3159
3160 odm_initialize_work_item(
3161 dm,
3162 &dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item,
3163 (RT_WORKITEM_CALL_BACK)hal_com_txbf_reset_tx_path_work_item_callback,
3164 (void *)adapter,
3165 "txbf_reset_tx_path_work_item");
3166
3167 odm_initialize_work_item(
3168 dm,
3169 &dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item,
3170 (RT_WORKITEM_CALL_BACK)hal_com_txbf_get_tx_rate_work_item_callback,
3171 (void *)adapter,
3172 "txbf_get_tx_rate_work_item");
3173 #endif
3174
3175 #if (PHYDM_LA_MODE_SUPPORT == 1)
3176 odm_initialize_work_item(
3177 dm,
3178 &dm->adcsmp.adc_smp_work_item,
3179 (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
3180 (void *)adapter,
3181 "adc_smp_work_item");
3182
3183 odm_initialize_work_item(
3184 dm,
3185 &dm->adcsmp.adc_smp_work_item_1,
3186 (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
3187 (void *)adapter,
3188 "adc_smp_work_item_1");
3189 #endif
3190 }
3191
odm_free_all_work_items(struct dm_struct * dm)3192 void odm_free_all_work_items(struct dm_struct *dm)
3193 {
3194 #if USE_WORKITEM
3195
3196 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
3197 odm_free_work_item(&dm->dm_swat_table.phydm_sw_antenna_switch_workitem);
3198 #endif
3199
3200 #ifdef CONFIG_ADAPTIVE_SOML
3201 odm_free_work_item(&dm->dm_soml_table.phydm_adaptive_soml_workitem);
3202 #endif
3203
3204 #ifdef ODM_EVM_ENHANCE_ANTDIV
3205 odm_free_work_item(&dm->phydm_evm_antdiv_workitem);
3206 #endif
3207
3208 #if (defined(CONFIG_HL_SMART_ANTENNA))
3209 odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_workitem);
3210 odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_decision_workitem);
3211 #endif
3212
3213 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
3214 odm_free_work_item(&dm->fast_ant_training_workitem);
3215 #endif
3216 odm_free_work_item(&dm->ra_rpt_workitem);
3217 /*odm_free_work_item((&dm->sbdcnt_workitem));*/
3218 #endif
3219
3220 #ifdef PHYDM_BEAMFORMING_SUPPORT
3221 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_enter_work_item));
3222 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_leave_work_item));
3223 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item));
3224 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_clk_work_item));
3225 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_rate_work_item));
3226 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_status_work_item));
3227 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item));
3228 odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item));
3229 #endif
3230
3231 #if (PHYDM_LA_MODE_SUPPORT == 1)
3232 odm_free_work_item((&dm->adcsmp.adc_smp_work_item));
3233 odm_free_work_item((&dm->adcsmp.adc_smp_work_item_1));
3234 #endif
3235 }
3236 #endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
3237
odm_init_all_timers(struct dm_struct * dm)3238 void odm_init_all_timers(struct dm_struct *dm)
3239 {
3240 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
3241 odm_ant_div_timers(dm, INIT_ANTDIV_TIMMER);
3242 #endif
3243 #if (defined(PHYDM_TDMA_DIG_SUPPORT))
3244 #ifdef IS_USE_NEW_TDMA
3245 phydm_tdma_dig_timers(dm, INIT_TDMA_DIG_TIMMER);
3246 #endif
3247 #endif
3248 #ifdef CONFIG_ADAPTIVE_SOML
3249 phydm_adaptive_soml_timers(dm, INIT_SOML_TIMMER);
3250 #endif
3251 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
3252 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
3253 phydm_lna_sat_chk_timers(dm, INIT_LNA_SAT_CHK_TIMMER);
3254 #endif
3255 #endif
3256
3257 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3258 odm_initialize_timer(dm, &dm->sbdcnt_timer,
3259 (void *)phydm_sbd_callback, NULL, "SbdTimer");
3260 #ifdef PHYDM_BEAMFORMING_SUPPORT
3261 odm_initialize_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer,
3262 (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL,
3263 "txbf_fw_ndpa_timer");
3264 #endif
3265 #endif
3266
3267 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3268 #ifdef PHYDM_BEAMFORMING_SUPPORT
3269 odm_initialize_timer(dm, &dm->beamforming_info.beamforming_timer,
3270 (void *)beamforming_sw_timer_callback, NULL,
3271 "beamforming_timer");
3272 #endif
3273 #endif
3274 }
3275
odm_cancel_all_timers(struct dm_struct * dm)3276 void odm_cancel_all_timers(struct dm_struct *dm)
3277 {
3278 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3279 /* @2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in win7*/
3280 if (dm->adapter == NULL)
3281 return;
3282 #endif
3283
3284 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
3285 odm_ant_div_timers(dm, CANCEL_ANTDIV_TIMMER);
3286 #endif
3287 #ifdef PHYDM_TDMA_DIG_SUPPORT
3288 #ifdef IS_USE_NEW_TDMA
3289 phydm_tdma_dig_timers(dm, CANCEL_TDMA_DIG_TIMMER);
3290 #endif
3291 #endif
3292 #ifdef CONFIG_ADAPTIVE_SOML
3293 phydm_adaptive_soml_timers(dm, CANCEL_SOML_TIMMER);
3294 #endif
3295 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
3296 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
3297 phydm_lna_sat_chk_timers(dm, CANCEL_LNA_SAT_CHK_TIMMER);
3298 #endif
3299 #endif
3300
3301 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3302 odm_cancel_timer(dm, &dm->sbdcnt_timer);
3303 #ifdef PHYDM_BEAMFORMING_SUPPORT
3304 odm_cancel_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
3305 #endif
3306 #endif
3307
3308 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3309 #ifdef PHYDM_BEAMFORMING_SUPPORT
3310 odm_cancel_timer(dm, &dm->beamforming_info.beamforming_timer);
3311 #endif
3312 #endif
3313 }
3314
odm_release_all_timers(struct dm_struct * dm)3315 void odm_release_all_timers(struct dm_struct *dm)
3316 {
3317 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
3318 odm_ant_div_timers(dm, RELEASE_ANTDIV_TIMMER);
3319 #endif
3320 #ifdef PHYDM_TDMA_DIG_SUPPORT
3321 #ifdef IS_USE_NEW_TDMA
3322 phydm_tdma_dig_timers(dm, RELEASE_TDMA_DIG_TIMMER);
3323 #endif
3324 #endif
3325 #ifdef CONFIG_ADAPTIVE_SOML
3326 phydm_adaptive_soml_timers(dm, RELEASE_SOML_TIMMER);
3327 #endif
3328 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
3329 #ifdef PHYDM_LNA_SAT_CHK_TYPE1
3330 phydm_lna_sat_chk_timers(dm, RELEASE_LNA_SAT_CHK_TIMMER);
3331 #endif
3332 #endif
3333
3334 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3335 odm_release_timer(dm, &dm->sbdcnt_timer);
3336 #ifdef PHYDM_BEAMFORMING_SUPPORT
3337 odm_release_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
3338 #endif
3339 #endif
3340
3341 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3342 #ifdef PHYDM_BEAMFORMING_SUPPORT
3343 odm_release_timer(dm, &dm->beamforming_info.beamforming_timer);
3344 #endif
3345 #endif
3346 }
3347
3348 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
odm_init_all_threads(struct dm_struct * dm)3349 void odm_init_all_threads(
3350 struct dm_struct *dm)
3351 {
3352 #ifdef TPT_THREAD
3353 k_tpt_task_init(dm->priv);
3354 #endif
3355 }
3356
odm_stop_all_threads(struct dm_struct * dm)3357 void odm_stop_all_threads(
3358 struct dm_struct *dm)
3359 {
3360 #ifdef TPT_THREAD
3361 k_tpt_task_stop(dm->priv);
3362 #endif
3363 }
3364 #endif
3365
3366 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3367 /* @Justin: According to the current RRSI to adjust Response Frame TX power,
3368 * 2012/11/05
3369 */
odm_dtc(struct dm_struct * dm)3370 void odm_dtc(struct dm_struct *dm)
3371 {
3372 #ifdef CONFIG_DM_RESP_TXAGC
3373 /* RSSI higher than this value, start to decade TX power */
3374 #define DTC_BASE 35
3375
3376 /* RSSI lower than this value, start to increase TX power */
3377 #define DTC_DWN_BASE (DTC_BASE - 5)
3378
3379 /* RSSI vs TX power step mapping: decade TX power */
3380 static const u8 dtc_table_down[] = {
3381 DTC_BASE,
3382 (DTC_BASE + 5),
3383 (DTC_BASE + 10),
3384 (DTC_BASE + 15),
3385 (DTC_BASE + 20),
3386 (DTC_BASE + 25)};
3387
3388 /* RSSI vs TX power step mapping: increase TX power */
3389 static const u8 dtc_table_up[] = {
3390 DTC_DWN_BASE,
3391 (DTC_DWN_BASE - 5),
3392 (DTC_DWN_BASE - 10),
3393 (DTC_DWN_BASE - 15),
3394 (DTC_DWN_BASE - 15),
3395 (DTC_DWN_BASE - 20),
3396 (DTC_DWN_BASE - 20),
3397 (DTC_DWN_BASE - 25),
3398 (DTC_DWN_BASE - 25),
3399 (DTC_DWN_BASE - 30),
3400 (DTC_DWN_BASE - 35)};
3401
3402 u8 i;
3403 u8 dtc_steps = 0;
3404 u8 sign;
3405 u8 resp_txagc = 0;
3406
3407 if (dm->rssi_min > DTC_BASE) {
3408 /* need to decade the CTS TX power */
3409 sign = 1;
3410 for (i = 0; i < ARRAY_SIZE(dtc_table_down); i++) {
3411 if (dtc_table_down[i] >= dm->rssi_min || dtc_steps >= 6)
3412 break;
3413 else
3414 dtc_steps++;
3415 }
3416 }
3417 #if 0
3418 else if (dm->rssi_min > DTC_DWN_BASE) {
3419 /* needs to increase the CTS TX power */
3420 sign = 0;
3421 dtc_steps = 1;
3422 for (i = 0; i < ARRAY_SIZE(dtc_table_up); i++) {
3423 if (dtc_table_up[i] <= dm->rssi_min || dtc_steps >= 10)
3424 break;
3425 else
3426 dtc_steps++;
3427 }
3428 }
3429 #endif
3430 else {
3431 sign = 0;
3432 dtc_steps = 0;
3433 }
3434
3435 resp_txagc = dtc_steps | (sign << 4);
3436 resp_txagc = resp_txagc | (resp_txagc << 5);
3437 odm_write_1byte(dm, 0x06d9, resp_txagc);
3438
3439 PHYDM_DBG(dm, ODM_COMP_PWR_TRAIN,
3440 "%s rssi_min:%u, set RESP_TXAGC to %s %u\n", __func__,
3441 dm->rssi_min, sign ? "minus" : "plus", dtc_steps);
3442 #endif /* @CONFIG_RESP_TXAGC_ADJUST */
3443 }
3444
3445 #endif /* @#if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
3446
3447 /*@<20170126, BB-Kevin>8188F D-CUT DC cancellation and 8821C*/
phydm_dc_cancellation(struct dm_struct * dm)3448 void phydm_dc_cancellation(struct dm_struct *dm)
3449 {
3450 #ifdef PHYDM_DC_CANCELLATION
3451 u32 offset_i_hex[PHYDM_MAX_RF_PATH] = {0};
3452 u32 offset_q_hex[PHYDM_MAX_RF_PATH] = {0};
3453 u32 reg_value32[PHYDM_MAX_RF_PATH] = {0};
3454 u8 path = RF_PATH_A;
3455 u8 set_result;
3456
3457 if (!(dm->support_ic_type & ODM_DC_CANCELLATION_SUPPORT))
3458 return;
3459 if ((dm->support_ic_type & ODM_RTL8188F) &&
3460 dm->cut_version < ODM_CUT_D)
3461 return;
3462 if ((dm->support_ic_type & ODM_RTL8192F) &&
3463 dm->cut_version == ODM_CUT_A)
3464 return;
3465 if (*dm->band_width == CHANNEL_WIDTH_5)
3466 return;
3467 if (*dm->band_width == CHANNEL_WIDTH_10)
3468 return;
3469
3470 PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
3471
3472 /*@DC_Estimation (only for 2x2 ic now) */
3473
3474 for (path = RF_PATH_A; path < PHYDM_MAX_RF_PATH; path++) {
3475 if (path > RF_PATH_A &&
3476 dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8188F |
3477 ODM_RTL8710B | ODM_RTL8721D |
3478 ODM_RTL8710C | ODM_RTL8723D))
3479 break;
3480 else if (path > RF_PATH_B &&
3481 dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8192F))
3482 break;
3483 if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
3484 PHYDM_DBG(dm, ODM_COMP_API, "STOP_TRX_FAIL\n");
3485 return;
3486 }
3487 odm_write_dig(dm, 0x7e);
3488 /*@Disable LNA*/
3489 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D |
3490 ODM_RTL8710C))
3491 halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);
3492 /*@Enable ADC short*/
3493 if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C))
3494 odm_set_bb_reg(dm, R_0x880, BIT(15), 0x1);
3495 /*Turn off 3-wire*/
3496 phydm_stop_3_wire(dm, PHYDM_SET);
3497 if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8723D |
3498 ODM_RTL8710B)) {
3499 /*set debug port to 0x235*/
3500 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
3501 PHYDM_DBG(dm, ODM_COMP_API,
3502 "Set Debug port Fail\n");
3503 return;
3504 }
3505 } else if (dm->support_ic_type & (ODM_RTL8721D |
3506 ODM_RTL8710C)) {
3507 /*set debug port to 0x200*/
3508 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x200)) {
3509 PHYDM_DBG(dm, ODM_COMP_API,
3510 "Set Debug port Fail\n");
3511 return;
3512 }
3513 } else if (dm->support_ic_type & ODM_RTL8821C) {
3514 if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
3515 /*set debug port to 0x200*/
3516 PHYDM_DBG(dm, ODM_COMP_API,
3517 "Set Debug port Fail\n");
3518 return;
3519 }
3520 phydm_bb_dbg_port_header_sel(dm, 0x0);
3521 } else if (dm->support_ic_type & ODM_RTL8822B) {
3522 if (path == RF_PATH_A &&
3523 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
3524 /*set debug port to 0x200*/
3525 PHYDM_DBG(dm, ODM_COMP_API,
3526 "Set Debug port Fail\n");
3527 return;
3528 }
3529 if (path == RF_PATH_B &&
3530 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x202)) {
3531 /*set debug port to 0x200*/
3532 PHYDM_DBG(dm, ODM_COMP_API,
3533 "Set Debug port Fail\n");
3534 return;
3535 }
3536 phydm_bb_dbg_port_header_sel(dm, 0x0);
3537 } else if (dm->support_ic_type & ODM_RTL8192F) {
3538 if (path == RF_PATH_A &&
3539 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
3540 /*set debug port to 0x235*/
3541 PHYDM_DBG(dm, ODM_COMP_API,
3542 "Set Debug port Fail\n");
3543 return;
3544 }
3545 if (path == RF_PATH_B &&
3546 !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x23d)) {
3547 /*set debug port to 0x23d*/
3548 PHYDM_DBG(dm, ODM_COMP_API,
3549 "Set Debug port Fail\n");
3550 return;
3551 }
3552 }
3553
3554 /*@disable CCK DCNF*/
3555 odm_set_bb_reg(dm, R_0xa78, MASKBYTE1, 0x0);
3556
3557 PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation Begin!!!\n");
3558
3559 phydm_stop_ck320(dm, true); /*stop ck320*/
3560
3561 /* the same debug port both for path-a and path-b*/
3562 reg_value32[path] = phydm_get_bb_dbg_port_val(dm);
3563
3564 phydm_stop_ck320(dm, false); /*start ck320*/
3565
3566 phydm_release_bb_dbg_port(dm);
3567 /* @Turn on 3-wire*/
3568 phydm_stop_3_wire(dm, PHYDM_REVERT);
3569 /* @Disable ADC short*/
3570 if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C))
3571 odm_set_bb_reg(dm, R_0x880, BIT(15), 0x0);
3572 /* @Enable LNA*/
3573 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D |
3574 ODM_RTL8710C))
3575 halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);
3576
3577 odm_write_dig(dm, 0x20);
3578
3579 set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);
3580
3581 PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation OK!!!\n");
3582 }
3583
3584 /*@DC_Cancellation*/
3585 /*@DC compensation to CCK data path*/
3586 odm_set_bb_reg(dm, R_0xa9c, BIT(20), 0x1);
3587 if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8723D |
3588 ODM_RTL8710B)) {
3589 offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
3590 offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
3591
3592 /*@Before filling into registers,
3593 *offset should be multiplexed (-1)
3594 */
3595 offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
3596 (0x400 - offset_i_hex[0]) :
3597 (0x1ff - offset_i_hex[0]);
3598 offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
3599 (0x400 - offset_q_hex[0]) :
3600 (0x1ff - offset_q_hex[0]);
3601
3602 odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
3603 odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
3604 } else if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) {
3605 /* Path-a */
3606 offset_i_hex[0] = (reg_value32[0] & 0xffc00) >> 10;
3607 offset_q_hex[0] = reg_value32[0] & 0x3ff;
3608
3609 /*@Before filling into registers,
3610 *offset should be multiplexed (-1)
3611 */
3612 offset_i_hex[0] = 0x400 - offset_i_hex[0];
3613 offset_q_hex[0] = 0x400 - offset_q_hex[0];
3614
3615 odm_set_bb_reg(dm, R_0xc10, 0x3c000000,
3616 (0x3c0 & offset_i_hex[0]) >> 6);
3617 odm_set_bb_reg(dm, R_0xc10, 0xfc00, 0x3f & offset_i_hex[0]);
3618 odm_set_bb_reg(dm, R_0xc14, 0x3c000000,
3619 (0x3c0 & offset_q_hex[0]) >> 6);
3620 odm_set_bb_reg(dm, R_0xc14, 0xfc00, 0x3f & offset_q_hex[0]);
3621
3622 /* Path-b */
3623 if (dm->rf_type > RF_1T1R) {
3624 offset_i_hex[1] = (reg_value32[1] & 0xffc00) >> 10;
3625 offset_q_hex[1] = reg_value32[1] & 0x3ff;
3626
3627 /*@Before filling into registers,
3628 *offset should be multiplexed (-1)
3629 */
3630 offset_i_hex[1] = 0x400 - offset_i_hex[1];
3631 offset_q_hex[1] = 0x400 - offset_q_hex[1];
3632
3633 odm_set_bb_reg(dm, R_0xe10, 0x3c000000,
3634 (0x3c0 & offset_i_hex[1]) >> 6);
3635 odm_set_bb_reg(dm, R_0xe10, 0xfc00,
3636 0x3f & offset_i_hex[1]);
3637 odm_set_bb_reg(dm, R_0xe14, 0x3c000000,
3638 (0x3c0 & offset_q_hex[1]) >> 6);
3639 odm_set_bb_reg(dm, R_0xe14, 0xfc00,
3640 0x3f & offset_q_hex[1]);
3641 }
3642 } else if (dm->support_ic_type & (ODM_RTL8192F)) {
3643 /* Path-a I:df4[27:18],Q:df4[17:8]*/
3644 offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
3645 offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
3646
3647 /*@Before filling into registers,
3648 *offset should be multiplexed (-1)
3649 */
3650 offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
3651 (0x400 - offset_i_hex[0]) :
3652 (0xff - offset_i_hex[0]);
3653 offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
3654 (0x400 - offset_q_hex[0]) :
3655 (0xff - offset_q_hex[0]);
3656 /*Path-a I:c10[7:0],Q:c10[15:8]*/
3657 odm_set_bb_reg(dm, R_0xc10, 0xff, offset_i_hex[0]);
3658 odm_set_bb_reg(dm, R_0xc10, 0xff00, offset_q_hex[0]);
3659
3660 /* Path-b */
3661 if (dm->rf_type > RF_1T1R) {
3662 /* @I:df4[27:18],Q:df4[17:8]*/
3663 offset_i_hex[1] = (reg_value32[1] & 0xffc0000) >> 18;
3664 offset_q_hex[1] = (reg_value32[1] & 0x3ff00) >> 8;
3665
3666 /*@Before filling into registers,
3667 *offset should be multiplexed (-1)
3668 */
3669 offset_i_hex[1] = (offset_i_hex[1] >= 0x200) ?
3670 (0x400 - offset_i_hex[1]) :
3671 (0xff - offset_i_hex[1]);
3672 offset_q_hex[1] = (offset_q_hex[1] >= 0x200) ?
3673 (0x400 - offset_q_hex[1]) :
3674 (0xff - offset_q_hex[1]);
3675 /*Path-b I:c18[7:0],Q:c18[15:8]*/
3676 odm_set_bb_reg(dm, R_0xc18, 0xff, offset_i_hex[1]);
3677 odm_set_bb_reg(dm, R_0xc18, 0xff00, offset_q_hex[1]);
3678 }
3679 } else if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) {
3680 /*judy modified 20180517*/
3681 offset_i_hex[0] = (reg_value32[0] & 0xff80000) >> 19;
3682 offset_q_hex[0] = (reg_value32[0] & 0x3fe00) >> 9;
3683
3684 if ((offset_i_hex[0] > 0xF && offset_i_hex[0] < 0x1F1)
3685 || (offset_q_hex[0] > 0xF && offset_q_hex[0] < 0x1F1)) {
3686 /*@Discard outliers*/
3687 offset_i_hex[0] = 0x0;
3688 offset_q_hex[0] = 0x0;
3689 } else {
3690 /*@Before filling into registers,
3691 *offset should be multiplexed (-1)
3692 */
3693 offset_i_hex[0] = 0x200 - offset_i_hex[0];
3694 offset_q_hex[0] = 0x200 - offset_q_hex[0];
3695 }
3696 odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
3697 odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
3698 }
3699 #endif
3700 }
3701
phydm_receiver_blocking(void * dm_void)3702 void phydm_receiver_blocking(void *dm_void)
3703 {
3704 #ifdef CONFIG_RECEIVER_BLOCKING
3705 struct dm_struct *dm = (struct dm_struct *)dm_void;
3706 u32 chnl = *dm->channel;
3707 u8 bw = *dm->band_width;
3708 u32 bb_regf0 = odm_get_bb_reg(dm, R_0xf0, 0xf000);
3709
3710 if (!(dm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT) ||
3711 *dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
3712 return;
3713
3714 if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 < 8) ||
3715 dm->support_ic_type & ODM_RTL8192E) {
3716 /*@8188E_T version*/
3717 if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
3718 goto end;
3719
3720 if (bw == CHANNEL_WIDTH_20 && chnl == 1) {
3721 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2410,
3722 PHYDM_DONT_CARE);
3723 dm->is_rx_blocking_en = true;
3724 } else if ((bw == CHANNEL_WIDTH_20) && (chnl == 13)) {
3725 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
3726 PHYDM_DONT_CARE);
3727 dm->is_rx_blocking_en = true;
3728 } else if (dm->is_rx_blocking_en && chnl != 1 && chnl != 13) {
3729 phydm_nbi_enable(dm, FUNC_DISABLE);
3730 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3731 dm->is_rx_blocking_en = false;
3732 }
3733 return;
3734 } else if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 >= 8)) {
3735 /*@8188E_S version*/
3736 if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
3737 goto end;
3738
3739 if (bw == CHANNEL_WIDTH_20 && chnl == 13) {
3740 phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
3741 PHYDM_DONT_CARE);
3742 dm->is_rx_blocking_en = true;
3743 } else if (dm->is_rx_blocking_en && chnl != 13) {
3744 phydm_nbi_enable(dm, FUNC_DISABLE);
3745 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3746 dm->is_rx_blocking_en = false;
3747 }
3748 return;
3749 }
3750
3751 end:
3752 if (dm->is_rx_blocking_en) {
3753 phydm_nbi_enable(dm, FUNC_DISABLE);
3754 odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
3755 dm->is_rx_blocking_en = false;
3756 }
3757 #endif
3758 }
3759
phydm_dyn_bw_indication(void * dm_void)3760 void phydm_dyn_bw_indication(void *dm_void)
3761 {
3762 #ifdef CONFIG_BW_INDICATION
3763 struct dm_struct *dm = (struct dm_struct *)dm_void;
3764 u8 en_auto_bw_th = dm->en_auto_bw_th;
3765
3766 if (!(dm->support_ic_type & ODM_DYM_BW_INDICATION_SUPPORT))
3767 return;
3768
3769 /*driver decide bw cobime timing*/
3770 if (dm->dis_dym_bw_indication) {
3771 if (*dm->dis_dym_bw_indication)
3772 return;
3773 }
3774
3775 /*check for auto bw*/
3776 if (dm->rssi_min <= en_auto_bw_th && dm->is_linked) {
3777 phydm_bw_fixed_enable(dm, FUNC_DISABLE);
3778 return;
3779 }
3780
3781 phydm_bw_fixed_setting(dm);
3782 #endif
3783 }
3784
3785