1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 * ************************************************************
29 */
30
31 #include "mp_precomp.h"
32 #include "phydm_precomp.h"
33
34 #if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
35 RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
36 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\
37 RTL8812F_SUPPORT == 1 || RTL8710C_SUPPORT == 1 ||\
38 RTL8197G_SUPPORT == 1)
39
_iqk_check_if_reload(void * dm_void)40 void _iqk_check_if_reload(void *dm_void)
41 {
42 struct dm_struct *dm = (struct dm_struct *)dm_void;
43 struct dm_iqk_info *iqk_info = &dm->IQK_info;
44
45 iqk_info->is_reload = (boolean)odm_get_bb_reg(dm, R_0x1bf0, BIT(16));
46 }
47
_iqk_page_switch(void * dm_void)48 void _iqk_page_switch(void *dm_void)
49 {
50 struct dm_struct *dm = (struct dm_struct *)dm_void;
51
52 if (dm->support_ic_type == ODM_RTL8821C)
53 odm_write_4byte(dm, 0x1b00, 0xf8000008);
54 else
55 odm_write_4byte(dm, 0x1b00, 0xf800000a);
56 }
57
halrf_psd_log2base(u32 val)58 u32 halrf_psd_log2base(u32 val)
59 {
60 u8 j;
61 u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0;
62 u32 result, val_fractiond_b = 0;
63 u32 table_fraction[21] = {
64 0, 432, 332, 274, 232, 200, 174, 151, 132, 115,
65 100, 86, 74, 62, 51, 42, 32, 23, 15, 7, 0};
66
67 if (val == 0)
68 return 0;
69
70 tmp = val;
71
72 while (1) {
73 if (tmp == 1)
74 break;
75
76 tmp = (tmp >> 1);
77 shiftcount++;
78 }
79
80 val_integerd_b = shiftcount + 1;
81
82 tmp2 = 1;
83 for (j = 1; j <= val_integerd_b; j++)
84 tmp2 = tmp2 * 2;
85
86 tmp = (val * 100) / tmp2;
87 tindex = tmp / 5;
88
89 if (tindex > 20)
90 tindex = 20;
91
92 val_fractiond_b = table_fraction[tindex];
93
94 result = val_integerd_b * 100 - val_fractiond_b;
95
96 return result;
97 }
98 #if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
99 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
halrf_iqk_xym_enable(struct dm_struct * dm,u8 xym_enable)100 void halrf_iqk_xym_enable(struct dm_struct *dm, u8 xym_enable)
101 {
102 struct dm_iqk_info *iqk_info = &dm->IQK_info;
103
104 if (xym_enable == 0)
105 iqk_info->xym_read = false;
106 else
107 iqk_info->xym_read = true;
108
109 RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s %s\n", "xym_read = ",
110 (iqk_info->xym_read ? "true" : "false"));
111 }
112
113 /*xym_type => 0: rx_sym; 1: tx_xym; 2:gs1_xym; 3:gs2_sym; 4: rxk1_xym*/
halrf_iqk_xym_read(void * dm_void,u8 path,u8 xym_type)114 void halrf_iqk_xym_read(void *dm_void, u8 path, u8 xym_type)
115 {
116 struct dm_struct *dm = (struct dm_struct *)dm_void;
117 struct dm_iqk_info *iqk_info = &dm->IQK_info;
118 u8 i, start, num;
119 u32 tmp1, tmp2;
120
121 if (!iqk_info->xym_read)
122 return;
123
124 if (*dm->band_width == 0) {
125 start = 3;
126 num = 4;
127 } else if (*dm->band_width == 1) {
128 start = 2;
129 num = 6;
130 } else {
131 start = 0;
132 num = 10;
133 }
134
135 odm_write_4byte(dm, 0x1b00, 0xf8000008);
136 tmp1 = odm_read_4byte(dm, 0x1b1c);
137 odm_write_4byte(dm, 0x1b1c, 0xa2193c32);
138
139 odm_write_4byte(dm, 0x1b00, 0xf800000a);
140 tmp2 = odm_read_4byte(dm, 0x1b1c);
141 odm_write_4byte(dm, 0x1b1c, 0xa2193c32);
142
143 for (path = 0; path < 2; path++) {
144 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
145 switch (xym_type) {
146 case 0:
147 for (i = 0; i < num; i++) {
148 odm_write_4byte(dm, 0x1b14, 0xe6 + start + i);
149 odm_write_4byte(dm, 0x1b14, 0x0);
150 iqk_info->rx_xym[path][i] =
151 odm_read_4byte(dm, 0x1b38);
152 }
153 break;
154 case 1:
155 for (i = 0; i < num; i++) {
156 odm_write_4byte(dm, 0x1b14, 0xe6 + start + i);
157 odm_write_4byte(dm, 0x1b14, 0x0);
158 iqk_info->tx_xym[path][i] =
159 odm_read_4byte(dm, 0x1b38);
160 }
161 break;
162 case 2:
163 for (i = 0; i < 6; i++) {
164 odm_write_4byte(dm, 0x1b14, 0xe0 + i);
165 odm_write_4byte(dm, 0x1b14, 0x0);
166 iqk_info->gs1_xym[path][i] =
167 odm_read_4byte(dm, 0x1b38);
168 }
169 break;
170 case 3:
171 for (i = 0; i < 6; i++) {
172 odm_write_4byte(dm, 0x1b14, 0xe0 + i);
173 odm_write_4byte(dm, 0x1b14, 0x0);
174 iqk_info->gs2_xym[path][i] =
175 odm_read_4byte(dm, 0x1b38);
176 }
177 break;
178 case 4:
179 for (i = 0; i < 6; i++) {
180 odm_write_4byte(dm, 0x1b14, 0xe0 + i);
181 odm_write_4byte(dm, 0x1b14, 0x0);
182 iqk_info->rxk1_xym[path][i] =
183 odm_read_4byte(dm, 0x1b38);
184 }
185 break;
186 }
187 odm_write_4byte(dm, 0x1b38, 0x20000000);
188 odm_write_4byte(dm, 0x1b00, 0xf8000008);
189 odm_write_4byte(dm, 0x1b1c, tmp1);
190 odm_write_4byte(dm, 0x1b00, 0xf800000a);
191 odm_write_4byte(dm, 0x1b1c, tmp2);
192 _iqk_page_switch(dm);
193 }
194 }
195
196 /*xym_type => 0: rx_sym; 1: tx_xym; 2:gs1_xym; 3:gs2_sym; 4: rxk1_xym*/
halrf_iqk_xym_show(struct dm_struct * dm,u8 xym_type)197 void halrf_iqk_xym_show(struct dm_struct *dm, u8 xym_type)
198 {
199 u8 num, path, path_num, i;
200 struct dm_iqk_info *iqk_info = &dm->IQK_info;
201
202 if (dm->rf_type == RF_1T1R)
203 path_num = 0x1;
204 else if (dm->rf_type == RF_2T2R)
205 path_num = 0x2;
206 else
207 path_num = 0x4;
208
209 if (*dm->band_width == CHANNEL_WIDTH_20)
210 num = 4;
211 else if (*dm->band_width == CHANNEL_WIDTH_40)
212 num = 6;
213 else
214 num = 10;
215
216 for (path = 0; path < path_num; path++) {
217 switch (xym_type) {
218 case 0:
219 for (i = 0; i < num; i++)
220 RF_DBG(dm, DBG_RF_IQK,
221 "[IQK]%-20s %-2d: 0x%x\n",
222 (path == 0) ? "PATH A RX-XYM " :
223 "PATH B RX-XYM", i,
224 iqk_info->rx_xym[path][i]);
225 break;
226 case 1:
227 for (i = 0; i < num; i++)
228 RF_DBG(dm, DBG_RF_IQK,
229 "[IQK]%-20s %-2d: 0x%x\n",
230 (path == 0) ? "PATH A TX-XYM " :
231 "PATH B TX-XYM", i,
232 iqk_info->tx_xym[path][i]);
233 break;
234 case 2:
235 for (i = 0; i < 6; i++)
236 RF_DBG(dm, DBG_RF_IQK,
237 "[IQK]%-20s %-2d: 0x%x\n",
238 (path == 0) ? "PATH A GS1-XYM " :
239 "PATH B GS1-XYM", i,
240 iqk_info->gs1_xym[path][i]);
241 break;
242 case 3:
243 for (i = 0; i < 6; i++)
244 RF_DBG(dm, DBG_RF_IQK,
245 "[IQK]%-20s %-2d: 0x%x\n",
246 (path == 0) ? "PATH A GS2-XYM " :
247 "PATH B GS2-XYM", i,
248 iqk_info->gs2_xym[path][i]);
249 break;
250 case 4:
251 for (i = 0; i < 6; i++)
252 RF_DBG(dm, DBG_RF_IQK,
253 "[IQK]%-20s %-2d: 0x%x\n",
254 (path == 0) ? "PATH A RXK1-XYM " :
255 "PATH B RXK1-XYM", i,
256 iqk_info->rxk1_xym[path][i]);
257 break;
258 }
259 }
260 }
261
halrf_iqk_xym_dump(void * dm_void)262 void halrf_iqk_xym_dump(void *dm_void)
263 {
264 u32 tmp1, tmp2;
265 struct dm_struct *dm = (struct dm_struct *)dm_void;
266
267 odm_write_4byte(dm, 0x1b00, 0xf8000008);
268 tmp1 = odm_read_4byte(dm, 0x1b1c);
269 odm_write_4byte(dm, 0x1b00, 0xf800000a);
270 tmp2 = odm_read_4byte(dm, 0x1b1c);
271 #if 0
272 /*halrf_iqk_xym_read(dm, xym_type);*/
273 #endif
274 odm_write_4byte(dm, 0x1b00, 0xf8000008);
275 odm_write_4byte(dm, 0x1b1c, tmp1);
276 odm_write_4byte(dm, 0x1b00, 0xf800000a);
277 odm_write_4byte(dm, 0x1b1c, tmp2);
278 _iqk_page_switch(dm);
279 }
280 #endif
halrf_iqk_info_dump(void * dm_void,u32 * _used,char * output,u32 * _out_len)281 void halrf_iqk_info_dump(void *dm_void, u32 *_used, char *output, u32 *_out_len)
282 {
283 struct dm_struct *dm = (struct dm_struct *)dm_void;
284 u32 used = *_used;
285 u32 out_len = *_out_len;
286 u8 rf_path, j, reload_iqk = 0;
287 u32 tmp;
288 /*two channel, PATH, TX/RX, 0:pass 1 :fail*/
289 boolean iqk_result[2][NUM][2];
290 struct dm_iqk_info *iqk_info = &dm->IQK_info;
291
292 if (!(dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)))
293 return;
294
295 /* IQK INFO */
296 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s\n",
297 "% IQK Info %");
298 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s\n",
299 (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW-IQK" :
300 "Driver-IQK");
301
302 reload_iqk = (u8)odm_get_bb_reg(dm, R_0x1bf0, BIT(16));
303 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
304 "reload", (reload_iqk) ? "True" : "False");
305
306 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
307 "rfk_forbidden", (iqk_info->rfk_forbidden) ? "True" : "False");
308 #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
309 RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
310 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
311 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
312 "segment_iqk", (iqk_info->segment_iqk) ? "True" : "False");
313 #endif
314
315 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s:%d %d\n",
316 "iqk count / fail count", dm->n_iqk_cnt, dm->n_iqk_fail_cnt);
317
318 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %d\n",
319 "channel", *dm->channel);
320
321 if (*dm->band_width == CHANNEL_WIDTH_20)
322 PDM_SNPF(out_len, used, output + used, out_len - used,
323 "%-20s: %s\n", "bandwidth", "BW_20");
324 else if (*dm->band_width == CHANNEL_WIDTH_40)
325 PDM_SNPF(out_len, used, output + used, out_len - used,
326 "%-20s: %s\n", "bandwidth", "BW_40");
327 else if (*dm->band_width == CHANNEL_WIDTH_80)
328 PDM_SNPF(out_len, used, output + used, out_len - used,
329 "%-20s: %s\n", "bandwidth", "BW_80");
330 else if (*dm->band_width == CHANNEL_WIDTH_160)
331 PDM_SNPF(out_len, used, output + used, out_len - used,
332 "%-20s: %s\n", "bandwidth", "BW_160");
333 else if (*dm->band_width == CHANNEL_WIDTH_80_80)
334 PDM_SNPF(out_len, used, output + used, out_len - used,
335 "%-20s: %s\n", "bandwidth", "BW_80_80");
336 else
337 PDM_SNPF(out_len, used, output + used, out_len - used,
338 "%-20s: %s\n", "bandwidth", "BW_UNKNOWN");
339
340 PDM_SNPF(out_len, used, output + used, out_len - used,
341 "%-20s: %llu %s\n", "progressing_time",
342 dm->rf_calibrate_info.iqk_total_progressing_time, "(ms)");
343
344 tmp = odm_read_4byte(dm, 0x1bf0);
345 for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++)
346 for (j = 0; j < 2; j++)
347 iqk_result[0][rf_path][j] = (boolean)
348 (tmp & (BIT(rf_path + (j * 4)) >> (rf_path + (j * 4))));
349
350 PDM_SNPF(out_len, used, output + used, out_len - used,
351 "%-20s: 0x%08x\n", "Reg0x1bf0", tmp);
352 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
353 "PATH_A-Tx result",
354 (iqk_result[0][RF_PATH_A][0]) ? "Fail" : "Pass");
355 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
356 "PATH_A-Rx result",
357 (iqk_result[0][RF_PATH_A][1]) ? "Fail" : "Pass");
358 #if (RTL8822B_SUPPORT == 1)
359 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
360 "PATH_B-Tx result",
361 (iqk_result[0][RF_PATH_B][0]) ? "Fail" : "Pass");
362 PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
363 "PATH_B-Rx result",
364 (iqk_result[0][RF_PATH_B][1]) ? "Fail" : "Pass");
365 #endif
366 *_used = used;
367 *_out_len = out_len;
368 }
369
halrf_get_fw_version(void * dm_void)370 void halrf_get_fw_version(void *dm_void)
371 {
372 struct dm_struct *dm = (struct dm_struct *)dm_void;
373 struct _hal_rf_ *rf = &dm->rf_table;
374
375 rf->fw_ver = (dm->fw_version << 16) | dm->fw_sub_version;
376 }
377
halrf_iqk_dbg(void * dm_void)378 void halrf_iqk_dbg(void *dm_void)
379 {
380 struct dm_struct *dm = (struct dm_struct *)dm_void;
381 u8 rf_path, j;
382 u32 tmp;
383 /*two channel, PATH, TX/RX, 0:pass 1 :fail*/
384 boolean iqk_result[2][NUM][2];
385 struct dm_iqk_info *iqk_info = &dm->IQK_info;
386 struct _hal_rf_ *rf = &dm->rf_table;
387
388 /* IQK INFO */
389 RF_DBG(dm, DBG_RF_IQK, "%-20s\n", "====== IQK Info ======");
390
391 RF_DBG(dm, DBG_RF_IQK, "%-20s\n",
392 (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW-IQK" :
393 "Driver-IQK");
394
395 if (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) {
396 halrf_get_fw_version(dm);
397 RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%x\n", "FW_VER", rf->fw_ver);
398 } else {
399 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "IQK_VER", HALRF_IQK_VER);
400 }
401
402 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "reload",
403 (iqk_info->is_reload) ? "True" : "False");
404
405 RF_DBG(dm, DBG_RF_IQK, "%-20s: %d %d\n", "iqk count / fail count",
406 dm->n_iqk_cnt, dm->n_iqk_fail_cnt);
407
408 RF_DBG(dm, DBG_RF_IQK, "%-20s: %d\n", "channel", *dm->channel);
409
410 if (*dm->band_width == CHANNEL_WIDTH_20)
411 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_20");
412 else if (*dm->band_width == CHANNEL_WIDTH_40)
413 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_40");
414 else if (*dm->band_width == CHANNEL_WIDTH_80)
415 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_80");
416 else if (*dm->band_width == CHANNEL_WIDTH_160)
417 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_160");
418 else if (*dm->band_width == CHANNEL_WIDTH_80_80)
419 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_80_80");
420 else
421 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth",
422 "BW_UNKNOWN");
423 #if 0
424 /*
425 * RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n",
426 * "progressing_time",
427 * dm->rf_calibrate_info.iqk_total_progressing_time, "(ms)");
428 */
429 #endif
430 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "rfk_forbidden",
431 (iqk_info->rfk_forbidden) ? "True" : "False");
432 #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
433 RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
434 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
435 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "segment_iqk",
436 (iqk_info->segment_iqk) ? "True" : "False");
437 #endif
438
439 RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n", "progressing_time",
440 dm->rf_calibrate_info.iqk_progressing_time, "(ms)");
441
442 tmp = odm_read_4byte(dm, 0x1bf0);
443 for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++)
444 for (j = 0; j < 2; j++)
445 iqk_result[0][rf_path][j] = (boolean)
446 (tmp & (BIT(rf_path + (j * 4)) >> (rf_path + (j * 4))));
447
448 RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%08x\n", "Reg0x1bf0", tmp);
449 RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%08x\n", "Reg0x1be8",
450 odm_read_4byte(dm, 0x1be8));
451 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_A-Tx result",
452 (iqk_result[0][RF_PATH_A][0]) ? "Fail" : "Pass");
453 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_A-Rx result",
454 (iqk_result[0][RF_PATH_A][1]) ? "Fail" : "Pass");
455 #if (RTL8822B_SUPPORT == 1)
456 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_B-Tx result",
457 (iqk_result[0][RF_PATH_B][0]) ? "Fail" : "Pass");
458 RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_B-Rx result",
459 (iqk_result[0][RF_PATH_B][1]) ? "Fail" : "Pass");
460 #endif
461 }
462
halrf_lck_dbg(struct dm_struct * dm)463 void halrf_lck_dbg(struct dm_struct *dm)
464 {
465 RF_DBG(dm, DBG_RF_IQK, "%-20s\n", "====== LCK Info ======");
466 #if 0
467 /*RF_DBG(dm, DBG_RF_IQK, "%-20s\n",
468 * (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "LCK" : "RTK"));
469 */
470 #endif
471 RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n", "progressing_time",
472 dm->rf_calibrate_info.lck_progressing_time, "(ms)");
473 }
phydm_get_iqk_cfir(void * dm_void,u8 idx,u8 path,boolean debug)474 void phydm_get_iqk_cfir(void *dm_void, u8 idx, u8 path, boolean debug)
475 {
476 struct dm_struct *dm = (struct dm_struct *)dm_void;
477
478 switch (dm->support_ic_type) {
479 #if (RTL8822B_SUPPORT == 1)
480 case ODM_RTL8822B:
481 phy_get_iqk_cfir_8822b(dm, idx, path, debug);
482 break;
483 #endif
484 #if (RTL8822C_SUPPORT == 1)
485 case ODM_RTL8822C:
486 phy_get_iqk_cfir_8822c(dm, idx, path, debug);
487 break;
488 #endif
489 #if (RTL8814B_SUPPORT == 1)
490 case ODM_RTL8814B:
491 phy_get_iqk_cfir_8814b(dm, idx, path, debug);
492 break;
493 #endif
494 default:
495 break;
496 }
497 }
498
499
halrf_iqk_dbg_cfir_backup(void * dm_void)500 void halrf_iqk_dbg_cfir_backup(void *dm_void)
501 {
502 struct dm_struct *dm = (struct dm_struct *)dm_void;
503 struct dm_iqk_info *iqk_info = &dm->IQK_info;
504 u8 path, idx, i;
505
506 switch (dm->support_ic_type) {
507 #if (RTL8822B_SUPPORT == 1)
508 case ODM_RTL8822B:
509 phy_iqk_dbg_cfir_backup_8822b(dm);
510 break;
511 #endif
512 #if (RTL8822C_SUPPORT == 1)
513 case ODM_RTL8822C:
514 phy_iqk_dbg_cfir_backup_8822c(dm);
515 break;
516 #endif
517 #if (RTL8814B_SUPPORT == 1)
518 case ODM_RTL8814B:
519 phy_iqk_dbg_cfir_backup_8814b(dm);
520 break;
521 #endif
522 default:
523 break;
524 }
525
526 }
527
halrf_iqk_dbg_cfir_backup_update(void * dm_void)528 void halrf_iqk_dbg_cfir_backup_update(void *dm_void)
529 {
530 struct dm_struct *dm = (struct dm_struct *)dm_void;
531 struct dm_iqk_info *iqk = &dm->IQK_info;
532 u8 i, path, idx;
533 u32 bmask13_12 = BIT(13) | BIT(12);
534 u32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
535 u32 data;
536
537 switch (dm->support_ic_type) {
538 #if (RTL8822B_SUPPORT == 1)
539 case ODM_RTL8822B:
540 phy_iqk_dbg_cfir_backup_update_8822b(dm);
541 break;
542 #endif
543 #if (RTL8822C_SUPPORT == 1)
544 case ODM_RTL8822C:
545 phy_iqk_dbg_cfir_backup_update_8822c(dm);
546 break;
547 #endif
548 default:
549 break;
550 }
551 }
552
halrf_iqk_dbg_cfir_reload(void * dm_void)553 void halrf_iqk_dbg_cfir_reload(void *dm_void)
554 {
555 struct dm_struct *dm = (struct dm_struct *)dm_void;
556 struct dm_iqk_info *iqk = &dm->IQK_info;
557 u8 i, path, idx;
558 u32 bmask13_12 = BIT(13) | BIT(12);
559 u32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
560 u32 data;
561
562 switch (dm->support_ic_type) {
563 #if (RTL8822B_SUPPORT == 1)
564 case ODM_RTL8822B:
565 phy_iqk_dbg_cfir_reload_8822b(dm);
566 break;
567 #endif
568 #if (RTL8822C_SUPPORT == 1)
569 case ODM_RTL8822C:
570 phy_iqk_dbg_cfir_reload_8822c(dm);
571 break;
572 #endif
573 default:
574 break;
575 }
576 }
577
halrf_iqk_dbg_cfir_write(void * dm_void,u8 type,u32 path,u32 idx,u32 i,u32 data)578 void halrf_iqk_dbg_cfir_write(void *dm_void, u8 type, u32 path, u32 idx,
579 u32 i, u32 data)
580 {
581 struct dm_struct *dm = (struct dm_struct *)dm_void;
582 struct dm_iqk_info *iqk_info = &dm->IQK_info;
583
584 switch (dm->support_ic_type) {
585 #if (RTL8822B_SUPPORT == 1)
586 case ODM_RTL8822B:
587 phy_iqk_dbg_cfir_write_8822b(dm, type, path, idx, i, data);
588 break;
589 #endif
590 #if (RTL8822C_SUPPORT == 1)
591 case ODM_RTL8822C:
592 phy_iqk_dbg_cfir_write_8822c(dm, type, path, idx, i, data);
593 break;
594 #endif
595 default:
596 break;
597 }
598 }
599
halrf_iqk_dbg_cfir_backup_show(void * dm_void)600 void halrf_iqk_dbg_cfir_backup_show(void *dm_void)
601 {
602 struct dm_struct *dm = (struct dm_struct *)dm_void;
603 struct dm_iqk_info *iqk_info = &dm->IQK_info;
604 u8 path, idx, i;
605
606 switch (dm->support_ic_type) {
607 #if (RTL8822B_SUPPORT == 1)
608 case ODM_RTL8822B:
609 phy_iqk_dbg_cfir_backup_8822b(dm);
610 break;
611 #endif
612 #if (RTL8822C_SUPPORT == 1)
613 case ODM_RTL8822C:
614 phy_iqk_dbg_cfir_backup_8822c(dm);
615 break;
616 #endif
617 default:
618 break;
619 }
620 }
621
halrf_do_imr_test(void * dm_void,u8 flag_imr_test)622 void halrf_do_imr_test(void *dm_void, u8 flag_imr_test)
623 {
624 struct dm_struct *dm = (struct dm_struct *)dm_void;
625
626 if (flag_imr_test != 0x0)
627 switch (dm->support_ic_type) {
628 #if (RTL8822B_SUPPORT == 1)
629 case ODM_RTL8822B:
630 do_imr_test_8822b(dm);
631 break;
632 #endif
633 #if (RTL8821C_SUPPORT == 1)
634 case ODM_RTL8821C:
635 do_imr_test_8821c(dm);
636 break;
637 #endif
638 default:
639 break;
640 }
641 }
642
643 #if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
halrf_iqk_debug(void * dm_void,u32 * const dm_value,u32 * _used,char * output,u32 * _out_len)644 void halrf_iqk_debug(void *dm_void, u32 *const dm_value, u32 *_used,
645 char *output, u32 *_out_len)
646 {
647 struct dm_struct *dm = (struct dm_struct *)dm_void;
648
649 #if 0
650 /*dm_value[0]=0x0: backup from SRAM & show*/
651 /*dm_value[0]=0x1: write backup CFIR to SRAM*/
652 /*dm_value[0]=0x2: reload default CFIR to SRAM*/
653 /*dm_value[0]=0x3: show backup*/
654 /*dm_value[0]=0x10: write backup CFIR real part*/
655 /*--> dm_value[1]:path, dm_value[2]:tx/rx, dm_value[3]:index, dm_value[4]:data*/
656 /*dm_value[0]=0x11: write backup CFIR imag*/
657 /*--> dm_value[1]:path, dm_value[2]:tx/rx, dm_value[3]:index, dm_value[4]:data*/
658 /*dm_value[0]=0x20 :xym_read enable*/
659 /*--> dm_value[1]:0:disable, 1:enable*/
660 /*if dm_value[0]=0x20 = enable, */
661 /*0x1:show rx_sym; 0x2: tx_xym; 0x3:gs1_xym; 0x4:gs2_sym; 0x5:rxk1_xym*/
662 #endif
663 if (dm_value[0] == 0x0)
664 halrf_iqk_dbg_cfir_backup(dm);
665 else if (dm_value[0] == 0x1)
666 halrf_iqk_dbg_cfir_backup_update(dm);
667 else if (dm_value[0] == 0x2)
668 halrf_iqk_dbg_cfir_reload(dm);
669 else if (dm_value[0] == 0x3)
670 halrf_iqk_dbg_cfir_backup_show(dm);
671 else if (dm_value[0] == 0x10)
672 halrf_iqk_dbg_cfir_write(dm, 0, dm_value[1], dm_value[2],
673 dm_value[3], dm_value[4]);
674 else if (dm_value[0] == 0x11)
675 halrf_iqk_dbg_cfir_write(dm, 1, dm_value[1], dm_value[2],
676 dm_value[3], dm_value[4]);
677 else if (dm_value[0] == 0x20)
678 halrf_iqk_xym_enable(dm, (u8)dm_value[1]);
679 else if (dm_value[0] == 0x21)
680 halrf_iqk_xym_show(dm, (u8)dm_value[1]);
681 else if (dm_value[0] == 0x30)
682 halrf_do_imr_test(dm, (u8)dm_value[1]);
683 }
684 #endif
685
halrf_iqk_hwtx_check(void * dm_void,boolean is_check)686 void halrf_iqk_hwtx_check(void *dm_void, boolean is_check)
687 {
688 #if 0
689 struct dm_struct *dm = (struct dm_struct *)dm_void;
690 struct dm_iqk_info *iqk_info = &dm->IQK_info;
691 u32 tmp_b04;
692
693 if (is_check) {
694 iqk_info->is_hwtx = (boolean)odm_get_bb_reg(dm, R_0xb00, BIT(8));
695 } else {
696 if (iqk_info->is_hwtx) {
697 tmp_b04 = odm_read_4byte(dm, 0xb04);
698 odm_set_bb_reg(dm, R_0xb04, BIT(3) | BIT(2), 0x0);
699 odm_write_4byte(dm, 0xb04, tmp_b04);
700 }
701 }
702 #endif
703 }
704 #endif
705
halrf_match_iqk_version(void * dm_void)706 u8 halrf_match_iqk_version(void *dm_void)
707 {
708 struct dm_struct *dm = (struct dm_struct *)dm_void;
709
710 u32 iqk_version = 0;
711 char temp[10] = {0};
712
713 odm_move_memory(dm, temp, HALRF_IQK_VER, sizeof(temp));
714 PHYDM_SSCANF(temp + 2, DCMD_HEX, &iqk_version);
715
716 if (dm->support_ic_type == ODM_RTL8822B) {
717 if (iqk_version >= 0x24 && (odm_get_hw_img_version(dm) >= 72))
718 return 1;
719 else if ((iqk_version <= 0x23) &&
720 (odm_get_hw_img_version(dm) <= 71))
721 return 1;
722 else
723 return 0;
724 }
725
726 if (dm->support_ic_type == ODM_RTL8821C) {
727 if (iqk_version >= 0x18 && (odm_get_hw_img_version(dm) >= 37))
728 return 1;
729 else
730 return 0;
731 }
732
733 return 1;
734 }
735
halrf_rf_lna_setting(void * dm_void,enum halrf_lna_set type)736 void halrf_rf_lna_setting(void *dm_void, enum halrf_lna_set type)
737 {
738 struct dm_struct *dm = (struct dm_struct *)dm_void;
739
740 switch (dm->support_ic_type) {
741 #if (RTL8188E_SUPPORT == 1)
742 case ODM_RTL8188E:
743 halrf_rf_lna_setting_8188e(dm, type);
744 break;
745 #endif
746 #if (RTL8192E_SUPPORT == 1)
747 case ODM_RTL8192E:
748 halrf_rf_lna_setting_8192e(dm, type);
749 break;
750 #endif
751 #if (RTL8192F_SUPPORT == 1)
752 case ODM_RTL8192F:
753 halrf_rf_lna_setting_8192f(dm, type);
754 break;
755 #endif
756
757 #if (RTL8723B_SUPPORT == 1)
758 case ODM_RTL8723B:
759 halrf_rf_lna_setting_8723b(dm, type);
760 break;
761 #endif
762 #if (RTL8812A_SUPPORT == 1)
763 case ODM_RTL8812:
764 halrf_rf_lna_setting_8812a(dm, type);
765 break;
766 #endif
767 #if ((RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1))
768 case ODM_RTL8881A:
769 case ODM_RTL8821:
770 halrf_rf_lna_setting_8821a(dm, type);
771 break;
772 #endif
773 #if (RTL8822B_SUPPORT == 1)
774 case ODM_RTL8822B:
775 halrf_rf_lna_setting_8822b(dm_void, type);
776 break;
777 #endif
778 #if (RTL8822C_SUPPORT == 1)
779 case ODM_RTL8822C:
780 halrf_rf_lna_setting_8822c(dm_void, type);
781 break;
782 #endif
783 #if (RTL8812F_SUPPORT == 1)
784 case ODM_RTL8812F:
785 halrf_rf_lna_setting_8812f(dm_void, type);
786 break;
787 #endif
788 #if (RTL8821C_SUPPORT == 1)
789 case ODM_RTL8821C:
790 halrf_rf_lna_setting_8821c(dm_void, type);
791 break;
792 #endif
793 #if (RTL8710C_SUPPORT == 1)
794 case ODM_RTL8710C:
795 halrf_rf_lna_setting_8710c(dm_void, type);
796 break;
797 #endif
798 #if (RTL8721D_SUPPORT == 1)
799 case ODM_RTL8721D:
800 halrf_rf_lna_setting_8721d(dm, type);
801 break;
802 #endif
803 #if (RTL8814B_SUPPORT == 1)
804 case ODM_RTL8814B:
805 break;
806 #endif
807 default:
808 break;
809 }
810 }
811
halrf_support_ability_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)812 void halrf_support_ability_debug(void *dm_void, char input[][16], u32 *_used,
813 char *output, u32 *_out_len)
814 {
815 struct dm_struct *dm = (struct dm_struct *)dm_void;
816 struct _hal_rf_ *rf = &dm->rf_table;
817 u32 dm_value[10] = {0};
818 u32 used = *_used;
819 u32 out_len = *_out_len;
820 u8 i;
821
822 for (i = 0; i < 5; i++)
823 if (input[i + 1])
824 PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &dm_value[i]);
825
826 if (dm_value[0] == 100) {
827 PDM_SNPF(out_len, used, output + used, out_len - used,
828 "\n[RF Supportability]\n");
829 PDM_SNPF(out_len, used, output + used, out_len - used,
830 "00. (( %s ))Power Tracking\n",
831 ((rf->rf_supportability & HAL_RF_TX_PWR_TRACK) ?
832 ("V") : (".")));
833 PDM_SNPF(out_len, used, output + used, out_len - used,
834 "01. (( %s ))IQK\n",
835 ((rf->rf_supportability & HAL_RF_IQK) ? ("V") :
836 (".")));
837 PDM_SNPF(out_len, used, output + used, out_len - used,
838 "02. (( %s ))LCK\n",
839 ((rf->rf_supportability & HAL_RF_LCK) ? ("V") :
840 (".")));
841 PDM_SNPF(out_len, used, output + used, out_len - used,
842 "03. (( %s ))DPK\n",
843 ((rf->rf_supportability & HAL_RF_DPK) ? ("V") :
844 (".")));
845 PDM_SNPF(out_len, used, output + used, out_len - used,
846 "04. (( %s ))HAL_RF_TXGAPK\n",
847 ((rf->rf_supportability & HAL_RF_TXGAPK) ? ("V") :
848 (".")));
849 PDM_SNPF(out_len, used, output + used, out_len - used,
850 "05. (( %s ))HAL_RF_DACK\n",
851 ((rf->rf_supportability & HAL_RF_DACK) ? ("V") :
852 (".")));
853 PDM_SNPF(out_len, used, output + used, out_len - used,
854 "06. (( %s ))DPK_TRACK\n",
855 ((rf->rf_supportability & HAL_RF_DPK_TRACK) ? ("V") :
856 (".")));
857 #ifdef CONFIG_2G_BAND_SHIFT
858 PDM_SNPF(out_len, used, output + used, out_len - used,
859 "07. (( %s ))HAL_2GBAND_SHIFT\n",
860 ((rf->rf_supportability & HAL_2GBAND_SHIFT) ? ("V") :
861 (".")));
862 #endif
863 PDM_SNPF(out_len, used, output + used, out_len - used,
864 "08. (( %s ))HAL_RF_RXDCK\n",
865 ((rf->rf_supportability & HAL_RF_RXDCK) ? ("V") :
866 (".")));
867
868 } else {
869 if (dm_value[1] == 1) /* enable */
870 rf->rf_supportability |= BIT(dm_value[0]);
871 else if (dm_value[1] == 2) /* disable */
872 rf->rf_supportability &= ~(BIT(dm_value[0]));
873 else
874 PDM_SNPF(out_len, used, output + used, out_len - used,
875 "[Warning!!!] 1:enable, 2:disable\n");
876 }
877 PDM_SNPF(out_len, used, output + used, out_len - used,
878 "\nCurr-RF_supportability = 0x%x\n\n", rf->rf_supportability);
879
880 *_used = used;
881 *_out_len = out_len;
882 }
883
884 #ifdef CONFIG_2G_BAND_SHIFT
halrf_support_band_shift_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)885 void halrf_support_band_shift_debug(void *dm_void, char input[][16], u32 *_used,
886 char *output, u32 *_out_len)
887 {
888 struct dm_struct *dm = (struct dm_struct *)dm_void;
889 struct _hal_rf_ *rf = &dm->rf_table;
890 //u32 band_value[2] = {00};
891 u32 dm_value[10] = {0};
892 u32 used = *_used;
893 u32 out_len = *_out_len;
894 u8 i;
895
896 #if (RTL8192F_SUPPORT == 1)
897 for (i = 0; i < 7; i++)
898 if (input[i + 1])
899 PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &dm_value[i]);
900
901 if (!(rf->rf_supportability & HAL_2GBAND_SHIFT)) {
902 PDM_SNPF(out_len, used, output + used, out_len - used,
903 "\nCurr-RF_supportability[07. (( . ))HAL_2GBAND_SHIFT]\nNo RF Band Shift,default: 2.4G!\n");
904 } else {
905 if (dm_value[0] == 01) {
906 rf->rf_shift_band = HAL_RF_2P3;
907 halrf_lck_trigger(dm);
908 PDM_SNPF(out_len, used, output + used, out_len - used,
909 "\n[rf_shift_band] = %d\nRF Band Shift to 2.3G!\n",
910 rf->rf_shift_band);
911 } else if (dm_value[0] == 02) {
912 rf->rf_shift_band = HAL_RF_2P5;
913 halrf_lck_trigger(dm);
914 PDM_SNPF(out_len, used, output + used, out_len - used,
915 "\n[rf_shift_band] = %d\nRF Band Shift to 2.5G!\n",
916 rf->rf_shift_band);
917 } else {
918 rf->rf_shift_band = HAL_RF_2P4;
919 halrf_lck_trigger(dm);
920 PDM_SNPF(out_len, used, output + used, out_len - used,
921 "\n[rf_shift_band] = %d\nNo RF Band Shift,default: 2.4G!\n",
922 rf->rf_shift_band);
923 }
924 }
925 *_used = used;
926 *_out_len = out_len;
927 #endif
928 }
929 #endif
930
halrf_cmn_info_init(void * dm_void,enum halrf_cmninfo_init cmn_info,u32 value)931 void halrf_cmn_info_init(void *dm_void, enum halrf_cmninfo_init cmn_info,
932 u32 value)
933 {
934 struct dm_struct *dm = (struct dm_struct *)dm_void;
935 struct _hal_rf_ *rf = &dm->rf_table;
936
937 switch (cmn_info) {
938 case HALRF_CMNINFO_EEPROM_THERMAL_VALUE:
939 rf->eeprom_thermal = (u8)value;
940 break;
941 case HALRF_CMNINFO_PWT_TYPE:
942 rf->pwt_type = (u8)value;
943 break;
944 case HALRF_CMNINFO_MP_POWER_TRACKING_TYPE:
945 rf->mp_pwt_type = (u8)value;
946 break;
947 default:
948 break;
949 }
950 }
951
halrf_cmn_info_hook(void * dm_void,enum halrf_cmninfo_hook cmn_info,void * value)952 void halrf_cmn_info_hook(void *dm_void, enum halrf_cmninfo_hook cmn_info,
953 void *value)
954 {
955 struct dm_struct *dm = (struct dm_struct *)dm_void;
956 struct _hal_rf_ *rf = &dm->rf_table;
957
958 switch (cmn_info) {
959 case HALRF_CMNINFO_CON_TX:
960 rf->is_con_tx = (boolean *)value;
961 break;
962 case HALRF_CMNINFO_SINGLE_TONE:
963 rf->is_single_tone = (boolean *)value;
964 break;
965 case HALRF_CMNINFO_CARRIER_SUPPRESSION:
966 rf->is_carrier_suppresion = (boolean *)value;
967 break;
968 case HALRF_CMNINFO_MP_RATE_INDEX:
969 rf->mp_rate_index = (u8 *)value;
970 break;
971 case HALRF_CMNINFO_MANUAL_RF_SUPPORTABILITY:
972 rf->manual_rf_supportability = (u32 *)value;
973 break;
974 default:
975 /*do nothing*/
976 break;
977 }
978 }
979
halrf_cmn_info_set(void * dm_void,u32 cmn_info,u64 value)980 void halrf_cmn_info_set(void *dm_void, u32 cmn_info, u64 value)
981 {
982 /* This init variable may be changed in run time. */
983 struct dm_struct *dm = (struct dm_struct *)dm_void;
984 struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
985 struct _hal_rf_ *rf = &dm->rf_table;
986
987 switch (cmn_info) {
988 case HALRF_CMNINFO_ABILITY:
989 rf->rf_supportability = (u32)value;
990 break;
991
992 case HALRF_CMNINFO_DPK_EN:
993 rf->dpk_en = (u8)value;
994 break;
995 case HALRF_CMNINFO_RFK_FORBIDDEN:
996 dm->IQK_info.rfk_forbidden = (boolean)value;
997 break;
998 #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
999 RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
1000 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
1001 case HALRF_CMNINFO_IQK_SEGMENT:
1002 dm->IQK_info.segment_iqk = (boolean)value;
1003 break;
1004 #endif
1005 case HALRF_CMNINFO_RATE_INDEX:
1006 rf->p_rate_index = (u32)value;
1007 break;
1008 #if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
1009 case HALRF_CMNINFO_MP_PSD_POINT:
1010 rf->halrf_psd_data.point = (u32)value;
1011 break;
1012 case HALRF_CMNINFO_MP_PSD_START_POINT:
1013 rf->halrf_psd_data.start_point = (u32)value;
1014 break;
1015 case HALRF_CMNINFO_MP_PSD_STOP_POINT:
1016 rf->halrf_psd_data.stop_point = (u32)value;
1017 break;
1018 case HALRF_CMNINFO_MP_PSD_AVERAGE:
1019 rf->halrf_psd_data.average = (u32)value;
1020 break;
1021 #endif
1022 case HALRF_CMNINFO_POWER_TRACK_CONTROL:
1023 cali_info->txpowertrack_control = (u8)value;
1024 break;
1025 default:
1026 /* do nothing */
1027 break;
1028 }
1029 }
1030
halrf_cmn_info_get(void * dm_void,u32 cmn_info)1031 u64 halrf_cmn_info_get(void *dm_void, u32 cmn_info)
1032 {
1033 /* This init variable may be changed in run time. */
1034 struct dm_struct *dm = (struct dm_struct *)dm_void;
1035 struct _hal_rf_ *rf = &dm->rf_table;
1036 u64 return_value = 0;
1037
1038 switch (cmn_info) {
1039 case HALRF_CMNINFO_ABILITY:
1040 return_value = (u32)rf->rf_supportability;
1041 break;
1042 case HALRF_CMNINFO_RFK_FORBIDDEN:
1043 return_value = dm->IQK_info.rfk_forbidden;
1044 break;
1045 #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
1046 RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
1047 RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
1048 case HALRF_CMNINFO_IQK_SEGMENT:
1049 return_value = dm->IQK_info.segment_iqk;
1050 break;
1051 case HALRF_CMNINFO_IQK_TIMES:
1052 return_value = dm->IQK_info.iqk_times;
1053 break;
1054 #endif
1055 default:
1056 /* do nothing */
1057 break;
1058 }
1059
1060 return return_value;
1061 }
1062
halrf_supportability_init_mp(void * dm_void)1063 void halrf_supportability_init_mp(void *dm_void)
1064 {
1065 struct dm_struct *dm = (struct dm_struct *)dm_void;
1066 struct _hal_rf_ *rf = &dm->rf_table;
1067
1068 switch (dm->support_ic_type) {
1069 case ODM_RTL8814B:
1070 #if (RTL8814B_SUPPORT == 1)
1071 rf->rf_supportability =
1072 /*HAL_RF_TX_PWR_TRACK |*/
1073 HAL_RF_IQK |
1074 HAL_RF_LCK |
1075 HAL_RF_DPK |
1076 HAL_RF_DACK |
1077 /*HAL_RF_TXGAPK |*/
1078 HAL_RF_DPK_TRACK |
1079 0;
1080 #endif
1081 break;
1082 #if (RTL8822B_SUPPORT == 1)
1083 case ODM_RTL8822B:
1084 rf->rf_supportability =
1085 /*HAL_RF_TX_PWR_TRACK |*/
1086 HAL_RF_IQK |
1087 HAL_RF_LCK |
1088 /*@HAL_RF_DPK |*/
1089 0;
1090 break;
1091 #endif
1092 #if (RTL8822C_SUPPORT == 1)
1093 case ODM_RTL8822C:
1094 rf->rf_supportability =
1095 /*HAL_RF_TX_PWR_TRACK |*/
1096 HAL_RF_IQK |
1097 HAL_RF_LCK |
1098 HAL_RF_DPK |
1099 HAL_RF_DACK |
1100 HAL_RF_DPK_TRACK |
1101 HAL_RF_RXDCK |
1102 HAL_RF_TXGAPK |
1103 0;
1104 break;
1105 #endif
1106 #if (RTL8821C_SUPPORT == 1)
1107 case ODM_RTL8821C:
1108 rf->rf_supportability =
1109 /*HAL_RF_TX_PWR_TRACK |*/
1110 HAL_RF_IQK |
1111 HAL_RF_LCK |
1112 /*@HAL_RF_DPK |*/
1113 /*@HAL_RF_TXGAPK |*/
1114 0;
1115 break;
1116 #endif
1117 #if (RTL8195B_SUPPORT == 1)
1118 case ODM_RTL8195B:
1119 rf->rf_supportability =
1120 /*HAL_RF_TX_PWR_TRACK |*/
1121 HAL_RF_IQK |
1122 HAL_RF_LCK |
1123 HAL_RF_DPK |
1124 /*HAL_RF_TXGAPK |*/
1125 HAL_RF_DPK_TRACK |
1126 0;
1127 break;
1128 #endif
1129 #if (RTL8812F_SUPPORT == 1)
1130 case ODM_RTL8812F:
1131 rf->rf_supportability =
1132 /*HAL_RF_TX_PWR_TRACK |*/
1133 HAL_RF_IQK |
1134 HAL_RF_LCK |
1135 HAL_RF_DPK |
1136 HAL_RF_DACK |
1137 HAL_RF_DPK_TRACK |
1138 0;
1139 break;
1140 #endif
1141
1142 #if (RTL8198F_SUPPORT == 1)
1143 case ODM_RTL8198F:
1144 rf->rf_supportability =
1145 /*HAL_RF_TX_PWR_TRACK |*/
1146 HAL_RF_IQK |
1147 HAL_RF_LCK |
1148 HAL_RF_DPK |
1149 /*@HAL_RF_TXGAPK |*/
1150 0;
1151 break;
1152 #endif
1153
1154 #if (RTL8192F_SUPPORT == 1)
1155 case ODM_RTL8192F:
1156 rf->rf_supportability =
1157 /*HAL_RF_TX_PWR_TRACK |*/
1158 HAL_RF_IQK |
1159 HAL_RF_LCK |
1160 HAL_RF_DPK |
1161 /*@HAL_RF_TXGAPK |*/
1162 #ifdef CONFIG_2G_BAND_SHIFT
1163 /*@HAL_2GBAND_SHIFT |*/
1164 #endif
1165 0;
1166 break;
1167 #endif
1168
1169 #if (RTL8197F_SUPPORT == 1)
1170 case ODM_RTL8197F:
1171 rf->rf_supportability =
1172 /*HAL_RF_TX_PWR_TRACK |*/
1173 HAL_RF_IQK |
1174 HAL_RF_LCK |
1175 HAL_RF_DPK |
1176 /*@HAL_RF_TXGAPK |*/
1177 0;
1178 break;
1179 #endif
1180 #if (RTL8197G_SUPPORT == 1)
1181 case ODM_RTL8197G:
1182 rf->rf_supportability =
1183 /*HAL_RF_TX_PWR_TRACK |*/
1184 HAL_RF_IQK |
1185 /*HAL_RF_LCK |*/
1186 HAL_RF_DPK |
1187 /*@HAL_RF_TXGAPK |*/
1188 HAL_RF_DPK_TRACK |
1189 0;
1190 break;
1191 #endif
1192 #if (RTL8721D_SUPPORT == 1)
1193 case ODM_RTL8721D:
1194 rf->rf_supportability =
1195 HAL_RF_TX_PWR_TRACK |
1196 HAL_RF_IQK |
1197 HAL_RF_LCK |
1198 HAL_RF_DPK |
1199 HAL_RF_DPK_TRACK |
1200 /*@HAL_RF_TXGAPK |*/
1201 0;
1202 break;
1203 #endif
1204
1205 default:
1206 rf->rf_supportability =
1207 /*HAL_RF_TX_PWR_TRACK |*/
1208 HAL_RF_IQK |
1209 HAL_RF_LCK |
1210 /*@HAL_RF_DPK |*/
1211 /*@HAL_RF_TXGAPK |*/
1212 0;
1213 break;
1214 }
1215
1216 RF_DBG(dm, DBG_RF_INIT,
1217 "IC = ((0x%x)), RF_Supportability Init MP = ((0x%x))\n",
1218 dm->support_ic_type, rf->rf_supportability);
1219 }
1220
halrf_supportability_init(void * dm_void)1221 void halrf_supportability_init(void *dm_void)
1222 {
1223 struct dm_struct *dm = (struct dm_struct *)dm_void;
1224 struct _hal_rf_ *rf = &dm->rf_table;
1225
1226 switch (dm->support_ic_type) {
1227 case ODM_RTL8814B:
1228 #if (RTL8814B_SUPPORT == 1)
1229 rf->rf_supportability =
1230 HAL_RF_TX_PWR_TRACK |
1231 HAL_RF_IQK |
1232 HAL_RF_LCK |
1233 HAL_RF_DPK |
1234 HAL_RF_DACK |
1235 HAL_RF_DPK_TRACK |
1236 0;
1237 #endif
1238 break;
1239 #if (RTL8822B_SUPPORT == 1)
1240 case ODM_RTL8822B:
1241 rf->rf_supportability =
1242 HAL_RF_TX_PWR_TRACK |
1243 HAL_RF_IQK |
1244 HAL_RF_LCK |
1245 /*@HAL_RF_DPK |*/
1246 0;
1247 break;
1248 #endif
1249 #if (RTL8822C_SUPPORT == 1)
1250 case ODM_RTL8822C:
1251 rf->rf_supportability =
1252 HAL_RF_TX_PWR_TRACK |
1253 HAL_RF_IQK |
1254 HAL_RF_LCK |
1255 HAL_RF_DPK |
1256 HAL_RF_DACK |
1257 HAL_RF_DPK_TRACK |
1258 HAL_RF_RXDCK |
1259 HAL_RF_TXGAPK |
1260 0;
1261 break;
1262 #endif
1263 #if (RTL8821C_SUPPORT == 1)
1264 case ODM_RTL8821C:
1265 rf->rf_supportability =
1266 HAL_RF_TX_PWR_TRACK |
1267 HAL_RF_IQK |
1268 HAL_RF_LCK |
1269 /*@HAL_RF_DPK |*/
1270 /*@HAL_RF_TXGAPK |*/
1271 0;
1272 break;
1273 #endif
1274 #if (RTL8195B_SUPPORT == 1)
1275 case ODM_RTL8195B:
1276 rf->rf_supportability =
1277 HAL_RF_TX_PWR_TRACK |
1278 HAL_RF_IQK |
1279 HAL_RF_LCK |
1280 HAL_RF_DPK |
1281 /*HAL_RF_TXGAPK |*/
1282 HAL_RF_DPK_TRACK |
1283 0;
1284 break;
1285 #endif
1286 #if (RTL8812F_SUPPORT == 1)
1287 case ODM_RTL8812F:
1288 rf->rf_supportability =
1289 HAL_RF_TX_PWR_TRACK |
1290 HAL_RF_IQK |
1291 HAL_RF_LCK |
1292 HAL_RF_DPK |
1293 HAL_RF_DACK |
1294 HAL_RF_DPK_TRACK |
1295 0;
1296 break;
1297 #endif
1298
1299 #if (RTL8198F_SUPPORT == 1)
1300 case ODM_RTL8198F:
1301 rf->rf_supportability =
1302 HAL_RF_TX_PWR_TRACK |
1303 HAL_RF_IQK |
1304 HAL_RF_LCK |
1305 HAL_RF_DPK |
1306 /*@HAL_RF_TXGAPK |*/
1307 0;
1308 break;
1309 #endif
1310
1311 #if (RTL8192F_SUPPORT == 1)
1312 case ODM_RTL8192F:
1313 rf->rf_supportability =
1314 HAL_RF_TX_PWR_TRACK |
1315 HAL_RF_IQK |
1316 HAL_RF_LCK |
1317 HAL_RF_DPK |
1318 /*@HAL_RF_TXGAPK |*/
1319 #ifdef CONFIG_2G_BAND_SHIFT
1320 /*@HAL_2GBAND_SHIFT |*/
1321 #endif
1322 0;
1323 break;
1324 #endif
1325
1326 #if (RTL8197F_SUPPORT == 1)
1327 case ODM_RTL8197F:
1328 rf->rf_supportability =
1329 HAL_RF_TX_PWR_TRACK |
1330 HAL_RF_IQK |
1331 HAL_RF_LCK |
1332 HAL_RF_DPK |
1333 /*@HAL_RF_TXGAPK |*/
1334 0;
1335 break;
1336 #endif
1337 #if (RTL8197G_SUPPORT == 1)
1338 case ODM_RTL8197G:
1339 rf->rf_supportability =
1340 HAL_RF_TX_PWR_TRACK |
1341 HAL_RF_IQK |
1342 /*HAL_RF_LCK |*/
1343 HAL_RF_DPK |
1344 /*@HAL_RF_TXGAPK |*/
1345 HAL_RF_DPK_TRACK |
1346 #ifdef CONFIG_2G_BAND_SHIFT
1347 HAL_2GBAND_SHIFT |
1348 #endif
1349 0;
1350 break;
1351 #endif
1352 #if (RTL8721D_SUPPORT == 1)
1353 case ODM_RTL8721D:
1354 rf->rf_supportability =
1355 HAL_RF_TX_PWR_TRACK |
1356 HAL_RF_IQK |
1357 HAL_RF_LCK |
1358 HAL_RF_DPK |
1359 HAL_RF_DPK_TRACK |
1360 /*@HAL_RF_TXGAPK |*/
1361 0;
1362 break;
1363 #endif
1364
1365 default:
1366 rf->rf_supportability =
1367 HAL_RF_TX_PWR_TRACK |
1368 HAL_RF_IQK |
1369 HAL_RF_LCK |
1370 /*@HAL_RF_DPK |*/
1371 0;
1372 break;
1373 }
1374
1375 RF_DBG(dm, DBG_RF_INIT,
1376 "IC = ((0x%x)), RF_Supportability Init = ((0x%x))\n",
1377 dm->support_ic_type, rf->rf_supportability);
1378 }
1379
halrf_watchdog(void * dm_void)1380 void halrf_watchdog(void *dm_void)
1381 {
1382 struct dm_struct *dm = (struct dm_struct *)dm_void;
1383 struct _hal_rf_ *rf = &dm->rf_table;
1384 #if 0
1385 /*RF_DBG(dm, DBG_RF_TMP, "%s\n", __func__);*/
1386 #endif
1387
1388 if (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||
1389 rf->is_tssi_in_progress)
1390 return;
1391
1392 phydm_rf_watchdog(dm);
1393 halrf_dpk_track(dm);
1394 }
1395
1396 #if 0
1397 void
1398 halrf_iqk_init(
1399 void *dm_void
1400 )
1401 {
1402 struct dm_struct *dm = (struct dm_struct *)dm_void;
1403 struct _hal_rf_ *rf = &dm->rf_table;
1404
1405 switch (dm->support_ic_type) {
1406 #if (RTL8814B_SUPPORT == 1)
1407 case ODM_RTL8814B:
1408 break;
1409 #endif
1410 #if (RTL8822B_SUPPORT == 1)
1411 case ODM_RTL8822B:
1412 _iq_calibrate_8822b_init(dm);
1413 break;
1414 #endif
1415 #if (RTL8822C_SUPPORT == 1)
1416 case ODM_RTL8822C:
1417 _iq_calibrate_8822c_init(dm);
1418 break;
1419 #endif
1420 #if (RTL8821C_SUPPORT == 1)
1421 case ODM_RTL8821C:
1422 break;
1423 #endif
1424
1425 default:
1426 break;
1427 }
1428 }
1429 #endif
1430
halrf_rfk_power_save(void * dm_void,boolean is_power_save)1431 void halrf_rfk_power_save(void *dm_void, boolean is_power_save)
1432 {
1433 struct dm_struct *dm = (struct dm_struct *)dm_void;
1434 struct dm_iqk_info *iqk_info = &dm->IQK_info;
1435
1436 switch (dm->support_ic_type) {
1437 #if (RTL8822C_SUPPORT == 1)
1438 case ODM_RTL8822C:
1439 halrf_rfk_power_save_8822c(dm, is_power_save);
1440 break;
1441 #endif
1442 default:
1443 break;
1444 }
1445 }
1446
1447
1448
halrf_reload_iqk(void * dm_void,boolean reset)1449 void halrf_reload_iqk(void *dm_void, boolean reset)
1450 {
1451 struct dm_struct *dm = (struct dm_struct *)dm_void;
1452 struct dm_iqk_info *iqk_info = &dm->IQK_info;
1453 u8 i, ch;
1454 u32 tmp;
1455 u32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
1456
1457 halrf_rfk_power_save(dm, false);
1458 switch (dm->support_ic_type) {
1459 #if (RTL8822C_SUPPORT == 1)
1460 case ODM_RTL8822C:
1461 iqk_reload_iqk_8822c(dm, reset);
1462 break;
1463 #endif
1464 #if (RTL8195B_SUPPORT == 1)
1465 case ODM_RTL8195B:
1466 iqk_reload_iqk_8195b(dm, reset);
1467 break;
1468 #endif
1469
1470 default:
1471 break;
1472 }
1473 halrf_rfk_power_save(dm, true);
1474 }
1475
halrf_rfk_handshake(void * dm_void,boolean is_before_k)1476 void halrf_rfk_handshake(void *dm_void, boolean is_before_k)
1477 {
1478 struct dm_struct *dm = (struct dm_struct *)dm_void;
1479
1480 if (!dm->mp_mode)
1481 return;
1482
1483 if (*dm->mp_mode)
1484 return;
1485
1486 switch (dm->support_ic_type) {
1487 #if (RTL8822C_SUPPORT == 1)
1488 case ODM_RTL8822C:
1489 halrf_rfk_handshake_8822c(dm, is_before_k);
1490 break;
1491 #endif
1492 #if (RTL8710C_SUPPORT == 1)
1493 case ODM_RTL8710C:
1494 halrf_rfk_handshake_8710c(dm, is_before_k);
1495 break;
1496 #endif
1497 default:
1498 break;
1499 }
1500 }
1501
halrf_bbreset(void * dm_void)1502 void halrf_bbreset(void *dm_void)
1503 {
1504 struct dm_struct *dm = (struct dm_struct *)dm_void;
1505
1506
1507 switch (dm->support_ic_type) {
1508 #if (RTL8814B_SUPPORT == 1)
1509 case ODM_RTL8814B:
1510 phydm_bb_reset_8814b(dm);
1511 break;
1512 #endif
1513 default:
1514 break;
1515 }
1516 }
1517
halrf_rf_k_connect_trigger(void * dm_void,boolean is_recovery,enum halrf_k_segment_time seg_time)1518 void halrf_rf_k_connect_trigger(void *dm_void, boolean is_recovery,
1519 enum halrf_k_segment_time seg_time)
1520 {
1521 struct dm_struct *dm = (struct dm_struct *)dm_void;
1522 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1523 struct _hal_rf_ *rf = &dm->rf_table;
1524
1525 if (!dm->mp_mode)
1526 return;
1527
1528 if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
1529 rf->is_carrier_suppresion) {
1530 if (*dm->mp_mode &
1531 (*rf->is_con_tx || *rf->is_single_tone ||
1532 *rf->is_carrier_suppresion))
1533 return;
1534 }
1535
1536 /*[TX GAP K]*/
1537 halrf_txgapk_trigger(dm);
1538
1539 /*[LOK, IQK]*/
1540 halrf_segment_iqk_trigger(dm, true, seg_time);
1541
1542 /*[TSSI Trk]*/
1543 halrf_tssi_trigger(dm);
1544 /*[DPK]*/
1545 if(dpk_info->is_dpk_by_channel == true)
1546 halrf_dpk_trigger(dm);
1547 else
1548 halrf_dpk_reload(dm);
1549 //ADDA restore to MP_UI setting;
1550 config_halrf_path_adda_setting_trigger(dm);
1551
1552 halrf_bbreset(dm);
1553 }
1554
config_halrf_path_adda_setting_trigger(void * dm_void)1555 void config_halrf_path_adda_setting_trigger(void *dm_void)
1556 {
1557 struct dm_struct *dm = (struct dm_struct *)dm_void;
1558
1559 #if (RTL8814B_SUPPORT == 1)
1560 if (dm->support_ic_type & ODM_RTL8814B)
1561 config_phydm_path_adda_setting_8814b(dm);
1562 #endif
1563
1564 }
1565
halrf_dack_restore(void * dm_void)1566 void halrf_dack_restore(void *dm_void)
1567 {
1568 struct dm_struct *dm = (struct dm_struct *)dm_void;
1569 struct _hal_rf_ *rf = &dm->rf_table;
1570
1571 if (!(rf->rf_supportability & HAL_RF_DACK))
1572 return;
1573 switch (dm->support_ic_type) {
1574 #if (RTL8822C_SUPPORT == 1)
1575 case ODM_RTL8822C:
1576 halrf_dack_restore_8822c(dm);
1577 break;
1578 #endif
1579 default:
1580 break;
1581 }
1582 }
halrf_dack_trigger(void * dm_void,boolean force)1583 void halrf_dack_trigger(void *dm_void, boolean force)
1584 {
1585 struct dm_struct *dm = (struct dm_struct *)dm_void;
1586 struct _hal_rf_ *rf = &dm->rf_table;
1587
1588 u64 start_time;
1589
1590 if (!(rf->rf_supportability & HAL_RF_DACK))
1591 return;
1592
1593 start_time = odm_get_current_time(dm);
1594
1595 switch (dm->support_ic_type) {
1596 #if (RTL8822C_SUPPORT == 1)
1597 case ODM_RTL8822C:
1598 halrf_dac_cal_8822c(dm, force);
1599 break;
1600 #endif
1601 #if (RTL8812F_SUPPORT == 1)
1602 case ODM_RTL8812F:
1603 halrf_dac_cal_8812f(dm);
1604 break;
1605 #endif
1606 #if (RTL8814B_SUPPORT == 1)
1607 case ODM_RTL8814B:
1608 halrf_dac_cal_8814b(dm);
1609 break;
1610 #endif
1611 default:
1612 break;
1613 }
1614 rf->dpk_progressing_time = odm_get_progressing_time(dm, start_time);
1615 RF_DBG(dm, DBG_RF_DACK, "[DACK]DACK progressing_time = %lld ms\n",
1616 rf->dpk_progressing_time);
1617 }
1618
1619
halrf_dack_dbg(void * dm_void)1620 void halrf_dack_dbg(void *dm_void)
1621 {
1622 struct dm_struct *dm = (struct dm_struct *)dm_void;
1623 struct _hal_rf_ *rf = &dm->rf_table;
1624
1625 u64 start_time;
1626
1627 if (!(rf->rf_supportability & HAL_RF_DACK))
1628 return;
1629
1630 switch (dm->support_ic_type) {
1631 #if (RTL8822C_SUPPORT == 1)
1632 case ODM_RTL8822C:
1633 halrf_dack_dbg_8822c(dm);
1634 break;
1635 #endif
1636 default:
1637 break;
1638 }
1639 }
1640
1641
halrf_segment_iqk_trigger(void * dm_void,boolean clear,boolean segment_iqk)1642 void halrf_segment_iqk_trigger(void *dm_void, boolean clear,
1643 boolean segment_iqk)
1644 {
1645 struct dm_struct *dm = (struct dm_struct *)dm_void;
1646 struct dm_iqk_info *iqk_info = &dm->IQK_info;
1647 struct _hal_rf_ *rf = &dm->rf_table;
1648 u64 start_time;
1649
1650 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1651 if (odm_check_power_status(dm) == false)
1652 return;
1653 #endif
1654
1655 if (!dm->mp_mode)
1656 return;
1657
1658 if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
1659 rf->is_carrier_suppresion) {
1660 if (*dm->mp_mode &
1661 (*rf->is_con_tx || *rf->is_single_tone ||
1662 *rf->is_carrier_suppresion))
1663 return;
1664 }
1665
1666 if (!(rf->rf_supportability & HAL_RF_IQK))
1667 return;
1668
1669 #if DISABLE_BB_RF
1670 return;
1671 #endif
1672 if (iqk_info->rfk_forbidden)
1673 return;
1674
1675 halrf_rfk_handshake(dm, true);
1676
1677 if (!dm->rf_calibrate_info.is_iqk_in_progress) {
1678 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
1679 dm->rf_calibrate_info.is_iqk_in_progress = true;
1680 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
1681 start_time = odm_get_current_time(dm);
1682 dm->IQK_info.segment_iqk = segment_iqk;
1683
1684 halrf_rfk_power_save(dm, false);
1685 switch (dm->support_ic_type) {
1686 #if (RTL8822B_SUPPORT == 1)
1687 case ODM_RTL8822B:
1688 phy_iq_calibrate_8822b(dm, clear, segment_iqk);
1689 break;
1690 #endif
1691 #if (RTL8822C_SUPPORT == 1)
1692 case ODM_RTL8822C:
1693 phy_iq_calibrate_8822c(dm, clear, segment_iqk);
1694 break;
1695 #endif
1696 #if (RTL8821C_SUPPORT == 1)
1697 case ODM_RTL8821C:
1698 phy_iq_calibrate_8821c(dm, clear, segment_iqk);
1699 break;
1700 #endif
1701 #if (RTL8814B_SUPPORT == 1)
1702 case ODM_RTL8814B:
1703 phy_iq_calibrate_8814b(dm, clear, segment_iqk);
1704 break;
1705 #endif
1706 #if (RTL8195B_SUPPORT == 1)
1707 case ODM_RTL8195B:
1708 phy_iq_calibrate_8195b(dm, clear, segment_iqk);
1709 break;
1710 #endif
1711 #if (RTL8710C_SUPPORT == 1)
1712 case ODM_RTL8710C:
1713 phy_iq_calibrate_8710c(dm, clear, segment_iqk);
1714 break;
1715 #endif
1716 #if (RTL8198F_SUPPORT == 1)
1717 case ODM_RTL8198F:
1718 phy_iq_calibrate_8198f(dm, clear, segment_iqk);
1719 break;
1720 #endif
1721 #if (RTL8812F_SUPPORT == 1)
1722 case ODM_RTL8812F:
1723 phy_iq_calibrate_8812f(dm, clear, segment_iqk);
1724 break;
1725 #endif
1726 #if (RTL8197G_SUPPORT == 1)
1727 case ODM_RTL8197G:
1728 phy_iq_calibrate_8197g(dm, clear, segment_iqk);
1729 break;
1730 #endif
1731 #if (RTL8188E_SUPPORT == 1)
1732 case ODM_RTL8188E:
1733 phy_iq_calibrate_8188e(dm, false);
1734 break;
1735 #endif
1736 #if (RTL8188F_SUPPORT == 1)
1737 case ODM_RTL8188F:
1738 phy_iq_calibrate_8188f(dm, false);
1739 break;
1740 #endif
1741 #if (RTL8192E_SUPPORT == 1)
1742 case ODM_RTL8192E:
1743 phy_iq_calibrate_8192e(dm, false);
1744 break;
1745 #endif
1746 #if (RTL8197F_SUPPORT == 1)
1747 case ODM_RTL8197F:
1748 phy_iq_calibrate_8197f(dm, false);
1749 break;
1750 #endif
1751 #if (RTL8192F_SUPPORT == 1)
1752 case ODM_RTL8192F:
1753 phy_iq_calibrate_8192f(dm, false);
1754 break;
1755 #endif
1756 #if (RTL8703B_SUPPORT == 1)
1757 case ODM_RTL8703B:
1758 phy_iq_calibrate_8703b(dm, false);
1759 break;
1760 #endif
1761 #if (RTL8710B_SUPPORT == 1)
1762 case ODM_RTL8710B:
1763 phy_iq_calibrate_8710b(dm, false);
1764 break;
1765 #endif
1766 #if (RTL8723B_SUPPORT == 1)
1767 case ODM_RTL8723B:
1768 phy_iq_calibrate_8723b(dm, false);
1769 break;
1770 #endif
1771 #if (RTL8723D_SUPPORT == 1)
1772 case ODM_RTL8723D:
1773 phy_iq_calibrate_8723d(dm, false);
1774 break;
1775 #endif
1776 #if (RTL8721D_SUPPORT == 1)
1777 case ODM_RTL8721D:
1778 phy_iq_calibrate_8721d(dm, false);
1779 break;
1780 #endif
1781 #if (RTL8812A_SUPPORT == 1)
1782 case ODM_RTL8812:
1783 phy_iq_calibrate_8812a(dm, false);
1784 break;
1785 #endif
1786 #if (RTL8821A_SUPPORT == 1)
1787 case ODM_RTL8821:
1788 phy_iq_calibrate_8821a(dm, false);
1789 break;
1790 #endif
1791 #if (RTL8814A_SUPPORT == 1)
1792 case ODM_RTL8814A:
1793 phy_iq_calibrate_8814a(dm, false);
1794 break;
1795 #endif
1796 default:
1797 break;
1798 }
1799
1800 halrf_rfk_power_save(dm, true);
1801 dm->rf_calibrate_info.iqk_progressing_time =
1802 odm_get_progressing_time(dm, start_time);
1803 RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK progressing_time = %lld ms\n",
1804 dm->rf_calibrate_info.iqk_progressing_time);
1805
1806 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
1807 dm->rf_calibrate_info.is_iqk_in_progress = false;
1808 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
1809
1810 halrf_rfk_handshake(dm, false);
1811 } else {
1812 RF_DBG(dm, DBG_RF_IQK,
1813 "== Return the IQK CMD, because RFKs in Progress ==\n");
1814 }
1815 }
1816
1817
halrf_iqk_trigger(void * dm_void,boolean is_recovery)1818 void halrf_iqk_trigger(void *dm_void, boolean is_recovery)
1819 {
1820 struct dm_struct *dm = (struct dm_struct *)dm_void;
1821 struct dm_iqk_info *iqk_info = &dm->IQK_info;
1822 struct dm_dpk_info *dpk_info = &dm->dpk_info;
1823 struct _hal_rf_ *rf = &dm->rf_table;
1824 u64 start_time;
1825
1826 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1827 if (odm_check_power_status(dm) == false)
1828 return;
1829 #endif
1830
1831 if (!dm->mp_mode)
1832 return;
1833
1834 if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
1835 rf->is_carrier_suppresion) {
1836 if (*dm->mp_mode &
1837 (*rf->is_con_tx || *rf->is_single_tone ||
1838 *rf->is_carrier_suppresion))
1839 return;
1840 }
1841
1842 if (!(rf->rf_supportability & HAL_RF_IQK))
1843 return;
1844
1845 #if DISABLE_BB_RF
1846 return;
1847 #endif
1848
1849 if (iqk_info->rfk_forbidden)
1850 return;
1851
1852 halrf_rfk_handshake(dm, true);
1853
1854 if (!dm->rf_calibrate_info.is_iqk_in_progress) {
1855 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
1856 dm->rf_calibrate_info.is_iqk_in_progress = true;
1857 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
1858 start_time = odm_get_current_time(dm);
1859 halrf_rfk_power_save(dm, false);
1860 switch (dm->support_ic_type) {
1861 #if (RTL8188E_SUPPORT == 1)
1862 case ODM_RTL8188E:
1863 phy_iq_calibrate_8188e(dm, is_recovery);
1864 break;
1865 #endif
1866 #if (RTL8188F_SUPPORT == 1)
1867 case ODM_RTL8188F:
1868 phy_iq_calibrate_8188f(dm, is_recovery);
1869 break;
1870 #endif
1871 #if (RTL8192E_SUPPORT == 1)
1872 case ODM_RTL8192E:
1873 phy_iq_calibrate_8192e(dm, is_recovery);
1874 break;
1875 #endif
1876 #if (RTL8197F_SUPPORT == 1)
1877 case ODM_RTL8197F:
1878 phy_iq_calibrate_8197f(dm, is_recovery);
1879 break;
1880 #endif
1881 #if (RTL8192F_SUPPORT == 1)
1882 case ODM_RTL8192F:
1883 phy_iq_calibrate_8192f(dm, is_recovery);
1884 break;
1885 #endif
1886 #if (RTL8703B_SUPPORT == 1)
1887 case ODM_RTL8703B:
1888 phy_iq_calibrate_8703b(dm, is_recovery);
1889 break;
1890 #endif
1891 #if (RTL8710B_SUPPORT == 1)
1892 case ODM_RTL8710B:
1893 phy_iq_calibrate_8710b(dm, is_recovery);
1894 break;
1895 #endif
1896 #if (RTL8723B_SUPPORT == 1)
1897 case ODM_RTL8723B:
1898 phy_iq_calibrate_8723b(dm, is_recovery);
1899 break;
1900 #endif
1901 #if (RTL8723D_SUPPORT == 1)
1902 case ODM_RTL8723D:
1903 phy_iq_calibrate_8723d(dm, is_recovery);
1904 break;
1905 #endif
1906 #if (RTL8721D_SUPPORT == 1)
1907 case ODM_RTL8721D:
1908 phy_iq_calibrate_8721d(dm, is_recovery);
1909 break;
1910 #endif
1911 #if (RTL8812A_SUPPORT == 1)
1912 case ODM_RTL8812:
1913 phy_iq_calibrate_8812a(dm, is_recovery);
1914 break;
1915 #endif
1916 #if (RTL8821A_SUPPORT == 1)
1917 case ODM_RTL8821:
1918 phy_iq_calibrate_8821a(dm, is_recovery);
1919 break;
1920 #endif
1921 #if (RTL8814A_SUPPORT == 1)
1922 case ODM_RTL8814A:
1923 phy_iq_calibrate_8814a(dm, is_recovery);
1924 break;
1925 #endif
1926 #if (RTL8822B_SUPPORT == 1)
1927 case ODM_RTL8822B:
1928 phy_iq_calibrate_8822b(dm, false, false);
1929 break;
1930 #endif
1931 #if (RTL8822C_SUPPORT == 1)
1932 case ODM_RTL8822C:
1933 phy_iq_calibrate_8822c(dm, false, false);
1934 break;
1935 #endif
1936 #if (RTL8821C_SUPPORT == 1)
1937 case ODM_RTL8821C:
1938 phy_iq_calibrate_8821c(dm, false, false);
1939 break;
1940 #endif
1941 #if (RTL8814B_SUPPORT == 1)
1942 case ODM_RTL8814B:
1943 phy_iq_calibrate_8814b(dm, false, false);
1944 break;
1945 #endif
1946 #if (RTL8195B_SUPPORT == 1)
1947 case ODM_RTL8195B:
1948 phy_iq_calibrate_8195b(dm, false, false);
1949 break;
1950 #endif
1951 #if (RTL8710C_SUPPORT == 1)
1952 case ODM_RTL8710C:
1953 phy_iq_calibrate_8710c(dm, false, false);
1954 break;
1955 #endif
1956 #if (RTL8198F_SUPPORT == 1)
1957 case ODM_RTL8198F:
1958 phy_iq_calibrate_8198f(dm, false, false);
1959 break;
1960 #endif
1961 #if (RTL8812F_SUPPORT == 1)
1962 case ODM_RTL8812F:
1963 phy_iq_calibrate_8812f(dm, false, false);
1964 break;
1965 #endif
1966 #if (RTL8197G_SUPPORT == 1)
1967 case ODM_RTL8197G:
1968 phy_iq_calibrate_8197g(dm, false, false);
1969 break;
1970 #endif
1971 default:
1972 break;
1973 }
1974
1975 halrf_rfk_power_save(dm, true);
1976 rf->iqk_progressing_time = odm_get_progressing_time(dm, start_time);
1977 RF_DBG(dm, DBG_RF_LCK, "[IQK]Trigger IQK progressing_time = %lld ms\n",
1978 rf->iqk_progressing_time);
1979 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
1980 dm->rf_calibrate_info.is_iqk_in_progress = false;
1981 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
1982
1983 halrf_rfk_handshake(dm, false);
1984 } else {
1985 RF_DBG(dm, DBG_RF_IQK,
1986 "== Return the IQK CMD, because RFKs in Progress ==\n");
1987 }
1988 }
1989
halrf_lck_trigger(void * dm_void)1990 void halrf_lck_trigger(void *dm_void)
1991 {
1992 struct dm_struct *dm = (struct dm_struct *)dm_void;
1993 struct dm_iqk_info *iqk_info = &dm->IQK_info;
1994 struct _hal_rf_ *rf = &dm->rf_table;
1995 u64 start_time;
1996
1997 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1998 if (odm_check_power_status(dm) == false)
1999 return;
2000 #endif
2001
2002 if (!dm->mp_mode)
2003 return;
2004
2005 if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
2006 rf->is_carrier_suppresion) {
2007 if (*dm->mp_mode &
2008 (*rf->is_con_tx || *rf->is_single_tone ||
2009 *rf->is_carrier_suppresion))
2010 return;
2011 }
2012
2013 if (!(rf->rf_supportability & HAL_RF_LCK))
2014 return;
2015
2016 #if DISABLE_BB_RF
2017 return;
2018 #endif
2019 if (iqk_info->rfk_forbidden)
2020 return;
2021 while (*dm->is_scan_in_process) {
2022 RF_DBG(dm, DBG_RF_LCK, "[LCK]scan is in process, bypass LCK\n");
2023 return;
2024 }
2025
2026 if (!dm->rf_calibrate_info.is_lck_in_progress) {
2027 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2028 dm->rf_calibrate_info.is_lck_in_progress = true;
2029 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2030 start_time = odm_get_current_time(dm);
2031 switch (dm->support_ic_type) {
2032 #if (RTL8188E_SUPPORT == 1)
2033 case ODM_RTL8188E:
2034 phy_lc_calibrate_8188e(dm);
2035 break;
2036 #endif
2037 #if (RTL8188F_SUPPORT == 1)
2038 case ODM_RTL8188F:
2039 phy_lc_calibrate_8188f(dm);
2040 break;
2041 #endif
2042 #if (RTL8192E_SUPPORT == 1)
2043 case ODM_RTL8192E:
2044 phy_lc_calibrate_8192e(dm);
2045 break;
2046 #endif
2047 #if (RTL8197F_SUPPORT == 1)
2048 case ODM_RTL8197F:
2049 phy_lc_calibrate_8197f(dm);
2050 break;
2051 #endif
2052 #if (RTL8192F_SUPPORT == 1)
2053 case ODM_RTL8192F:
2054 phy_lc_calibrate_8192f(dm);
2055 break;
2056 #endif
2057 #if (RTL8703B_SUPPORT == 1)
2058 case ODM_RTL8703B:
2059 phy_lc_calibrate_8703b(dm);
2060 break;
2061 #endif
2062 #if (RTL8710B_SUPPORT == 1)
2063 case ODM_RTL8710B:
2064 phy_lc_calibrate_8710b(dm);
2065 break;
2066 #endif
2067 #if (RTL8721D_SUPPORT == 1)
2068 case ODM_RTL8721D:
2069 phy_lc_calibrate_8721d(dm);
2070 break;
2071 #endif
2072 #if (RTL8723B_SUPPORT == 1)
2073 case ODM_RTL8723B:
2074 phy_lc_calibrate_8723b(dm);
2075 break;
2076 #endif
2077 #if (RTL8723D_SUPPORT == 1)
2078 case ODM_RTL8723D:
2079 phy_lc_calibrate_8723d(dm);
2080 break;
2081 #endif
2082 #if (RTL8812A_SUPPORT == 1)
2083 case ODM_RTL8812:
2084 phy_lc_calibrate_8812a(dm);
2085 break;
2086 #endif
2087 #if (RTL8821A_SUPPORT == 1)
2088 case ODM_RTL8821:
2089 phy_lc_calibrate_8821a(dm);
2090 break;
2091 #endif
2092 #if (RTL8814A_SUPPORT == 1)
2093 case ODM_RTL8814A:
2094 phy_lc_calibrate_8814a(dm);
2095 break;
2096 #endif
2097 #if (RTL8822B_SUPPORT == 1)
2098 case ODM_RTL8822B:
2099 phy_lc_calibrate_8822b(dm);
2100 break;
2101 #endif
2102 #if (RTL8822C_SUPPORT == 1)
2103 case ODM_RTL8822C:
2104 phy_lc_calibrate_8822c(dm);
2105 break;
2106 #endif
2107 #if (RTL8812F_SUPPORT == 1)
2108 case ODM_RTL8812F:
2109 phy_lc_calibrate_8812f(dm);
2110 break;
2111 #endif
2112 #if (RTL8821C_SUPPORT == 1)
2113 case ODM_RTL8821C:
2114 phy_lc_calibrate_8821c(dm);
2115 break;
2116 #endif
2117 #if (RTL8814B_SUPPORT == 1)
2118 case ODM_RTL8814B:
2119 phy_lc_calibrate_8814b(dm);
2120 break;
2121 #endif
2122 #if (RTL8197G_SUPPORT == 1)
2123 case ODM_RTL8197G:
2124 phy_lc_calibrate_8197g(dm);
2125 break;
2126 #endif
2127 #if (RTL8198F_SUPPORT == 1)
2128 case ODM_RTL8198F:
2129 phy_lc_calibrate_8198f(dm);
2130 break;
2131 #endif
2132 #if (RTL8710C_SUPPORT == 1)
2133 case ODM_RTL8710C:
2134 phy_lc_calibrate_8710c(dm);
2135 break;
2136 #endif
2137 default:
2138 break;
2139 }
2140 dm->rf_calibrate_info.lck_progressing_time =
2141 odm_get_progressing_time(dm, start_time);
2142 RF_DBG(dm, DBG_RF_LCK, "[LCK]LCK progressing_time = %lld ms\n",
2143 dm->rf_calibrate_info.lck_progressing_time);
2144 #if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
2145 halrf_lck_dbg(dm);
2146 #endif
2147 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2148 dm->rf_calibrate_info.is_lck_in_progress = false;
2149 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2150 } else {
2151 RF_DBG(dm, DBG_RF_LCK,
2152 "[LCK]= Return the LCK CMD, because RFK is in Progress =\n");
2153 }
2154 }
2155
halrf_aac_check(struct dm_struct * dm)2156 void halrf_aac_check(struct dm_struct *dm)
2157 {
2158 switch (dm->support_ic_type) {
2159 #if (RTL8821C_SUPPORT == 1)
2160 case ODM_RTL8821C:
2161 #if 0
2162 aac_check_8821c(dm);
2163 #endif
2164 break;
2165 #endif
2166 #if (RTL8822B_SUPPORT == 1)
2167 case ODM_RTL8822B:
2168 #if 1
2169 aac_check_8822b(dm);
2170 #endif
2171 break;
2172 #endif
2173 default:
2174 break;
2175 }
2176 }
2177
halrf_rxdck(void * dm_void)2178 void halrf_rxdck(void *dm_void)
2179 {
2180 struct dm_struct *dm = (struct dm_struct *)dm_void;
2181 struct _hal_rf_ *rf = &dm->rf_table;
2182
2183 if (!(rf->rf_supportability & HAL_RF_RXDCK))
2184 return;
2185
2186 switch (dm->support_ic_type) {
2187 case ODM_RTL8822C:
2188 #if (RTL8822C_SUPPORT == 1)
2189 halrf_rxdck_8822c(dm);
2190 break;
2191 #endif
2192 default:
2193 break;
2194 }
2195 }
2196
halrf_x2k_check(struct dm_struct * dm)2197 void halrf_x2k_check(struct dm_struct *dm)
2198 {
2199
2200 switch (dm->support_ic_type) {
2201 case ODM_RTL8821C:
2202 #if (RTL8821C_SUPPORT == 1)
2203 #endif
2204 break;
2205 case ODM_RTL8822C:
2206 #if (RTL8822C_SUPPORT == 1)
2207 phy_x2_check_8822c(dm);
2208 break;
2209 #endif
2210 case ODM_RTL8812F:
2211 #if (RTL8812F_SUPPORT == 1)
2212 phy_x2_check_8812f(dm);
2213 break;
2214 #endif
2215 default:
2216 break;
2217 }
2218 }
2219
halrf_set_rfsupportability(void * dm_void)2220 void halrf_set_rfsupportability(void *dm_void)
2221 {
2222 struct dm_struct *dm = (struct dm_struct *)dm_void;
2223 struct _hal_rf_ *rf = &dm->rf_table;
2224
2225 if (!dm->mp_mode)
2226 return;
2227
2228 if (rf->manual_rf_supportability &&
2229 *rf->manual_rf_supportability != 0xffffffff) {
2230 rf->rf_supportability = *rf->manual_rf_supportability;
2231 } else if (*dm->mp_mode) {
2232 halrf_supportability_init_mp(dm);
2233 } else {
2234 halrf_supportability_init(dm);
2235 }
2236 }
2237
halrf_rfe_definition(struct dm_struct * dm)2238 void halrf_rfe_definition(struct dm_struct *dm)
2239 {
2240 struct _hal_rf_ *rf = &dm->rf_table;
2241
2242 switch (dm->support_ic_type) {
2243 case ODM_RTL8822C:
2244 #if (RTL8822C_SUPPORT == 1)
2245 if (dm->rfe_type == 21 || dm->rfe_type == 22) {
2246 rf->ext_pa_5g = 1;
2247 rf->ext_lna_5g = 1;
2248 }
2249 break;
2250 #endif
2251 default:
2252 break;
2253 }
2254 }
2255
halrf_init(void * dm_void)2256 void halrf_init(void *dm_void)
2257 {
2258 struct dm_struct *dm = (struct dm_struct *)dm_void;
2259 struct _hal_rf_ *rf = &dm->rf_table;
2260
2261 RF_DBG(dm, DBG_RF_INIT, "HALRF_Init\n");
2262 rf->aac_checked = false;
2263 halrf_init_debug_setting(dm);
2264 halrf_set_rfsupportability(dm);
2265 halrf_rfe_definition(dm);
2266 #if 1
2267 /*Init all RF funciton*/
2268 halrf_aac_check(dm);
2269 halrf_dack_trigger(dm, false);
2270 halrf_x2k_check(dm);
2271 #endif
2272
2273 /*power trim, thrmal trim, pa bias*/
2274 phydm_config_new_kfree(dm);
2275
2276 /*TSSI Init*/
2277 halrf_tssi_dck(dm, true);
2278 halrf_tssi_get_efuse(dm);
2279 halrf_tssi_set_de(dm);
2280
2281 /*TX Gap K*/
2282 halrf_txgapk_write_gain_table(dm);
2283 }
2284
halrf_dpk_trigger(void * dm_void)2285 void halrf_dpk_trigger(void *dm_void)
2286 {
2287 struct dm_struct *dm = (struct dm_struct *)dm_void;
2288 struct _hal_rf_ *rf = &dm->rf_table;
2289 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2290 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2291
2292 u64 start_time;
2293
2294 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
2295 if (odm_check_power_status(dm) == false)
2296 return;
2297 #endif
2298
2299 if (!dm->mp_mode)
2300 return;
2301
2302 if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
2303 rf->is_carrier_suppresion) {
2304 if (*dm->mp_mode &
2305 (*rf->is_con_tx || *rf->is_single_tone ||
2306 *rf->is_carrier_suppresion))
2307 return;
2308 }
2309
2310 if (!(rf->rf_supportability & HAL_RF_DPK))
2311 return;
2312
2313 #if DISABLE_BB_RF
2314 return;
2315 #endif
2316
2317 if (iqk_info->rfk_forbidden)
2318 return;
2319
2320 halrf_rfk_handshake(dm, true);
2321
2322 if (!rf->is_dpk_in_progress) {
2323 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2324 rf->is_dpk_in_progress = true;
2325 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2326 start_time = odm_get_current_time(dm);
2327 halrf_rfk_power_save(dm, false);
2328 switch (dm->support_ic_type) {
2329 #if (RTL8822C_SUPPORT == 1)
2330 case ODM_RTL8822C:
2331 do_dpk_8822c(dm);
2332 break;
2333 #endif
2334
2335 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2336 #if (RTL8197F_SUPPORT == 1)
2337 case ODM_RTL8197F:
2338 do_dpk_8197f(dm);
2339 break;
2340 #endif
2341 #if (RTL8192F_SUPPORT == 1)
2342 case ODM_RTL8192F:
2343 do_dpk_8192f(dm);
2344 break;
2345 #endif
2346
2347 #if (RTL8198F_SUPPORT == 1)
2348 case ODM_RTL8198F:
2349 do_dpk_8198f(dm);
2350 break;
2351 #endif
2352 #if (RTL8812F_SUPPORT == 1)
2353 case ODM_RTL8812F:
2354 do_dpk_8812f(dm);
2355 break;
2356 #endif
2357 #if (RTL8197G_SUPPORT == 1)
2358 case ODM_RTL8197G:
2359 do_dpk_8197g(dm);
2360 break;
2361 #endif
2362
2363 #endif
2364
2365 #if (RTL8814B_SUPPORT == 1)
2366 case ODM_RTL8814B:
2367 do_dpk_8814b(dm);
2368 break;
2369 #endif
2370
2371 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
2372 #if (RTL8195B_SUPPORT == 1)
2373 case ODM_RTL8195B:
2374 do_dpk_8195b(dm);
2375 break;
2376 #endif
2377 #if (RTL8721D_SUPPORT == 1)
2378 case ODM_RTL8721D:
2379 do_dpk_8721d(dm);
2380 break;
2381 #endif
2382 #endif
2383 default:
2384 break;
2385 }
2386 halrf_rfk_power_save(dm, true);
2387 rf->dpk_progressing_time = odm_get_progressing_time(dm, start_time);
2388 RF_DBG(dm, DBG_RF_DPK, "[DPK]DPK progressing_time = %lld ms\n",
2389 rf->dpk_progressing_time);
2390
2391 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2392 rf->is_dpk_in_progress = false;
2393 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2394
2395 halrf_rfk_handshake(dm, false);
2396 } else {
2397 RF_DBG(dm, DBG_RF_DPK,
2398 "== Return the DPK CMD, because RFKs in Progress ==\n");
2399 }
2400 }
2401
halrf_set_dpkbychannel(void * dm_void,boolean dpk_by_ch)2402 void halrf_set_dpkbychannel(void *dm_void, boolean dpk_by_ch)
2403 {
2404 struct dm_struct *dm = (struct dm_struct *)dm_void;
2405 struct _hal_rf_ *rf = &dm->rf_table;
2406 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2407 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2408
2409
2410 switch (dm->support_ic_type) {
2411 #if (RTL8814B_SUPPORT == 1)
2412 case ODM_RTL8814B:
2413 dpk_set_dpkbychannel_8814b(dm, dpk_by_ch);
2414 break;
2415 #endif
2416
2417 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
2418 #if (RTL8195B_SUPPORT == 1)
2419 case ODM_RTL8195B:
2420 dpk_set_dpkbychannel_8195b(dm,dpk_by_ch);
2421 break;
2422 #endif
2423 #endif
2424 default:
2425 if (dpk_by_ch)
2426 dpk_info->is_dpk_by_channel = 1;
2427 else
2428 dpk_info->is_dpk_by_channel = 0;
2429 break;
2430 }
2431
2432 }
2433
halrf_set_dpkenable(void * dm_void,boolean is_dpk_enable)2434 void halrf_set_dpkenable(void *dm_void, boolean is_dpk_enable)
2435 {
2436 struct dm_struct *dm = (struct dm_struct *)dm_void;
2437 struct _hal_rf_ *rf = &dm->rf_table;
2438 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2439 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2440
2441
2442 switch (dm->support_ic_type) {
2443 #if (RTL8814B_SUPPORT == 1)
2444 case ODM_RTL8814B:
2445 dpk_set_is_dpk_enable_8814b(dm, is_dpk_enable);
2446 break;
2447 #endif
2448
2449 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
2450 #if (RTL8195B_SUPPORT == 1)
2451 case ODM_RTL8195B:
2452 dpk_set_is_dpk_enable_8195b(dm, is_dpk_enable);
2453 break;
2454 #endif
2455
2456 #if (RTL8721D_SUPPORT == 1)
2457 case ODM_RTL8721D:
2458 dpk_set_is_dpk_enable_8721d(dm, is_dpk_enable);
2459 break;
2460 #endif
2461
2462 #endif
2463 default:
2464 break;
2465 }
2466
2467 }
halrf_get_dpkbychannel(void * dm_void)2468 boolean halrf_get_dpkbychannel(void *dm_void)
2469 {
2470 struct dm_struct *dm = (struct dm_struct *)dm_void;
2471 struct _hal_rf_ *rf = &dm->rf_table;
2472 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2473 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2474 boolean is_dpk_by_channel = true;
2475
2476 switch (dm->support_ic_type) {
2477 #if (RTL8814B_SUPPORT == 1)
2478 case ODM_RTL8814B:
2479 is_dpk_by_channel = dpk_get_dpkbychannel_8814b(dm);
2480 break;
2481 #endif
2482
2483 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
2484 #if (RTL8195B_SUPPORT == 1)
2485 case ODM_RTL8195B:
2486 is_dpk_by_channel = dpk_get_dpkbychannel_8195b(dm);
2487 break;
2488 #endif
2489 #endif
2490
2491 default:
2492 break;
2493 }
2494 return is_dpk_by_channel;
2495
2496 }
2497
2498
halrf_get_dpkenable(void * dm_void)2499 boolean halrf_get_dpkenable(void *dm_void)
2500 {
2501 struct dm_struct *dm = (struct dm_struct *)dm_void;
2502 struct _hal_rf_ *rf = &dm->rf_table;
2503 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2504 struct dm_iqk_info *iqk_info = &dm->IQK_info;
2505 boolean is_dpk_enable = true;
2506
2507
2508 switch (dm->support_ic_type) {
2509 #if (RTL8814B_SUPPORT == 1)
2510 case ODM_RTL8814B:
2511 is_dpk_enable = dpk_get_is_dpk_enable_8814b(dm);
2512 break;
2513 #endif
2514
2515 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
2516 #if (RTL8195B_SUPPORT == 1)
2517 case ODM_RTL8195B:
2518 is_dpk_enable = dpk_get_is_dpk_enable_8195b(dm);
2519 break;
2520 #endif
2521 #endif
2522 default:
2523 break;
2524 }
2525 return is_dpk_enable;
2526
2527 }
2528
halrf_dpk_result_check(void * dm_void)2529 u8 halrf_dpk_result_check(void *dm_void)
2530 {
2531 struct dm_struct *dm = (struct dm_struct *)dm_void;
2532 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2533
2534 u8 result = 0;
2535
2536 switch (dm->support_ic_type) {
2537 #if (RTL8822C_SUPPORT == 1)
2538 case ODM_RTL8822C:
2539 if (dpk_info->dpk_path_ok == 0x3)
2540 result = 1;
2541 else
2542 result = 0;
2543 break;
2544 #endif
2545
2546 #if (RTL8195B_SUPPORT == 1)
2547 case ODM_RTL8195B:
2548 if (dpk_info->dpk_path_ok == 0x1)
2549 result = 1;
2550 else
2551 result = 0;
2552 break;
2553 #endif
2554
2555 #if (RTL8721D_SUPPORT == 1)
2556 case ODM_RTL8721D:
2557 if (dpk_info->dpk_path_ok == 0x1)
2558 result = 1;
2559 else
2560 result = 0;
2561 break;
2562 #endif
2563
2564 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2565
2566 #if (RTL8197F_SUPPORT == 1)
2567 case ODM_RTL8197F:
2568 if (dpk_info->dpk_path_ok == 0x3)
2569 result = 1;
2570 else
2571 result = 0;
2572 break;
2573 #endif
2574
2575 #if (RTL8192F_SUPPORT == 1)
2576 case ODM_RTL8192F:
2577 if (dpk_info->dpk_path_ok == 0x3)
2578 result = 1;
2579 else
2580 result = 0;
2581 break;
2582 #endif
2583
2584 #if (RTL8198F_SUPPORT == 1)
2585 case ODM_RTL8198F:
2586 if (dpk_info->dpk_path_ok == 0xf)
2587 result = 1;
2588 else
2589 result = 0;
2590 break;
2591 #endif
2592
2593 #if (RTL8814B_SUPPORT == 1)
2594 case ODM_RTL8814B:
2595 if (dpk_info->dpk_path_ok == 0xf)
2596 result = 1;
2597 else
2598 result = 0;
2599 break;
2600 #endif
2601
2602 #if (RTL8812F_SUPPORT == 1)
2603 case ODM_RTL8812F:
2604 if (dpk_info->dpk_path_ok == 0x3)
2605 result = 1;
2606 else
2607 result = 0;
2608 break;
2609 #endif
2610
2611 #if (RTL8197G_SUPPORT == 1)
2612 case ODM_RTL8197G:
2613 if (dpk_info->dpk_path_ok == 0x3)
2614 result = 1;
2615 else
2616 result = 0;
2617 break;
2618 #endif
2619
2620 #endif
2621 default:
2622 break;
2623 }
2624 return result;
2625 }
2626
halrf_dpk_sram_read(void * dm_void)2627 void halrf_dpk_sram_read(void *dm_void)
2628 {
2629 struct dm_struct *dm = (struct dm_struct *)dm_void;
2630
2631 u8 path, group;
2632
2633 switch (dm->support_ic_type) {
2634 #if (RTL8822C_SUPPORT == 1)
2635 case ODM_RTL8822C:
2636 dpk_coef_read_8822c(dm);
2637 break;
2638 #endif
2639
2640 #if (RTL8195B_SUPPORT == 1)
2641 case ODM_RTL8195B:
2642 dpk_sram_read_8195b(dm);
2643 break;
2644 #endif
2645
2646 #if (RTL8721D_SUPPORT == 1)
2647 case ODM_RTL8721D:
2648 dpk_sram_read_8721d(dm);
2649 break;
2650 #endif
2651
2652 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2653
2654 #if (RTL8197F_SUPPORT == 1)
2655 case ODM_RTL8197F:
2656 dpk_sram_read_8197f(dm);
2657 break;
2658 #endif
2659
2660 #if (RTL8192F_SUPPORT == 1)
2661 case ODM_RTL8192F:
2662 dpk_sram_read_8192f(dm);
2663 break;
2664 #endif
2665
2666 #if (RTL8198F_SUPPORT == 1)
2667 case ODM_RTL8198F:
2668 dpk_sram_read_8198f(dm);
2669 break;
2670 #endif
2671
2672 #if (RTL8814B_SUPPORT == 1)
2673 case ODM_RTL8814B:
2674 dpk_sram_read_8814b(dm);
2675 break;
2676 #endif
2677
2678 #if (RTL8812F_SUPPORT == 1)
2679 case ODM_RTL8812F:
2680 dpk_coef_read_8812f(dm);
2681 break;
2682 #endif
2683
2684 #if (RTL8197G_SUPPORT == 1)
2685 case ODM_RTL8197G:
2686 dpk_sram_read_8197g(dm);
2687 break;
2688 #endif
2689
2690 #endif
2691 default:
2692 break;
2693 }
2694 }
2695
halrf_dpk_enable_disable(void * dm_void)2696 void halrf_dpk_enable_disable(void *dm_void)
2697 {
2698 struct dm_struct *dm = (struct dm_struct *)dm_void;
2699 struct _hal_rf_ *rf = &dm->rf_table;
2700
2701 if (!(rf->rf_supportability & HAL_RF_DPK))
2702 return;
2703
2704 if (!rf->is_dpk_in_progress) {
2705 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2706 rf->is_dpk_in_progress = true;
2707 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2708
2709 switch (dm->support_ic_type) {
2710 #if (RTL8822C_SUPPORT == 1)
2711 case ODM_RTL8822C:
2712 dpk_enable_disable_8822c(dm);
2713 break;
2714 #endif
2715 #if (RTL8195B_SUPPORT == 1)
2716 case ODM_RTL8195B:
2717 dpk_enable_disable_8195b(dm);
2718 break;
2719 #endif
2720 #if (RTL8721D_SUPPORT == 1)
2721 case ODM_RTL8721D:
2722 phy_dpk_enable_disable_8721d(dm);
2723 break;
2724 #endif
2725
2726 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2727
2728 #if (RTL8197F_SUPPORT == 1)
2729 case ODM_RTL8197F:
2730 phy_dpk_enable_disable_8197f(dm);
2731 break;
2732 #endif
2733 #if (RTL8192F_SUPPORT == 1)
2734 case ODM_RTL8192F:
2735 phy_dpk_enable_disable_8192f(dm);
2736 break;
2737 #endif
2738
2739 #if (RTL8198F_SUPPORT == 1)
2740 case ODM_RTL8198F:
2741 dpk_enable_disable_8198f(dm);
2742 break;
2743 #endif
2744
2745 #if (RTL8814B_SUPPORT == 1)
2746 case ODM_RTL8814B:
2747 dpk_enable_disable_8814b(dm);
2748 break;
2749 #endif
2750
2751 #if (RTL8812F_SUPPORT == 1)
2752 case ODM_RTL8812F:
2753 dpk_enable_disable_8812f(dm);
2754 break;
2755 #endif
2756
2757 #if (RTL8197G_SUPPORT == 1)
2758 case ODM_RTL8197G:
2759 dpk_enable_disable_8197g(dm);
2760 break;
2761 #endif
2762
2763 #endif
2764 default:
2765 break;
2766 }
2767
2768 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
2769 rf->is_dpk_in_progress = false;
2770 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
2771 } else {
2772 RF_DBG(dm, DBG_RF_DPK,
2773 "== Return the DPK CMD, because RFKs in Progress ==\n");
2774 }
2775 }
2776
halrf_dpk_track(void * dm_void)2777 void halrf_dpk_track(void *dm_void)
2778 {
2779 struct dm_struct *dm = (struct dm_struct *)dm_void;
2780 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2781 struct _hal_rf_ *rf = &dm->rf_table;
2782
2783 if (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||
2784 dm->is_psd_in_process || (dpk_info->dpk_path_ok == 0) ||
2785 !(rf->rf_supportability & HAL_RF_DPK_TRACK) || rf->is_tssi_in_progress
2786 || rf->is_txgapk_in_progress)
2787 return;
2788
2789 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2790 if (*dm->is_fcs_mode_enable)
2791 return;
2792 #endif
2793
2794 switch (dm->support_ic_type) {
2795 #if (RTL8814B_SUPPORT == 1)
2796 case ODM_RTL8814B:
2797 dpk_track_8814b(dm);
2798 break;
2799 #endif
2800
2801 #if (RTL8822C_SUPPORT == 1)
2802 case ODM_RTL8822C:
2803 dpk_track_8822c(dm);
2804 break;
2805 #endif
2806
2807 #if (RTL8195B_SUPPORT == 1)
2808 case ODM_RTL8195B:
2809 dpk_track_8195b(dm);
2810 break;
2811 #endif
2812
2813 #if (RTL8721D_SUPPORT == 1)
2814 case ODM_RTL8721D:
2815 phy_dpk_track_8721d(dm);
2816 break;
2817 #endif
2818
2819 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2820
2821 #if (RTL8197F_SUPPORT == 1)
2822 case ODM_RTL8197F:
2823 phy_dpk_track_8197f(dm);
2824 break;
2825 #endif
2826
2827 #if (RTL8192F_SUPPORT == 1)
2828 case ODM_RTL8192F:
2829 phy_dpk_track_8192f(dm);
2830 break;
2831 #endif
2832
2833 #if (RTL8198F_SUPPORT == 1)
2834 case ODM_RTL8198F:
2835 dpk_track_8198f(dm);
2836 break;
2837 #endif
2838
2839 #if (RTL8812F_SUPPORT == 1)
2840 case ODM_RTL8812F:
2841 dpk_track_8812f(dm);
2842 break;
2843 #endif
2844
2845 #if (RTL8197G_SUPPORT == 1)
2846 case ODM_RTL8197G:
2847 dpk_track_8197g(dm);
2848 break;
2849 #endif
2850
2851 #endif
2852 default:
2853 break;
2854 }
2855 }
2856
halrf_set_dpk_track(void * dm_void,u8 enable)2857 void halrf_set_dpk_track(void *dm_void, u8 enable)
2858 {
2859 struct dm_struct *dm = (struct dm_struct *)dm_void;
2860 struct _hal_rf_ *rf = &(dm->rf_table);
2861
2862 if (enable)
2863 rf->rf_supportability = rf->rf_supportability | HAL_RF_DPK_TRACK;
2864 else
2865 rf->rf_supportability = rf->rf_supportability & ~HAL_RF_DPK_TRACK;
2866 }
2867
halrf_dpk_reload(void * dm_void)2868 void halrf_dpk_reload(void *dm_void)
2869 {
2870 struct dm_struct *dm = (struct dm_struct *)dm_void;
2871 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2872
2873 switch (dm->support_ic_type) {
2874 #if (RTL8195B_SUPPORT == 1)
2875 case ODM_RTL8195B:
2876 if (dpk_info->dpk_path_ok > 0)
2877 dpk_reload_8195b(dm);
2878 break;
2879 #endif
2880 #if (RTL8721D_SUPPORT == 1)
2881 case ODM_RTL8721D:
2882 if (dpk_info->dpk_path_ok > 0)
2883 dpk_reload_8721d(dm);
2884 break;
2885 #endif
2886
2887 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
2888
2889 #if (RTL8197F_SUPPORT == 1)
2890 case ODM_RTL8197F:
2891 if (dpk_info->dpk_path_ok > 0)
2892 dpk_reload_8197f(dm);
2893 break;
2894 #endif
2895
2896 #if (RTL8192F_SUPPORT == 1)
2897 case ODM_RTL8192F:
2898 if (dpk_info->dpk_path_ok > 0)
2899 dpk_reload_8192f(dm);
2900
2901 break;
2902 #endif
2903
2904 #if (RTL8198F_SUPPORT == 1)
2905 case ODM_RTL8198F:
2906 if (dpk_info->dpk_path_ok > 0)
2907 dpk_reload_8198f(dm);
2908 break;
2909 #endif
2910
2911 #if (RTL8814B_SUPPORT == 1)
2912 case ODM_RTL8814B:
2913 if (dpk_info->dpk_path_ok > 0)
2914 dpk_reload_8814b(dm);
2915 break;
2916 #endif
2917
2918 #endif
2919 default:
2920 break;
2921 }
2922 }
2923
halrf_dpk_switch(void * dm_void,u8 enable)2924 void halrf_dpk_switch(void *dm_void, u8 enable)
2925 {
2926 struct dm_struct *dm = (struct dm_struct *)dm_void;
2927 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2928 struct _hal_rf_ *rf = &dm->rf_table;
2929
2930 if (enable) {
2931 rf->rf_supportability = rf->rf_supportability | HAL_RF_DPK;
2932 dpk_info->is_dpk_enable = true;
2933 halrf_dpk_enable_disable(dm);
2934 halrf_dpk_trigger(dm);
2935 halrf_set_dpk_track(dm, 1);
2936 } else {
2937 halrf_set_dpk_track(dm, 0);
2938 dpk_info->is_dpk_enable = false;
2939 halrf_dpk_enable_disable(dm);
2940 rf->rf_supportability = rf->rf_supportability & ~HAL_RF_DPK;
2941 }
2942 }
2943
_halrf_dpk_info_by_chip(void * dm_void,u32 * _used,char * output,u32 * _out_len)2944 void _halrf_dpk_info_by_chip(void *dm_void, u32 *_used, char *output, u32 *_out_len)
2945 {
2946 struct dm_struct *dm = (struct dm_struct *)dm_void;
2947
2948 u32 used = *_used;
2949 u32 out_len = *_out_len;
2950
2951 switch (dm->support_ic_type) {
2952 #if (RTL8822C_SUPPORT == 1)
2953 case ODM_RTL8822C:
2954 dpk_info_by_8822c(dm, &used, output, &out_len);
2955 break;
2956 #endif
2957
2958 #if (RTL8812F_SUPPORT == 1)
2959 case ODM_RTL8812F:
2960 dpk_info_by_8812f(dm, &used, output, &out_len);
2961 break;
2962 #endif
2963
2964 #if (RTL8197G_SUPPORT == 1)
2965 case ODM_RTL8197G:
2966 dpk_info_by_8197g(dm, &used, output, &out_len);
2967 break;
2968 #endif
2969
2970 default:
2971 break;
2972 }
2973
2974 *_used = used;
2975 *_out_len = out_len;
2976 }
2977
_halrf_display_dpk_info(void * dm_void,u32 * _used,char * output,u32 * _out_len)2978 void _halrf_display_dpk_info(void *dm_void, u32 *_used, char *output, u32 *_out_len)
2979 {
2980 struct dm_struct *dm = (struct dm_struct *)dm_void;
2981 struct dm_dpk_info *dpk_info = &dm->dpk_info;
2982 struct _hal_rf_ *rf = &(dm->rf_table);
2983
2984 u32 used = *_used;
2985 u32 out_len = *_out_len;
2986 char *ic_name = NULL;
2987 u8 path;
2988
2989 switch (dm->support_ic_type) {
2990
2991 #if (RTL8822C_SUPPORT)
2992 case ODM_RTL8822C:
2993 ic_name = "8822C";
2994 break;
2995 #endif
2996
2997 #if (RTL8814B_SUPPORT)
2998 case ODM_RTL8814B:
2999 ic_name = "8814B";
3000 break;
3001 #endif
3002
3003 #if (RTL8812F_SUPPORT)
3004 case ODM_RTL8812F:
3005 ic_name = "8812F";
3006 break;
3007 #endif
3008
3009 #if (RTL8198F_SUPPORT)
3010 case ODM_RTL8198F:
3011 ic_name = "8198F";
3012 break;
3013 #endif
3014
3015 #if (RTL8197F_SUPPORT)
3016 case ODM_RTL8197F:
3017 ic_name = "8197F";
3018 break;
3019 #endif
3020
3021 #if (RTL8192F_SUPPORT)
3022 case ODM_RTL8192F:
3023 ic_name = "8192F";
3024 break;
3025 #endif
3026
3027 #if (RTL8197G_SUPPORT)
3028 case ODM_RTL8197G:
3029 ic_name = "8197G";
3030 break;
3031 #endif
3032
3033 #if (RTL8710B_SUPPORT)
3034 case ODM_RTL8721D:
3035 ic_name = "8721D";
3036 break;
3037 #endif
3038
3039 #if (RTL8195B_SUPPORT)
3040 case ODM_RTL8195B:
3041 ic_name = "8195B";
3042 break;
3043 #endif
3044 }
3045
3046 PDM_SNPF(out_len, used, output + used, out_len - used,
3047 "\n===============[ DPK info %s ]===============\n", ic_name);
3048
3049 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s %s\n",
3050 "DPK type", (dm->fw_offload_ability & PHYDM_RF_DPK_OFFLOAD) ? "FW" : "Driver",
3051 (dpk_info->is_dpk_by_channel) ? "(By channel)" : "(By group)");
3052
3053 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d (%d)\n",
3054 "FW Ver (Sub Ver)", dm->fw_version, dm->fw_sub_version);
3055
3056 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3057 "DPK Ver", HALRF_DPK_VER);
3058
3059 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3060 "RFK init ver", HALRF_RFK_INIT_VER);
3061
3062 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d / %d (RFE type:%d)\n",
3063 "Ext_PA 2G / 5G", dm->ext_pa, dm->ext_pa_5g, dm->rfe_type);
3064
3065 if ((dpk_info->dpk_ch == 0) && (dpk_info->thermal_dpk[0] == 0)) {
3066 PDM_SNPF(out_len, used, output + used, out_len - used, "\n %-25s\n",
3067 "No DPK had been done before!!!");
3068 return;
3069 }
3070
3071 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d / %d / %d\n",
3072 "DPK Cal / OK / Reload", dpk_info->dpk_cal_cnt, dpk_info->dpk_ok_cnt,
3073 dpk_info->dpk_reload_cnt);
3074
3075 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3076 "RFK H2C timeout", (rf->is_rfk_h2c_timeout) ? "Yes" : "No");
3077
3078 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3079 "DPD Reload", (dpk_info->dpk_status & BIT(0)) ? "Yes" : "No");
3080
3081 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3082 "DPD status", dpk_info->is_dpk_enable ? "Enable" : "Disable");
3083
3084 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
3085 "DPD track status", (rf->rf_supportability & HAL_RF_DPK_TRACK) ? "Enable" : "Disable");
3086
3087 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s / %s / %d / %s\n",
3088 "TSSI / Band / CH / BW", dpk_info->is_tssi_mode == 1 ? "On" : "Off",
3089 dpk_info->dpk_band == 0 ? "2G" : "5G", dpk_info->dpk_ch,
3090 dpk_info->dpk_bw == 3 ? "20M" : (dpk_info->dpk_bw == 2 ? "40M" : "80M"));
3091
3092 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s / %s / %s / %s\n",
3093 "DPK result (path)", dpk_info->dpk_path_ok & BIT(0) ? "OK" : "Fail",
3094 (dm->support_ic_type & ODM_IC_2SS) ? ((dpk_info->dpk_path_ok & BIT(1)) >> 1 ? "OK" : "Fail") : "NA",
3095 (dm->support_ic_type & ODM_IC_3SS) ? ((dpk_info->dpk_path_ok & BIT(2)) >> 2 ? "OK" : "Fail") : "NA",
3096 (dm->support_ic_type & ODM_IC_4SS) ? ((dpk_info->dpk_path_ok & BIT(3)) >> 3 ? "OK" : "Fail") : "NA");
3097 #if 0
3098 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d / %d / %d / %d\n",
3099 "DPK thermal (path)", dpk_info->thermal_dpk[0], dpk_info->thermal_dpk[1],
3100 dpk_info->thermal_dpk[2], dpk_info->thermal_dpk[3]);
3101 #endif
3102 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = ",
3103 "DPK thermal (path)");
3104 for (path = 0; path < KPATH; path++) {
3105 PDM_SNPF(out_len, used, output + used, out_len - used,
3106 path == (KPATH - 1) ? "%d\n" : "%d / ",
3107 dpk_info->thermal_dpk[path]);
3108 }
3109
3110 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n",
3111 "DPK bkup GNT control", dpk_info->gnt_control);
3112
3113 PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n",
3114 "DPK bkup GNT value", dpk_info->gnt_value);
3115
3116 _halrf_dpk_info_by_chip(dm, &used, output, &out_len);
3117
3118 *_used = used;
3119 *_out_len = out_len;
3120 }
3121
halrf_dpk_debug_cmd(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)3122 void halrf_dpk_debug_cmd(void *dm_void, char input[][16], u32 *_used,
3123 char *output, u32 *_out_len)
3124 {
3125 struct dm_struct *dm = (struct dm_struct *)dm_void;
3126 struct dm_dpk_info *dpk_info = &dm->dpk_info;
3127 struct _hal_rf_ *rf = &(dm->rf_table);
3128
3129 char *cmd[5] = {"-h", "on", "off", "info", "switch"};
3130 u32 used = *_used;
3131 u32 out_len = *_out_len;
3132 u8 i;
3133
3134 if ((strcmp(input[2], cmd[4]) != 0)) {
3135 if (!(rf->rf_supportability & HAL_RF_DPK)) {
3136 PDM_SNPF(out_len, used, output + used, out_len - used,
3137 "DPK is Unsupported!!!\n");
3138 return;
3139 }
3140 }
3141
3142 if ((strcmp(input[2], cmd[0]) == 0)) {
3143 for (i = 1; i < 4; i++) {
3144 PDM_SNPF(out_len, used, output + used, out_len - used,
3145 " %s\n", cmd[i]);
3146 }
3147 } else if ((strcmp(input[2], cmd[1]) == 0)) {
3148 PDM_SNPF(out_len, used, output + used, out_len - used,
3149 "DPK is Enabled!!\n");
3150 dpk_info->is_dpk_enable = true;
3151 halrf_dpk_enable_disable(dm);
3152 } else if ((strcmp(input[2], cmd[2]) == 0)){
3153 PDM_SNPF(out_len, used, output + used, out_len - used,
3154 "DPK is Disabled!!\n");
3155 dpk_info->is_dpk_enable = false;
3156 halrf_dpk_enable_disable(dm);
3157 } else if ((strcmp(input[2], cmd[3]) == 0))
3158 _halrf_display_dpk_info(dm, &used, output, &out_len);
3159 else if ((strcmp(input[2], cmd[4]) == 0) && (strcmp(input[3], cmd[1]) == 0)) {
3160 PDM_SNPF(out_len, used, output + used, out_len - used,
3161 "DPK Switch on!!\n");
3162 halrf_dpk_switch(dm, 1);
3163 } else if ((strcmp(input[2], cmd[4]) == 0) && (strcmp(input[3], cmd[2]) == 0)) {
3164 PDM_SNPF(out_len, used, output + used, out_len - used,
3165 "DPK Switch off!!\n");
3166 halrf_dpk_switch(dm, 0);
3167 } else {
3168 PDM_SNPF(out_len, used, output + used, out_len - used,
3169 "DPK Trigger start!!\n");
3170 halrf_dpk_trigger(dm);
3171 PDM_SNPF(out_len, used, output + used, out_len - used,
3172 "DPK Trigger finish!!\n");
3173 }
3174 }
3175
halrf_dpk_c2h_report_transfer(void * dm_void,boolean is_ok,u8 * buf,u8 buf_size)3176 void halrf_dpk_c2h_report_transfer(void *dm_void, boolean is_ok, u8 *buf, u8 buf_size)
3177 {
3178 struct dm_struct *dm = (struct dm_struct *)dm_void;
3179 struct _hal_rf_ *rf = &dm->rf_table;
3180 struct dm_dpk_info *dpk_info = &dm->dpk_info;
3181
3182 if (!(rf->rf_supportability & HAL_RF_DPK))
3183 return;
3184
3185 switch (dm->support_ic_type) {
3186 #if (RTL8822C_SUPPORT == 1)
3187 case ODM_RTL8822C:
3188 dpk_c2h_report_transfer_8822c(dm, is_ok, buf, buf_size);
3189 break;
3190 #endif
3191 default:
3192 break;
3193 }
3194 }
3195
halrf_dpk_info_rsvd_page(void * dm_void,u8 * buf,u32 * buf_size)3196 void halrf_dpk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size)
3197 {
3198 struct dm_struct *dm = (struct dm_struct *)dm_void;
3199 struct _hal_rf_ *rf = &dm->rf_table;
3200 struct dm_dpk_info *dpk_info = &dm->dpk_info;
3201
3202 if (!(rf->rf_supportability & HAL_RF_DPK) || rf->is_dpk_in_progress)
3203 return;
3204
3205 switch (dm->support_ic_type) {
3206 #if (RTL8822C_SUPPORT == 1)
3207 case ODM_RTL8822C:
3208 dpk_info_rsvd_page_8822c(dm, buf, buf_size);
3209 break;
3210 #endif
3211 default:
3212 break;
3213 }
3214 }
3215
halrf_iqk_info_rsvd_page(void * dm_void,u8 * buf,u32 * buf_size)3216 void halrf_iqk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size)
3217 {
3218 struct dm_struct *dm = (struct dm_struct *)dm_void;
3219 struct _hal_rf_ *rf = &dm->rf_table;
3220
3221 if (!(rf->rf_supportability & HAL_RF_IQK))
3222 return;
3223
3224 if (dm->rf_calibrate_info.is_iqk_in_progress)
3225 return;
3226
3227 switch (dm->support_ic_type) {
3228 #if (RTL8822C_SUPPORT == 1)
3229 case ODM_RTL8822C:
3230 iqk_info_rsvd_page_8822c(dm, buf, buf_size);
3231 break;
3232 #endif
3233 #if (RTL8195B_SUPPORT == 1)
3234 case ODM_RTL8195B:
3235 iqk_info_rsvd_page_8195b(dm, buf, buf_size);
3236 break;
3237 #endif
3238
3239 default:
3240 break;
3241 }
3242 }
3243
3244 enum hal_status
halrf_config_rfk_with_header_file(void * dm_void,u32 config_type)3245 halrf_config_rfk_with_header_file(void *dm_void, u32 config_type)
3246 {
3247 struct dm_struct *dm = (struct dm_struct *)dm_void;
3248 enum hal_status result = HAL_STATUS_SUCCESS;
3249 #if 0
3250 #if (RTL8822B_SUPPORT == 1)
3251 if (dm->support_ic_type == ODM_RTL8822B) {
3252 if (config_type == CONFIG_BB_RF_CAL_INIT)
3253 odm_read_and_config_mp_8822b_cal_init(dm);
3254 }
3255 #endif
3256 #endif
3257 #if (RTL8197G_SUPPORT == 1)
3258 if (dm->support_ic_type == ODM_RTL8197G) {
3259 if (config_type == CONFIG_BB_RF_CAL_INIT)
3260 odm_read_and_config_mp_8197g_cal_init(dm);
3261 }
3262 #endif
3263 #if (RTL8198F_SUPPORT == 1)
3264 if (dm->support_ic_type == ODM_RTL8198F) {
3265 if (config_type == CONFIG_BB_RF_CAL_INIT)
3266 odm_read_and_config_mp_8198f_cal_init(dm);
3267 }
3268 #endif
3269 #if (RTL8812F_SUPPORT == 1)
3270 if (dm->support_ic_type == ODM_RTL8812F) {
3271 if (config_type == CONFIG_BB_RF_CAL_INIT)
3272 odm_read_and_config_mp_8812f_cal_init(dm);
3273 }
3274 #endif
3275 #if (RTL8822C_SUPPORT == 1)
3276 if (dm->support_ic_type == ODM_RTL8822C) {
3277 if (config_type == CONFIG_BB_RF_CAL_INIT)
3278 odm_read_and_config_mp_8822c_cal_init(dm);
3279 }
3280 #endif
3281 #if (RTL8814B_SUPPORT == 1)
3282 if (dm->support_ic_type == ODM_RTL8814B) {
3283 if (config_type == CONFIG_BB_RF_CAL_INIT)
3284 odm_read_and_config_mp_8814b_cal_init(dm);
3285 }
3286 #endif
3287 #if (RTL8195B_SUPPORT == 1)
3288 if (dm->support_ic_type == ODM_RTL8195B) {
3289 if (config_type == CONFIG_BB_RF_CAL_INIT)
3290 odm_read_and_config_mp_8195b_cal_init(dm);
3291 }
3292 #endif
3293 #if (RTL8721D_SUPPORT == 1)
3294 if (dm->support_ic_type == ODM_RTL8721D) {
3295 if (config_type == CONFIG_BB_RF_CAL_INIT)
3296 odm_read_and_config_mp_8721d_cal_init(dm);
3297 }
3298 #endif
3299 #if 1
3300 if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
3301 result = phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_END, 0, 0, 0, (enum rf_path)0, 0);
3302 RF_DBG(dm, DBG_RF_IQK,"phy param offload end!result = %d", result);
3303 }
3304 #endif
3305 return result;
3306 }
3307
halrf_txgapk_trigger(void * dm_void)3308 void halrf_txgapk_trigger(void *dm_void)
3309 {
3310 struct dm_struct *dm = (struct dm_struct *)dm_void;
3311 struct _hal_rf_ *rf = &dm->rf_table;
3312 u64 start_time = 0x0;
3313
3314 if (!(rf->rf_supportability & HAL_RF_TXGAPK))
3315 return;
3316
3317 halrf_rfk_handshake(dm, true);
3318
3319 start_time = odm_get_current_time(dm);
3320 rf->is_txgapk_in_progress = true;
3321 halrf_rfk_power_save(dm, false);
3322
3323 switch (dm->support_ic_type) {
3324 #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
3325 #if (RTL8195B_SUPPORT == 1)
3326 case ODM_RTL8195B:
3327 /*phy_txgap_calibrate_8195b(dm, false);*/
3328 break;
3329 #endif
3330 #if (RTL8721D_SUPPORT == 1)
3331 case ODM_RTL8721D:
3332 /*phy_txgap_calibrate_8721d(dm, false);*/
3333 break;
3334 #endif
3335
3336 #endif
3337
3338 #if (RTL8814B_SUPPORT == 1)
3339 case ODM_RTL8814B:
3340 /*phy_txgap_calibrate_8814b(dm, false);*/
3341 break;
3342 #endif
3343
3344 #if (RTL8822C_SUPPORT == 1)
3345 case ODM_RTL8822C:
3346 halrf_txgapk_8822c(dm);
3347 break;
3348 #endif
3349
3350 default:
3351 break;
3352 }
3353 halrf_rfk_power_save(dm, true);
3354 rf->is_txgapk_in_progress = false;
3355
3356 halrf_rfk_handshake(dm, false);
3357
3358 rf->dpk_progressing_time =
3359 odm_get_progressing_time(dm_void, start_time);
3360 RF_DBG(dm, DBG_RF_TXGAPK, "[TGGC]TXGAPK progressing_time = %lld ms\n",
3361 rf->dpk_progressing_time);
3362 }
3363
halrf_tssi_get_efuse(void * dm_void)3364 void halrf_tssi_get_efuse(void *dm_void)
3365 {
3366 struct dm_struct *dm = (struct dm_struct *)dm_void;
3367
3368 #if (RTL8822C_SUPPORT == 1)
3369 if (dm->support_ic_type & ODM_RTL8822C) {
3370 halrf_tssi_get_efuse_8822c(dm);
3371 halrf_get_efuse_thermal_pwrtype_8822c(dm);
3372 }
3373 #endif
3374
3375 #if (RTL8812F_SUPPORT == 1)
3376 if (dm->support_ic_type & ODM_RTL8812F) {
3377 halrf_tssi_get_efuse_8812f(dm);
3378 }
3379 #endif
3380
3381 #if (RTL8814B_SUPPORT == 1)
3382 if (dm->support_ic_type & ODM_RTL8814B) {
3383 halrf_tssi_get_efuse_8814b(dm);
3384 halrf_get_efuse_thermal_pwrtype_8814b(dm);
3385 }
3386 #endif
3387
3388 #if (RTL8197G_SUPPORT == 1)
3389 if (dm->support_ic_type & ODM_RTL8197G) {
3390 halrf_tssi_get_efuse_8197g(dm);
3391 }
3392 #endif
3393
3394 }
3395
halrf_do_rxbb_dck(void * dm_void)3396 void halrf_do_rxbb_dck(void *dm_void)
3397 {
3398 struct dm_struct *dm = (struct dm_struct *)dm_void;
3399
3400
3401 #if (RTL8814B_SUPPORT == 1)
3402 if (dm->support_ic_type == ODM_RTL8814B)
3403 halrf_do_rxbb_dck_8814b(dm);
3404 #endif
3405
3406 }
3407
halrf_do_tssi(void * dm_void)3408 void halrf_do_tssi(void *dm_void)
3409 {
3410 struct dm_struct *dm = (struct dm_struct *)dm_void;
3411
3412 #if (RTL8822C_SUPPORT == 1)
3413 if (dm->support_ic_type == ODM_RTL8822C)
3414 halrf_do_tssi_8822c(dm);
3415 #endif
3416
3417 #if (RTL8812F_SUPPORT == 1)
3418 if (dm->support_ic_type == ODM_RTL8812F)
3419 halrf_do_tssi_8812f(dm);
3420 #endif
3421
3422 #if (RTL8197G_SUPPORT == 1)
3423 if (dm->support_ic_type == ODM_RTL8197G)
3424 halrf_do_tssi_8197g(dm);
3425 #endif
3426
3427 }
3428
halrf_set_tssi_enable(void * dm_void,boolean enable)3429 void halrf_set_tssi_enable(void *dm_void, boolean enable)
3430 {
3431 struct dm_struct *dm = (struct dm_struct *)dm_void;
3432 struct _hal_rf_ *rf = &(dm->rf_table);
3433
3434 if (enable == 1) {
3435 rf->power_track_type = 4;
3436 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x1);
3437 } else {
3438 rf->power_track_type = 0;
3439 odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
3440 }
3441 }
3442
3443
halrf_do_thermal(void * dm_void)3444 void halrf_do_thermal(void *dm_void)
3445 {
3446 struct dm_struct *dm = (struct dm_struct *)dm_void;
3447
3448 #if (RTL8822C_SUPPORT == 1)
3449 if (dm->support_ic_type & ODM_RTL8822C)
3450 halrf_do_thermal_8822c(dm);
3451 #endif
3452 }
3453
3454
3455
halrf_set_tssi_value(void * dm_void,u32 tssi_value)3456 u32 halrf_set_tssi_value(void *dm_void, u32 tssi_value)
3457 {
3458 struct dm_struct *dm = (struct dm_struct *)dm_void;
3459
3460 #if (RTL8822C_SUPPORT == 1)
3461 if (dm->support_ic_type & ODM_RTL8822C)
3462 return halrf_set_tssi_value_8822c(dm, tssi_value);
3463 #endif
3464
3465 #if (RTL8814B_SUPPORT == 1)
3466 if (dm->support_ic_type & ODM_RTL8814B)
3467 return halrf_set_tssi_value_8814b(dm, tssi_value);
3468 #endif
3469
3470 return 0;
3471 }
3472
halrf_set_tssi_power(void * dm_void,s8 power)3473 void halrf_set_tssi_power(void *dm_void, s8 power)
3474 {
3475 struct dm_struct *dm = (struct dm_struct *)dm_void;
3476
3477 #if (RTL8822C_SUPPORT == 1)
3478 /*halrf_set_tssi_poewr_8822c(dm, power);*/
3479 #endif
3480 }
3481
halrf_tssi_set_de_for_tx_verify(void * dm_void,u32 tssi_de,u8 path)3482 void halrf_tssi_set_de_for_tx_verify(void *dm_void, u32 tssi_de, u8 path)
3483 {
3484 struct dm_struct *dm = (struct dm_struct *)dm_void;
3485
3486 #if (RTL8822C_SUPPORT == 1)
3487 if (dm->support_ic_type & ODM_RTL8822C)
3488 halrf_tssi_set_de_for_tx_verify_8822c(dm, tssi_de, path);
3489 #endif
3490
3491 #if (RTL8814B_SUPPORT == 1)
3492 if (dm->support_ic_type & ODM_RTL8814B)
3493 halrf_tssi_set_de_for_tx_verify_8814b(dm, tssi_de, path);
3494 #endif
3495
3496 #if (RTL8812F_SUPPORT == 1)
3497 if (dm->support_ic_type & ODM_RTL8812F)
3498 halrf_tssi_set_de_for_tx_verify_8812f(dm, tssi_de, path);
3499 #endif
3500
3501 #if (RTL8197G_SUPPORT == 1)
3502 if (dm->support_ic_type & ODM_RTL8197G)
3503 halrf_tssi_set_de_for_tx_verify_8197g(dm, tssi_de, path);
3504 #endif
3505
3506 }
3507
halrf_query_tssi_value(void * dm_void)3508 u32 halrf_query_tssi_value(void *dm_void)
3509 {
3510 struct dm_struct *dm = (struct dm_struct *)dm_void;
3511
3512 #if (RTL8822C_SUPPORT == 1)
3513 if (dm->support_ic_type & ODM_RTL8822C)
3514 return halrf_query_tssi_value_8822c(dm);
3515 #endif
3516
3517 #if (RTL8814B_SUPPORT == 1)
3518 if (dm->support_ic_type & ODM_RTL8814B)
3519 return halrf_query_tssi_value_8814b(dm);
3520 #endif
3521 return 0;
3522 }
3523
halrf_tssi_cck(void * dm_void)3524 void halrf_tssi_cck(void *dm_void)
3525 {
3526 struct dm_struct *dm = (struct dm_struct *)dm_void;
3527
3528 #if (RTL8822C_SUPPORT == 1)
3529 /*halrf_tssi_cck_8822c(dm);*/
3530 if (dm->support_ic_type & ODM_RTL8822C)
3531 halrf_thermal_cck_8822c(dm);
3532 #endif
3533
3534 }
3535
halrf_thermal_cck(void * dm_void)3536 void halrf_thermal_cck(void *dm_void)
3537 {
3538 struct dm_struct *dm = (struct dm_struct *)dm_void;
3539
3540 #if (RTL8822C_SUPPORT == 1)
3541 if (dm->support_ic_type & ODM_RTL8822C)
3542 halrf_thermal_cck_8822c(dm);
3543 #endif
3544
3545 }
3546
halrf_tssi_set_de(void * dm_void)3547 void halrf_tssi_set_de(void *dm_void)
3548 {
3549 struct dm_struct *dm = (struct dm_struct *)dm_void;
3550
3551 #if (RTL8814B_SUPPORT == 1)
3552 if (dm->support_ic_type & ODM_RTL8814B)
3553 halrf_tssi_set_de_8814b(dm);
3554 #endif
3555 }
3556
halrf_tssi_dck(void * dm_void,u8 direct_do)3557 void halrf_tssi_dck(void *dm_void, u8 direct_do)
3558 {
3559 struct dm_struct *dm = (struct dm_struct *)dm_void;
3560
3561 halrf_rfk_handshake(dm, true);
3562
3563 #if (RTL8814B_SUPPORT == 1)
3564 if (dm->support_ic_type & ODM_RTL8814B) {
3565 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
3566 if (dm->rfe_type == 1 || dm->rfe_type == 4 || dm->rfe_type == 5)
3567 return;
3568 #else
3569 if (dm->rfe_type == 1 || dm->rfe_type == 6)
3570 return;
3571 #endif
3572 halrf_tssi_dck_8814b(dm, direct_do);
3573 }
3574 #endif
3575
3576 #if (RTL8822C_SUPPORT == 1)
3577 if (dm->support_ic_type & ODM_RTL8822C)
3578 halrf_tssi_dck_8822c(dm);
3579 #endif
3580
3581 #if (RTL8812F_SUPPORT == 1)
3582 if (dm->support_ic_type & ODM_RTL8812F)
3583 halrf_tssi_dck_8812f(dm);
3584 #endif
3585
3586 #if (RTL8197G_SUPPORT == 1)
3587 if (dm->support_ic_type == ODM_RTL8197G)
3588 halrf_tssi_dck_8197g(dm);
3589 #endif
3590
3591 halrf_rfk_handshake(dm, false);
3592
3593 }
3594
halrf_calculate_tssi_codeword(void * dm_void)3595 void halrf_calculate_tssi_codeword(void *dm_void)
3596 {
3597 struct dm_struct *dm = (struct dm_struct *)dm_void;
3598
3599 #if (RTL8814B_SUPPORT == 1)
3600 if (dm->support_ic_type & ODM_RTL8814B)
3601 halrf_calculate_tssi_codeword_8814b(dm, RF_PATH_A);
3602 #endif
3603
3604 #if (RTL8822C_SUPPORT == 1)
3605 if (dm->support_ic_type & ODM_RTL8822C)
3606 halrf_calculate_tssi_codeword_8822c(dm);
3607 #endif
3608 }
3609
halrf_set_tssi_codeword(void * dm_void)3610 void halrf_set_tssi_codeword(void *dm_void)
3611 {
3612 struct dm_struct *dm = (struct dm_struct *)dm_void;
3613 struct _hal_rf_ *rf = &dm->rf_table;
3614 #if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
3615 struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
3616 #endif
3617
3618 #if (RTL8814B_SUPPORT == 1)
3619 if (dm->support_ic_type & ODM_RTL8814B)
3620 halrf_set_tssi_codeword_8814b(dm, tssi->tssi_codeword);
3621 #endif
3622
3623 #if (RTL8822C_SUPPORT == 1)
3624 if (dm->support_ic_type & ODM_RTL8822C)
3625 halrf_set_tssi_codeword_8822c(dm, tssi->tssi_codeword);
3626 #endif
3627
3628 }
3629
halrf_get_tssi_codeword_for_txindex(void * dm_void)3630 u8 halrf_get_tssi_codeword_for_txindex(void *dm_void)
3631 {
3632 struct dm_struct *dm = (struct dm_struct *)dm_void;
3633
3634 #if (RTL8814B_SUPPORT == 1)
3635 if (dm->support_ic_type & ODM_RTL8814B) {
3636 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
3637 return 100;
3638 #else
3639 return 60;
3640 #endif
3641 }
3642 #endif
3643
3644 #if (RTL8822C_SUPPORT == 1)
3645 if (dm->support_ic_type & ODM_RTL8822C)
3646 return 64;
3647 #endif
3648
3649 #if (RTL8812F_SUPPORT == 1)
3650 if (dm->support_ic_type & ODM_RTL8812F)
3651 return 100;
3652 #endif
3653
3654 #if (RTL8197G_SUPPORT == 1)
3655 if (dm->support_ic_type & ODM_RTL8197G)
3656 return 100;
3657 #endif
3658
3659 return 60;
3660 }
3661
halrf_tssi_clean_de(void * dm_void)3662 void halrf_tssi_clean_de(
3663 void *dm_void)
3664 {
3665 struct dm_struct *dm = (struct dm_struct *)dm_void;
3666
3667 #if (RTL8812F_SUPPORT == 1)
3668 if (dm->support_ic_type & ODM_RTL8812F)
3669 halrf_tssi_clean_de_8812f(dm);
3670 #endif
3671
3672 #if (RTL8814B_SUPPORT == 1)
3673 if (dm->support_ic_type & ODM_RTL8814B)
3674 halrf_tssi_clean_de_8814b(dm);
3675 #endif
3676
3677 #if (RTL8197G_SUPPORT == 1)
3678 if (dm->support_ic_type & ODM_RTL8197G)
3679 halrf_tssi_clean_de_8197g(dm);
3680 #endif
3681
3682 }
3683
halrf_tssi_trigger_de(void * dm_void,u8 path)3684 u32 halrf_tssi_trigger_de(void *dm_void, u8 path)
3685 {
3686 struct dm_struct *dm = (struct dm_struct *)dm_void;
3687
3688 #if (RTL8812F_SUPPORT == 1)
3689 if (dm->support_ic_type & ODM_RTL8812F)
3690 return halrf_tssi_trigger_de_8812f(dm, path);
3691 #endif
3692
3693 #if (RTL8814B_SUPPORT == 1)
3694 if (dm->support_ic_type & ODM_RTL8814B)
3695 return halrf_tssi_trigger_de_8814b(dm, path);
3696 #endif
3697
3698 #if (RTL8197G_SUPPORT == 1)
3699 if (dm->support_ic_type & ODM_RTL8197G)
3700 return halrf_tssi_trigger_de_8197g(dm, path);
3701 #endif
3702 return 0;
3703 }
3704
halrf_tssi_get_de(void * dm_void,u8 path)3705 u32 halrf_tssi_get_de(void *dm_void, u8 path)
3706 {
3707 struct dm_struct *dm = (struct dm_struct *)dm_void;
3708
3709 #if (RTL8822C_SUPPORT == 1)
3710 if (dm->support_ic_type & ODM_RTL8822C)
3711 return halrf_tssi_get_de_8822c(dm, path);
3712 #endif
3713
3714 #if (RTL8812F_SUPPORT == 1)
3715 if (dm->support_ic_type & ODM_RTL8812F)
3716 return halrf_tssi_get_de_8812f(dm, path);
3717 #endif
3718
3719 #if (RTL8814B_SUPPORT == 1)
3720 if (dm->support_ic_type & ODM_RTL8814B)
3721 return halrf_tssi_get_de_8814b(dm, path);
3722 #endif
3723
3724 #if (RTL8197G_SUPPORT == 1)
3725 if (dm->support_ic_type & ODM_RTL8197G)
3726 return halrf_tssi_get_de_8197g(dm, path);
3727 #endif
3728 return 0;
3729 }
3730
halrf_tssi_trigger(void * dm_void)3731 void halrf_tssi_trigger(void *dm_void)
3732 {
3733 struct dm_struct *dm = (struct dm_struct *)dm_void;
3734 struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
3735 struct _hal_rf_ *rf = &(dm->rf_table);
3736
3737 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
3738 if (*dm->mp_mode == 1) {
3739 if (cali_info->txpowertrack_control == 0 ||
3740 cali_info->txpowertrack_control == 1) {
3741 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
3742 "[TSSI]======>%s MP Mode UI chose thermal tracking. return !!!\n", __func__);
3743 return;
3744 }
3745 } else {
3746 if (rf->power_track_type >= 0 && rf->power_track_type <= 3) {
3747 RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
3748 "[TSSI]======>%s Normal Mode efues is thermal tracking. return !!!\n", __func__);
3749 return;
3750 }
3751 }
3752 #endif
3753
3754 halrf_calculate_tssi_codeword(dm);
3755 halrf_set_tssi_codeword(dm);
3756 halrf_tssi_dck(dm, false);
3757 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
3758 halrf_tssi_get_efuse(dm);
3759 #endif
3760 halrf_tssi_set_de(dm);
3761 halrf_do_tssi(dm);
3762 }
3763
halrf_txgapk_write_gain_table(void * dm_void)3764 void halrf_txgapk_write_gain_table(void *dm_void)
3765 {
3766 struct dm_struct *dm = (struct dm_struct *)dm_void;
3767
3768 #if (RTL8822C_SUPPORT == 1)
3769 if (dm->support_ic_type & ODM_RTL8822C)
3770 halrf_txgapk_save_all_tx_gain_table_8822c(dm);
3771 #endif
3772 }
3773
halrf_txgapk_reload_tx_gain(void * dm_void)3774 void halrf_txgapk_reload_tx_gain(void *dm_void)
3775 {
3776 struct dm_struct *dm = (struct dm_struct *)dm_void;
3777
3778 #if (RTL8822C_SUPPORT == 1)
3779 if (dm->support_ic_type & ODM_RTL8822C)
3780 halrf_txgapk_reload_tx_gain_8822c(dm);
3781 #endif
3782 }
3783
halrf_txgap_enable_disable(void * dm_void,u8 enable)3784 void halrf_txgap_enable_disable(void *dm_void, u8 enable)
3785 {
3786 struct dm_struct *dm = (struct dm_struct *)dm_void;
3787 struct _hal_rf_ *rf = &(dm->rf_table);
3788
3789 if (enable) {
3790 rf->rf_supportability = rf->rf_supportability | HAL_RF_TXGAPK;
3791 halrf_txgapk_trigger(dm);
3792 } else {
3793 rf->rf_supportability = rf->rf_supportability & ~HAL_RF_TXGAPK;
3794 halrf_txgapk_reload_tx_gain(dm);
3795 }
3796 }
3797
_halrf_dump_subpage(void * dm_void,u32 * _used,char * output,u32 * _out_len,u8 page)3798 void _halrf_dump_subpage(void *dm_void, u32 *_used, char *output, u32 *_out_len, u8 page)
3799 {
3800 struct dm_struct *dm = (struct dm_struct *)dm_void;
3801
3802 u32 used = *_used;
3803 u32 out_len = *_out_len;
3804 u32 addr;
3805
3806 PDM_SNPF(out_len, used, output + used, out_len - used,
3807 "\n===============[ Subpage_%d start]===============\n", page);
3808
3809 RF_DBG(dm, DBG_RF_RFK, " ===============[ Subpage_%d start]===============\n", page);
3810
3811 odm_set_bb_reg(dm, R_0x1b00, BIT(2) | BIT(1), page);
3812
3813 for (addr = 0x1b00; addr < 0x1c00; addr += 0x10) {
3814 PDM_SNPF(out_len, used, output + used, out_len - used,
3815 " 0x%x : 0x%08x 0x%08x 0x%08x 0x%08x\n", addr,
3816 odm_get_bb_reg(dm, addr, MASKDWORD),
3817 odm_get_bb_reg(dm, addr + 0x4, MASKDWORD),
3818 odm_get_bb_reg(dm, addr + 0x8, MASKDWORD),
3819 odm_get_bb_reg(dm, addr + 0xc, MASKDWORD));
3820 RF_DBG(dm, DBG_RF_RFK, " 0x%x : 0x%08x 0x%08x 0x%08x 0x%08x\n", addr,
3821 odm_get_bb_reg(dm, addr, MASKDWORD),
3822 odm_get_bb_reg(dm, addr + 0x4, MASKDWORD),
3823 odm_get_bb_reg(dm, addr + 0x8, MASKDWORD),
3824 odm_get_bb_reg(dm, addr + 0xc, MASKDWORD));
3825 }
3826
3827 *_used = used;
3828 *_out_len = out_len;
3829 }
3830
halrf_dump_rfk_reg(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)3831 void halrf_dump_rfk_reg(void *dm_void, char input[][16], u32 *_used,
3832 char *output, u32 *_out_len)
3833 {
3834 struct dm_struct *dm = (struct dm_struct *)dm_void;
3835 struct _hal_rf_ *rf = &dm->rf_table;
3836
3837 char help[] = "-h";
3838 u32 var1[10] = {0};
3839 u32 used = *_used;
3840 u32 out_len = *_out_len;
3841 u32 reg_1b00, supportability;
3842 u8 page;
3843
3844 if (!(dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES))) {
3845 PDM_SNPF(out_len, used, output + used, out_len - used,
3846 "CMD is Unsupported due to IC type!!!\n");
3847 RF_DBG(dm, DBG_RF_RFK, "[RFK] CMD is Unsupported due to IC type!!!\n");
3848 return;
3849 } else if (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||
3850 dm->is_psd_in_process || rf->is_tssi_in_progress || rf->is_txgapk_in_progress) {
3851 PDM_SNPF(out_len, used, output + used, out_len - used,
3852 "Bypass CMD due to RFK is doing!!!\n");
3853 RF_DBG(dm, DBG_RF_RFK, "[RFK] Bypass CMD due to RFK is doing!!!\n");
3854 return;
3855 }
3856
3857 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3858 if (*dm->is_fcs_mode_enable) {
3859 PDM_SNPF(out_len, used, output + used, out_len - used,
3860 "Bypass CMD due to FCS mode!!!\n");
3861 RF_DBG(dm, DBG_RF_RFK, "[RFK] Bypass CMD due to FCS mode!!!\n");
3862 return;
3863 }
3864 #endif
3865 supportability = rf->rf_supportability;
3866
3867 /*to avoid DPK track interruption*/
3868 rf->rf_supportability = rf->rf_supportability & ~HAL_RF_DPK_TRACK;
3869
3870 reg_1b00 = odm_get_bb_reg(dm, R_0x1b00, MASKDWORD);
3871
3872 if (input[2])
3873 PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[0]);
3874
3875 if ((strcmp(input[2], help) == 0))
3876 PDM_SNPF(out_len, used, output + used, out_len - used,
3877 "dump subpage {0:Page0, 1:Page1, 2:Page2, 3:Page3, 4:all}\n");
3878 else if (var1[0] > 4)
3879 PDM_SNPF(out_len, used, output + used, out_len - used,
3880 "Wrong subpage number!!\n");
3881 else if (var1[0] == 4) {
3882 for (page = 0; page < 4; page++)
3883 _halrf_dump_subpage(dm, &used, output, &out_len, page);
3884 } else
3885 _halrf_dump_subpage(dm, &used, output, &out_len, (u8)var1[0]);
3886
3887 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, reg_1b00);
3888
3889 rf->rf_supportability = supportability;
3890
3891 *_used = used;
3892 *_out_len = out_len;
3893 }
3894
3895 /*Golbal function*/
halrf_reload_bp(void * dm_void,u32 * bp_reg,u32 * bp,u32 num)3896 void halrf_reload_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num)
3897 {
3898 struct dm_struct *dm = (struct dm_struct *)dm_void;
3899 u32 i;
3900
3901 for (i = 0; i < num; i++)
3902 odm_write_4byte(dm, bp_reg[i], bp[i]);
3903 }
3904
halrf_reload_bprf(void * dm_void,u32 * bp_reg,u32 bp[][4],u32 num,u8 ss)3905 void halrf_reload_bprf(void *dm_void, u32 *bp_reg, u32 bp[][4], u32 num,
3906 u8 ss)
3907 {
3908 struct dm_struct *dm = (struct dm_struct *)dm_void;
3909 u32 i, path;
3910
3911 for (i = 0; i < num; i++) {
3912 for (path = 0; path < ss; path++)
3913 odm_set_rf_reg(dm, (enum rf_path)path, bp_reg[i],
3914 MASK20BITS, bp[i][path]);
3915 }
3916 }
3917
halrf_bp(void * dm_void,u32 * bp_reg,u32 * bp,u32 num)3918 void halrf_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num)
3919 {
3920 struct dm_struct *dm = (struct dm_struct *)dm_void;
3921 u32 i;
3922
3923 for (i = 0; i < num; i++)
3924 bp[i] = odm_read_4byte(dm, bp_reg[i]);
3925 }
3926
halrf_bprf(void * dm_void,u32 * bp_reg,u32 bp[][4],u32 num,u8 ss)3927 void halrf_bprf(void *dm_void, u32 *bp_reg, u32 bp[][4], u32 num, u8 ss)
3928 {
3929 struct dm_struct *dm = (struct dm_struct *)dm_void;
3930 u32 i, path;
3931
3932 for (i = 0; i < num; i++) {
3933 for (path = 0; path < ss; path++) {
3934 bp[i][path] =
3935 odm_get_rf_reg(dm, (enum rf_path)path,
3936 bp_reg[i], MASK20BITS);
3937 }
3938 }
3939 }
3940
halrf_swap(void * dm_void,u32 * v1,u32 * v2)3941 void halrf_swap(void *dm_void, u32 *v1, u32 *v2)
3942 {
3943 struct dm_struct *dm = (struct dm_struct *)dm_void;
3944 u32 temp;
3945
3946 temp = *v1;
3947 *v1 = *v2;
3948 *v2 = temp;
3949 }
3950
halrf_bubble(void * dm_void,u32 * v1,u32 * v2)3951 void halrf_bubble(void *dm_void, u32 *v1, u32 *v2)
3952 {
3953 struct dm_struct *dm = (struct dm_struct *)dm_void;
3954 u32 temp;
3955
3956 if (*v1 >= 0x200 && *v2 >= 0x200) {
3957 if (*v1 > *v2)
3958 halrf_swap(dm, v1, v2);
3959 } else if (*v1 < 0x200 && *v2 < 0x200) {
3960 if (*v1 > *v2)
3961 halrf_swap(dm, v1, v2);
3962 } else if (*v1 < 0x200 && *v2 >= 0x200) {
3963 halrf_swap(dm, v1, v2);
3964 }
3965 }
3966
halrf_b_sort(void * dm_void,u32 * iv,u32 * qv)3967 void halrf_b_sort(void *dm_void, u32 *iv, u32 *qv)
3968 {
3969 struct dm_struct *dm = (struct dm_struct *)dm_void;
3970 u32 temp;
3971 u32 i, j;
3972
3973 RF_DBG(dm, DBG_RF_DACK, "[DACK]bubble!!!!!!!!!!!!");
3974 for (i = 0; i < SN - 1; i++) {
3975 for (j = 0; j < (SN - 1 - i) ; j++) {
3976 halrf_bubble(dm, &iv[j], &iv[j + 1]);
3977 halrf_bubble(dm, &qv[j], &qv[j + 1]);
3978 }
3979 }
3980 }
3981
halrf_minmax_compare(void * dm_void,u32 value,u32 * min,u32 * max)3982 void halrf_minmax_compare(void *dm_void, u32 value, u32 *min,
3983 u32 *max)
3984 {
3985 struct dm_struct *dm = (struct dm_struct *)dm_void;
3986
3987 if (value >= 0x200) {
3988 if (*min >= 0x200) {
3989 if (*min > value)
3990 *min = value;
3991 } else {
3992 *min = value;
3993 }
3994 if (*max >= 0x200) {
3995 if (*max < value)
3996 *max = value;
3997 }
3998 } else {
3999 if (*min < 0x200) {
4000 if (*min > value)
4001 *min = value;
4002 }
4003
4004 if (*max >= 0x200) {
4005 *max = value;
4006 } else {
4007 if (*max < value)
4008 *max = value;
4009 }
4010 }
4011 }
4012
halrf_delta(void * dm_void,u32 v1,u32 v2)4013 u32 halrf_delta(void *dm_void, u32 v1, u32 v2)
4014 {
4015 struct dm_struct *dm = (struct dm_struct *)dm_void;
4016
4017 if (v1 >= 0x200 && v2 >= 0x200) {
4018 if (v1 > v2)
4019 return v1 - v2;
4020 else
4021 return v2 - v1;
4022 } else if (v1 >= 0x200 && v2 < 0x200) {
4023 return v2 + (0x400 - v1);
4024 } else if (v1 < 0x200 && v2 >= 0x200) {
4025 return v1 + (0x400 - v2);
4026 }
4027
4028 if (v1 > v2)
4029 return v1 - v2;
4030 else
4031 return v2 - v1;
4032 }
4033
halrf_compare(void * dm_void,u32 value)4034 boolean halrf_compare(void *dm_void, u32 value)
4035 {
4036 struct dm_struct *dm = (struct dm_struct *)dm_void;
4037
4038 boolean fail = false;
4039
4040 if (value >= 0x200 && (0x400 - value) > 0x64)
4041 fail = true;
4042 else if (value < 0x200 && value > 0x64)
4043 fail = true;
4044
4045 if (fail)
4046 RF_DBG(dm, DBG_RF_DACK, "[DACK]overflow!!!!!!!!!!!!!!!");
4047 return fail;
4048 }
4049
halrf_mode(void * dm_void,u32 * i_value,u32 * q_value)4050 void halrf_mode(void *dm_void, u32 *i_value, u32 *q_value)
4051 {
4052 struct dm_struct *dm = (struct dm_struct *)dm_void;
4053 u32 iv[SN], qv[SN], im[SN], qm[SN], temp, temp1, temp2;
4054 u32 p, m, t;
4055 u32 i_max = 0, q_max = 0, i_min = 0x0, q_min = 0x0, c = 0x0;
4056 u32 i_delta, q_delta;
4057 u8 i, j, ii = 0, qi = 0;
4058 boolean fail = false;
4059
4060 ODM_delay_ms(10);
4061 for (i = 0; i < SN; i++) {
4062 im[i] = 0;
4063 qm[i] = 0;
4064 }
4065 i = 0;
4066 c = 0;
4067 while (i < SN && c < 1000) {
4068 c++;
4069 temp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);
4070 iv[i] = (temp & 0x3ff000) >> 12;
4071 qv[i] = temp & 0x3ff;
4072
4073 fail = false;
4074 if (halrf_compare(dm, iv[i]))
4075 fail = true;
4076 if (halrf_compare(dm, qv[i]))
4077 fail = true;
4078 if (!fail)
4079 i++;
4080 }
4081 c = 0;
4082 do {
4083 c++;
4084 i_min = iv[0];
4085 i_max = iv[0];
4086 q_min = qv[0];
4087 q_max = qv[0];
4088 for (i = 0; i < SN; i++) {
4089 halrf_minmax_compare(dm, iv[i], &i_min, &i_max);
4090 halrf_minmax_compare(dm, qv[i], &q_min, &q_max);
4091 }
4092 RF_DBG(dm, DBG_RF_DACK, "[DACK]i_min=0x%x, i_max=0x%x",
4093 i_min, i_max);
4094 RF_DBG(dm, DBG_RF_DACK, "[DACK]q_min=0x%x, q_max=0x%x",
4095 q_min, q_max);
4096 if (i_max < 0x200 && i_min < 0x200)
4097 i_delta = i_max - i_min;
4098 else if (i_max >= 0x200 && i_min >= 0x200)
4099 i_delta = i_max - i_min;
4100 else
4101 i_delta = i_max + (0x400 - i_min);
4102
4103 if (q_max < 0x200 && q_min < 0x200)
4104 q_delta = q_max - q_min;
4105 else if (q_max >= 0x200 && q_min >= 0x200)
4106 q_delta = q_max - q_min;
4107 else
4108 q_delta = q_max + (0x400 - q_min);
4109 RF_DBG(dm, DBG_RF_DACK, "[DACK]i_delta=0x%x, q_delta=0x%x",
4110 i_delta, q_delta);
4111 halrf_b_sort(dm, iv, qv);
4112 if (i_delta > 5 || q_delta > 5) {
4113 temp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);
4114 iv[0] = (temp & 0x3ff000) >> 12;
4115 qv[0] = temp & 0x3ff;
4116 temp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);
4117 iv[SN - 1] = (temp & 0x3ff000) >> 12;
4118 qv[SN - 1] = temp & 0x3ff;
4119 } else {
4120 break;
4121 }
4122 } while (c < 100);
4123 #if 1
4124 #if 0
4125 for (i = 0; i < SN; i++)
4126 RF_DBG(dm, DBG_RF_DACK, "[DACK]iv[%d] = 0x%x\n", i, iv[i]);
4127 for (i = 0; i < SN; i++)
4128 RF_DBG(dm, DBG_RF_DACK, "[DACK]qv[%d] = 0x%x\n", i, qv[i]);
4129 #endif
4130 /*i*/
4131 m = 0;
4132 p = 0;
4133 for (i = 10; i < SN - 10; i++) {
4134 if (iv[i] > 0x200)
4135 m = (0x400 - iv[i]) + m;
4136 else
4137 p = iv[i] + p;
4138 }
4139
4140 if (p > m) {
4141 t = p - m;
4142 t = t / (SN - 20);
4143 } else {
4144 t = m - p;
4145 t = t / (SN - 20);
4146 if (t != 0x0)
4147 t = 0x400 - t;
4148 }
4149 *i_value = t;
4150 /*q*/
4151 m = 0;
4152 p = 0;
4153 for (i = 10; i < SN - 10; i++) {
4154 if (qv[i] > 0x200)
4155 m = (0x400 - qv[i]) + m;
4156 else
4157 p = qv[i] + p;
4158 }
4159 if (p > m) {
4160 t = p - m;
4161 t = t / (SN - 20);
4162 } else {
4163 t = m - p;
4164 t = t / (SN - 20);
4165 if (t != 0x0)
4166 t = 0x400 - t;
4167 }
4168 *q_value = t;
4169 #endif
4170 }
halrf_delay_10us(u16 v1)4171 void halrf_delay_10us(u16 v1)
4172 {
4173 u16 i = 0;
4174
4175 for (i = 0; i < v1; i++)
4176 ODM_delay_us(10);
4177 }
4178
4179