1 /******************************************************************************
2 *
3 * Copyright(c) 2013 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 #include <rtw_odm.h>
17 #include <hal_data.h>
18
rtw_phydm_ability_ops(_adapter * adapter,HAL_PHYDM_OPS ops,u32 ability)19 u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability)
20 {
21 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
22 struct dm_struct *podmpriv = &pHalData->odmpriv;
23 u32 result = 0;
24
25 switch (ops) {
26 case HAL_PHYDM_DIS_ALL_FUNC:
27 podmpriv->support_ability = DYNAMIC_FUNC_DISABLE;
28 halrf_cmn_info_set(podmpriv, HALRF_CMNINFO_ABILITY, DYNAMIC_FUNC_DISABLE);
29 break;
30 case HAL_PHYDM_FUNC_SET:
31 podmpriv->support_ability |= ability;
32 break;
33 case HAL_PHYDM_FUNC_CLR:
34 podmpriv->support_ability &= ~(ability);
35 break;
36 case HAL_PHYDM_ABILITY_BK:
37 /* dm flag backup*/
38 podmpriv->bk_support_ability = podmpriv->support_ability;
39 pHalData->bk_rf_ability = halrf_cmn_info_get(podmpriv, HALRF_CMNINFO_ABILITY);
40 break;
41 case HAL_PHYDM_ABILITY_RESTORE:
42 /* restore dm flag */
43 podmpriv->support_ability = podmpriv->bk_support_ability;
44 halrf_cmn_info_set(podmpriv, HALRF_CMNINFO_ABILITY, pHalData->bk_rf_ability);
45 break;
46 case HAL_PHYDM_ABILITY_SET:
47 podmpriv->support_ability = ability;
48 break;
49 case HAL_PHYDM_ABILITY_GET:
50 result = podmpriv->support_ability;
51 break;
52 }
53 return result;
54 }
55
56 /* set ODM_CMNINFO_IC_TYPE based on chip_type */
rtw_odm_init_ic_type(_adapter * adapter)57 void rtw_odm_init_ic_type(_adapter *adapter)
58 {
59 struct dm_struct *odm = adapter_to_phydm(adapter);
60 u32 ic_type = chip_type_to_odm_ic_type(rtw_get_chip_type(adapter));
61
62 rtw_warn_on(!ic_type);
63
64 odm_cmn_info_init(odm, ODM_CMNINFO_IC_TYPE, ic_type);
65 }
66
rtw_odm_adaptivity_ver_msg(void * sel,_adapter * adapter)67 void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter)
68 {
69 RTW_PRINT_SEL(sel, "ADAPTIVITY_VERSION "ADAPTIVITY_VERSION"\n");
70 }
71
72 #define RTW_ADAPTIVITY_EN_DISABLE 0
73 #define RTW_ADAPTIVITY_EN_ENABLE 1
74
rtw_odm_adaptivity_en_msg(void * sel,_adapter * adapter)75 void rtw_odm_adaptivity_en_msg(void *sel, _adapter *adapter)
76 {
77 struct registry_priv *regsty = &adapter->registrypriv;
78
79 RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_EN_");
80
81 if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_DISABLE)
82 _RTW_PRINT_SEL(sel, "DISABLE\n");
83 else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE)
84 _RTW_PRINT_SEL(sel, "ENABLE\n");
85 else
86 _RTW_PRINT_SEL(sel, "INVALID\n");
87 }
88
89 #define RTW_ADAPTIVITY_MODE_NORMAL 0
90 #define RTW_ADAPTIVITY_MODE_CARRIER_SENSE 1
91
rtw_odm_adaptivity_mode_msg(void * sel,_adapter * adapter)92 void rtw_odm_adaptivity_mode_msg(void *sel, _adapter *adapter)
93 {
94 struct registry_priv *regsty = &adapter->registrypriv;
95
96 RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_MODE_");
97
98 if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_NORMAL)
99 _RTW_PRINT_SEL(sel, "NORMAL\n");
100 else if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_CARRIER_SENSE)
101 _RTW_PRINT_SEL(sel, "CARRIER_SENSE\n");
102 else
103 _RTW_PRINT_SEL(sel, "INVALID\n");
104 }
105
rtw_odm_adaptivity_config_msg(void * sel,_adapter * adapter)106 void rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter)
107 {
108 rtw_odm_adaptivity_ver_msg(sel, adapter);
109 rtw_odm_adaptivity_en_msg(sel, adapter);
110 rtw_odm_adaptivity_mode_msg(sel, adapter);
111 }
112
rtw_odm_adaptivity_needed(_adapter * adapter)113 bool rtw_odm_adaptivity_needed(_adapter *adapter)
114 {
115 struct registry_priv *regsty = &adapter->registrypriv;
116 bool ret = _FALSE;
117
118 if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE)
119 ret = _TRUE;
120
121 return ret;
122 }
123
rtw_odm_adaptivity_parm_msg(void * sel,_adapter * adapter)124 void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter)
125 {
126 struct dm_struct *odm = adapter_to_phydm(adapter);
127
128 rtw_odm_adaptivity_config_msg(sel, adapter);
129
130 RTW_PRINT_SEL(sel, "%10s %16s\n"
131 , "th_l2h_ini", "th_edcca_hl_diff");
132 RTW_PRINT_SEL(sel, "0x%-8x %-16d\n"
133 , (u8)odm->th_l2h_ini
134 , odm->th_edcca_hl_diff
135 );
136 }
137
rtw_odm_adaptivity_parm_set(_adapter * adapter,s8 th_l2h_ini,s8 th_edcca_hl_diff)138 void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff)
139 {
140 struct dm_struct *odm = adapter_to_phydm(adapter);
141
142 odm->th_l2h_ini = th_l2h_ini;
143 odm->th_edcca_hl_diff = th_edcca_hl_diff;
144 }
145
rtw_odm_get_perpkt_rssi(void * sel,_adapter * adapter)146 void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter)
147 {
148 struct dm_struct *odm = adapter_to_phydm(adapter);
149
150 RTW_PRINT_SEL(sel, "rx_rate = %s, rssi_a = %d(%%), rssi_b = %d(%%)\n",
151 HDATA_RATE(odm->rx_rate), odm->rssi_a, odm->rssi_b);
152 }
153
154
rtw_odm_acquirespinlock(_adapter * adapter,enum rt_spinlock_type type)155 void rtw_odm_acquirespinlock(_adapter *adapter, enum rt_spinlock_type type)
156 {
157 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
158 _irqL irqL;
159
160 switch (type) {
161 case RT_IQK_SPINLOCK:
162 _enter_critical_bh(&pHalData->IQKSpinLock, &irqL);
163 default:
164 break;
165 }
166 }
167
rtw_odm_releasespinlock(_adapter * adapter,enum rt_spinlock_type type)168 void rtw_odm_releasespinlock(_adapter *adapter, enum rt_spinlock_type type)
169 {
170 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
171 _irqL irqL;
172
173 switch (type) {
174 case RT_IQK_SPINLOCK:
175 _exit_critical_bh(&pHalData->IQKSpinLock, &irqL);
176 default:
177 break;
178 }
179 }
180
rtw_odm_get_tx_power_mbm(struct dm_struct * dm,u8 rfpath,u8 rate,u8 bw,u8 cch)181 s16 rtw_odm_get_tx_power_mbm(struct dm_struct *dm, u8 rfpath, u8 rate, u8 bw, u8 cch)
182 {
183 return phy_get_txpwr_single_mbm(dm->adapter, rfpath, mgn_rate_to_rs(rate), rate, bw, cch, 0, 0, NULL);
184 }
185
186 #ifdef CONFIG_DFS_MASTER
rtw_odm_radar_detect_reset(_adapter * adapter)187 inline void rtw_odm_radar_detect_reset(_adapter *adapter)
188 {
189 phydm_radar_detect_reset(adapter_to_phydm(adapter));
190 }
191
rtw_odm_radar_detect_disable(_adapter * adapter)192 inline void rtw_odm_radar_detect_disable(_adapter *adapter)
193 {
194 phydm_radar_detect_disable(adapter_to_phydm(adapter));
195 }
196
197 /* called after ch, bw is set */
rtw_odm_radar_detect_enable(_adapter * adapter)198 inline void rtw_odm_radar_detect_enable(_adapter *adapter)
199 {
200 phydm_radar_detect_enable(adapter_to_phydm(adapter));
201 }
202
rtw_odm_radar_detect(_adapter * adapter)203 inline BOOLEAN rtw_odm_radar_detect(_adapter *adapter)
204 {
205 return phydm_radar_detect(adapter_to_phydm(adapter));
206 }
207
rtw_odm_radar_detect_polling_int_ms(struct dvobj_priv * dvobj)208 inline u8 rtw_odm_radar_detect_polling_int_ms(struct dvobj_priv *dvobj)
209 {
210 return phydm_dfs_polling_time(dvobj_to_phydm(dvobj));
211 }
212 #endif /* CONFIG_DFS_MASTER */
213
rtw_odm_parse_rx_phy_status_chinfo(union recv_frame * rframe,u8 * phys)214 void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys)
215 {
216 #ifndef DBG_RX_PHYSTATUS_CHINFO
217 #define DBG_RX_PHYSTATUS_CHINFO 0
218 #endif
219
220 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
221 _adapter *adapter = rframe->u.hdr.adapter;
222 struct dm_struct *phydm = adapter_to_phydm(adapter);
223 struct rx_pkt_attrib *attrib = &rframe->u.hdr.attrib;
224 u8 *wlanhdr = get_recvframe_data(rframe);
225
226 if (phydm->support_ic_type & PHYSTS_2ND_TYPE_IC) {
227 /*
228 * 8723D:
229 * type_0(CCK)
230 * l_rxsc
231 * is filled with primary channel SC, not real rxsc.
232 * 0:LSC, 1:USC
233 * type_1(OFDM)
234 * rf_mode
235 * RF bandwidth when RX
236 * l_rxsc(legacy), ht_rxsc
237 * see below RXSC N-series
238 * type_2(Not used)
239 */
240 /*
241 * 8821C, 8822B:
242 * type_0(CCK)
243 * l_rxsc
244 * is filled with primary channel SC, not real rxsc.
245 * 0:LSC, 1:USC
246 * type_1(OFDM)
247 * rf_mode
248 * RF bandwidth when RX
249 * l_rxsc(legacy), ht_rxsc
250 * see below RXSC AC-series
251 * type_2(Not used)
252 */
253
254 if ((*phys & 0xf) == 0) {
255 struct phy_sts_rpt_jgr2_type0 *phys_t0 = (struct phy_sts_rpt_jgr2_type0 *)phys;
256
257 if (DBG_RX_PHYSTATUS_CHINFO) {
258 RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u)\n"
259 , *phys & 0xf
260 , MAC_ARG(get_ta(wlanhdr))
261 , is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
262 , HDATA_RATE(attrib->data_rate)
263 , phys_t0->band, phys_t0->channel, phys_t0->rxsc
264 );
265 }
266
267 } else if ((*phys & 0xf) == 1) {
268 struct phy_sts_rpt_jgr2_type1 *phys_t1 = (struct phy_sts_rpt_jgr2_type1 *)phys;
269 u8 rxsc = (attrib->data_rate > DESC_RATE11M && attrib->data_rate < DESC_RATEMCS0) ? phys_t1->l_rxsc : phys_t1->ht_rxsc;
270 u8 pkt_cch = 0;
271 u8 pkt_bw = CHANNEL_WIDTH_20;
272
273 #if ODM_IC_11N_SERIES_SUPPORT
274 if (phydm->support_ic_type & ODM_IC_11N_SERIES) {
275 /* RXSC N-series */
276 #define RXSC_DUP 0
277 #define RXSC_LSC 1
278 #define RXSC_USC 2
279 #define RXSC_40M 3
280
281 static const s8 cch_offset_by_rxsc[4] = {0, -2, 2, 0};
282
283 if (phys_t1->rf_mode == 0) {
284 pkt_cch = phys_t1->channel;
285 pkt_bw = CHANNEL_WIDTH_20;
286 } else if (phys_t1->rf_mode == 1) {
287 if (rxsc == RXSC_LSC || rxsc == RXSC_USC) {
288 pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
289 pkt_bw = CHANNEL_WIDTH_20;
290 } else if (rxsc == RXSC_40M) {
291 pkt_cch = phys_t1->channel;
292 pkt_bw = CHANNEL_WIDTH_40;
293 }
294 } else
295 rtw_warn_on(1);
296
297 goto type1_end;
298 }
299 #endif /* ODM_IC_11N_SERIES_SUPPORT */
300
301 #if ODM_IC_11AC_SERIES_SUPPORT
302 if (phydm->support_ic_type & ODM_IC_11AC_SERIES) {
303 /* RXSC AC-series */
304 #define RXSC_DUP 0 /* 0: RX from all SC of current rf_mode */
305
306 #define RXSC_LL20M_OF_160M 8 /* 1~8: RX from 20MHz SC */
307 #define RXSC_L20M_OF_160M 6
308 #define RXSC_L20M_OF_80M 4
309 #define RXSC_L20M_OF_40M 2
310 #define RXSC_U20M_OF_40M 1
311 #define RXSC_U20M_OF_80M 3
312 #define RXSC_U20M_OF_160M 5
313 #define RXSC_UU20M_OF_160M 7
314
315 #define RXSC_L40M_OF_160M 12 /* 9~12: RX from 40MHz SC */
316 #define RXSC_L40M_OF_80M 10
317 #define RXSC_U40M_OF_80M 9
318 #define RXSC_U40M_OF_160M 11
319
320 #define RXSC_L80M_OF_160M 14 /* 13~14: RX from 80MHz SC */
321 #define RXSC_U80M_OF_160M 13
322
323 static const s8 cch_offset_by_rxsc[15] = {0, 2, -2, 6, -6, 10, -10, 14, -14, 4, -4, 12, -12, 8, -8};
324
325 if (phys_t1->rf_mode == 0) {
326 /* RF 20MHz */
327 pkt_cch = phys_t1->channel;
328 pkt_bw = CHANNEL_WIDTH_20;
329 goto type1_end;
330 }
331
332 if (rxsc == 0) {
333 /* RF and RX with same BW */
334 if (attrib->data_rate >= DESC_RATEMCS0) {
335 pkt_cch = phys_t1->channel;
336 pkt_bw = phys_t1->rf_mode;
337 }
338 goto type1_end;
339 }
340
341 if ((phys_t1->rf_mode == 1 && rxsc >= 1 && rxsc <= 2) /* RF 40MHz, RX 20MHz */
342 || (phys_t1->rf_mode == 2 && rxsc >= 1 && rxsc <= 4) /* RF 80MHz, RX 20MHz */
343 || (phys_t1->rf_mode == 3 && rxsc >= 1 && rxsc <= 8) /* RF 160MHz, RX 20MHz */
344 ) {
345 pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
346 pkt_bw = CHANNEL_WIDTH_20;
347 } else if ((phys_t1->rf_mode == 2 && rxsc >= 9 && rxsc <= 10) /* RF 80MHz, RX 40MHz */
348 || (phys_t1->rf_mode == 3 && rxsc >= 9 && rxsc <= 12) /* RF 160MHz, RX 40MHz */
349 ) {
350 if (attrib->data_rate >= DESC_RATEMCS0) {
351 pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
352 pkt_bw = CHANNEL_WIDTH_40;
353 }
354 } else if ((phys_t1->rf_mode == 3 && rxsc >= 13 && rxsc <= 14) /* RF 160MHz, RX 80MHz */
355 ) {
356 if (attrib->data_rate >= DESC_RATEMCS0) {
357 pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
358 pkt_bw = CHANNEL_WIDTH_80;
359 }
360 } else
361 rtw_warn_on(1);
362
363 }
364 #endif /* ODM_IC_11AC_SERIES_SUPPORT */
365
366 type1_end:
367 if (DBG_RX_PHYSTATUS_CHINFO) {
368 RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, rf_mode:%u, l_rxsc:%u, ht_rxsc:%u) => %u,%u\n"
369 , *phys & 0xf
370 , MAC_ARG(get_ta(wlanhdr))
371 , is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
372 , HDATA_RATE(attrib->data_rate)
373 , phys_t1->band, phys_t1->channel, phys_t1->rf_mode, phys_t1->l_rxsc, phys_t1->ht_rxsc
374 , pkt_cch, pkt_bw
375 );
376 }
377
378 /* for now, only return cneter channel of 20MHz packet */
379 if (pkt_cch && pkt_bw == CHANNEL_WIDTH_20)
380 attrib->ch = pkt_cch;
381
382 } else {
383 struct phy_sts_rpt_jgr2_type2 *phys_t2 = (struct phy_sts_rpt_jgr2_type2 *)phys;
384
385 if (DBG_RX_PHYSTATUS_CHINFO) {
386 RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u, ht_rxsc:%u)\n"
387 , *phys & 0xf
388 , MAC_ARG(get_ta(wlanhdr))
389 , is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
390 , HDATA_RATE(attrib->data_rate)
391 , phys_t2->band, phys_t2->channel, phys_t2->l_rxsc, phys_t2->ht_rxsc
392 );
393 }
394 }
395 }
396 #endif /* (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) */
397
398 }
399
400 #if defined(CONFIG_RTL8822C) && defined(CONFIG_LPS_PG)
401 void
debug_DACK(struct dm_struct * dm)402 debug_DACK(
403 struct dm_struct *dm
404 )
405 {
406 //P_PHYDM_FUNC dm;
407 //dm = &(SysMib.ODM.Phydm);
408 //PIQK_OFFLOAD_PARM pIQK_info;
409 //pIQK_info= &(SysMib.ODM.IQKParm);
410 u8 i;
411 u32 temp1, temp2, temp3;
412
413 temp1 = odm_get_bb_reg(dm, 0x1860, bMaskDWord);
414 temp2 = odm_get_bb_reg(dm, 0x4160, bMaskDWord);
415 temp3 = odm_get_bb_reg(dm, 0x9b4, bMaskDWord);
416
417 odm_set_bb_reg(dm, 0x9b4, bMaskDWord, 0xdb66db00);
418
419 //pathA
420 odm_set_bb_reg(dm, 0x1830, BIT(30), 0x0);
421 odm_set_bb_reg(dm, 0x1860, 0xfc000000, 0x3c);
422
423 RTW_INFO("path A i\n");
424 //i
425 for (i = 0; i < 0xf; i++) {
426 odm_set_bb_reg(dm, 0x18b0, 0xf0000000, i);
427 RTW_INFO("[0][0][%d] = 0x%08x\n", i, (u16)odm_get_bb_reg(dm,0x2810,0x7fc0000));
428 //pIQK_info->msbk_d[0][0][i] = (u16)odm_get_bb_reg(dm,0x2810,0x7fc0000);
429 }
430 RTW_INFO("path A q\n");
431 //q
432 for (i = 0; i < 0xf; i++) {
433 odm_set_bb_reg(dm, 0x18cc, 0xf0000000, i);
434 RTW_INFO("[0][1][%d] = 0x%08x\n", i, (u16)odm_get_bb_reg(dm,0x283c,0x7fc0000));
435 //pIQK_info->msbk_d[0][1][i] = (u16)odm_get_bb_reg(dm,0x283c,0x7fc0000);
436 }
437 //pathB
438 odm_set_bb_reg(dm, 0x4130, BIT(30), 0x0);
439 odm_set_bb_reg(dm, 0x4160, 0xfc000000, 0x3c);
440
441 RTW_INFO("\npath B i\n");
442 //i
443 for (i = 0; i < 0xf; i++) {
444 odm_set_bb_reg(dm, 0x41b0, 0xf0000000, i);
445 RTW_INFO("[1][0][%d] = 0x%08x\n", i, (u16)odm_get_bb_reg(dm,0x4510,0x7fc0000));
446 //pIQK_info->msbk_d[1][0][i] = (u16)odm_get_bb_reg(dm,0x2810,0x7fc0000);
447 }
448 RTW_INFO("path B q\n");
449 //q
450 for (i = 0; i < 0xf; i++) {
451 odm_set_bb_reg(dm, 0x41cc, 0xf0000000, i);
452 RTW_INFO("[1][1][%d] = 0x%08x\n", i, (u16)odm_get_bb_reg(dm,0x453c,0x7fc0000));
453 //pIQK_info->msbk_d[1][1][i] = (u16)odm_get_bb_reg(dm,0x283c,0x7fc0000);
454 }
455
456 //restore to normal
457 odm_set_bb_reg(dm, 0x1830, BIT(30), 0x1);
458 odm_set_bb_reg(dm, 0x4130, BIT(30), 0x1);
459 odm_set_bb_reg(dm, 0x1860, bMaskDWord, temp1);
460 odm_set_bb_reg(dm, 0x4160, bMaskDWord, temp2);
461 odm_set_bb_reg(dm, 0x9b4, bMaskDWord, temp3);
462
463
464 }
465
466 void
debug_IQK(struct dm_struct * dm,IN u8 idx,IN u8 path)467 debug_IQK(
468 struct dm_struct *dm,
469 IN u8 idx,
470 IN u8 path
471 )
472 {
473 u8 i, ch;
474 u32 tmp;
475 u32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
476
477 RTW_INFO("idx = %d, path = %d\n", idx, path);
478
479 odm_set_bb_reg(dm, 0x1b00, MASKDWORD, 0x8 | path << 1);
480
481 if (idx == TX_IQK) {//TXCFIR
482 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x3);
483 } else {//RXCFIR
484 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x1);
485 }
486 odm_set_bb_reg(dm, R_0x1bd4, BIT(21), 0x1);
487 odm_set_bb_reg(dm, R_0x1bd4, bit_mask_20_16, 0x10);
488 for (i = 0; i <= 16; i++) {
489 odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000001 | i << 2);
490 tmp = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
491 RTW_INFO("iqk_cfir_real[%d][%d][%d] = 0x%x\n", path, idx, i, ((tmp & 0x0fff0000) >> 16));
492 //iqk_info->iqk_cfir_real[ch][path][idx][i] =
493 // (tmp & 0x0fff0000) >> 16;
494 RTW_INFO("iqk_cfir_imag[%d][%d][%d] = 0x%x\n", path, idx, i, (tmp & 0x0fff));
495 //iqk_info->iqk_cfir_imag[ch][path][idx][i] = tmp & 0x0fff;
496 }
497 odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x0);
498 //odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);
499 }
500
501 __odm_func__ void
debug_information_8822c(struct dm_struct * dm)502 debug_information_8822c(
503 struct dm_struct *dm)
504 {
505 struct dm_dpk_info *dpk_info = &dm->dpk_info;
506
507 u32 reg_rf18;
508
509 if (odm_get_bb_reg(dm, R_0x1e7c, BIT(30)))
510 dpk_info->is_tssi_mode = true;
511 else
512 dpk_info->is_tssi_mode = false;
513
514 reg_rf18 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK);
515
516 dpk_info->dpk_band = (u8)((reg_rf18 & BIT(16)) >> 16); /*0/1:G/A*/
517 dpk_info->dpk_ch = (u8)reg_rf18 & 0xff;
518 dpk_info->dpk_bw = (u8)((reg_rf18 & 0x3000) >> 12); /*3/2/1:20/40/80*/
519
520 RTW_INFO("[DPK] TSSI/ Band/ CH/ BW = %d / %s / %d / %s\n",
521 dpk_info->is_tssi_mode, dpk_info->dpk_band == 0 ? "2G" : "5G",
522 dpk_info->dpk_ch,
523 dpk_info->dpk_bw == 3 ? "20M" : (dpk_info->dpk_bw == 2 ? "40M" : "80M"));
524 }
525
526 extern void _dpk_get_coef_8822c(void *dm_void, u8 path);
527
528 __odm_func__ void
debug_reload_data_8822c(void * dm_void)529 debug_reload_data_8822c(
530 void *dm_void)
531 {
532 struct dm_struct *dm = (struct dm_struct *)dm_void;
533 struct dm_dpk_info *dpk_info = &dm->dpk_info;
534
535 u8 path;
536 u32 u32tmp;
537
538 debug_information_8822c(dm);
539
540 for (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {
541
542 RTW_INFO("[DPK] Reload path: 0x%x\n", path);
543
544 odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x8 | (path << 1));
545
546 /*txagc bnd*/
547 if (dpk_info->dpk_band == 0x0)
548 u32tmp = odm_get_bb_reg(dm, R_0x1b60, MASKDWORD);
549 else
550 u32tmp = odm_get_bb_reg(dm, R_0x1b60, MASKDWORD);
551
552 RTW_INFO("[DPK] txagc bnd = 0x%08x\n", u32tmp);
553
554 u32tmp = odm_get_bb_reg(dm, R_0x1b64, MASKBYTE3);
555 RTW_INFO("[DPK] dpk_txagc = 0x%08x\n", u32tmp);
556
557 //debug_coef_write_8822c(dm, path, dpk_info->dpk_path_ok & BIT(path) >> path);
558 _dpk_get_coef_8822c(dm, path);
559
560 //debug_one_shot_8822c(dm, path, DPK_ON);
561
562 odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0xc);
563
564 if (path == RF_PATH_A)
565 u32tmp = odm_get_bb_reg(dm, R_0x1b04, 0x0fffffff);
566 else
567 u32tmp = odm_get_bb_reg(dm, R_0x1b5c, 0x0fffffff);
568
569 RTW_INFO("[DPK] dpk_gs = 0x%08x\n", u32tmp);
570
571 }
572 }
573
odm_lps_pg_debug_8822c(void * dm_void)574 void odm_lps_pg_debug_8822c(void *dm_void)
575 {
576 struct dm_struct *dm = (struct dm_struct *)dm_void;
577
578 debug_DACK(dm);
579 debug_IQK(dm, TX_IQK, RF_PATH_A);
580 debug_IQK(dm, RX_IQK, RF_PATH_A);
581 debug_IQK(dm, TX_IQK, RF_PATH_B);
582 debug_IQK(dm, RX_IQK, RF_PATH_B);
583 debug_reload_data_8822c(dm);
584 }
585 #endif /* defined(CONFIG_RTL8822C) && defined(CONFIG_LPS_PG) */
586
587