1 /****************************************************************************** 2 * 3 * Copyright(c) 2015 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef _RTL8814B_HAL_H_ 16 #define _RTL8814B_HAL_H_ 17 18 #include <osdep_service.h> /* BIT(x) */ 19 #include <drv_types.h> /* PADAPTER */ 20 #include "../hal/halmac/halmac_api.h" /* MAC REG definition */ 21 22 23 #ifdef CONFIG_SUPPORT_TRX_SHARED 24 #define MAX_RECVBUF_SZ 46080 /* 45KB, TX: (256-64)KB */ 25 #else /* !CONFIG_SUPPORT_TRX_SHARED */ 26 #define MAX_RECVBUF_SZ 24576 /* 24KB, TX: 256KB */ 27 #endif /* !CONFIG_SUPPORT_TRX_SHARED */ 28 29 #if 0 30 /* 31 * MAC Register definition 32 */ 33 #define REG_AFE_XTAL_CTRL REG_AFE_CTRL1_8814B /* hal_com.c & phydm */ 34 #define REG_AFE_PLL_CTRL REG_AFE_CTRL2_8814B /* hal_com.c & phydm */ 35 #define REG_MAC_PHY_CTRL REG_AFE_CTRL3_8814B /* phydm only */ 36 #endif 37 #define REG_LEDCFG0 REG_LED_CFG_8814B /* rtw_mp.c */ 38 #if 0 39 #define MSR (REG_CR_8814B + 2) /* rtw_mp.c & hal_com.c */ 40 #define MSR1 REG_CR_EXT_8814B /* rtw_mp.c & hal_com.c */ 41 #endif 42 #define REG_C2HEVT_MSG_NORMAL 0x1A0 /* hal_com.c */ 43 #if 0 44 #define REG_C2HEVT_CLEAR 0x1AF /* hal_com.c */ 45 46 #define REG_GPIO_PIN_CTRL_2 REG_GPIO_EXT_CTRL_8814B /* hal_com.c */ 47 #endif 48 #define REG_WKFMCAM_NUM REG_WKFMCAM_CMD_8814B /* hal_com.c: WOWLAN */ 49 #define REG_WOWLAN_WAKE_REASON 0x01C7 /* hal_com.c: WOWLAN */ 50 #define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL_8814B + 2) /* hal_com.c: WOWLAN */ 51 #define REG_RXPKT_NUM REG_RXDMA_CTRL_8814B /* hal_com.c: WOWLAN */ 52 53 /* RXERR_RPT, for rtw_mp.c */ 54 #define RXERR_TYPE_OFDM_PPDU 0 55 #define RXERR_TYPE_OFDM_FALSE_ALARM 2 56 #define RXERR_TYPE_OFDM_MPDU_OK 0 57 #define RXERR_TYPE_OFDM_MPDU_FAIL 1 58 #define RXERR_TYPE_CCK_PPDU 3 59 #define RXERR_TYPE_CCK_FALSE_ALARM 5 60 #define RXERR_TYPE_CCK_MPDU_OK 3 61 #define RXERR_TYPE_CCK_MPDU_FAIL 4 62 #define RXERR_TYPE_HT_PPDU 8 63 #define RXERR_TYPE_HT_FALSE_ALARM 9 64 #define RXERR_TYPE_HT_MPDU_TOTAL 6 65 #define RXERR_TYPE_HT_MPDU_OK 6 66 #define RXERR_TYPE_HT_MPDU_FAIL 7 67 #define RXERR_TYPE_RX_FULL_DROP 10 68 69 #define RXERR_COUNTER_MASK BIT_MASK_RPT_COUNTER_8814B 70 #define RXERR_RPT_RST BIT_RXERR_RPT_RST_8814B 71 #define _RXERR_RPT_SEL(type) (BIT_RXERR_RPT_SEL_V1_3_0_8814B(type) \ 72 | ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8814B : 0)) 73 74 /* hal_com.c:rtw_lps_state_chk() */ 75 #define BIT_PWRBIT_OW_EN BIT_WMAC_TCRPWRMGT_HWDATA_EN_8814B 76 77 /* 78 * BB Register definition 79 */ 80 #define rPMAC_Reset 0x100 /* hal_mp.c */ 81 82 #define rFPGA0_RFMOD 0x800 83 #define rFPGA0_TxInfo 0x804 84 #define rOFDMCCKEN_Jaguar 0x808 /* hal_mp.c */ 85 #define rFPGA0_TxGainStage 0x80C /* phydm only */ 86 #define rFPGA0_XA_HSSIParameter1 0x820 /* hal_mp.c */ 87 #define rFPGA0_XA_HSSIParameter2 0x824 /* hal_mp.c */ 88 #define rFPGA0_XB_HSSIParameter1 0x828 /* hal_mp.c */ 89 #define rFPGA0_XB_HSSIParameter2 0x82C /* hal_mp.c */ 90 #define rTxAGC_B_Rate18_06 0x830 91 #define rTxAGC_B_Rate54_24 0x834 92 #define rTxAGC_B_CCK1_55_Mcs32 0x838 93 #define rCCAonSec_Jaguar 0x838 /* hal_mp.c */ 94 #define rTxAGC_B_Mcs03_Mcs00 0x83C 95 #define rTxAGC_B_Mcs07_Mcs04 0x848 96 #define rTxAGC_B_Mcs11_Mcs08 0x84C 97 #define rFPGA0_XA_RFInterfaceOE 0x860 98 #define rFPGA0_XB_RFInterfaceOE 0x864 99 #define rTxAGC_B_Mcs15_Mcs12 0x868 100 #define rTxAGC_B_CCK11_A_CCK2_11 0x86C 101 #define rFPGA0_XAB_RFInterfaceSW 0x870 102 #define rFPGA0_XAB_RFParameter 0x878 103 #define rFPGA0_AnalogParameter4 0x88C /* hal_mp.c & phydm */ 104 #define rFPGA0_XB_LSSIReadBack 0x8A4 /* phydm */ 105 #define rHSSIRead_Jaguar 0x8B0 /* RF read addr (rtl8814b_phy.c) */ 106 107 #define rC_TxScale_Jaguar2 0x181C /* Pah_C TX scaling factor (hal_mp.c) */ 108 #define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C (hal_mp.c) */ 109 110 #define rFPGA1_TxInfo 0x90C /* hal_mp.c */ 111 #define rSingleTone_ContTx_Jaguar 0x914 /* hal_mp.c */ 112 /* TX BeamForming */ 113 #define REG_BB_TX_PATH_SEL_1_8814B 0x93C /* rtl8814b_phy.c */ 114 #define REG_BB_TX_PATH_SEL_2_8814B 0x940 /* rtl8814b_phy.c */ 115 116 /* TX BeamForming */ 117 #define REG_BB_TXBF_ANT_SET_BF1_8814B 0x19AC /* rtl8814b_phy.c */ 118 #define REG_BB_TXBF_ANT_SET_BF0_8814B 0x19B4 /* rtl8814b_phy.c */ 119 120 #define rCCK0_System 0xA00 121 #define rCCK0_AFESetting 0xA04 122 123 #define rCCK0_DSPParameter2 0xA1C 124 #define rCCK0_TxFilter1 0xA20 125 #define rCCK0_TxFilter2 0xA24 126 #define rCCK0_DebugPort 0xA28 127 #define rCCK0_FalseAlarmReport 0xA2C 128 129 #define rD_TxScale_Jaguar2 0x1A1C /* Path_D TX scaling factor (hal_mp.c) */ 130 #define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D (hal_mp.c) */ 131 132 #define rOFDM0_TRxPathEnable 0xC04 133 #define rOFDM0_TRMuxPar 0xC08 134 #define rA_TxScale_Jaguar 0xC1C /* Pah_A TX scaling factor (hal_mp.c) */ 135 #define rOFDM0_RxDetector1 0xC30 /* rtw_mp.c */ 136 #define rOFDM0_ECCAThreshold 0xC4C /* phydm only */ 137 #define rOFDM0_XAAGCCore1 0xC50 /* phydm only */ 138 #define rA_IGI_Jaguar 0xC50 /* Initial Gain for path-A (hal_mp.c) */ 139 #define rOFDM0_XBAGCCore1 0xC58 /* phydm only */ 140 #define rOFDM0_XATxIQImbalance 0xC80 /* phydm only */ 141 #define rA_LSSIWrite_Jaguar 0xC90 /* RF write addr, LSSI Parameter (rtl8814b_phy.c) */ 142 143 #define rOFDM1_LSTF 0xD00 144 #define rOFDM1_TRxPathEnable 0xD04 /* hal_mp.c */ 145 #define rA_PIRead_Jaguar 0xD04 /* RF readback with PI (rtl8814b_phy.c) */ 146 #define rA_SIRead_Jaguar 0xD08 /* RF readback with SI (rtl8814b_phy.c) */ 147 #define rB_PIRead_Jaguar 0xD44 /* RF readback with PI (rtl8814b_phy.c) */ 148 #define rB_SIRead_Jaguar 0xD48 /* RF readback with SI (rtl8814b_phy.c) */ 149 150 #define rTxAGC_A_Rate18_06 0xE00 151 #define rTxAGC_A_Rate54_24 0xE04 152 #define rTxAGC_A_CCK1_Mcs32 0xE08 153 #define rTxAGC_A_Mcs03_Mcs00 0xE10 154 #define rTxAGC_A_Mcs07_Mcs04 0xE14 155 #define rTxAGC_A_Mcs11_Mcs08 0xE18 156 #define rTxAGC_A_Mcs15_Mcs12 0xE1C 157 #define rB_TxScale_Jaguar 0xE1C /* Path_B TX scaling factor (hal_mp.c) */ 158 #define rB_IGI_Jaguar 0xE50 /* Initial Gain for path-B (hal_mp.c) */ 159 #define rB_LSSIWrite_Jaguar 0xE90 /* RF write addr, LSSI Parameter (rtl8814b_phy.c) */ 160 /* RFE */ 161 #define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */ 162 #define rB_RFE_Pinmux_Jaguar 0xEB0 /* Path_B RFE control pinmux */ 163 #define rA_RFE_Inv_Jaguar 0xCB4 /* Path_A RFE cotrol */ 164 #define rB_RFE_Inv_Jaguar 0xEB4 /* Path_B RFE control */ 165 #define rA_RFE_Jaguar 0xCB8 /* Path_A RFE cotrol */ 166 #define rB_RFE_Jaguar 0xEB8 /* Path_B RFE control */ 167 #define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */ 168 #define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */ 169 #define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */ 170 #define bMask_RFEInv_Jaguar 0x3FF00000 171 #define bMask_AntselPathFollow_Jaguar 0x00030000 172 173 #define rC_RFE_Pinmux_Jaguar 0x18B4 /* Path_C RFE cotrol pinmux*/ 174 #define rD_RFE_Pinmux_Jaguar 0x1AB4 /* Path_D RFE cotrol pinmux*/ 175 #define rA_RFE_Sel_Jaguar2 0x1990 176 177 /* Page1(0x100) */ 178 #define bBBResetB 0x100 179 180 /* Page8(0x800) */ 181 #define bCCKEn 0x1000000 182 #define bOFDMEn 0x2000000 183 /* Reg 0x80C rFPGA0_TxGainStage */ 184 #define bXBTxAGC 0xF00 185 #define bXCTxAGC 0xF000 186 #define bXDTxAGC 0xF0000 187 188 /* PageA(0xA00) */ 189 #define bCCKBBMode 0x3 190 191 #define bCCKScramble 0x8 192 #define bCCKTxRate 0x3000 193 194 /* General */ 195 #define bMaskByte0 0xFF /* mp, rtw_odm.c & phydm */ 196 #define bMaskByte1 0xFF00 /* hal_mp.c & phydm */ 197 #define bMaskByte2 0xFF0000 /* hal_mp.c & phydm */ 198 #define bMaskByte3 0xFF000000 /* hal_mp.c & phydm */ 199 #define bMaskHWord 0xFFFF0000 /* hal_com.c, rtw_mp.c */ 200 #define bMaskLWord 0x0000FFFF /* mp, hal_com.c & phydm */ 201 #define bMaskDWord 0xFFFFFFFF /* mp, hal, rtw_odm.c & phydm */ 202 203 #define bEnable 0x1 /* hal_mp.c, rtw_mp.c */ 204 #define bDisable 0x0 /* rtw_mp.c */ 205 206 #define MAX_STALL_TIME 50 /* unit: us, hal_com_phycfg.c */ 207 208 #define Rx_Smooth_Factor 20 /* phydm only */ 209 210 /* 211 * RF Register definition 212 */ 213 #define RF_AC 0x00 214 #define RF_AC_Jaguar 0x00 /* hal_mp.c */ 215 #define RF_CHNLBW 0x18 /* rtl8814b_phy.c */ 216 #define RF_ModeTableAddr 0x30 /* rtl8814b_phy.c */ 217 #define RF_ModeTableData0 0x31 /* rtl8814b_phy.c */ 218 #define RF_ModeTableData1 0x32 /* rtl8814b_phy.c */ 219 #define RF_0x52 0x52 220 #define RF_WeLut_Jaguar 0xEF /* rtl8814b_phy.c */ 221 222 /* General Functions */ 223 void rtl8814b_init_hal_spec(PADAPTER); /* hal/hal_com.c */ 224 225 #ifdef CONFIG_MP_INCLUDED 226 /* MP Functions */ 227 #include <rtw_mp.h> /* struct mp_priv */ 228 void rtl8814b_prepare_mp_txdesc(PADAPTER, struct mp_priv *); /* rtw_mp.c */ 229 void rtl8814b_mp_config_rfpath(PADAPTER); /* hal_mp.c */ 230 #endif 231 void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus); 232 233 #ifdef CONFIG_USB_HCI 234 #include <rtl8814bu_hal.h> 235 #elif defined(CONFIG_PCI_HCI) 236 #include <rtl8814be_hal.h> 237 #endif 238 239 #endif /* _RTL8814B_HAL_H_ */ 240