1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __RTL8703B_SPEC_H__ 16 #define __RTL8703B_SPEC_H__ 17 18 #include <drv_conf.h> 19 20 21 #define HAL_NAV_UPPER_UNIT_8703B 128 /* micro-second */ 22 23 /* ----------------------------------------------------- 24 * 25 * 0x0000h ~ 0x00FFh System Configuration 26 * 27 * ----------------------------------------------------- */ 28 #define REG_SYS_ISO_CTRL_8703B 0x0000 /* 2 Byte */ 29 #define REG_SYS_FUNC_EN_8703B 0x0002 /* 2 Byte */ 30 #define REG_APS_FSMCO_8703B 0x0004 /* 4 Byte */ 31 #define REG_SYS_CLKR_8703B 0x0008 /* 2 Byte */ 32 #define REG_9346CR_8703B 0x000A /* 2 Byte */ 33 #define REG_EE_VPD_8703B 0x000C /* 2 Byte */ 34 #define REG_AFE_MISC_8703B 0x0010 /* 1 Byte */ 35 #define REG_SPS0_CTRL_8703B 0x0011 /* 7 Byte */ 36 #define REG_SPS_OCP_CFG_8703B 0x0018 /* 4 Byte */ 37 #define REG_RSV_CTRL_8703B 0x001C /* 3 Byte */ 38 #define REG_RF_CTRL_8703B 0x001F /* 1 Byte */ 39 #define REG_LPLDO_CTRL_8703B 0x0023 /* 1 Byte */ 40 #define REG_AFE_XTAL_CTRL_8703B 0x0024 /* 4 Byte */ 41 #define REG_AFE_PLL_CTRL_8703B 0x0028 /* 4 Byte */ 42 #define REG_MAC_PLL_CTRL_EXT_8703B 0x002c /* 4 Byte */ 43 #define REG_EFUSE_CTRL_8703B 0x0030 44 #define REG_EFUSE_TEST_8703B 0x0034 45 #define REG_PWR_DATA_8703B 0x0038 46 #define REG_CAL_TIMER_8703B 0x003C 47 #define REG_ACLK_MON_8703B 0x003E 48 #define REG_GPIO_MUXCFG_8703B 0x0040 49 #define REG_GPIO_IO_SEL_8703B 0x0042 50 #define REG_MAC_PINMUX_CFG_8703B 0x0043 51 #define REG_GPIO_PIN_CTRL_8703B 0x0044 52 #define REG_GPIO_INTM_8703B 0x0048 53 #define REG_LEDCFG0_8703B 0x004C 54 #define REG_LEDCFG1_8703B 0x004D 55 #define REG_LEDCFG2_8703B 0x004E 56 #define REG_LEDCFG3_8703B 0x004F 57 #define REG_FSIMR_8703B 0x0050 58 #define REG_FSISR_8703B 0x0054 59 #define REG_HSIMR_8703B 0x0058 60 #define REG_HSISR_8703B 0x005c 61 #define REG_GPIO_EXT_CTRL 0x0060 62 #define REG_PAD_CTRL1_8703B 0x0064 63 #define REG_MULTI_FUNC_CTRL_8703B 0x0068 64 #define REG_GPIO_STATUS_8703B 0x006C 65 #define REG_SDIO_CTRL_8703B 0x0070 66 #define REG_OPT_CTRL_8703B 0x0074 67 #define REG_AFE_CTRL_4_8703B 0x0078 68 #define REG_MCUFWDL_8703B 0x0080 69 #define REG_HMEBOX_DBG_0_8703B 0x0088 70 #define REG_HMEBOX_DBG_1_8703B 0x008A 71 #define REG_HMEBOX_DBG_2_8703B 0x008C 72 #define REG_HMEBOX_DBG_3_8703B 0x008E 73 #define REG_HIMR0_8703B 0x00B0 74 #define REG_HISR0_8703B 0x00B4 75 #define REG_HIMR1_8703B 0x00B8 76 #define REG_HISR1_8703B 0x00BC 77 #define REG_PMC_DBG_CTRL2_8703B 0x00CC 78 #define REG_EFUSE_BURN_GNT_8703B 0x00CF 79 #define REG_HPON_FSM_8703B 0x00EC 80 #define REG_SYS_CFG_8703B 0x00F0 81 #define REG_SYS_CFG1_8703B 0x00FC 82 #define REG_ROM_VERSION 0x00FD 83 84 /* ----------------------------------------------------- 85 * 86 * 0x0100h ~ 0x01FFh MACTOP General Configuration 87 * 88 * ----------------------------------------------------- */ 89 #define REG_C2HEVT_CMD_ID_8703B 0x01A0 90 #define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 91 #define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 92 #define REG_C2HEVT_CMD_LEN_8703B 0x01AE 93 #define REG_C2HEVT_CMD_LEN_88XX REG_C2HEVT_CMD_LEN_8703B 94 #define REG_C2HEVT_CLEAR_8703B 0x01AF 95 #define REG_MCUTST_1_8703B 0x01C0 96 #define REG_WOWLAN_WAKE_REASON 0x01C7 97 #define REG_FMETHR_8703B 0x01C8 98 #define REG_HMETFR_8703B 0x01CC 99 #define REG_HMEBOX_0_8703B 0x01D0 100 #define REG_HMEBOX_1_8703B 0x01D4 101 #define REG_HMEBOX_2_8703B 0x01D8 102 #define REG_HMEBOX_3_8703B 0x01DC 103 #define REG_LLT_INIT_8703B 0x01E0 104 #define REG_HMEBOX_EXT0_8703B 0x01F0 105 #define REG_HMEBOX_EXT1_8703B 0x01F4 106 #define REG_HMEBOX_EXT2_8703B 0x01F8 107 #define REG_HMEBOX_EXT3_8703B 0x01FC 108 109 /* ----------------------------------------------------- 110 * 111 * 0x0200h ~ 0x027Fh TXDMA Configuration 112 * 113 * ----------------------------------------------------- */ 114 #define REG_RQPN_8703B 0x0200 115 #define REG_FIFOPAGE_8703B 0x0204 116 #define REG_DWBCN0_CTRL_8703B REG_TDECTRL 117 #define REG_TXDMA_OFFSET_CHK_8703B 0x020C 118 #define REG_TXDMA_STATUS_8703B 0x0210 119 #define REG_RQPN_NPQ_8703B 0x0214 120 #define REG_DWBCN1_CTRL_8703B 0x0228 121 122 123 /* ----------------------------------------------------- 124 * 125 * 0x0280h ~ 0x02FFh RXDMA Configuration 126 * 127 * ----------------------------------------------------- */ 128 #define REG_RXDMA_AGG_PG_TH_8703B 0x0280 129 #define REG_FW_UPD_RDPTR_8703B 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */ 130 #define REG_RXDMA_CONTROL_8703B 0x0286 /* Control the RX DMA. */ 131 #define REG_RXPKT_NUM_8703B 0x0287 /* The number of packets in RXPKTBUF. */ 132 #define REG_RXDMA_STATUS_8703B 0x0288 133 #define REG_RXDMA_MODE_CTRL_8703B 0x0290 134 #define REG_EARLY_MODE_CONTROL_8703B 0x02BC 135 #define REG_RSVD5_8703B 0x02F0 136 #define REG_RSVD6_8703B 0x02F4 137 138 /* ----------------------------------------------------- 139 * 140 * 0x0300h ~ 0x03FFh PCIe 141 * 142 * ----------------------------------------------------- */ 143 #define REG_PCIE_CTRL_REG_8703B 0x0300 144 #define REG_INT_MIG_8703B 0x0304 /* Interrupt Migration */ 145 #define REG_BCNQ_DESA_8703B 0x0308 /* TX Beacon Descriptor Address */ 146 #define REG_HQ_DESA_8703B 0x0310 /* TX High Queue Descriptor Address */ 147 #define REG_MGQ_DESA_8703B 0x0318 /* TX Manage Queue Descriptor Address */ 148 #define REG_VOQ_DESA_8703B 0x0320 /* TX VO Queue Descriptor Address */ 149 #define REG_VIQ_DESA_8703B 0x0328 /* TX VI Queue Descriptor Address */ 150 #define REG_BEQ_DESA_8703B 0x0330 /* TX BE Queue Descriptor Address */ 151 #define REG_BKQ_DESA_8703B 0x0338 /* TX BK Queue Descriptor Address */ 152 #define REG_RX_DESA_8703B 0x0340 /* RX Queue Descriptor Address */ 153 #define REG_DBI_WDATA_8703B 0x0348 /* DBI Write Data */ 154 #define REG_DBI_RDATA_8703B 0x034C /* DBI Read Data */ 155 #define REG_DBI_ADDR_8703B 0x0350 /* DBI Address */ 156 #define REG_DBI_FLAG_8703B 0x0352 /* DBI Read/Write Flag */ 157 #define REG_MDIO_WDATA_8703B 0x0354 /* MDIO for Write PCIE PHY */ 158 #define REG_MDIO_RDATA_8703B 0x0356 /* MDIO for Reads PCIE PHY */ 159 #define REG_MDIO_CTL_8703B 0x0358 /* MDIO for Control */ 160 #define REG_DBG_SEL_8703B 0x0360 /* Debug Selection Register */ 161 #define REG_PCIE_HRPWM_8703B 0x0361 /* PCIe RPWM */ 162 #define REG_PCIE_HCPWM_8703B 0x0363 /* PCIe CPWM */ 163 #define REG_PCIE_MULTIFET_CTRL_8703B 0x036A /* PCIE Multi-Fethc Control */ 164 165 /* ----------------------------------------------------- 166 * 167 * 0x0400h ~ 0x047Fh Protocol Configuration 168 * 169 * ----------------------------------------------------- */ 170 #define REG_VOQ_INFORMATION_8703B 0x0400 171 #define REG_VIQ_INFORMATION_8703B 0x0404 172 #define REG_BEQ_INFORMATION_8703B 0x0408 173 #define REG_BKQ_INFORMATION_8703B 0x040C 174 #define REG_MGQ_INFORMATION_8703B 0x0410 175 #define REG_HGQ_INFORMATION_8703B 0x0414 176 #define REG_BCNQ_INFORMATION_8703B 0x0418 177 #define REG_TXPKT_EMPTY_8703B 0x041A 178 179 #define REG_FWHW_TXQ_CTRL_8703B 0x0420 180 #define REG_HWSEQ_CTRL_8703B 0x0423 181 #define REG_TXPKTBUF_BCNQ_BDNY_8703B 0x0424 182 #define REG_TXPKTBUF_MGQ_BDNY_8703B 0x0425 183 #define REG_LIFECTRL_CTRL_8703B 0x0426 184 #define REG_MULTI_BCNQ_OFFSET_8703B 0x0427 185 #define REG_SPEC_SIFS_8703B 0x0428 186 #define REG_RL_8703B 0x042A 187 #define REG_TXBF_CTRL_8703B 0x042C 188 #define REG_DARFRC_8703B 0x0430 189 #define REG_RARFRC_8703B 0x0438 190 #define REG_RRSR_8703B 0x0440 191 #define REG_ARFR0_8703B 0x0444 192 #define REG_ARFR1_8703B 0x044C 193 #define REG_CCK_CHECK_8703B 0x0454 194 #define REG_AMPDU_MAX_TIME_8703B 0x0456 195 #define REG_TXPKTBUF_BCNQ_BDNY1_8703B 0x0457 196 197 #define REG_AMPDU_MAX_LENGTH_8703B 0x0458 198 #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8703B 0x045D 199 #define REG_NDPA_OPT_CTRL_8703B 0x045F 200 #define REG_FAST_EDCA_CTRL_8703B 0x0460 201 #define REG_RD_RESP_PKT_TH_8703B 0x0463 202 #define REG_DATA_SC_8703B 0x0483 203 #ifdef CONFIG_WOWLAN 204 #define REG_TXPKTBUF_IV_LOW 0x0484 205 #define REG_TXPKTBUF_IV_HIGH 0x0488 206 #endif 207 #define REG_TXRPT_START_OFFSET 0x04AC 208 #define REG_POWER_STAGE1_8703B 0x04B4 209 #define REG_POWER_STAGE2_8703B 0x04B8 210 #define REG_AMPDU_BURST_MODE_8703B 0x04BC 211 #define REG_PKT_VO_VI_LIFE_TIME_8703B 0x04C0 212 #define REG_PKT_BE_BK_LIFE_TIME_8703B 0x04C2 213 #define REG_STBC_SETTING_8703B 0x04C4 214 #define REG_HT_SINGLE_AMPDU_8703B 0x04C7 215 #define REG_PROT_MODE_CTRL_8703B 0x04C8 216 #define REG_MAX_AGGR_NUM_8703B 0x04CA 217 #define REG_RTS_MAX_AGGR_NUM_8703B 0x04CB 218 #define REG_BAR_MODE_CTRL_8703B 0x04CC 219 #define REG_RA_TRY_RATE_AGG_LMT_8703B 0x04CF 220 #define REG_MACID_PKT_DROP0_8703B 0x04D0 221 #define REG_MACID_PKT_SLEEP_8703B 0x04D4 222 223 /* ----------------------------------------------------- 224 * 225 * 0x0500h ~ 0x05FFh EDCA Configuration 226 * 227 * ----------------------------------------------------- */ 228 #define REG_EDCA_VO_PARAM_8703B 0x0500 229 #define REG_EDCA_VI_PARAM_8703B 0x0504 230 #define REG_EDCA_BE_PARAM_8703B 0x0508 231 #define REG_EDCA_BK_PARAM_8703B 0x050C 232 #define REG_BCNTCFG_8703B 0x0510 233 #define REG_PIFS_8703B 0x0512 234 #define REG_RDG_PIFS_8703B 0x0513 235 #define REG_SIFS_CTX_8703B 0x0514 236 #define REG_SIFS_TRX_8703B 0x0516 237 #define REG_AGGR_BREAK_TIME_8703B 0x051A 238 #define REG_SLOT_8703B 0x051B 239 #define REG_TX_PTCL_CTRL_8703B 0x0520 240 #define REG_TXPAUSE_8703B 0x0522 241 #define REG_DIS_TXREQ_CLR_8703B 0x0523 242 #define REG_RD_CTRL_8703B 0x0524 243 /* 244 * Format for offset 540h-542h: 245 * [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. 246 * [7:4]: Reserved. 247 * [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. 248 * [23:20]: Reserved 249 * Description: 250 * | 251 * |<--Setup--|--Hold------------>| 252 * --------------|---------------------- 253 * | 254 * TBTT 255 * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. 256 * Described by Designer Tim and Bruce, 2011-01-14. 257 * */ 258 #define REG_TBTT_PROHIBIT_8703B 0x0540 259 #define REG_RD_NAV_NXT_8703B 0x0544 260 #define REG_NAV_PROT_LEN_8703B 0x0546 261 #define REG_BCN_CTRL_8703B 0x0550 262 #define REG_BCN_CTRL_1_8703B 0x0551 263 #define REG_MBID_NUM_8703B 0x0552 264 #define REG_DUAL_TSF_RST_8703B 0x0553 265 #define REG_BCN_INTERVAL_8703B 0x0554 266 #define REG_DRVERLYINT_8703B 0x0558 267 #define REG_BCNDMATIM_8703B 0x0559 268 #define REG_ATIMWND_8703B 0x055A 269 #define REG_USTIME_TSF_8703B 0x055C 270 #define REG_BCN_MAX_ERR_8703B 0x055D 271 #define REG_RXTSF_OFFSET_CCK_8703B 0x055E 272 #define REG_RXTSF_OFFSET_OFDM_8703B 0x055F 273 #define REG_TSFTR_8703B 0x0560 274 #define REG_CTWND_8703B 0x0572 275 #define REG_SECONDARY_CCA_CTRL_8703B 0x0577 276 #define REG_PSTIMER_8703B 0x0580 277 #define REG_TIMER0_8703B 0x0584 278 #define REG_TIMER1_8703B 0x0588 279 #define REG_ACMHWCTRL_8703B 0x05C0 280 #define REG_SCH_TXCMD_8703B 0x05F8 281 282 /* ----------------------------------------------------- 283 * 284 * 0x0600h ~ 0x07FFh WMAC Configuration 285 * 286 * ----------------------------------------------------- */ 287 #define REG_MAC_CR_8703B 0x0600 288 #define REG_TCR_8703B 0x0604 289 #define REG_RCR_8703B 0x0608 290 #define REG_RX_PKT_LIMIT_8703B 0x060C 291 #define REG_RX_DLK_TIME_8703B 0x060D 292 #define REG_RX_DRVINFO_SZ_8703B 0x060F 293 294 #define REG_MACID_8703B 0x0610 295 #define REG_BSSID_8703B 0x0618 296 #define REG_MAR_8703B 0x0620 297 #define REG_MBIDCAMCFG_8703B 0x0628 298 #define REG_WOWLAN_GTK_DBG1 0x630 299 #define REG_WOWLAN_GTK_DBG2 0x634 300 301 #define REG_USTIME_EDCA_8703B 0x0638 302 #define REG_MAC_SPEC_SIFS_8703B 0x063A 303 #define REG_RESP_SIFP_CCK_8703B 0x063C 304 #define REG_RESP_SIFS_OFDM_8703B 0x063E 305 #define REG_ACKTO_8703B 0x0640 306 #define REG_CTS2TO_8703B 0x0641 307 #define REG_EIFS_8703B 0x0642 308 309 #define REG_NAV_UPPER_8703B 0x0652 /* unit of 128 */ 310 #define REG_TRXPTCL_CTL_8703B 0x0668 311 312 /* Security */ 313 #define REG_CAMCMD_8703B 0x0670 314 #define REG_CAMWRITE_8703B 0x0674 315 #define REG_CAMREAD_8703B 0x0678 316 #define REG_CAMDBG_8703B 0x067C 317 #define REG_SECCFG_8703B 0x0680 318 319 /* Power */ 320 #define REG_WOW_CTRL_8703B 0x0690 321 #define REG_PS_RX_INFO_8703B 0x0692 322 #define REG_UAPSD_TID_8703B 0x0693 323 #define REG_WKFMCAM_CMD_8703B 0x0698 324 #define REG_WKFMCAM_NUM_8703B 0x0698 325 #define REG_WKFMCAM_RWD_8703B 0x069C 326 #define REG_RXFLTMAP0_8703B 0x06A0 327 #define REG_RXFLTMAP1_8703B 0x06A2 328 #define REG_RXFLTMAP2_8703B 0x06A4 329 #define REG_BCN_PSR_RPT_8703B 0x06A8 330 #define REG_BT_COEX_TABLE_8703B 0x06C0 331 #define REG_BFMER0_INFO_8703B 0x06E4 332 #define REG_BFMER1_INFO_8703B 0x06EC 333 #define REG_CSI_RPT_PARAM_BW20_8703B 0x06F4 334 #define REG_CSI_RPT_PARAM_BW40_8703B 0x06F8 335 #define REG_CSI_RPT_PARAM_BW80_8703B 0x06FC 336 337 /* Hardware Port 2 */ 338 #define REG_MACID1_8703B 0x0700 339 #define REG_BSSID1_8703B 0x0708 340 #define REG_BFMEE_SEL_8703B 0x0714 341 #define REG_SND_PTCL_CTRL_8703B 0x0718 342 343 /* LTE_COEX */ 344 #define REG_LTECOEX_CTRL 0x07C0 345 #define REG_LTECOEX_WRITE_DATA 0x07C4 346 #define REG_LTECOEX_READ_DATA 0x07C8 347 #define REG_LTECOEX_PATH_CONTROL 0x70 348 349 /* ************************************************************ 350 * SDIO Bus Specification 351 * ************************************************************ */ 352 353 /* ----------------------------------------------------- 354 * SDIO CMD Address Mapping 355 * ----------------------------------------------------- */ 356 357 /* ----------------------------------------------------- 358 * I/O bus domain (Host) 359 * ----------------------------------------------------- */ 360 361 /* ----------------------------------------------------- 362 * SDIO register 363 * ----------------------------------------------------- */ 364 #define SDIO_REG_HCPWM1_8703B 0x025 /* HCI Current Power Mode 1 */ 365 366 367 /* **************************************************************************** 368 * 8703 Regsiter Bit and Content definition 369 * **************************************************************************** */ 370 371 #define BIT_USB_RXDMA_AGG_EN BIT(31) 372 #define RXDMA_AGG_MODE_EN BIT(1) 373 374 #ifdef CONFIG_WOWLAN 375 #define RXPKT_RELEASE_POLL BIT(16) 376 #define RXDMA_IDLE BIT(17) 377 #define RW_RELEASE_EN BIT(18) 378 #endif 379 380 /* 2 HSISR 381 * interrupt mask which needs to clear */ 382 #define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\ 383 HSISR_SPS_OCP_INT |\ 384 HSISR_RON_INT |\ 385 HSISR_PDNINT |\ 386 HSISR_GPIO9_INT) 387 388 389 /* ---------------------------------------------------------------------------- 390 * 8703B REG_CCK_CHECK (offset 0x454) 391 * ---------------------------------------------------------------------------- */ 392 #define BIT_BCN_PORT_SEL BIT(5) 393 394 #ifdef CONFIG_RF_POWER_TRIM 395 396 #ifdef CONFIG_RTL8703B 397 #define EEPROM_RF_GAIN_OFFSET 0xC1 398 #endif 399 400 #define EEPROM_RF_GAIN_VAL 0x1F6 401 #endif /*CONFIG_RF_POWER_TRIM*/ 402 403 404 /* ---------------------------------------------------------------------------- 405 * 8195 IMR/ISR bits (offset 0xB0, 8bits) 406 * ---------------------------------------------------------------------------- */ 407 #define IMR_DISABLED_8703B 0 408 /* IMR DW0(0x00B0-00B3) Bit 0-31 */ 409 #define IMR_TIMER2_8703B BIT(31) /* Timeout interrupt 2 */ 410 #define IMR_TIMER1_8703B BIT(30) /* Timeout interrupt 1 */ 411 #define IMR_PSTIMEOUT_8703B BIT(29) /* Power Save Time Out Interrupt */ 412 #define IMR_GTINT4_8703B BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ 413 #define IMR_GTINT3_8703B BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ 414 #define IMR_TXBCN0ERR_8703B BIT(26) /* Transmit Beacon0 Error */ 415 #define IMR_TXBCN0OK_8703B BIT(25) /* Transmit Beacon0 OK */ 416 #define IMR_TSF_BIT32_TOGGLE_8703B BIT(24) /* TSF Timer BIT32 toggle indication interrupt */ 417 #define IMR_BCNDMAINT0_8703B BIT(20) /* Beacon DMA Interrupt 0 */ 418 #define IMR_BCNDERR0_8703B BIT(16) /* Beacon Queue DMA OK0 */ 419 #define IMR_HSISR_IND_ON_INT_8703B BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ 420 #define IMR_BCNDMAINT_E_8703B BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ 421 #define IMR_ATIMEND_8703B BIT(12) /* CTWidnow End or ATIM Window End */ 422 #define IMR_C2HCMD_8703B BIT(10) /* CPU to Host Command INT Status, Write 1 clear */ 423 #define IMR_CPWM2_8703B BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */ 424 #define IMR_CPWM_8703B BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */ 425 #define IMR_HIGHDOK_8703B BIT(7) /* High Queue DMA OK */ 426 #define IMR_MGNTDOK_8703B BIT(6) /* Management Queue DMA OK */ 427 #define IMR_BKDOK_8703B BIT(5) /* AC_BK DMA OK */ 428 #define IMR_BEDOK_8703B BIT(4) /* AC_BE DMA OK */ 429 #define IMR_VIDOK_8703B BIT(3) /* AC_VI DMA OK */ 430 #define IMR_VODOK_8703B BIT(2) /* AC_VO DMA OK */ 431 #define IMR_RDU_8703B BIT(1) /* Rx Descriptor Unavailable */ 432 #define IMR_ROK_8703B BIT(0) /* Receive DMA OK */ 433 434 /* IMR DW1(0x00B4-00B7) Bit 0-31 */ 435 #define IMR_BCNDMAINT7_8703B BIT(27) /* Beacon DMA Interrupt 7 */ 436 #define IMR_BCNDMAINT6_8703B BIT(26) /* Beacon DMA Interrupt 6 */ 437 #define IMR_BCNDMAINT5_8703B BIT(25) /* Beacon DMA Interrupt 5 */ 438 #define IMR_BCNDMAINT4_8703B BIT(24) /* Beacon DMA Interrupt 4 */ 439 #define IMR_BCNDMAINT3_8703B BIT(23) /* Beacon DMA Interrupt 3 */ 440 #define IMR_BCNDMAINT2_8703B BIT(22) /* Beacon DMA Interrupt 2 */ 441 #define IMR_BCNDMAINT1_8703B BIT(21) /* Beacon DMA Interrupt 1 */ 442 #define IMR_BCNDOK7_8703B BIT(20) /* Beacon Queue DMA OK Interrupt 7 */ 443 #define IMR_BCNDOK6_8703B BIT(19) /* Beacon Queue DMA OK Interrupt 6 */ 444 #define IMR_BCNDOK5_8703B BIT(18) /* Beacon Queue DMA OK Interrupt 5 */ 445 #define IMR_BCNDOK4_8703B BIT(17) /* Beacon Queue DMA OK Interrupt 4 */ 446 #define IMR_BCNDOK3_8703B BIT(16) /* Beacon Queue DMA OK Interrupt 3 */ 447 #define IMR_BCNDOK2_8703B BIT(15) /* Beacon Queue DMA OK Interrupt 2 */ 448 #define IMR_BCNDOK1_8703B BIT(14) /* Beacon Queue DMA OK Interrupt 1 */ 449 #define IMR_ATIMEND_E_8703B BIT(13) /* ATIM Window End Extension for Win7 */ 450 #define IMR_TXERR_8703B BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */ 451 #define IMR_RXERR_8703B BIT(10) /* Rx Error Flag INT Status, Write 1 clear */ 452 #define IMR_TXFOVW_8703B BIT(9) /* Transmit FIFO Overflow */ 453 #define IMR_RXFOVW_8703B BIT(8) /* Receive FIFO Overflow */ 454 455 #ifdef CONFIG_PCI_HCI 456 /* #define IMR_RX_MASK (IMR_ROK_8703B|IMR_RDU_8703B|IMR_RXFOVW_8703B) */ 457 #define IMR_TX_MASK (IMR_VODOK_8703B | IMR_VIDOK_8703B | IMR_BEDOK_8703B | IMR_BKDOK_8703B | IMR_MGNTDOK_8703B | IMR_HIGHDOK_8703B) 458 459 #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8703B | IMR_TXBCN0OK_8703B | IMR_TXBCN0ERR_8703B | IMR_BCNDERR0_8703B) 460 461 #define RT_AC_INT_MASKS (IMR_VIDOK_8703B | IMR_VODOK_8703B | IMR_BEDOK_8703B | IMR_BKDOK_8703B) 462 #endif 463 464 #endif /* __RTL8703B_SPEC_H__ */ 465