1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _RTL8188F_PHYCFG_C_
16
17 #include <rtl8188f_hal.h>
18
19
20 /*---------------------------Define Local Constant---------------------------*/
21 /* Channel switch:The size of command tables for switch channel*/
22 #define MAX_PRECMD_CNT 16
23 #define MAX_RFDEPENDCMD_CNT 16
24 #define MAX_POSTCMD_CNT 16
25
26 #define MAX_DOZE_WAITING_TIMES_9x 64
27
28 /*---------------------------Define Local Constant---------------------------*/
29
30
31 /*------------------------Define global variable-----------------------------*/
32
33 /*------------------------Define local variable------------------------------*/
34
35
36 /*--------------------Define export function prototype-----------------------*/
37 /* Please refer to header file */
38 /*--------------------Define export function prototype-----------------------*/
39
40 /*----------------------------Function Body----------------------------------*/
41 /* */
42 /* 1. BB register R/W API */
43 /* */
44
45 /**
46 * Function: phy_CalculateBitShift
47 *
48 * OverView: Get shifted position of the BitMask
49 *
50 * Input:
51 * u32 BitMask,
52 *
53 * Output: none
54 * Return: u32 Return the shift bit bit position of the mask
55 */
56 static u32
phy_CalculateBitShift(u32 BitMask)57 phy_CalculateBitShift(
58 u32 BitMask
59 )
60 {
61 u32 i;
62
63 for (i = 0; i <= 31; i++) {
64 if (((BitMask >> i) & 0x1) == 1)
65 break;
66 }
67
68 return i;
69 }
70
71
72 /**
73 * Function: PHY_QueryBBReg
74 *
75 * OverView: Read "sepcific bits" from BB register
76 *
77 * Input:
78 * PADAPTER Adapter,
79 * u32 RegAddr, The target address to be readback
80 * u32 BitMask The target bit position in the target address
81 * to be readback
82 * Output: None
83 * Return: u32 Data The readback register value
84 * Note: This function is equal to "GetRegSetting" in PHY programming guide
85 */
86 u32
PHY_QueryBBReg_8188F(PADAPTER Adapter,u32 RegAddr,u32 BitMask)87 PHY_QueryBBReg_8188F(
88 PADAPTER Adapter,
89 u32 RegAddr,
90 u32 BitMask
91 )
92 {
93 u32 ReturnValue = 0, OriginalValue, BitShift;
94 u16 BBWaitCounter = 0;
95
96 #if (DISABLE_BB_RF == 1)
97 return 0;
98 #endif
99
100
101 OriginalValue = rtw_read32(Adapter, RegAddr);
102 BitShift = phy_CalculateBitShift(BitMask);
103 ReturnValue = (OriginalValue & BitMask) >> BitShift;
104
105 return ReturnValue;
106
107 }
108
109
110 /**
111 * Function: PHY_SetBBReg
112 *
113 * OverView: Write "Specific bits" to BB register (page 8~)
114 *
115 * Input:
116 * PADAPTER Adapter,
117 * u32 RegAddr, The target address to be modified
118 * u32 BitMask The target bit position in the target address
119 * to be modified
120 * u32 Data The new register value in the target bit position
121 * of the target address
122 *
123 * Output: None
124 * Return: None
125 * Note: This function is equal to "PutRegSetting" in PHY programming guide
126 */
127
128 void
PHY_SetBBReg_8188F(PADAPTER Adapter,u32 RegAddr,u32 BitMask,u32 Data)129 PHY_SetBBReg_8188F(
130 PADAPTER Adapter,
131 u32 RegAddr,
132 u32 BitMask,
133 u32 Data
134 )
135 {
136 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
137 /*u16 BBWaitCounter = 0; */
138 u32 OriginalValue, BitShift;
139
140 #if (DISABLE_BB_RF == 1)
141 return;
142 #endif
143
144
145 if (BitMask != bMaskDWord) { /*if not "double word" write */
146 OriginalValue = rtw_read32(Adapter, RegAddr);
147 BitShift = phy_CalculateBitShift(BitMask);
148 Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask));
149 }
150
151 rtw_write32(Adapter, RegAddr, Data);
152 }
153
154
155 /* */
156 /* 2. RF register R/W API */
157 /* */
158 static u32
phy_RFSerialRead_8188F(PADAPTER Adapter,enum rf_path eRFPath,u32 Offset)159 phy_RFSerialRead_8188F(
160 PADAPTER Adapter,
161 enum rf_path eRFPath,
162 u32 Offset
163 )
164 {
165 u32 retValue = 0;
166 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
167 BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
168 u32 NewOffset;
169 u32 tmplong, tmplong2;
170 u8 RfPiEnable = 0;
171 u32 MaskforPhySet = 0;
172 int i = 0;
173
174 _enter_critical_mutex(&(adapter_to_dvobj(Adapter)->rf_read_reg_mutex) , NULL);
175 /* */
176 /* Make sure RF register offset is correct */
177 /* */
178 Offset &= 0xff;
179
180 NewOffset = Offset;
181
182 if (eRFPath == RF_PATH_A) {
183 tmplong2 = phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
184 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge; /*T65 RF */
185 phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
186 } else {
187 tmplong2 = phy_query_bb_reg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord);
188 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge; /*T65 RF */
189 phy_set_bb_reg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
190 }
191
192 tmplong2 = phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
193 phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
194 phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
195
196 rtw_udelay_os(10);
197
198 for (i = 0; i < 2; i++)
199 rtw_udelay_os(MAX_STALL_TIME);
200 rtw_udelay_os(10);
201
202 if (eRFPath == RF_PATH_A)
203 RfPiEnable = (u8)phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter1 | MaskforPhySet, BIT8);
204 else if (eRFPath == RF_PATH_B)
205 RfPiEnable = (u8)phy_query_bb_reg(Adapter, rFPGA0_XB_HSSIParameter1 | MaskforPhySet, BIT8);
206
207 if (RfPiEnable) {
208 /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
209 retValue = phy_query_bb_reg(Adapter, pPhyReg->rfLSSIReadBackPi | MaskforPhySet, bLSSIReadBackData);
210
211 /*RT_DISP(FINIT, INIT_RF, ("Readback from RF-PI : 0x%x\n", retValue)); */
212 } else {
213 /*Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
214 retValue = phy_query_bb_reg(Adapter, pPhyReg->rfLSSIReadBack | MaskforPhySet, bLSSIReadBackData);
215
216 /*RT_DISP(FINIT, INIT_RF,("Readback from RF-SI : 0x%x\n", retValue)); */
217 }
218 _exit_critical_mutex(&(adapter_to_dvobj(Adapter)->rf_read_reg_mutex) , NULL);
219 return retValue;
220
221 }
222
223 /**
224 * Function: phy_RFSerialWrite_8188F
225 *
226 * OverView: Write data to RF register (page 8~)
227 *
228 * Input:
229 * PADAPTER Adapter,
230 enum rf_path RFPath, Radio path of A/B/C/D
231 * u32 Offset, The target address to be read
232 * u32 Data The new register Data in the target bit position
233 * of the target to be read
234 *
235 * Output: None
236 * Return: None
237 * Note: Threre are three types of serial operations:
238 * 1. Software serial write
239 * 2. Hardware LSSI-Low Speed Serial Interface
240 * 3. Hardware HSSI-High speed
241 * serial write. Driver need to implement (1) and (2).
242 * This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
243 *
244 * Note: For RF8256 only
245 * The total count of RTL8256(Zebra4) register is around 36 bit it only employs
246 * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
247 * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
248 * programming guide" for more details.
249 * Thus, we define a sub-finction for RTL8526 register address conversion
250 * ===========================================================
251 * Register Mode RegCTL[1] RegCTL[0] Note
252 * (Reg00[12]) (Reg00[10])
253 * ===========================================================
254 * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
255 * ------------------------------------------------------------------
256 * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
257 * ------------------------------------------------------------------
258 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
259 * ------------------------------------------------------------------
260 *
261 * 2008/09/02 MH Add 92S RF definition
262 *
263 *
264 *
265 */
266 static void
phy_RFSerialWrite_8188F(PADAPTER Adapter,enum rf_path eRFPath,u32 Offset,u32 Data)267 phy_RFSerialWrite_8188F(
268 PADAPTER Adapter,
269 enum rf_path eRFPath,
270 u32 Offset,
271 u32 Data
272 )
273 {
274 u32 DataAndAddr = 0;
275 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
276 BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
277 u32 NewOffset;
278
279 Offset &= 0xff;
280
281 /* */
282 /* Shadow Update */
283 /* */
284 /*PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data); */
285
286 /* */
287 /* Switch page for 8256 RF IC */
288 /* */
289 NewOffset = Offset;
290
291 /* */
292 /* Put write addr in [5:0] and write data in [31:16] */
293 /* */
294 /*DataAndAddr = (Data<<16) | (NewOffset&0x3f); */
295 DataAndAddr = ((NewOffset << 20) | (Data & 0x000fffff)) & 0x0fffffff; /* T65 RF */
296
297 /* */
298 /* Write Operation */
299 /* */
300 phy_set_bb_reg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
301 /*RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr)); */
302
303 }
304
305
306 /**
307 * Function: PHY_QueryRFReg
308 *
309 * OverView: Query "Specific bits" to RF register (page 8~)
310 *
311 * Input:
312 * PADAPTER Adapter,
313 enum rf_path eRFPath, Radio path of A/B/C/D
314 * u32 RegAddr, The target address to be read
315 * u32 BitMask The target bit position in the target address
316 * to be read
317 *
318 * Output: None
319 * Return: u32 Readback value
320 * Note: This function is equal to "GetRFRegSetting" in PHY programming guide
321 */
322 u32
PHY_QueryRFReg_8188F(PADAPTER Adapter,enum rf_path eRFPath,u32 RegAddr,u32 BitMask)323 PHY_QueryRFReg_8188F(
324 PADAPTER Adapter,
325 enum rf_path eRFPath,
326 u32 RegAddr,
327 u32 BitMask
328 )
329 {
330 u32 Original_Value, Readback_Value, BitShift;
331
332 #if (DISABLE_BB_RF == 1)
333 return 0;
334 #endif
335
336 Original_Value = phy_RFSerialRead_8188F(Adapter, eRFPath, RegAddr);
337
338 BitShift = phy_CalculateBitShift(BitMask);
339 Readback_Value = (Original_Value & BitMask) >> BitShift;
340
341 return Readback_Value;
342 }
343
344 /**
345 * Function: PHY_SetRFReg
346 *
347 * OverView: Write "Specific bits" to RF register (page 8~)
348 *
349 * Input:
350 * PADAPTER Adapter,
351 enum rf_path eRFPath, Radio path of A/B/C/D
352 * u32 RegAddr, The target address to be modified
353 * u32 BitMask The target bit position in the target address
354 * to be modified
355 * u32 Data The new register Data in the target bit position
356 * of the target address
357 *
358 * Output: None
359 * Return: None
360 * Note: This function is equal to "PutRFRegSetting" in PHY programming guide
361 */
362 void
PHY_SetRFReg_8188F(PADAPTER Adapter,enum rf_path eRFPath,u32 RegAddr,u32 BitMask,u32 Data)363 PHY_SetRFReg_8188F(
364 PADAPTER Adapter,
365 enum rf_path eRFPath,
366 u32 RegAddr,
367 u32 BitMask,
368 u32 Data
369 )
370 {
371 u32 Original_Value, BitShift;
372
373 #if (DISABLE_BB_RF == 1)
374 return;
375 #endif
376
377 /* RF data is 12 bits only */
378 if (BitMask != bRFRegOffsetMask) {
379 Original_Value = phy_RFSerialRead_8188F(Adapter, eRFPath, RegAddr);
380 BitShift = phy_CalculateBitShift(BitMask);
381 Data = ((Original_Value & (~BitMask)) | (Data << BitShift));
382 }
383
384 phy_RFSerialWrite_8188F(Adapter, eRFPath, RegAddr, Data);
385 }
386
387
388 /* */
389 /* 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. */
390 /* */
391
392
393 /*-----------------------------------------------------------------------------
394 * Function: PHY_MACConfig8192C
395 *
396 * Overview: Condig MAC by header file or parameter file.
397 *
398 * Input: NONE
399 *
400 * Output: NONE
401 *
402 * Return: NONE
403 *
404 * Revised History:
405 * When Who Remark
406 * 08/12/2008 MHC Create Version 0.
407 *
408 *---------------------------------------------------------------------------*/
PHY_MACConfig8188F(PADAPTER Adapter)409 s32 PHY_MACConfig8188F(PADAPTER Adapter)
410 {
411 int rtStatus = _SUCCESS;
412 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
413
414 /* */
415 /* Config MAC */
416 /* */
417 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
418 rtStatus = phy_ConfigMACWithParaFile(Adapter, PHY_FILE_MAC_REG);
419 if (rtStatus == _FAIL)
420 #endif
421 {
422 #ifdef CONFIG_EMBEDDED_FWIMG
423 odm_config_mac_with_header_file(&pHalData->odmpriv);
424 rtStatus = _SUCCESS;
425 #endif/*CONFIG_EMBEDDED_FWIMG */
426 }
427
428 return rtStatus;
429 }
430
431 /**
432 * Function: phy_InitBBRFRegisterDefinition
433 *
434 * OverView: Initialize Register definition offset for Radio Path A/B/C/D
435 *
436 * Input:
437 * PADAPTER Adapter,
438 *
439 * Output: None
440 * Return: None
441 * Note: The initialization value is constant and it should never be changes
442 */
443 static void
phy_InitBBRFRegisterDefinition(PADAPTER Adapter)444 phy_InitBBRFRegisterDefinition(
445 PADAPTER Adapter
446 )
447 {
448 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
449
450 /* RF Interface Sowrtware Control */
451 pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */
452 pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
453
454 /* RF Interface Output (and Enable) */
455 pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */
456 pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x864 */
457
458 /* RF Interface (Output and) Enable */
459 pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
460 pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
461
462 pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /*LSSI Parameter */
463 pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
464
465 pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; /*wire control parameter2 */
466 pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; /*wire control parameter2 */
467
468 /* Tranceiver Readback LSSI/HSPI mode */
469 pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
470 pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
471 pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
472 pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
473
474 }
475
476 static int
phy_BB8188f_Config_ParaFile(PADAPTER Adapter)477 phy_BB8188f_Config_ParaFile(
478 PADAPTER Adapter
479 )
480 {
481 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
482 int rtStatus = _SUCCESS;
483
484 /* */
485 /* 1. Read PHY_REG.TXT BB INIT!! */
486 /* */
487 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
488 if (phy_ConfigBBWithParaFile(Adapter, PHY_FILE_PHY_REG, CONFIG_BB_PHY_REG) == _FAIL)
489 #endif
490 {
491 #ifdef CONFIG_EMBEDDED_FWIMG
492 if (HAL_STATUS_SUCCESS != odm_config_bb_with_header_file(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
493 rtStatus = _FAIL;
494 #endif
495 }
496
497 if (rtStatus != _SUCCESS) {
498 RTW_INFO("%s():Write BB Reg Fail!!", __func__);
499 goto phy_BB8190_Config_ParaFile_Fail;
500 }
501
502 #if MP_DRIVER == 1
503 if (Adapter->registrypriv.mp_mode == 1) {
504 /* */
505 /* 1.1 Read PHY_REG_MP.TXT BB INIT!! */
506 /* */
507 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
508 if (phy_ConfigBBWithMpParaFile(Adapter, PHY_FILE_PHY_REG_MP) == _FAIL)
509 #endif
510 {
511 #ifdef CONFIG_EMBEDDED_FWIMG
512 if (HAL_STATUS_SUCCESS != odm_config_bb_with_header_file(&pHalData->odmpriv, CONFIG_BB_PHY_REG_MP))
513 rtStatus = _FAIL;
514 #endif
515 }
516
517 if (rtStatus != _SUCCESS) {
518 RTW_INFO("%s():Write BB Reg MP Fail!!", __func__);
519 goto phy_BB8190_Config_ParaFile_Fail;
520 }
521 }
522 #endif /* #if (MP_DRIVER == 1) */
523
524 /* */
525 /* 2. Read BB AGC table Initialization */
526 /* */
527 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
528 if (phy_ConfigBBWithParaFile(Adapter, PHY_FILE_AGC_TAB, CONFIG_BB_AGC_TAB) == _FAIL)
529 #endif
530 {
531 #ifdef CONFIG_EMBEDDED_FWIMG
532 if (HAL_STATUS_SUCCESS != odm_config_bb_with_header_file(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
533 rtStatus = _FAIL;
534 #endif
535 }
536
537 if (rtStatus != _SUCCESS) {
538 RTW_INFO("%s():AGC Table Fail\n", __func__);
539 goto phy_BB8190_Config_ParaFile_Fail;
540 }
541
542 phy_BB8190_Config_ParaFile_Fail:
543
544 return rtStatus;
545 }
546
547
548 int
PHY_BBConfig8188F(PADAPTER Adapter)549 PHY_BBConfig8188F(
550 PADAPTER Adapter
551 )
552 {
553 int rtStatus = _SUCCESS;
554 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
555 u16 RegVal;
556 u8 TmpU1B = 0;
557 u8 value8;
558
559 phy_InitBBRFRegisterDefinition(Adapter);
560
561 /* Enable BB and RF */
562 RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
563 RegVal |= BIT13 | FEN_BB_GLB_RSTn | FEN_BBRSTB;
564 rtw_write16(Adapter, REG_SYS_FUNC_EN, RegVal);
565
566 #if 0 /* TODO: [BB]. reg 948 is only use for bt_coex */
567 #ifdef CONFIG_USB_HCI
568 rtw_write32(Adapter, 0x948, 0x0); /* USB use Antenna S0 */
569 #else
570 if (pHalData->ant_path == RF_PATH_A)
571 rtw_write32(Adapter, 0x948, 0x280);
572 else
573 rtw_write32(Adapter, 0x948, 0x0);
574 #endif
575
576 #endif
577 rtw_write8(Adapter, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
578
579 rtw_usleep_os(10);
580
581 phy_set_rf_reg(Adapter, RF_PATH_A, 0x1, 0xfffff, 0x780);
582
583 #if 0
584 /* 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF. */
585 rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x83);
586 rtw_write8(Adapter, REG_AFE_PLL_CTRL + 1, 0xdb);
587 #endif
588
589 /* Config BB and AGC */
590 rtStatus = phy_BB8188f_Config_ParaFile(Adapter);
591
592 if (rtw_phydm_set_crystal_cap(Adapter, pHalData->crystal_cap) == _FALSE) {
593 RTW_ERR("Init crystal_cap failed\n");
594 rtw_warn_on(1);
595 rtStatus = _FAIL;
596 }
597
598 return rtStatus;
599 }
600
601 #if 0
602 /* Block & Path enable */
603 #define rOFDMCCKEN_Jaguar 0x808 /* OFDM/CCK block enable */
604 #define bOFDMEN_Jaguar 0x20000000
605 #define bCCKEN_Jaguar 0x10000000
606 #define rRxPath_Jaguar 0x808 /* Rx antenna */
607 #define bRxPath_Jaguar 0xff
608 #define rTxPath_Jaguar 0x80c /* Tx antenna */
609 #define bTxPath_Jaguar 0x0fffffff
610 #define rCCK_RX_Jaguar 0xa04 /* for cck rx path selection */
611 #define bCCK_RX_Jaguar 0x0c000000
612 #define rVhtlen_Use_Lsig_Jaguar 0x8c3 /* Use LSIG for VHT length */
613 void
614 PHY_BB8188F_Config_1T(
615 PADAPTER Adapter
616 )
617 {
618 /* BB OFDM RX Path_A */
619 phy_set_bb_reg(Adapter, rRxPath_Jaguar, bRxPath_Jaguar, 0x11);
620 /* BB OFDM TX Path_A */
621 phy_set_bb_reg(Adapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
622 /* BB CCK R/Rx Path_A */
623 phy_set_bb_reg(Adapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
624 /* MCS support */
625 phy_set_bb_reg(Adapter, 0x8bc, 0xc0000060, 0x4);
626 /* RF Path_B HSSI OFF */
627 phy_set_bb_reg(Adapter, 0xe00, 0xf, 0x4);
628 /* RF Path_B Power Down */
629 phy_set_bb_reg(Adapter, 0xe90, bMaskDWord, 0);
630 /* ADDA Path_B OFF */
631 phy_set_bb_reg(Adapter, 0xe60, bMaskDWord, 0);
632 phy_set_bb_reg(Adapter, 0xe64, bMaskDWord, 0);
633 }
634 #endif
635
636 int
PHY_RFConfig8188F(PADAPTER Adapter)637 PHY_RFConfig8188F(
638 PADAPTER Adapter
639 )
640 {
641 int rtStatus = _SUCCESS;
642
643 /* */
644 /* RF config */
645 /* */
646 rtStatus = PHY_RF6052_Config8188F(Adapter);
647
648 /*PHY_BB8188F_Config_1T(Adapter); */
649
650 return rtStatus;
651 }
652
653 /*-----------------------------------------------------------------------------
654 * Function: PHY_ConfigRFWithParaFile()
655 *
656 * Overview: This function read RF parameters from general file format, and do RF 3-wire
657 *
658 * Input: PADAPTER Adapter
659 * ps1Byte pFileName
660 * enum rf_path eRFPath
661 *
662 * Output: NONE
663 *
664 * Return: RT_STATUS_SUCCESS: configuration file exist
665 *
666 * Note: Delay may be required for RF configuration
667 *---------------------------------------------------------------------------*/
668 int
PHY_ConfigRFWithParaFile_8188F(PADAPTER Adapter,u8 * pFileName,enum rf_path eRFPath)669 PHY_ConfigRFWithParaFile_8188F(
670 PADAPTER Adapter,
671 u8 *pFileName,
672 enum rf_path eRFPath
673 )
674 {
675 return _SUCCESS;
676 }
677
678 #ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
phy_set_txpwr_idx_offload(_adapter * adapter)679 bool phy_set_txpwr_idx_offload(_adapter *adapter)
680 {
681 return GET_HAL_DATA(adapter)->intf_start
682 #ifdef CONFIG_MP_INCLUDED
683 && !rtw_mp_mode_check(adapter)
684 #endif
685 ;
686 }
687
rtw_hal_h2c_txpwr_idx_offload(_adapter * adapter)688 s32 rtw_hal_h2c_txpwr_idx_offload(_adapter *adapter)
689 {
690 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
691 u8 data[H2C_TXPWR_IDX_OFFLOAD_LEN] = {0};
692 s32 ret;
693
694 _rtw_memcpy(data, hal_data->txpwr_idx_offload_buf, 3);
695 SET_H2CCMD_TXPWR_IDX_EN(data, 1);
696
697 ret = rtw_hal_fill_h2c_cmd(adapter, H2C_TXPWR_IDX_OFFLOAD, H2C_TXPWR_IDX_OFFLOAD_LEN, data);
698 if (ret != _SUCCESS)
699 RTW_WARN("%s fail\n", __func__);
700
701 return ret;
702 }
703
phy_set_txpwr_offload_8188f(_adapter * adapter)704 s32 phy_set_txpwr_offload_8188f(_adapter *adapter)
705 {
706 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
707 struct submit_ctx *sctx = &hal_data->txpwr_idx_offload_sctx;
708 s32 ret = _SUCCESS;
709
710 rtw_sctx_init(sctx, 500);
711 ret = rtw_hal_h2c_txpwr_idx_offload(adapter);
712 if (ret != _SUCCESS)
713 goto exit;
714
715 /* wait till rpt done or timeout */
716 ret = c2h_txpwr_idx_offload_wait(adapter);
717
718 exit:
719 return ret;
720 }
721 #endif /* CONFIG_FW_OFFLOAD_SET_TXPWR_IDX */
722
723 /**************************************************************************************************************
724 * Description:
725 * The low-level interface to set TxAGC , called by both MP and Normal Driver.
726 *
727 * <20120830, Kordan>
728 **************************************************************************************************************/
729
730 void
PHY_SetTxPowerIndex_8188F(PADAPTER Adapter,u32 PowerIndex,enum rf_path RFPath,u8 Rate)731 PHY_SetTxPowerIndex_8188F(
732 PADAPTER Adapter,
733 u32 PowerIndex,
734 enum rf_path RFPath,
735 u8 Rate
736 )
737 {
738 #ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
739 if (phy_set_txpwr_idx_offload(Adapter)) {
740 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(Adapter);
741
742 if (Rate == MGN_11M)
743 hal_data->txpwr_idx_offload_buf[CCK] = PowerIndex;
744 else if (Rate == MGN_54M)
745 hal_data->txpwr_idx_offload_buf[OFDM] = PowerIndex;
746 else if (Rate == MGN_MCS7)
747 hal_data->txpwr_idx_offload_buf[HT_1SS] = PowerIndex;
748
749 return;
750 }
751 #endif
752
753 if (RFPath == RF_PATH_A || RFPath == RF_PATH_B) {
754 switch (Rate) {
755 case MGN_1M:
756 phy_set_bb_reg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, PowerIndex);
757 break;
758 case MGN_2M:
759 phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1, PowerIndex);
760 break;
761 case MGN_5_5M:
762 phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte2, PowerIndex);
763 break;
764 case MGN_11M:
765 phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte3, PowerIndex);
766 break;
767
768 case MGN_6M:
769 phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte0, PowerIndex);
770 break;
771 case MGN_9M:
772 phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte1, PowerIndex);
773 break;
774 case MGN_12M:
775 phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte2, PowerIndex);
776 break;
777 case MGN_18M:
778 phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte3, PowerIndex);
779 break;
780
781 case MGN_24M:
782 phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte0, PowerIndex);
783 break;
784 case MGN_36M:
785 phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte1, PowerIndex);
786 break;
787 case MGN_48M:
788 phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte2, PowerIndex);
789 break;
790 case MGN_54M:
791 phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte3, PowerIndex);
792 break;
793
794 case MGN_MCS0:
795 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte0, PowerIndex);
796 break;
797 case MGN_MCS1:
798 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte1, PowerIndex);
799 break;
800 case MGN_MCS2:
801 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte2, PowerIndex);
802 break;
803 case MGN_MCS3:
804 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte3, PowerIndex);
805 break;
806
807 case MGN_MCS4:
808 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte0, PowerIndex);
809 break;
810 case MGN_MCS5:
811 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte1, PowerIndex);
812 break;
813 case MGN_MCS6:
814 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte2, PowerIndex);
815 break;
816 case MGN_MCS7:
817 phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte3, PowerIndex);
818 break;
819
820 default:
821 RTW_INFO("Invalid Rate!!\n");
822 break;
823 }
824 }
825 }
826
827 void
PHY_SetTxPowerLevel8188F(PADAPTER Adapter,u8 Channel)828 PHY_SetTxPowerLevel8188F(
829 PADAPTER Adapter,
830 u8 Channel
831 )
832 {
833 phy_set_tx_power_level_by_path(Adapter, Channel, RF_PATH_A);
834 }
835
rtl8188f_set_txpwr_done(_adapter * adapter)836 void rtl8188f_set_txpwr_done(_adapter *adapter)
837 {
838 /* TODO: for not offload case */
839
840 #ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
841 if (phy_set_txpwr_idx_offload(adapter))
842 phy_set_txpwr_offload_8188f(adapter);
843 #endif
844 }
845
846 /* A workaround to eliminate the 2400MHz, 2440MHz, 2480MHz spur of 8188F. (Asked by David.) */
847 void
phy_SpurCalibration_8188F(PADAPTER pAdapter,u8 ToChannel,u8 threshold)848 phy_SpurCalibration_8188F(
849 PADAPTER pAdapter,
850 u8 ToChannel,
851 u8 threshold
852 )
853 {
854 u32 freq[7] = {0xFCCD, 0xFC4D, 0xFFCD, 0xFF4D, 0xFCCD, 0xFF9A, 0xFDCD}; /* {chnl 5, 6, 7, 8, 13, 14 , 11} */
855 u8 idx = 0;
856 u8 b_doNotch = FALSE;
857 u8 initial_gain;
858 BOOLEAN bHW_Ctrl = FALSE, bSW_Ctrl = FALSE, bHW_Ctrl_S1 = FALSE, bSW_Ctrl_S1 = FALSE;
859 u32 reg948;
860
861 /* add for notch */
862 u32 wlan_channel, CurrentChannel, Is40MHz;
863 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
864 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
865
866 #ifdef CONFIG_AUTO_NOTCH_FILTER
867 odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0x1F);
868 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1); /*enable notch filter */
869 #endif
870
871 /* check threshold */
872 if (threshold <= 0x0)
873 threshold = 0x16;
874
875 /* RTW_INFO("===> phy_SpurCalibration_8188F: Channel = %d\n", ToChannel); */
876
877 if (ToChannel == 5)
878 idx = 0;
879 else if (ToChannel == 6)
880 idx = 1;
881 else if (ToChannel == 7)
882 idx = 2;
883 else if (ToChannel == 8)
884 idx = 3;
885 else if (ToChannel == 13)
886 idx = 4;
887 else if (ToChannel == 14)
888 idx = 5;
889 else if (ToChannel == 11)
890 idx = 6;
891 else
892 idx = 10;
893
894 reg948 = phy_query_bb_reg(pAdapter, rS0S1_PathSwitch, bMaskDWord);
895 if ((reg948 & BIT6) == 0x0)
896 bSW_Ctrl = TRUE;
897 else
898 bHW_Ctrl = TRUE;
899
900 if (bHW_Ctrl)
901 bHW_Ctrl_S1 = (phy_query_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5 | BIT4 | BIT3) == 0x1) ? TRUE : FALSE;
902 else if (bSW_Ctrl)
903 bSW_Ctrl_S1 = ((reg948 & BIT9) == 0x0) ? TRUE : FALSE;
904
905 /* If wlan at S1 (both HW control & SW control) and current channel=5,6,7,8,13,14 */
906 if ((bHW_Ctrl_S1 || bSW_Ctrl_S1) && (idx <= 6)) {
907 initial_gain = (u8)(odm_get_bb_reg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0) & 0x7f);
908 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, BIT24, 0); /* Disable CCK block */
909 odm_write_dig(pDM_Odm, 0x30);
910 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xccf000c0); /* disable 3-wire */
911
912 phy_set_bb_reg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, freq[idx]); /* Setup PSD */
913 phy_set_bb_reg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, 0x400000 | freq[idx]); /* Start PSD */
914
915 rtw_msleep_os(30);
916
917 if (phy_query_bb_reg(pAdapter, rFPGA0_PSDReport, bMaskDWord) >= threshold)
918 b_doNotch = TRUE;
919
920 phy_set_bb_reg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, freq[idx]); /* turn off PSD */
921
922 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xccc000c0); /* enable 3-wire */
923 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, BIT24, 1); /* Enable CCK block */
924 odm_write_dig(pDM_Odm, initial_gain);
925 }
926
927 /* --- Notch Filter --- Asked by Rock */
928 if (b_doNotch) {
929 CurrentChannel = odm_get_rf_reg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
930 wlan_channel = CurrentChannel & 0x0f; /*Get center frequency */
931
932 switch (wlan_channel) { /*Set notch filter */
933 case 5:
934 case 13:
935 #ifndef CONFIG_AUTO_NOTCH_FILTER
936 odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0xB);
937 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1); /*enable notch filter */
938 #endif
939 odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x06000000);
940 odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
941 odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
942 odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000);
943 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1); /*enable CSI mask */
944 break;
945 case 6:
946 #ifndef CONFIG_AUTO_NOTCH_FILTER
947 odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0x4);
948 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1); /*enable notch filter */
949 #endif
950 odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000600);
951 odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
952 odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
953 odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000);
954 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1); /*enable CSI mask */
955 break;
956 case 7:
957 #ifndef CONFIG_AUTO_NOTCH_FILTER
958 odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0x3);
959 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1); /*enable notch filter */
960 #endif
961 odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
962 odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
963 odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
964 odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x06000000);
965 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1); /*enable CSI mask */
966 break;
967 case 8:
968 #ifndef CONFIG_AUTO_NOTCH_FILTER
969 odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0xA);
970 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1); /*enable notch filter */
971 #endif
972 odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
973 odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
974 odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
975 odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000380);
976 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1); /*enable CSI mask */
977 break;
978 case 11:
979 #ifndef CONFIG_AUTO_NOTCH_FILTER
980 odm_set_bb_reg(pDM_Odm, 0xC40, BIT28|BIT27|BIT26|BIT25|BIT24, 0x19);
981 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1); /*enable notch filter*/
982 #endif
983 odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
984 odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x04000000);
985 odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
986 odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000);
987 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1); /*enable CSI mask*/
988 break;
989 case 14:
990 #ifndef CONFIG_AUTO_NOTCH_FILTER
991 odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0x5);
992 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1); /*enable notch filter */
993 #endif
994 odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
995 odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
996 odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
997 odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00180000);
998 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1); /*enable CSI mask */
999 break;
1000 default:
1001 #ifndef CONFIG_AUTO_NOTCH_FILTER
1002 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x0); /*disable notch filter */
1003 #endif
1004 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x0); /*disable CSI mask function */
1005 break;
1006 } /*switch(wlan_channel) */
1007 return;
1008 }
1009
1010 #ifndef CONFIG_AUTO_NOTCH_FILTER
1011 odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x0); /*disable notch filter */
1012 #endif
1013 odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x0); /*disable CSI mask */
1014
1015 }
1016
1017 void
phy_SetRegBW_8188F(PADAPTER Adapter,enum channel_width CurrentBW)1018 phy_SetRegBW_8188F(
1019 PADAPTER Adapter,
1020 enum channel_width CurrentBW
1021 )
1022 {
1023 u16 RegRfMod_BW, u2tmp = 0;
1024 RegRfMod_BW = rtw_read16(Adapter, REG_TRXPTCL_CTL_8188F);
1025
1026 switch (CurrentBW) {
1027 case CHANNEL_WIDTH_20:
1028 rtw_write16(Adapter, REG_TRXPTCL_CTL_8188F, (RegRfMod_BW & 0xFE7F)); /* BIT 7 = 0, BIT 8 = 0 */
1029 break;
1030
1031 case CHANNEL_WIDTH_40:
1032 u2tmp = RegRfMod_BW | BIT7;
1033 rtw_write16(Adapter, REG_TRXPTCL_CTL_8188F, (u2tmp & 0xFEFF)); /* BIT 7 = 1, BIT 8 = 0 */
1034 break;
1035
1036 case CHANNEL_WIDTH_80:
1037 u2tmp = RegRfMod_BW | BIT8;
1038 rtw_write16(Adapter, REG_TRXPTCL_CTL_8188F, (u2tmp & 0xFF7F)); /* BIT 7 = 0, BIT 8 = 1 */
1039 break;
1040
1041 default:
1042 RTW_INFO("phy_PostSetBWMode8188F(): unknown Bandwidth: %#X\n", CurrentBW);
1043 break;
1044 }
1045 }
1046
1047 u8
phy_GetSecondaryChnl_8188F(PADAPTER Adapter)1048 phy_GetSecondaryChnl_8188F(
1049 PADAPTER Adapter
1050 )
1051 {
1052 u8 SCSettingOf40 = 0, SCSettingOf20 = 0;
1053 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
1054
1055 if (pHalData->current_channel_bw == CHANNEL_WIDTH_80) {
1056 if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
1057 SCSettingOf40 = VHT_DATA_SC_40_LOWER_OF_80MHZ;
1058 else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
1059 SCSettingOf40 = VHT_DATA_SC_40_UPPER_OF_80MHZ;
1060
1061
1062 if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
1063 SCSettingOf20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
1064 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
1065 SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
1066 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
1067 SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
1068 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
1069 SCSettingOf20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
1070
1071 } else if (pHalData->current_channel_bw == CHANNEL_WIDTH_40) {
1072
1073 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
1074 SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
1075 else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
1076 SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
1077
1078 }
1079
1080 return (SCSettingOf40 << 4) | SCSettingOf20;
1081 }
1082
1083 void
phy_PostSetBwMode8188F(PADAPTER Adapter)1084 phy_PostSetBwMode8188F(
1085 PADAPTER Adapter
1086 )
1087 {
1088 u8 SubChnlNum = 0;
1089 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1090
1091 /* RTW_INFO("===>%s: current_channel_bw = %s Mhz\n", __func__, pHalData->current_channel_bw?"40":"20"); */
1092
1093 switch (pHalData->current_channel_bw) {
1094 case CHANNEL_WIDTH_20:
1095 /*
1096 0x800[0]=1'b0
1097 0x900[0]=1'b0
1098 0x800[10:8]=3'b111(80M)
1099 0x800[14:12]=3'b101(80M)
1100 0xCE4[31:30]=2'b00
1101 0xCE4[29:28]=2'b01
1102 0xc10[29:28]=1
1103 0x954[19]=1'b0
1104 0x954[23:20]=3
1105 */
1106 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, BIT0, 0x0);
1107 phy_set_bb_reg(Adapter, rFPGA1_RFMOD, BIT0, 0x0);
1108 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, BIT10 | BIT9 | BIT8, 0x7); /* RXADC CLK */
1109 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, BIT14 | BIT13 | BIT12, 0x5); /* TXDAC CLK */
1110 phy_set_bb_reg(Adapter, rOFDM0_TxPseudoNoiseWgt, BIT31 | BIT30, 0x0); /* small BW */
1111 phy_set_bb_reg(Adapter, rOFDM0_TxPseudoNoiseWgt, BIT29 | BIT28, 0x1); /* adc buffer clk(TBD) */
1112 phy_set_bb_reg(Adapter, rOFDM0_XARxAFE, BIT29 | BIT28, 0x1); /* adc buffer clk(TBD) */
1113 phy_set_bb_reg(Adapter, BBrx_DFIR, BIT19, 0x0); /* OFDM RX DFIR */
1114 phy_set_bb_reg(Adapter, BBrx_DFIR, BIT23 | BIT22 | BIT21 | BIT20, 0x3); /* OFDM RX DFIR */
1115 break;
1116
1117 case CHANNEL_WIDTH_40:
1118 /*
1119 0x800[0]=1'b1
1120 0x900[0]=1'b1
1121 0x800[10:8]=3'b111(80M)
1122 0x800[14:12]=3'b101(80M)
1123 0xCE4[31:30]=2'b00
1124 0xCE4[29:28]=2'b01
1125 0xc10[29:28]: 1
1126 0x954[19]=1'b0
1127 0x954[23:20]=0x6(For ACPR)
1128
1129 0xa00[4]=1/0
1130
1131 0x483[3:0]=1/2
1132 0x440[22:21]=2'b00
1133 */
1134 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, BIT0, 0x1);
1135 phy_set_bb_reg(Adapter, rFPGA1_RFMOD, BIT0, 0x1);
1136 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, BIT10 | BIT9 | BIT8, 0x7); /* RXADC CLK */
1137 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, BIT14 | BIT13 | BIT12, 0x5); /* TXDAC CLK */
1138 phy_set_bb_reg(Adapter, rOFDM0_TxPseudoNoiseWgt, BIT31 | BIT30, 0x0); /* small BW */
1139 phy_set_bb_reg(Adapter, rOFDM0_TxPseudoNoiseWgt, BIT29 | BIT28, 0x1); /* adc buffer clk(TBD) */
1140 phy_set_bb_reg(Adapter, rOFDM0_XARxAFE, BIT29 | BIT28, 0x1); /* adc buffer clk(TBD) */
1141 phy_set_bb_reg(Adapter, BBrx_DFIR, BIT19, 0x0); /* OFDM RX DFIR */
1142 phy_set_bb_reg(Adapter, BBrx_DFIR, BIT23 | BIT22 | BIT21 | BIT20, 0x6); /* OFDM RX DFIR */
1143
1144 phy_set_bb_reg(Adapter, rCCK0_System, BIT4, (pHalData->nCur40MhzPrimeSC >> 1)); /* primary channel (CCK RXSC) */
1145
1146 SubChnlNum = phy_GetSecondaryChnl_8188F(Adapter);
1147 phy_set_mac_reg(Adapter, REG_DATA_SC_8188F, BIT3 | BIT2 | BIT1 | BIT0, SubChnlNum); /* txsc_20 */
1148 phy_set_mac_reg(Adapter, REG_RRSR_8188F, BIT22 | BIT21, 0x0); /* RRSR_RSC */
1149
1150 if (0)
1151 RTW_INFO("%s: REG_DATA_SC_8188F(%d) nCur40MhzPrimeSC(%d)\n", __func__, SubChnlNum, pHalData->nCur40MhzPrimeSC);
1152 break;
1153
1154 default:
1155 break;
1156 }
1157
1158 /*3<3>Set RF related register */
1159 PHY_RF6052SetBandwidth8188F(Adapter, pHalData->current_channel_bw);
1160 }
1161
1162 void
phy_SwChnl8188F(PADAPTER pAdapter)1163 phy_SwChnl8188F(
1164 PADAPTER pAdapter
1165 )
1166 {
1167 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1168 u8 channelToSW = pHalData->current_channel;
1169 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1170 struct dm_struct *pDM_Odm = &pHalData->DM_OutSrc;
1171 #else /* (DM_ODM_SUPPORT_TYPE == ODM_CE) */
1172 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1173 #endif
1174
1175 if (pHalData->rf_chip == RF_PSEUDO_11N) {
1176 return;
1177 }
1178
1179 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff00) | channelToSW);
1180 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]);
1181 /* phy_set_rf_reg(pAdapter, RF_PATH_B, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0] ); */
1182
1183 /* RTW_INFO("===>phy_SwChnl8188F: Channel = %d\n", channelToSW); */
1184
1185 phy_SpurCalibration_8188F(pAdapter, channelToSW, 0x16);
1186 }
1187
1188 void
PHY_HandleSwChnlAndSetBW8188F(PADAPTER Adapter,BOOLEAN bSwitchChannel,BOOLEAN bSetBandWidth,u8 ChannelNum,enum channel_width ChnlWidth,EXTCHNL_OFFSET ExtChnlOffsetOf40MHz,EXTCHNL_OFFSET ExtChnlOffsetOf80MHz,u8 CenterFrequencyIndex1)1189 PHY_HandleSwChnlAndSetBW8188F(
1190 PADAPTER Adapter,
1191 BOOLEAN bSwitchChannel,
1192 BOOLEAN bSetBandWidth,
1193 u8 ChannelNum,
1194 enum channel_width ChnlWidth,
1195 EXTCHNL_OFFSET ExtChnlOffsetOf40MHz,
1196 EXTCHNL_OFFSET ExtChnlOffsetOf80MHz,
1197 u8 CenterFrequencyIndex1
1198 )
1199 {
1200 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
1201
1202 /*check is swchnl or setbw */
1203 if (!bSwitchChannel && !bSetBandWidth) {
1204 RTW_INFO("PHY_HandleSwChnlAndSetBW8188F: not switch channel and not set bandwidth\n");
1205 return;
1206 }
1207
1208 if (RTW_CANNOT_RUN(Adapter))
1209 return;
1210
1211 /*skip change for channel or bandwidth is the same */
1212 if (bSwitchChannel) {
1213 if (pHalData->current_channel != ChannelNum) {
1214 if (HAL_IsLegalChannel(Adapter, ChannelNum))
1215 pHalData->bSwChnl = _TRUE;
1216 }
1217 }
1218
1219 if (bSetBandWidth) {
1220 if ((pHalData->current_channel_bw != ChnlWidth) || (pHalData->nCur40MhzPrimeSC != ExtChnlOffsetOf40MHz) || (pHalData->CurrentCenterFrequencyIndex1 != CenterFrequencyIndex1))
1221 pHalData->bSetChnlBW = _TRUE;
1222 }
1223
1224 if (Adapter->bNotifyChannelChange)
1225 RTW_INFO("[%s] bSwChnl=%d, ch=%d, bSetChnlBW=%d, bw=%d\n", __func__,
1226 pHalData->bSwChnl, ChannelNum, pHalData->bSetChnlBW, ChnlWidth);
1227
1228 if (!pHalData->bSetChnlBW && !pHalData->bSwChnl)
1229 goto exit_iqk;
1230
1231 pHalData->bSwChnl = _TRUE;
1232 pHalData->bSetChnlBW = _TRUE;
1233
1234 pHalData->current_channel = ChannelNum;
1235 pHalData->CurrentCenterFrequencyIndex1 = ChannelNum;
1236
1237 pHalData->current_channel_bw = ChnlWidth;
1238 pHalData->nCur40MhzPrimeSC = ExtChnlOffsetOf40MHz;
1239 pHalData->nCur80MhzPrimeSC = ExtChnlOffsetOf80MHz;
1240 pHalData->CurrentCenterFrequencyIndex1 = CenterFrequencyIndex1;
1241
1242 phy_SwChnl8188F(Adapter);
1243 pHalData->bSwChnl = _FALSE;
1244
1245 phy_PostSetBwMode8188F(Adapter);
1246 pHalData->bSetChnlBW = _FALSE;
1247
1248 rtw_hal_set_tx_power_level(Adapter, pHalData->current_channel);
1249
1250 exit_iqk:
1251 if (pHalData->bNeedIQK == _TRUE) {
1252 if (pHalData->neediqk_24g == _TRUE) {
1253 halrf_iqk_trigger(&pHalData->odmpriv, _FALSE);
1254 pHalData->bIQKInitialized = _TRUE;
1255 pHalData->neediqk_24g = _FALSE;
1256 }
1257 pHalData->bNeedIQK = _FALSE;
1258 }
1259 }
1260
1261 void
PHY_SetSwChnlBWMode8188F(PADAPTER Adapter,u8 channel,enum channel_width Bandwidth,u8 Offset40,u8 Offset80)1262 PHY_SetSwChnlBWMode8188F(
1263 PADAPTER Adapter,
1264 u8 channel,
1265 enum channel_width Bandwidth,
1266 u8 Offset40,
1267 u8 Offset80
1268 )
1269 {
1270 /*RTW_INFO("%s()===>\n",__func__); */
1271
1272 PHY_HandleSwChnlAndSetBW8188F(Adapter, _TRUE, _TRUE, channel, Bandwidth, Offset40, Offset80, channel);
1273
1274 /*RTW_INFO("<==%s()\n",__func__); */
1275 }
1276
1277 /* Set CCK and OFDM Block "ON" */
BBTurnOnBlock_8188F(_adapter * adapter)1278 void BBTurnOnBlock_8188F(_adapter *adapter)
1279 {
1280 #if (DISABLE_BB_RF)
1281 return;
1282 #endif
1283
1284 phy_set_bb_reg(adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1285 phy_set_bb_reg(adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1286 }
1287
1288