1 /****************************************************************************** 2 * 3 * Copyright(c) 2016 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 /***************************************************************************** 16 * Copyright(c) 2009, RealTEK Technology Inc. All Right Reserved. 17 * 18 * Module: __INC_HAL8188FREG_H 19 * 20 * 21 * Note: 1. Define Mac register address and corresponding bit mask map 22 * 23 * 24 * Export: Constants, macro, functions(API), global variables(None). 25 * 26 * Abbrev: 27 * 28 * History: 29 * data Who Remark 30 * 31 *****************************************************************************/ 32 #ifndef __INC_HAL8188FREG_H 33 #define __INC_HAL8188FREG_H 34 35 /* ************************************************************ 36 * 37 * ************************************************************ */ 38 39 /* ----------------------------------------------------- 40 * 41 * 0x0000h ~ 0x00FFh System Configuration 42 * 43 * ----------------------------------------------------- */ 44 #define REG_SYS_ISO_CTRL_8188F 0x0000 /* 2 Byte */ 45 #define REG_SYS_FUNC_EN_8188F 0x0002 /* 2 Byte */ 46 #define REG_APS_FSMCO_8188F 0x0004 /* 4 Byte */ 47 #define REG_SYS_CLKR_8188F 0x0008 /* 2 Byte */ 48 #define REG_9346CR_8188F 0x000A /* 2 Byte */ 49 #define REG_EE_VPD_8188F 0x000C /* 2 Byte */ 50 #define REG_AFE_MISC_8188F 0x0010 /* 1 Byte */ 51 #define REG_SPS0_CTRL_8188F 0x0011 /* 7 Byte */ 52 #define REG_SPS_OCP_CFG_8188F 0x0018 /* 4 Byte */ 53 #define REG_RSV_CTRL_8188F 0x001C /* 3 Byte */ 54 #define REG_RF_CTRL_8188F 0x001F /* 1 Byte */ 55 #define REG_LPLDO_CTRL_8188F 0x0023 /* 1 Byte */ 56 #define REG_AFE_XTAL_CTRL_8188F 0x0024 /* 4 Byte */ 57 #define REG_AFE_PLL_CTRL_8188F 0x0028 /* 4 Byte */ 58 #define REG_MAC_PLL_CTRL_EXT_8188F 0x002c /* 4 Byte */ 59 #define REG_EFUSE_CTRL_8188F 0x0030 60 #define REG_EFUSE_TEST_8188F 0x0034 61 #define REG_PWR_DATA_8188F 0x0038 62 #define REG_CAL_TIMER_8188F 0x003C 63 #define REG_ACLK_MON_8188F 0x003E 64 #define REG_GPIO_MUXCFG_8188F 0x0040 65 #define REG_GPIO_IO_SEL_8188F 0x0042 66 #define REG_MAC_PINMUX_CFG_8188F 0x0043 67 #define REG_GPIO_PIN_CTRL_8188F 0x0044 68 #define REG_GPIO_INTM_8188F 0x0048 69 #define REG_LEDCFG0_8188F 0x004C 70 #define REG_LEDCFG1_8188F 0x004D 71 #define REG_LEDCFG2_8188F 0x004E 72 #define REG_LEDCFG3_8188F 0x004F 73 #define REG_FSIMR_8188F 0x0050 74 #define REG_FSISR_8188F 0x0054 75 #define REG_HSIMR_8188F 0x0058 76 #define REG_HSISR_8188F 0x005c 77 #define REG_GPIO_EXT_CTRL 0x0060 78 #define REG_MULTI_FUNC_CTRL_8188F 0x0068 79 #define REG_GPIO_STATUS_8188F 0x006C 80 #define REG_SDIO_CTRL_8188F 0x0070 81 #define REG_OPT_CTRL_8188F 0x0074 82 #define REG_AFE_XTAL_CTRL_EXT_8188F 0x0078 83 #define REG_MCUFWDL_8188F 0x0080 84 #define REG_FW_DBG_STATUS_8188F 0x0088 85 #define REG_FW_DBG_CTRL_8188F 0x008F 86 #define REG_WLLPS_CTRL_8188F 0x0090 87 #define REG_HIMR0_8188F 0x00B0 88 #define REG_HISR0_8188F 0x00B4 89 #define REG_HIMR1_8188F 0x00B8 90 #define REG_HISR1_8188F 0x00BC 91 #define REG_PMC_DBG_CTRL2_8188F 0x00CC 92 #define REG_EFUSE_BURN_GNT_8188F 0x00CF 93 #define REG_HPON_FSM_8188F 0x00EC 94 #define REG_SYS_CFG_8188F 0x00F0 95 #define REG_SYS_CFG1_8188F 0x00FC 96 #define REG_ROM_VERSION 0x00FD 97 98 /* ----------------------------------------------------- 99 * 100 * 0x0100h ~ 0x01FFh MACTOP General Configuration 101 * 102 * ----------------------------------------------------- */ 103 #define REG_CR_8188F 0x0100 104 #define REG_PBP_8188F 0x0104 105 #define REG_PKT_BUFF_ACCESS_CTRL_8188F 0x0106 106 #define REG_TRXDMA_CTRL_8188F 0x010C 107 #define REG_TRXFF_BNDY_8188F 0x0114 108 #define REG_TRXFF_STATUS_8188F 0x0118 109 #define REG_RXFF_PTR_8188F 0x011C 110 #define REG_CPWM_8188F 0x012F 111 #define REG_FWIMR_8188F 0x0130 112 #define REG_FWISR_8188F 0x0134 113 #define REG_FTIMR_8188F 0x0138 114 #define REG_PKTBUF_DBG_CTRL_8188F 0x0140 115 #define REG_RXPKTBUF_CTRL_8188F 0x0142 116 #define REG_PKTBUF_DBG_DATA_L_8188F 0x0144 117 #define REG_PKTBUF_DBG_DATA_H_8188F 0x0148 118 119 #define REG_TC0_CTRL_8188F 0x0150 120 #define REG_TC1_CTRL_8188F 0x0154 121 #define REG_TC2_CTRL_8188F 0x0158 122 #define REG_TC3_CTRL_8188F 0x015C 123 #define REG_TC4_CTRL_8188F 0x0160 124 #define REG_TCUNIT_BASE_8188F 0x0164 125 #define REG_RSVD3_8188F 0x0168 126 #define REG_32K_CAL_REG1_8188F 0x0198 127 #define REG_C2HEVT_MSG_NORMAL_8188F 0x01A0 128 #define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 129 #define reg_c2h_evt_cmd_content_88xx 0x01A2 130 #define REG_C2HEVT_CMD_LEN_88XX 0x01AE 131 #define REG_C2HEVT_CLEAR_8188F 0x01AF 132 #define REG_MCUTST_1_8188F 0x01C0 133 #define REG_MCUTST_2_8188F 0x01C4 134 #define REG_MCUTST_WOWLAN_8188F 0x01C7 135 #define REG_FMETHR_8188F 0x01C8 136 #define REG_HMETFR_8188F 0x01CC 137 #define REG_HMEBOX_0_8188F 0x01D0 138 #define REG_HMEBOX_1_8188F 0x01D4 139 #define REG_HMEBOX_2_8188F 0x01D8 140 #define REG_HMEBOX_3_8188F 0x01DC 141 #define REG_LLT_INIT_8188F 0x01E0 142 #define REG_HMEBOX_EXT0_8188F 0x01F0 143 #define REG_HMEBOX_EXT1_8188F 0x01F4 144 #define REG_HMEBOX_EXT2_8188F 0x01F8 145 #define REG_HMEBOX_EXT3_8188F 0x01FC 146 147 /* ----------------------------------------------------- 148 * 149 * 0x0200h ~ 0x027Fh TXDMA Configuration 150 * 151 * ----------------------------------------------------- */ 152 #define REG_RQPN_8188F 0x0200 153 #define REG_FIFOPAGE_8188F 0x0204 154 #define REG_TDECTRL_8188F 0x0208 155 #define REG_DWBCN0_CTRL_8188F REG_TDECTRL 156 #define REG_TXDMA_OFFSET_CHK_8188F 0x020C 157 #define REG_TXDMA_STATUS_8188F 0x0210 158 #define REG_RQPN_NPQ_8188F 0x0214 159 #define REG_AUTO_LLT_8188F 0x0224 160 #define REG_TDECTRL1_8188F 0x0228 161 #define REG_DWBCN1_CTRL_8188F 0x0228 162 163 /* ----------------------------------------------------- 164 * 165 * 0x0280h ~ 0x02FFh RXDMA Configuration 166 * 167 * ----------------------------------------------------- */ 168 #define REG_RXDMA_AGG_PG_TH_8188F 0x0280 169 #define REG_FW_UPD_RDPTR_8188F 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */ 170 #define REG_RXDMA_CONTROL_8188F 0x0286 /* Control the RX DMA. */ 171 #define REG_RXPKT_NUM_8188F 0x0287 /* The number of packets in RXPKTBUF. */ 172 #define REG_RXDMA_STATUS_8188F 0x0288 173 #define REG_RXDMA_PRO_8188F 0x0290 174 #define REG_EARLY_MODE_CONTROL_8188F 0x02BC 175 #define REG_RSVD5_8188F 0x02F0 176 #define REG_RSVD6_8188F 0x02F4 177 178 /* ----------------------------------------------------- 179 * 180 * 0x0300h ~ 0x03FFh PCIe 181 * 182 * ----------------------------------------------------- */ 183 #define REG_PCIE_CTRL_REG_8188F 0x0300 184 #define REG_INT_MIG_8188F 0x0304 /* Interrupt Migration */ 185 #define REG_BCNQ_DESA_8188F 0x0308 /* TX Beacon Descriptor Address */ 186 #define REG_HQ_DESA_8188F 0x0310 /* TX High Queue Descriptor Address */ 187 #define REG_MGQ_DESA_8188F 0x0318 /* TX Manage Queue Descriptor Address */ 188 #define REG_VOQ_DESA_8188F 0x0320 /* TX VO Queue Descriptor Address */ 189 #define REG_VIQ_DESA_8188F 0x0328 /* TX VI Queue Descriptor Address */ 190 #define REG_BEQ_DESA_8188F 0x0330 /* TX BE Queue Descriptor Address */ 191 #define REG_BKQ_DESA_8188F 0x0338 /* TX BK Queue Descriptor Address */ 192 #define REG_RX_DESA_8188F 0x0340 /* RX Queue Descriptor Address */ 193 #define REG_DBI_WDATA_8188F 0x0348 /* DBI Write data */ 194 #define REG_DBI_RDATA_8188F 0x034C /* DBI Read data */ 195 #define REG_DBI_ADDR_8188F 0x0350 /* DBI Address */ 196 #define REG_DBI_FLAG_8188F 0x0352 /* DBI Read/Write Flag */ 197 #define REG_MDIO_WDATA_8188F 0x0354 /* MDIO for Write PCIE PHY */ 198 #define REG_MDIO_RDATA_8188F 0x0356 /* MDIO for Reads PCIE PHY */ 199 #define REG_MDIO_CTL_8188F 0x0358 /* MDIO for Control */ 200 #define REG_DBG_SEL_8188F 0x0360 /* Debug Selection Register */ 201 #define REG_PCIE_HRPWM_8188F 0x0361 /* PCIe RPWM */ 202 #define REG_PCIE_HCPWM_8188F 0x0363 /* PCIe CPWM */ 203 #define REG_PCIE_MULTIFET_CTRL_8188F 0x036A /* PCIE Multi-Fethc Control */ 204 205 #define REG_MGQ_TXBD_NUM_8188F 0x0380 206 207 /* spec version 11 208 * ----------------------------------------------------- 209 * 210 * 0x0400h ~ 0x047Fh Protocol Configuration 211 * 212 * ----------------------------------------------------- */ 213 #define REG_VOQ_INFORMATION_8188F 0x0400 214 #define REG_VIQ_INFORMATION_8188F 0x0404 215 #define REG_BEQ_INFORMATION_8188F 0x0408 216 #define REG_BKQ_INFORMATION_8188F 0x040C 217 #define REG_MGQ_INFORMATION_8188F 0x0410 218 #define REG_HGQ_INFORMATION_8188F 0x0414 219 #define REG_BCNQ_INFORMATION_8188F 0x0418 220 #define REG_TXPKT_EMPTY_8188F 0x041A 221 222 #define REG_FWHW_TXQ_CTRL_8188F 0x0420 223 #define REG_HWSEQ_CTRL_8188F 0x0423 224 #define REG_TXPKTBUF_BCNQ_BDNY_8188F 0x0424 225 #define REG_TXPKTBUF_MGQ_BDNY_8188F 0x0425 226 #define REG_LIFECTRL_CTRL_8188F 0x0426 227 #define REG_MULTI_BCNQ_OFFSET_8188F 0x0427 228 #define REG_SPEC_SIFS_8188F 0x0428 229 #define REG_RL_8188F 0x042A 230 #define REG_TXBF_CTRL_8188F 0x042C 231 #define REG_DARFRC_8188F 0x0430 232 #define REG_RARFRC_8188F 0x0438 233 #define REG_RRSR_8188F 0x0440 234 #define REG_ARFR0_8188F 0x0444 235 #define REG_ARFR1_8188F 0x044C 236 #define REG_CCK_CHECK_8188F 0x0454 237 #define REG_AMPDU_MAX_TIME_8188F 0x0456 238 #define REG_TXPKTBUF_BCNQ_BDNY1_8188F 0x0457 239 240 #define REG_AMPDU_MAX_LENGTH_8188F 0x0458 241 #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8188F 0x045D 242 #define REG_NDPA_OPT_CTRL_8188F 0x045F 243 #define REG_FAST_EDCA_CTRL_8188F 0x0460 244 #define REG_RD_RESP_PKT_TH_8188F 0x0463 245 #define REG_DATA_SC_8188F 0x0483 246 #define REG_TXRPT_START_OFFSET 0x04AC 247 #define REG_POWER_STAGE1_8188F 0x04B4 248 #define REG_POWER_STAGE2_8188F 0x04B8 249 #define REG_AMPDU_BURST_MODE_8188F 0x04BC 250 #define REG_PKT_VO_VI_LIFE_TIME_8188F 0x04C0 251 #define REG_PKT_BE_BK_LIFE_TIME_8188F 0x04C2 252 #define REG_STBC_SETTING_8188F 0x04C4 253 #define REG_HT_SINGLE_AMPDU_8188F 0x04C7 254 #define REG_PROT_MODE_CTRL_8188F 0x04C8 255 #define REG_MAX_AGGR_NUM_8188F 0x04CA 256 #define REG_RTS_MAX_AGGR_NUM_8188F 0x04CB 257 #define REG_BAR_MODE_CTRL_8188F 0x04CC 258 #define REG_RA_TRY_RATE_AGG_LMT_8188F 0x04CF 259 #define REG_MACID_PKT_DROP0_8188F 0x04D0 260 #define REG_MACID_PKT_SLEEP_8188F 0x04D4 261 262 /* ----------------------------------------------------- 263 * 264 * 0x0500h ~ 0x05FFh EDCA Configuration 265 * 266 * ----------------------------------------------------- */ 267 #define REG_EDCA_VO_PARAM_8188F 0x0500 268 #define REG_EDCA_VI_PARAM_8188F 0x0504 269 #define REG_EDCA_BE_PARAM_8188F 0x0508 270 #define REG_EDCA_BK_PARAM_8188F 0x050C 271 #define REG_BCNTCFG_8188F 0x0510 272 #define REG_PIFS_8188F 0x0512 273 #define REG_RDG_PIFS_8188F 0x0513 274 #define REG_SIFS_CTX_8188F 0x0514 275 #define REG_SIFS_TRX_8188F 0x0516 276 #define REG_AGGR_BREAK_TIME_8188F 0x051A 277 #define REG_SLOT_8188F 0x051B 278 #define REG_TX_PTCL_CTRL_8188F 0x0520 279 #define REG_TXPAUSE_8188F 0x0522 280 #define REG_DIS_TXREQ_CLR_8188F 0x0523 281 #define REG_RD_CTRL_8188F 0x0524 282 /* 283 * Format for offset 540h-542h: 284 * [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. 285 * [7:4]: Reserved. 286 * [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. 287 * [23:20]: Reserved 288 * Description: 289 * | 290 * |<--Setup--|--Hold------------>| 291 * --------------|---------------------- 292 * | 293 * TBTT 294 * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. 295 * Described by Designer Tim and Bruce, 2011-01-14. 296 * */ 297 #define REG_TBTT_PROHIBIT_8188F 0x0540 298 #define REG_RD_NAV_NXT_8188F 0x0544 299 #define REG_NAV_PROT_LEN_8188F 0x0546 300 #define REG_BCN_CTRL_8188F 0x0550 301 #define REG_BCN_CTRL_1_8188F 0x0551 302 #define REG_MBID_NUM_8188F 0x0552 303 #define REG_DUAL_TSF_RST_8188F 0x0553 304 #define REG_BCN_INTERVAL_8188F 0x0554 305 #define REG_DRVERLYINT_8188F 0x0558 306 #define REG_BCNDMATIM_8188F 0x0559 307 #define REG_ATIMWND_8188F 0x055A 308 #define REG_USTIME_TSF_8188F 0x055C 309 #define REG_BCN_MAX_ERR_8188F 0x055D 310 #define REG_RXTSF_OFFSET_CCK_8188F 0x055E 311 #define REG_RXTSF_OFFSET_OFDM_8188F 0x055F 312 #define REG_TSFTR_8188F 0x0560 313 #define REG_CTWND_8188F 0x0572 314 #define REG_SECONDARY_CCA_CTRL_8188F 0x0577 315 #define REG_PSTIMER_8188F 0x0580 316 #define REG_TIMER0_8188F 0x0584 317 #define REG_TIMER1_8188F 0x0588 318 #define REG_ACMHWCTRL_8188F 0x05C0 319 #define REG_SCH_TXCMD_8188F 0x05F8 320 321 /* ----------------------------------------------------- 322 * 323 * 0x0600h ~ 0x07FFh WMAC Configuration 324 * 325 * ----------------------------------------------------- */ 326 #define REG_MAC_CR_8188F 0x0600 327 #define REG_TCR_8188F 0x0604 328 #define REG_RCR_8188F 0x0608 329 #define REG_RX_PKT_LIMIT_8188F 0x060C 330 #define REG_RX_DLK_TIME_8188F 0x060D 331 #define REG_RX_DRVINFO_SZ_8188F 0x060F 332 333 #define REG_MACID_8188F 0x0610 334 #define REG_BSSID_8188F 0x0618 335 #define REG_MAR_8188F 0x0620 336 #define REG_MBIDCAMCFG_8188F 0x0628 337 338 #define REG_USTIME_EDCA_8188F 0x0638 339 #define REG_MAC_SPEC_SIFS_8188F 0x063A 340 #define REG_RESP_SIFP_CCK_8188F 0x063C 341 #define REG_RESP_SIFS_OFDM_8188F 0x063E 342 #define REG_ACKTO_8188F 0x0640 343 #define REG_CTS2TO_8188F 0x0641 344 #define REG_EIFS_8188F 0x0642 345 346 #define REG_NAV_UPPER_8188F 0x0652 /* unit of 128 */ 347 #define REG_TRXPTCL_CTL_8188F 0x0668 348 349 /* security */ 350 #define REG_CAMCMD_8188F 0x0670 351 #define REG_CAMWRITE_8188F 0x0674 352 #define REG_CAMREAD_8188F 0x0678 353 #define REG_CAMDBG_8188F 0x067C 354 #define REG_SECCFG_8188F 0x0680 355 356 /* Power */ 357 #define REG_WOW_CTRL_8188F 0x0690 358 #define REG_PS_RX_INFO_8188F 0x0692 359 #define REG_UAPSD_TID_8188F 0x0693 360 #define REG_WKFMCAM_CMD_8188F 0x0698 361 #define REG_WKFMCAM_NUM_8188F 0x0698 362 #define REG_WKFMCAM_RWD_8188F 0x069C 363 #define REG_RXFLTMAP0_8188F 0x06A0 364 #define REG_RXFLTMAP1_8188F 0x06A2 365 #define REG_RXFLTMAP2_8188F 0x06A4 366 #define REG_BCN_PSR_RPT_8188F 0x06A8 367 #define REG_BT_COEX_TABLE_8188F 0x06C0 368 #define REG_BFMER0_INFO_8188F 0x06E4 369 #define REG_BFMER1_INFO_8188F 0x06EC 370 #define REG_CSI_RPT_PARAM_BW20_8188F 0x06F4 371 #define REG_CSI_RPT_PARAM_BW40_8188F 0x06F8 372 #define REG_CSI_RPT_PARAM_BW80_8188F 0x06FC 373 374 /* Hardware Port 2 */ 375 #define REG_MACID1_8188F 0x0700 376 #define REG_BSSID1_8188F 0x0708 377 #define REG_BFMEE_SEL_8188F 0x0714 378 #define REG_SND_PTCL_CTRL_8188F 0x0718 379 380 /* LTE_COEX */ 381 #define REG_LTECOEX_CTRL 0x07C0 382 #define REG_LTECOEX_WRITE_DATA 0x07C4 383 384 /* ----------------------------------------------------- 385 * 386 * Redifine 8192C register definition for compatibility 387 * 388 * ----------------------------------------------------- */ 389 390 /* TODO: use these definition when using REG_xxx naming rule. 391 * NOTE: DO NOT Remove these definition. Use later. */ 392 #define EFUSE_CTRL_8188F REG_EFUSE_CTRL_8188F /* E-Fuse Control. */ 393 #define EFUSE_TEST_8188F REG_EFUSE_TEST_8188F /* E-Fuse Test. */ 394 #define MSR_8188F (REG_CR_8188F + 2) /* Media status register */ 395 #define ISR_8188F REG_HISR0_8188F 396 #define TSFR_8188F REG_TSFTR_8188F /* Timing Sync Function Timer Register. */ 397 398 #define PBP_8188F REG_PBP_8188F 399 400 /* Redifine MACID register, to compatible prior ICs. */ 401 #define IDR0_8188F REG_MACID_8188F /* MAC ID Register, Offset 0x0050-0x0053 */ 402 #define IDR4_8188F (REG_MACID_8188F + 4) /* MAC ID Register, Offset 0x0054-0x0055 */ 403 404 /* 405 * 9. security Control Registers (Offset: ) 406 * */ 407 #define RWCAM_8188F REG_CAMCMD_8188F /* 8190 data Sheet is called CAMcmd */ 408 #define WCAMI_8188F REG_CAMWRITE_8188F /* Software write CAM input content */ 409 #define RCAMO_8188F REG_CAMREAD_8188F /* Software read/write CAM config */ 410 #define CAMDBG_8188F REG_CAMDBG_8188F 411 #define SECR_8188F REG_SECCFG_8188F /* security Configuration Register */ 412 413 /* ---------------------------------------------------------------------------- 414 * 8195 IMR/ISR bits (offset 0xB0, 8bits) 415 * ---------------------------------------------------------------------------- */ 416 #define IMR_DISABLED_8188F 0 417 /* IMR DW0(0x00B0-00B3) Bit 0-31 */ 418 #define IMR_TIMER2_8188F BIT(31) /* Timeout interrupt 2 */ 419 #define IMR_TIMER1_8188F BIT(30) /* Timeout interrupt 1 */ 420 #define IMR_PSTIMEOUT_8188F BIT(29) /* Power Save Time Out Interrupt */ 421 #define IMR_GTINT4_8188F BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ 422 #define IMR_GTINT3_8188F BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ 423 #define IMR_TXBCN0ERR_8188F BIT(26) /* Transmit Beacon0 Error */ 424 #define IMR_TXBCN0OK_8188F BIT(25) /* Transmit Beacon0 OK */ 425 #define IMR_TSF_BIT32_TOGGLE_8188F BIT(24) /* TSF Timer BIT32 toggle indication interrupt */ 426 #define IMR_BCNDMAINT0_8188F BIT(20) /* Beacon DMA Interrupt 0 */ 427 #define IMR_BCNDERR0_8188F BIT(16) /* Beacon Queue DMA OK0 */ 428 #define IMR_HSISR_IND_ON_INT_8188F BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ 429 #define IMR_BCNDMAINT_E_8188F BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ 430 #define IMR_ATIMEND_8188F BIT(12) /* CTWidnow End or ATIM Window End */ 431 #define IMR_C2HCMD_8188F BIT(10) /* CPU to Host Command INT status, Write 1 clear */ 432 #define IMR_CPWM2_8188F BIT(9) /* CPU power mode exchange INT status, Write 1 clear */ 433 #define IMR_CPWM_8188F BIT(8) /* CPU power mode exchange INT status, Write 1 clear */ 434 #define IMR_HIGHDOK_8188F BIT(7) /* High Queue DMA OK */ 435 #define IMR_MGNTDOK_8188F BIT(6) /* Management Queue DMA OK */ 436 #define IMR_BKDOK_8188F BIT(5) /* AC_BK DMA OK */ 437 #define IMR_BEDOK_8188F BIT(4) /* AC_BE DMA OK */ 438 #define IMR_VIDOK_8188F BIT(3) /* AC_VI DMA OK */ 439 #define IMR_VODOK_8188F BIT(2) /* AC_VO DMA OK */ 440 #define IMR_RDU_8188F BIT(1) /* Rx Descriptor Unavailable */ 441 #define IMR_ROK_8188F BIT(0) /* Receive DMA OK */ 442 443 /* IMR DW1(0x00B4-00B7) Bit 0-31 */ 444 #define IMR_BCNDMAINT7_8188F BIT(27) /* Beacon DMA Interrupt 7 */ 445 #define IMR_BCNDMAINT6_8188F BIT(26) /* Beacon DMA Interrupt 6 */ 446 #define IMR_BCNDMAINT5_8188F BIT(25) /* Beacon DMA Interrupt 5 */ 447 #define IMR_BCNDMAINT4_8188F BIT(24) /* Beacon DMA Interrupt 4 */ 448 #define IMR_BCNDMAINT3_8188F BIT(23) /* Beacon DMA Interrupt 3 */ 449 #define IMR_BCNDMAINT2_8188F BIT(22) /* Beacon DMA Interrupt 2 */ 450 #define IMR_BCNDMAINT1_8188F BIT(21) /* Beacon DMA Interrupt 1 */ 451 #define IMR_BCNDOK7_8188F BIT(20) /* Beacon Queue DMA OK Interrup 7 */ 452 #define IMR_BCNDOK6_8188F BIT(19) /* Beacon Queue DMA OK Interrup 6 */ 453 #define IMR_BCNDOK5_8188F BIT(18) /* Beacon Queue DMA OK Interrup 5 */ 454 #define IMR_BCNDOK4_8188F BIT(17) /* Beacon Queue DMA OK Interrup 4 */ 455 #define IMR_BCNDOK3_8188F BIT(16) /* Beacon Queue DMA OK Interrup 3 */ 456 #define IMR_BCNDOK2_8188F BIT(15) /* Beacon Queue DMA OK Interrup 2 */ 457 #define IMR_BCNDOK1_8188F BIT(14) /* Beacon Queue DMA OK Interrup 1 */ 458 #define IMR_ATIMEND_E_8188F BIT(13) /* ATIM Window End Extension for Win7 */ 459 #define IMR_TXERR_8188F BIT(11) /* Tx Error Flag Interrupt status, write 1 clear. */ 460 #define IMR_RXERR_8188F BIT(10) /* Rx Error Flag INT status, Write 1 clear */ 461 #define IMR_TXFOVW_8188F BIT(9) /* Transmit FIFO Overflow */ 462 #define IMR_RXFOVW_8188F BIT(8) /* Receive FIFO Overflow */ 463 464 /*=================================================================== 465 ===================================================================== 466 Here the register defines are for 92C. When the define is as same with 92C, 467 we will use the 92C's define for the consistency 468 So the following defines for 92C is not entire!!!!!! 469 ===================================================================== 470 =====================================================================*/ 471 /* 472 Based on Datasheet V33---090401 473 Register Summary 474 Current IOREG MAP 475 0x0000h ~ 0x00FFh System Configuration (256 Bytes) 476 0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) 477 0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) 478 0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) 479 0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) 480 0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) 481 0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) 482 0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) 483 0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) 484 */ 485 /* ---------------------------------------------------------------------------- 486 * 8195 (TXPAUSE) transmission pause (Offset 0x522, 8 bits) 487 * ---------------------------------------------------------------------------- 488 * 489 #define StopBecon BIT(6) 490 #define StopHigh BIT(5) 491 #define StopMgt BIT(4) 492 #define StopVO BIT(3) 493 #define StopVI BIT(2) 494 #define StopBE BIT(1) 495 #define StopBK BIT(0) 496 */ 497 498 /* **************************************************************************** 499 * 8192C Regsiter Bit and Content definition 500 * **************************************************************************** 501 * ----------------------------------------------------- 502 * 503 * 0x0000h ~ 0x00FFh System Configuration 504 * 505 * ----------------------------------------------------- */ 506 #if 0 507 /* 2 SYS_ISO_CTRL */ 508 #define ISO_MD2PP BIT(0) 509 #define ISO_UA2USB BIT(1) 510 #define ISO_UD2CORE BIT(2) 511 #define ISO_PA2PCIE BIT(3) 512 #define ISO_PD2CORE BIT(4) 513 #define ISO_IP2MAC BIT(5) 514 #define ISO_DIOP BIT(6) 515 #define ISO_DIOE BIT(7) 516 #define ISO_EB2CORE BIT(8) 517 #define ISO_DIOR BIT(9) 518 #define PWC_EV12V BIT(15) 519 520 521 /* 2 SYS_FUNC_EN */ 522 #define FEN_BBRSTB BIT(0) 523 #define FEN_BB_GLB_RSTn BIT(1) 524 #define FEN_USBA BIT(2) 525 #define FEN_UPLL BIT(3) 526 #define FEN_USBD BIT(4) 527 #define FEN_DIO_PCIE BIT(5) 528 #define FEN_PCIEA BIT(6) 529 #define FEN_PPLL BIT(7) 530 #define FEN_PCIED BIT(8) 531 #define FEN_DIOE BIT(9) 532 #define FEN_CPUEN BIT(10) 533 #define FEN_DCORE BIT(11) 534 #define FEN_ELDR BIT(12) 535 #define FEN_DIO_RF BIT(13) 536 #define FEN_HWPDN BIT(14) 537 #define FEN_MREGEN BIT(15) 538 539 /* 2 APS_FSMCO */ 540 #define PFM_LDALL BIT(0) 541 #define PFM_ALDN BIT(1) 542 #define PFM_LDKP BIT(2) 543 #define PFM_WOWL BIT(3) 544 #define EnPDN BIT(4) 545 #define PDN_PL BIT(5) 546 #define APFM_ONMAC BIT(8) 547 #define APFM_OFF BIT(9) 548 #define APFM_RSM BIT(10) 549 #define AFSM_HSUS BIT(11) 550 #define AFSM_PCIE BIT(12) 551 #define APDM_MAC BIT(13) 552 #define APDM_HOST BIT(14) 553 #define APDM_HPDN BIT(15) 554 #define RDY_MACON BIT(16) 555 #define SUS_HOST BIT(17) 556 #define ROP_ALD BIT(20) 557 #define ROP_PWR BIT(21) 558 #define ROP_SPS BIT(22) 559 #define SOP_MRST BIT(25) 560 #define SOP_FUSE BIT(26) 561 #define SOP_ABG BIT(27) 562 #define SOP_AMB BIT(28) 563 #define SOP_RCK BIT(29) 564 #define SOP_A8M BIT(30) 565 #define XOP_BTCK BIT(31) 566 567 /* 2 SYS_CLKR */ 568 #define ANAD16V_EN BIT(0) 569 #define ANA8M BIT(1) 570 #define MACSLP BIT(4) 571 #define LOADER_CLK_EN BIT(5) 572 573 574 /* 2 9346CR */ 575 576 #define BOOT_FROM_EEPROM BIT(4) 577 #define EEPROM_EN BIT(5) 578 579 580 /* 2 RF_CTRL */ 581 #define RF_EN BIT(0) 582 #define RF_RSTB BIT(1) 583 #define RF_SDMRSTB BIT(2) 584 585 /* 2 LDOV12D_CTRL */ 586 #define LDV12_EN BIT(0) 587 #define LDV12_SDBY BIT(1) 588 #define LPLDO_HSM BIT(2) 589 #define LPLDO_LSM_DIS BIT(3) 590 #define _LDV12_VADJ(x) (((x) & 0xF) << 4) 591 592 593 /* 2 EFUSE_TEST (For RTL8188 partially) */ 594 #define EF_TRPT BIT(7) 595 #define EF_CELL_SEL (BIT(8) | BIT(9)) /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ 596 #define LDOE25_EN BIT(31) 597 #define EFUSE_SEL(x) (((x) & 0x3) << 8) 598 #define EFUSE_SEL_MASK 0x300 599 #define EFUSE_WIFI_SEL_0 0x0 600 #define EFUSE_BT_SEL_0 0x1 601 #define EFUSE_BT_SEL_1 0x2 602 #define EFUSE_BT_SEL_2 0x3 603 604 605 /* 2 8051FWDL */ 606 /* 2 MCUFWDL */ 607 #define MCUFWDL_EN BIT(0) 608 #define MCUFWDL_RDY BIT(1) 609 #define FWDL_ChkSum_rpt BIT(2) 610 #define MACINI_RDY BIT(3) 611 #define BBINI_RDY BIT(4) 612 #define RFINI_RDY BIT(5) 613 #define WINTINI_RDY BIT(6) 614 #define RAM_DL_SEL BIT(7) 615 #define ROM_DLEN BIT(19) 616 #define CPRST BIT(23) 617 618 619 620 /* 2 REG_SYS_CFG */ 621 #define XCLK_VLD BIT(0) 622 #define ACLK_VLD BIT(1) 623 #define UCLK_VLD BIT(2) 624 #define PCLK_VLD BIT(3) 625 #define PCIRSTB BIT(4) 626 #define V15_VLD BIT(5) 627 #define TRP_B15V_EN BIT(7) 628 #define SIC_IDLE BIT(8) 629 #define BD_MAC2 BIT(9) 630 #define BD_MAC1 BIT(10) 631 #define IC_MACPHY_MODE BIT(11) 632 #define CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15)) 633 #define BT_FUNC BIT(16) 634 #define VENDOR_ID BIT(19) 635 #define PAD_HWPD_IDN BIT(22) 636 #define TRP_VAUX_EN BIT(23) /* RTL ID */ 637 #define TRP_BT_EN BIT(24) 638 #define BD_PKG_SEL BIT(25) 639 #define BD_HCI_SEL BIT(26) 640 #define TYPE_ID BIT(27) 641 642 #define CHIP_VER_RTL_MASK 0xF000 /* Bit 12 ~ 15 */ 643 #define CHIP_VER_RTL_SHIFT 12 644 645 #endif 646 /* ----------------------------------------------------- 647 * 648 * 0x0100h ~ 0x01FFh MACTOP General Configuration 649 * 650 * ----------------------------------------------------- */ 651 #if 0 652 653 /* 2 Function Enable Registers */ 654 /* 2 CR 0x0100-0x0103 */ 655 656 #define HCI_TXDMA_EN BIT(0) 657 #define HCI_RXDMA_EN BIT(1) 658 #define TXDMA_EN BIT(2) 659 #define RXDMA_EN BIT(3) 660 #define PROTOCOL_EN BIT(4) 661 #define SCHEDULE_EN BIT(5) 662 #define MACTXEN BIT(6) 663 #define MACRXEN BIT(7) 664 #define ENSWBCN BIT(8) 665 #define ENSEC BIT(9) 666 #define CALTMR_EN BIT(10) /* 32k CAL TMR enable */ 667 668 /* Network type */ 669 #define _NETTYPE(x) (((x) & 0x3) << 16) 670 #define MASK_NETTYPE 0x30000 671 #define NT_NO_LINK 0x0 672 #define NT_LINK_AD_HOC 0x1 673 #define NT_LINK_AP 0x2 674 #define NT_AS_AP 0x3 675 676 677 /* 2 PBP - Page Size Register 0x0104 */ 678 #define GET_RX_PAGE_SIZE(value) ((value) & 0xF) 679 #define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) 680 #define _PSRX_MASK 0xF 681 #define _PSTX_MASK 0xF0 682 #define _PSRX(x) (x) 683 #define _PSTX(x) ((x) << 4) 684 685 #define PBP_64 0x0 686 #define PBP_128 0x1 687 #define PBP_256 0x2 688 #define PBP_512 0x3 689 #define PBP_1024 0x4 690 691 692 /* 2 TX/RXDMA 0x010C */ 693 #define RXDMA_ARBBW_EN BIT(0) 694 #define RXSHFT_EN BIT(1) 695 #define RXDMA_AGG_EN BIT(2) 696 #define QS_VO_QUEUE BIT(8) 697 #define QS_VI_QUEUE BIT(9) 698 #define QS_BE_QUEUE BIT(10) 699 #define QS_BK_QUEUE BIT(11) 700 #define QS_MANAGER_QUEUE BIT(12) 701 #define QS_HIGH_QUEUE BIT(13) 702 703 #define HQSEL_VOQ BIT(0) 704 #define HQSEL_VIQ BIT(1) 705 #define HQSEL_BEQ BIT(2) 706 #define HQSEL_BKQ BIT(3) 707 #define HQSEL_MGTQ BIT(4) 708 #define HQSEL_HIQ BIT(5) 709 710 /* For normal driver, 0x10C */ 711 #define _TXDMA_HIQ_MAP(x) (((x) & 0x3) << 14) 712 #define _TXDMA_MGQ_MAP(x) (((x) & 0x3) << 12) 713 #define _TXDMA_BKQ_MAP(x) (((x) & 0x3) << 10) 714 #define _TXDMA_BEQ_MAP(x) (((x) & 0x3) << 8) 715 #define _TXDMA_VIQ_MAP(x) (((x) & 0x3) << 6) 716 #define _TXDMA_VOQ_MAP(x) (((x) & 0x3) << 4) 717 718 #define QUEUE_LOW 1 719 #define QUEUE_NORMAL 2 720 #define QUEUE_HIGH 3 721 722 723 /* 2 REG_C2HEVT_CLEAR 0x01AF */ 724 #define C2H_EVT_HOST_CLOSE 0x00 /* Set by driver and notify FW that the driver has read the C2H command message */ 725 #define C2H_EVT_FW_CLOSE 0xFF /* Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. */ 726 727 728 729 /* 2 LLT_INIT 0x01E0 */ 730 #define _LLT_NO_ACTIVE 0x0 731 #define _LLT_WRITE_ACCESS 0x1 732 #define _LLT_READ_ACCESS 0x2 733 734 #define _LLT_INIT_DATA(x) ((x) & 0xFF) 735 #define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) 736 #define _LLT_OP(x) (((x) & 0x3) << 30) 737 #define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) 738 739 #endif 740 /* ----------------------------------------------------- 741 * 742 * 0x0200h ~ 0x027Fh TXDMA Configuration 743 * 744 * ----------------------------------------------------- */ 745 #if 0 746 /* 2 TDECTL 0x0208 */ 747 #define BLK_DESC_NUM_SHIFT 4 748 #define BLK_DESC_NUM_MASK 0xF 749 750 751 /* 2 TXDMA_OFFSET_CHK 0x020C */ 752 #define DROP_DATA_EN BIT(9) 753 #endif 754 /* ----------------------------------------------------- 755 * 756 * 0x0280h ~ 0x028Bh RX DMA Configuration 757 * 758 * ----------------------------------------------------- */ 759 #if 0 760 /* 2 REG_RXDMA_CONTROL, 0x0286h */ 761 762 /* Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before */ 763 /* this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. */ 764 #define RXPKT_RELEASE_POLL BIT(0) 765 /* Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in */ 766 /* this bit. FW can start releasing packets after RXDMA entering idle mode. */ 767 #define RXDMA_IDLE BIT(1) 768 /* When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host */ 769 /* completed, and stop DMA packet to host. RXDMA will then report Default: 0; */ 770 #define RW_RELEASE_EN BIT(2) 771 #endif 772 /* ----------------------------------------------------- 773 * 774 * 0x0400h ~ 0x047Fh Protocol Configuration 775 * 776 * ----------------------------------------------------- */ 777 #if 0 778 /* 2 FWHW_TXQ_CTRL 0x0420 */ 779 #define EN_AMPDU_RTY_NEW BIT(7) 780 781 782 /* 2 REG_LIFECTRL_CTRL 0x0426 */ 783 #define HAL92C_EN_PKT_LIFE_TIME_BK BIT(3) 784 #define HAL92C_EN_PKT_LIFE_TIME_BE BIT(2) 785 #define HAL92C_EN_PKT_LIFE_TIME_VI BIT(1) 786 #define HAL92C_EN_PKT_LIFE_TIME_VO BIT(0) 787 788 #define HAL92C_MSDU_LIFE_TIME_UNIT 128 /* in us, said by Tim. */ 789 790 791 /* 2 SPEC SIFS 0x0428 */ 792 #define _SPEC_SIFS_CCK(x) ((x) & 0xFF) 793 #define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) 794 795 /* 2 RL 0x042A */ 796 #define RETRY_LIMIT_SHORT_SHIFT 8 797 #define RETRY_LIMIT_LONG_SHIFT 0 798 799 #define _LRL(x) ((x) & 0x3F) 800 #define _SRL(x) (((x) & 0x3F) << 8) 801 #endif 802 803 /* ----------------------------------------------------- 804 * 805 * 0x0500h ~ 0x05FFh EDCA Configuration 806 * 807 * ----------------------------------------------------- */ 808 #if 0 809 /* 2 EDCA setting 0x050C */ 810 #define AC_PARAM_TXOP_LIMIT_OFFSET 16 811 #define AC_PARAM_ECW_MAX_OFFSET 12 812 #define AC_PARAM_ECW_MIN_OFFSET 8 813 #define AC_PARAM_AIFS_OFFSET 0 814 815 816 /* 2 BCN_CTRL 0x0550 */ 817 #define EN_TXBCN_RPT BIT(2) 818 #define EN_BCN_FUNCTION BIT(3) 819 820 /* 2 TxPause 0x0522 */ 821 #define STOP_BCNQ BIT(6) 822 #endif 823 824 /* 2 ACMHWCTRL 0x05C0 */ 825 #define acm_hw_hw_en_8188f BIT(0) 826 #define acm_hw_voq_en_8188f BIT(1) 827 #define acm_hw_viq_en_8188f BIT(2) 828 #define acm_hw_beq_en_8188f BIT(3) 829 #define acm_hw_voq_status_8188f BIT(5) 830 #define acm_hw_viq_status_8188f BIT(6) 831 #define acm_hw_beq_status_8188f BIT(7) 832 833 /* ----------------------------------------------------- 834 * 835 * 0x0600h ~ 0x07FFh WMAC Configuration 836 * 837 * ----------------------------------------------------- */ 838 #if 0 839 840 /* 2 TCR 0x0604 */ 841 #define DIS_GCLK BIT(1) 842 #define PAD_SEL BIT(2) 843 #define PWR_ST BIT(6) 844 #define PWRBIT_OW_EN BIT(7) 845 #define ACRC BIT(8) 846 #define CFENDFORM BIT(9) 847 #define ICV BIT(10) 848 #endif 849 850 /* ---------------------------------------------------------------------------- 851 * 8195 (RCR) Receive Configuration Register (Offset 0x608, 32 bits) 852 * ---------------------------------------------------------------------------- */ 853 #if 0 854 #define RCR_APPFCS BIT(31) /* WMAC append FCS after pauload */ 855 #define RCR_APP_MIC BIT(30) /* MACRX will retain the MIC at the bottom of the packet. */ 856 #define RCR_APP_ICV BIT(29) /* MACRX will retain the ICV at the bottom of the packet. */ 857 #define RCR_APP_PHYST_RXFF BIT(28) /* HY status is appended before RX packet in RXFF */ 858 #define RCR_APP_BA_SSN BIT(27) /* SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. */ 859 #define RCR_RSVD_BIT(26) BIT26 /* Reserved */ 860 #endif 861 #define RCR_TCPOFLD_EN BIT(25) /* Enable TCP checksum offload */ 862 863 #endif /* #ifndef __INC_HAL8188FREG_H */ 864