1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __PHYDMRAINFO_H__ 27 #define __PHYDMRAINFO_H__ 28 29 /* 2019.12.24 Add ra mask c2h & h2c API*/ 30 #define RAINFO_VERSION "8.6" 31 32 #define FORCED_UPDATE_RAMASK_PERIOD 5 33 34 #define H2C_MAX_LENGTH 7 35 36 #define RA_FLOOR_UP_GAP 3 37 #define RA_FLOOR_TABLE_SIZE 7 38 39 #define ACTIVE_TP_THRESHOLD 1 40 #define RA_RETRY_DESCEND_NUM 2 41 #define RA_RETRY_LIMIT_LOW 4 42 #define RA_RETRY_LIMIT_HIGH 32 43 44 #define PHYDM_IS_LEGACY_RATE(rate) ((rate <= ODM_RATE54M) ? true : false) 45 #define PHYDM_IS_CCK_RATE(rate) ((rate <= ODM_RATE11M) ? true : false) 46 47 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 48 #define FIRST_MACID 1 49 #else 50 #define FIRST_MACID 0 51 #endif 52 53 /* @1 ============================================================ 54 * 1 enumrate 55 * 1 ============================================================ 56 */ 57 58 enum phydm_ra_dbg_para { 59 RADBG_PCR_TH_OFFSET = 0, 60 RADBG_RTY_PENALTY = 1, 61 RADBG_N_HIGH = 2, 62 RADBG_N_LOW = 3, 63 RADBG_TRATE_UP_TABLE = 4, 64 RADBG_TRATE_DOWN_TABLE = 5, 65 RADBG_TRYING_NECESSARY = 6, 66 RADBG_TDROPING_NECESSARY = 7, 67 RADBG_RATE_UP_RTY_RATIO = 8, 68 RADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */ 69 70 RADBG_DEBUG_MONITOR1 = 0xc, 71 RADBG_DEBUG_MONITOR2 = 0xd, 72 RADBG_DEBUG_MONITOR3 = 0xe, 73 RADBG_DEBUG_MONITOR4 = 0xf, 74 RADBG_DEBUG_MONITOR5 = 0x10, 75 NUM_RA_PARA 76 }; 77 78 enum phydm_wireless_mode { 79 PHYDM_WIRELESS_MODE_UNKNOWN = 0x00, 80 PHYDM_WIRELESS_MODE_A = 0x01, 81 PHYDM_WIRELESS_MODE_B = 0x02, 82 PHYDM_WIRELESS_MODE_G = 0x04, 83 PHYDM_WIRELESS_MODE_AUTO = 0x08, 84 PHYDM_WIRELESS_MODE_N_24G = 0x10, 85 PHYDM_WIRELESS_MODE_N_5G = 0x20, 86 PHYDM_WIRELESS_MODE_AC_5G = 0x40, 87 PHYDM_WIRELESS_MODE_AC_24G = 0x80, 88 PHYDM_WIRELESS_MODE_AC_ONLY = 0x100, 89 PHYDM_WIRELESS_MODE_MAX = 0x800, 90 PHYDM_WIRELESS_MODE_ALL = 0xFFFF 91 }; 92 93 enum phydm_rateid_idx { 94 PHYDM_BGN_40M_2SS = 0, 95 PHYDM_BGN_40M_1SS = 1, 96 PHYDM_BGN_20M_2SS = 2, 97 PHYDM_BGN_20M_1SS = 3, 98 PHYDM_GN_N2SS = 4, 99 PHYDM_GN_N1SS = 5, 100 PHYDM_BG = 6, 101 PHYDM_G = 7, 102 PHYDM_B_20M = 8, 103 PHYDM_ARFR0_AC_2SS = 9, 104 PHYDM_ARFR1_AC_1SS = 10, 105 PHYDM_ARFR2_AC_2G_1SS = 11, 106 PHYDM_ARFR3_AC_2G_2SS = 12, 107 PHYDM_ARFR4_AC_3SS = 13, 108 PHYDM_ARFR5_N_3SS = 14, 109 PHYDM_ARFR7_N_4SS = 15, 110 PHYDM_ARFR6_AC_4SS = 16 111 }; 112 113 enum phydm_qam_order { 114 PHYDM_QAM_CCK = 0, 115 PHYDM_QAM_BPSK = 1, 116 PHYDM_QAM_QPSK = 2, 117 PHYDM_QAM_16QAM = 3, 118 PHYDM_QAM_64QAM = 4, 119 PHYDM_QAM_256QAM = 5 120 }; 121 122 #if (RATE_ADAPTIVE_SUPPORT == 1)/* @88E RA */ 123 124 struct _phydm_txstatistic_ { 125 u32 hw_total_tx; 126 u32 hw_tx_success; 127 u32 hw_tx_rty; 128 u32 hw_tx_drop; 129 }; 130 131 /* @1 ============================================================ 132 * 1 structure 133 * 1 ============================================================ 134 */ 135 struct _odm_ra_info_ { 136 u8 rate_id; 137 u32 rate_mask; 138 u32 ra_use_rate; 139 u8 rate_sgi; 140 u8 rssi_sta_ra; 141 u8 pre_rssi_sta_ra; 142 u8 sgi_enable; 143 u8 decision_rate; 144 u8 pre_rate; 145 u8 highest_rate; 146 u8 lowest_rate; 147 u32 nsc_up; 148 u32 nsc_down; 149 u16 RTY[5]; 150 u32 TOTAL; 151 u16 DROP; 152 u8 active; 153 u16 rpt_time; 154 u8 ra_waiting_counter; 155 u8 ra_pending_counter; 156 u8 ra_drop_after_down; 157 #if 1 /* POWER_TRAINING_ACTIVE == 1 */ /* For compile pass only~! */ 158 u8 pt_active; /* on or off */ 159 u8 pt_try_state; /* @0 trying state, 1 for decision state */ 160 u8 pt_stage; /* @0~6 */ 161 u8 pt_stop_count; /* Stop PT counter */ 162 u8 pt_pre_rate; /* @if rate change do PT */ 163 u8 pt_pre_rssi; /* @if RSSI change 5% do PT */ 164 u8 pt_mode_ss; /* @decide whitch rate should do PT */ 165 u8 ra_stage; /* @StageRA, decide how many times RA will be done between PT */ 166 u8 pt_smooth_factor; 167 #endif 168 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) 169 u8 rate_down_counter; 170 u8 rate_up_counter; 171 u8 rate_direction; 172 u8 bounding_type; 173 u8 bounding_counter; 174 u8 bounding_learning_time; 175 u8 rate_down_start_time; 176 #endif 177 }; 178 #endif 179 180 181 struct ra_table { 182 #ifdef MU_EX_MACID 183 u8 mu1_rate[MU_EX_MACID]; 184 #endif 185 u8 highest_client_tx_order; 186 u16 highest_client_tx_rate_order; 187 u8 power_tracking_flag; 188 u8 ra_th_ofst; /*RA_threshold_offset*/ 189 u8 ra_ofst_direc; /*RA_offset_direction*/ 190 u8 up_ramask_cnt; /*@force update_ra_mask counter*/ 191 u8 up_ramask_cnt_tmp; /*@Just for debug, should be removed latter*/ 192 u32 rrsr_val_init; /*0x440*/ 193 u32 rrsr_val_curr; /*0x440*/ 194 boolean dynamic_rrsr_en; 195 u8 ra_trigger_mode; /*0: pkt RA, 1: TBTT RA*/ 196 u8 ra_tx_cls_th; /*255: auto, xx: in dB*/ 197 #if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/ 198 u8 per_rate_retrylimit_20M[PHY_NUM_RATE_IDX]; 199 u8 per_rate_retrylimit_40M[PHY_NUM_RATE_IDX]; 200 u8 retry_descend_num; 201 u8 retrylimit_low; 202 u8 retrylimit_high; 203 #endif 204 u8 ldpc_thres; /* @if RSSI > ldpc_th => switch from LPDC to BCC */ 205 void (*record_ra_info)(void *dm_void, u8 macid, 206 struct cmn_sta_info *sta, u64 ra_mask); 207 u8 ra_mask_rpt_stamp; 208 u8 ra_mask_buf[8]; 209 }; 210 211 struct ra_mask_rpt_trig { 212 u8 ra_mask_rpt_stamp; 213 u8 macid; 214 }; 215 216 struct ra_mask_rpt { 217 u8 ra_mask_rpt_stamp; 218 u8 ra_mask_buf[8]; 219 }; 220 221 /* @1 ============================================================ 222 * 1 Function Prototype 223 * 1 ============================================================ 224 */ 225 boolean phydm_is_cck_rate(void *dm_void, u8 rate); 226 227 boolean phydm_is_ofdm_rate(void *dm_void, u8 rate); 228 229 boolean phydm_is_ht_rate(void *dm_void, u8 rate); 230 231 boolean phydm_is_vht_rate(void *dm_void, u8 rate); 232 233 u8 phydm_legacy_rate_2_spec_rate(void *dm_void, u8 rate); 234 235 u8 phydm_rate_2_rate_digit(void *dm_void, u8 rate); 236 237 u8 phydm_rate_type_2_num_ss(void *dm_void, enum PDM_RATE_TYPE type); 238 239 u8 phydm_rate_to_num_ss(void *dm_void, u8 data_rate); 240 241 void phydm_h2C_debug(void *dm_void, char input[][16], u32 *_used, 242 char *output, u32 *_out_len); 243 244 void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output, 245 u32 *_out_len); 246 247 void phydm_ra_mask_report_h2c_trigger(void *dm_void, 248 struct ra_mask_rpt_trig *trig_rpt); 249 250 void phydm_ra_mask_report_c2h_result(void *dm_void, struct ra_mask_rpt *rpt); 251 252 void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len); 253 254 void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component); 255 256 void phydm_print_rate_2_buff(void *dm_void, u8 rate, char *buf, u16 buf_size); 257 258 void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len); 259 260 u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx); 261 262 void phydm_rrsr_set_register(void *dm_void, u32 rrsr_val); 263 264 void phydm_ra_info_watchdog(void *dm_void); 265 266 void phydm_rrsr_en(void *dm_void, boolean en_rrsr); 267 268 void phydm_ra_info_init(void *dm_void); 269 270 void phydm_modify_RA_PCR_threshold(void *dm_void, u8 ra_ofst_direc, 271 u8 ra_th_ofst); 272 273 u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode); 274 275 u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw); 276 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 277 void phydm_update_hal_ra_mask( 278 void *dm_void, 279 u32 wireless_mode, 280 u8 rf_type, 281 u8 BW, 282 u8 mimo_ps_enable, 283 u8 disable_cck_rate, 284 u32 *ratr_bitmap_msb_in, 285 u32 *ratr_bitmap_in, 286 u8 tx_rate_level); 287 #endif 288 289 #if (DM_ODM_SUPPORT_TYPE == ODM_CE) 290 u8 phydm_get_plcp(void *dm_void, u16 macid); 291 #endif 292 293 void phydm_refresh_rate_adaptive_mask(void *dm_void); 294 295 u8 phydm_get_rx_stream_num(void *dm_void, enum rf_type type); 296 297 u8 phydm_rssi_lv_dec(void *dm_void, u32 rssi, u8 ratr_state); 298 299 void odm_ra_post_action_on_assoc(void *dm); 300 301 u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, boolean is_erp_protect); 302 303 void phydm_show_sta_info(void *dm_void, char input[][16], u32 *_used, 304 char *output, u32 *_out_len); 305 306 u8 phydm_get_rate_from_rssi_lv(void *dm_void, u8 sta_idx); 307 308 void phydm_ra_registed(void *dm_void, u8 macid, u8 rssi_from_assoc); 309 310 void phydm_ra_offline(void *dm_void, u8 macid); 311 312 void phydm_ra_mask_watchdog(void *dm_void); 313 314 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 315 void odm_refresh_basic_rate_mask( 316 void *dm_void); 317 #endif 318 319 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT 320 void phydm_ra_mode_selection(void *dm_void, u8 mode); 321 #endif 322 323 #endif /*@#ifndef __PHYDMRAINFO_H__*/ 324