1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 ************************************************************/
29
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
34 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
phydm_start_cck_cont_tx_jgr3(void * dm_void,struct phydm_pmac_info * tx_info)35 void phydm_start_cck_cont_tx_jgr3(void *dm_void,
36 struct phydm_pmac_info *tx_info)
37 {
38 struct dm_struct *dm = (struct dm_struct *)dm_void;
39 struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
40 u8 rate = tx_info->tx_rate; /* HW rate */
41
42 /* if CCK block on? */
43 if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1)))
44 odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 0x1);
45
46 /* Turn Off All Test mode */
47 odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
48
49 odm_set_bb_reg(dm, R_0x1a00, 0x3000, rate);
50 odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2); /* transmit mode */
51 odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1); /* turn on scrambler*/
52
53 /* Fix rate selection issue */
54 odm_set_bb_reg(dm, R_0x1a70, BIT(14), 0x1);
55 /* set RX weighting for path I & Q to 0 */
56 odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
57 /* set loopback mode */
58 odm_set_bb_reg(dm, R_0x1c3c, BIT(4), 0x1);
59
60 pmac_tx->cck_cont_tx = true;
61 pmac_tx->ofdm_cont_tx = false;
62 }
63
phydm_stop_cck_cont_tx_jgr3(void * dm_void)64 void phydm_stop_cck_cont_tx_jgr3(void *dm_void)
65 {
66 struct dm_struct *dm = (struct dm_struct *)dm_void;
67 struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
68
69 pmac_tx->cck_cont_tx = false;
70 pmac_tx->ofdm_cont_tx = false;
71
72 odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0); /* normal mode */
73 odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1); /* turn on scrambler*/
74
75 /* back to default */
76 odm_set_bb_reg(dm, R_0x1a70, BIT(14), 0x0);
77 odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
78 odm_set_bb_reg(dm, R_0x1c3c, BIT(4), 0x0);
79 /* BB Reset */
80 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
81 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
82 }
83
phydm_start_ofdm_cont_tx_jgr3(void * dm_void)84 void phydm_start_ofdm_cont_tx_jgr3(void *dm_void)
85 {
86 struct dm_struct *dm = (struct dm_struct *)dm_void;
87 struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
88
89 /* 1. if OFDM block on */
90 if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))
91 odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 0x1);
92
93 /* 2. set CCK test mode off, set to CCK normal mode */
94 odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0);
95
96 /* 3. turn on scramble setting */
97 odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1);
98
99 /* 4. Turn On Continue Tx and turn off the other test modes. */
100 odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x1);
101
102 pmac_tx->cck_cont_tx = false;
103 pmac_tx->ofdm_cont_tx = true;
104 }
105
phydm_stop_ofdm_cont_tx_jgr3(void * dm_void)106 void phydm_stop_ofdm_cont_tx_jgr3(void *dm_void)
107 {
108 struct dm_struct *dm = (struct dm_struct *)dm_void;
109 struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
110
111 pmac_tx->cck_cont_tx = false;
112 pmac_tx->ofdm_cont_tx = false;
113
114 /* Turn Off All Test mode */
115 odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
116
117 /* Delay 10 ms */
118 ODM_delay_ms(10);
119
120 /* BB Reset */
121 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
122 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
123 }
124
phydm_stop_pmac_tx_jgr3(void * dm_void,struct phydm_pmac_info * tx_info)125 void phydm_stop_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
126 {
127 struct dm_struct *dm = (struct dm_struct *)dm_void;
128 struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
129 u32 tmp = 0;
130
131 odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x2); /* TX Stop */
132
133 if (tx_info->mode == CONT_TX) {
134 if (pmac_tx->is_cck_rate)
135 phydm_stop_cck_cont_tx_jgr3(dm);
136 else
137 phydm_stop_ofdm_cont_tx_jgr3(dm);
138 }
139 }
140
phydm_set_mac_phy_txinfo_jgr3(void * dm_void,struct phydm_pmac_info * tx_info)141 void phydm_set_mac_phy_txinfo_jgr3(void *dm_void,
142 struct phydm_pmac_info *tx_info)
143 {
144 struct dm_struct *dm = (struct dm_struct *)dm_void;
145 struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
146 u32 tmp = 0;
147
148 odm_set_bb_reg(dm, R_0xa58, 0x003f8000, tx_info->tx_rate);
149
150 /*0x900[1] ndp_sound */
151 odm_set_bb_reg(dm, R_0x900, BIT(1), tx_info->ndp_sound);
152
153 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
154 tx_info->m_stbc = tx_info->m_stbc - 1;
155 #endif
156 /*0x900[27:24] txsc [29:28] bw [31:30] m_stbc */
157 tmp = (tx_info->tx_sc) | ((tx_info->bw) << 4) |
158 ((tx_info->m_stbc) << 6);
159 odm_set_bb_reg(dm, R_0x900, 0xff000000, tmp);
160
161 if (tx_info->tx_sc == 1) /*upper*/
162 odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x5);
163 else if (tx_info->tx_sc == 2) /*lower*/
164 odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x6);
165 else /* duplicate*/
166 odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x0);
167
168 if (pmac_tx->is_ofdm_rate) {
169 odm_set_bb_reg(dm, R_0x900, BIT(0), 0x0);
170 odm_set_bb_reg(dm, R_0x900, BIT(2), 0x0);
171 } else if (pmac_tx->is_ht_rate) {
172 odm_set_bb_reg(dm, R_0x900, BIT(0), 0x1);
173 odm_set_bb_reg(dm, R_0x900, BIT(2), 0x0);
174 } else if (pmac_tx->is_vht_rate) {
175 odm_set_bb_reg(dm, R_0x900, BIT(0), 0x0);
176 odm_set_bb_reg(dm, R_0x900, BIT(2), 0x1);
177 }
178
179 /* for TX interval */
180 odm_set_bb_reg(dm, R_0x9b8, MASKHWORD, tx_info->packet_period);
181 }
182
phydm_set_sig_jgr3(void * dm_void,struct phydm_pmac_info * tx_info)183 void phydm_set_sig_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
184 {
185 struct dm_struct *dm = (struct dm_struct *)dm_void;
186 struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
187 u32 tmp = 0;
188
189 if (pmac_tx->is_cck_rate)
190 return;
191
192 odm_set_bb_reg(dm, R_0x1eb4, 0xfffff, tx_info->packet_count);
193
194 /* L-SIG */
195 tmp = BYTE_2_DWORD(0, tx_info->lsig[2], tx_info->lsig[1],
196 tx_info->lsig[0]);
197 odm_set_bb_reg(dm, R_0x908, 0xffffff, tmp);
198 if (pmac_tx->is_ht_rate) {
199 /* HT SIG */
200 tmp = BYTE_2_DWORD(0, tx_info->ht_sig[2], tx_info->ht_sig[1],
201 tx_info->ht_sig[0]);
202 odm_set_bb_reg(dm, R_0x90c, 0xffffff, tmp);
203 tmp = BYTE_2_DWORD(0, tx_info->ht_sig[5], tx_info->ht_sig[4],
204 tx_info->ht_sig[3]);
205 odm_set_bb_reg(dm, R_0x910, 0xffffff, tmp);
206 } else if (pmac_tx->is_vht_rate) {
207 /* VHT SIG A/B/serv_field/delimiter */
208 tmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[2],
209 tx_info->vht_sig_a[1],
210 tx_info->vht_sig_a[0]);
211 odm_set_bb_reg(dm, R_0x90c, 0xffffff, tmp);
212 tmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[5],
213 tx_info->vht_sig_a[4],
214 tx_info->vht_sig_a[3]);
215 odm_set_bb_reg(dm, R_0x910, 0xffffff, tmp);
216 tmp = BYTE_2_DWORD(tx_info->vht_sig_b[3], tx_info->vht_sig_b[2],
217 tx_info->vht_sig_b[1],
218 tx_info->vht_sig_b[0]);
219 odm_set_bb_reg(dm, R_0x914, 0x1fffffff, tmp);
220 odm_set_bb_reg(dm, R_0x938, 0xff00, tx_info->vht_sig_b_crc);
221
222 tmp = BYTE_2_DWORD(tx_info->vht_delimiter[3],
223 tx_info->vht_delimiter[2],
224 tx_info->vht_delimiter[1],
225 tx_info->vht_delimiter[0]);
226 odm_set_bb_reg(dm, R_0x940, MASKDWORD, tmp);
227 }
228 }
229
phydm_set_cck_preamble_hdr_jgr3(void * dm_void,struct phydm_pmac_info * tx_info)230 void phydm_set_cck_preamble_hdr_jgr3(void *dm_void,
231 struct phydm_pmac_info *tx_info)
232 {
233 struct dm_struct *dm = (struct dm_struct *)dm_void;
234 struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
235 u32 tmp = 0;
236
237 if (!pmac_tx->is_cck_rate)
238 return;
239
240 tmp = tx_info->packet_count | (tx_info->sfd << 16);
241 odm_set_bb_reg(dm, R_0x1e64, MASKDWORD, tmp);
242 tmp = tx_info->signal_field | (tx_info->service_field << 8) |
243 (tx_info->length << 16);
244 odm_set_bb_reg(dm, R_0x1e68, MASKDWORD, tmp);
245 tmp = BYTE_2_DWORD(0, 0, tx_info->crc16[1], tx_info->crc16[0]);
246 odm_set_bb_reg(dm, R_0x1e6c, MASKLWORD, tmp);
247
248 if (tx_info->is_short_preamble)
249 odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 0x0);
250 else
251 odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 0x1);
252 }
253
phydm_set_mode_jgr3(void * dm_void,struct phydm_pmac_info * tx_info,enum phydm_pmac_mode mode)254 void phydm_set_mode_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
255 enum phydm_pmac_mode mode)
256 {
257 struct dm_struct *dm = (struct dm_struct *)dm_void;
258 struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
259
260 if (mode == CONT_TX) {
261 tx_info->packet_count = 1;
262
263 if (pmac_tx->is_cck_rate)
264 phydm_start_cck_cont_tx_jgr3(dm, tx_info);
265 else
266 phydm_start_ofdm_cont_tx_jgr3(dm);
267 }
268 }
269
phydm_set_pmac_txon_jgr3(void * dm_void,struct phydm_pmac_info * tx_info)270 void phydm_set_pmac_txon_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
271 {
272 struct dm_struct *dm = (struct dm_struct *)dm_void;
273 struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
274
275 odm_set_bb_reg(dm, R_0x1d08, BIT(0), 0x1); /*Turn on PMAC */
276
277 /*mac scramble seed setting, only in 8198F */
278 #if (RTL8198F_SUPPORT)
279 if (dm->support_ic_type & ODM_RTL8198F)
280 if (!odm_get_bb_reg(dm, R_0x1d10, BIT(16)))
281 odm_set_bb_reg(dm, R_0x1d10, BIT(16), 0x1);
282 #endif
283
284 if (pmac_tx->is_cck_rate) {
285 odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x8); /*TX CCK ON */
286 odm_set_bb_reg(dm, R_0x1a84, BIT(31), 0x0);
287 } else {
288 odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x4); /*TX Ofdm ON */
289 }
290 }
291
phydm_set_pmac_tx_jgr3(void * dm_void,struct phydm_pmac_info * tx_info,enum rf_path mpt_rf_path)292 void phydm_set_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
293 enum rf_path mpt_rf_path)
294 {
295 struct dm_struct *dm = (struct dm_struct *)dm_void;
296 struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
297
298 pmac_tx->is_cck_rate = phydm_is_cck_rate(dm, tx_info->tx_rate);
299 pmac_tx->is_ofdm_rate = phydm_is_ofdm_rate(dm, tx_info->tx_rate);
300 pmac_tx->is_ht_rate = phydm_is_ht_rate(dm, tx_info->tx_rate);
301 pmac_tx->is_vht_rate = phydm_is_vht_rate(dm, tx_info->tx_rate);
302 pmac_tx->path = mpt_rf_path;
303
304 if (!tx_info->en_pmac_tx) {
305 phydm_stop_pmac_tx_jgr3(dm, tx_info);
306 return;
307 }
308
309 phydm_set_mode_jgr3(dm, tx_info, tx_info->mode);
310
311 if (pmac_tx->is_cck_rate)
312 phydm_set_cck_preamble_hdr_jgr3(dm, tx_info);
313 else
314 phydm_set_sig_jgr3(dm, tx_info);
315
316 phydm_set_mac_phy_txinfo_jgr3(dm, tx_info);
317 phydm_set_pmac_txon_jgr3(dm, tx_info);
318 }
319
phydm_set_tmac_tx_jgr3(void * dm_void)320 void phydm_set_tmac_tx_jgr3(void *dm_void)
321 {
322 struct dm_struct *dm = (struct dm_struct *)dm_void;
323
324 /* Turn on TMAC */
325 if (odm_get_bb_reg(dm, R_0x1d08, BIT(0)))
326 odm_set_bb_reg(dm, R_0x1d08, BIT(0), 0x0);
327
328 /* mac scramble seed setting, only in 8198F */
329 #if (RTL8198F_SUPPORT)
330 if (dm->support_ic_type & ODM_RTL8198F)
331 if (odm_get_bb_reg(dm, R_0x1d10, BIT(16)))
332 odm_set_bb_reg(dm, R_0x1d10, BIT(16), 0x0);
333 #endif
334
335 /* Turn on TMAC CCK */
336 if (!odm_get_bb_reg(dm, R_0x1a84, BIT(31)))
337 odm_set_bb_reg(dm, R_0x1a84, BIT(31), 0x1);
338 }
339 #endif
340
phydm_start_cck_cont_tx(void * dm_void,struct phydm_pmac_info * tx_info)341 void phydm_start_cck_cont_tx(void *dm_void, struct phydm_pmac_info *tx_info)
342 {
343 struct dm_struct *dm = (struct dm_struct *)dm_void;
344
345 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
346 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
347 phydm_start_cck_cont_tx_jgr3(dm, tx_info);
348 #endif
349 }
350
phydm_stop_cck_cont_tx(void * dm_void)351 void phydm_stop_cck_cont_tx(void *dm_void)
352 {
353 struct dm_struct *dm = (struct dm_struct *)dm_void;
354
355 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
356 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
357 phydm_stop_cck_cont_tx_jgr3(dm);
358 #endif
359 }
360
phydm_start_ofdm_cont_tx(void * dm_void)361 void phydm_start_ofdm_cont_tx(void *dm_void)
362 {
363 struct dm_struct *dm = (struct dm_struct *)dm_void;
364
365 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
366 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
367 phydm_start_ofdm_cont_tx_jgr3(dm);
368 #endif
369 }
370
phydm_stop_ofdm_cont_tx(void * dm_void)371 void phydm_stop_ofdm_cont_tx(void *dm_void)
372 {
373 struct dm_struct *dm = (struct dm_struct *)dm_void;
374
375 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
376 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
377 phydm_stop_ofdm_cont_tx_jgr3(dm);
378 #endif
379 }
380
phydm_set_pmac_tx(void * dm_void,struct phydm_pmac_info * tx_info,enum rf_path mpt_rf_path)381 void phydm_set_pmac_tx(void *dm_void, struct phydm_pmac_info *tx_info,
382 enum rf_path mpt_rf_path)
383 {
384 struct dm_struct *dm = (struct dm_struct *)dm_void;
385
386 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
387 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
388 phydm_set_pmac_tx_jgr3(dm, tx_info, mpt_rf_path);
389 #endif
390 }
391
phydm_set_tmac_tx(void * dm_void)392 void phydm_set_tmac_tx(void *dm_void)
393 {
394 struct dm_struct *dm = (struct dm_struct *)dm_void;
395
396 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
397 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
398 phydm_set_tmac_tx_jgr3(dm);
399 #endif
400 }
401
phydm_pmac_tx_dbg(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)402 void phydm_pmac_tx_dbg(void *dm_void, char input[][16], u32 *_used,
403 char *output, u32 *_out_len)
404 {
405 struct dm_struct *dm = (struct dm_struct *)dm_void;
406 struct phydm_pmac_info tx_info;
407 char help[] = "-h";
408 char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
409 u32 var[10] = {0};
410 u32 used = *_used;
411 u32 out_len = *_out_len;
412 u8 i = 0;
413 u32 tx_cnt = 0x0;
414 u8 poll_cnt = 0x0;
415
416 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var[0]);
417
418 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
419 return;
420
421 if ((strcmp(input[1], help) == 0)) {
422 PDM_SNPF(out_len, used, output + used, out_len - used,
423 "[pmac_tx] basic : {1} {rate_idx}(only 1M & 6M) {count}\n");
424 } else {
425 for (i = 1; i < 7; i++) {
426 if (input[i + 1]) {
427 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
428 &var[i]);
429 }
430 }
431
432 tx_info.en_pmac_tx = true;
433 tx_info.mode = PKTS_TX;
434 tx_info.ndp_sound = false;
435 tx_info.bw = CHANNEL_WIDTH_20;
436 tx_info.tx_sc = 0x0; /*duplicate*/
437 tx_info.m_stbc = 0x0; /*disable*/
438 tx_info.packet_period = 2000; /*d'500 us*/
439 tx_info.tx_rate = (u8)var[1];
440 tx_info.packet_count = (u32)var[2];
441
442 if (tx_info.tx_rate == ODM_RATE1M) {
443 tx_info.signal_field = 0xa; /*rate = 1M*/
444 tx_info.service_field = 0x0;
445 tx_info.length = 8000; /*d'8000 us=1000 bytes*/
446 tx_info.crc16[0] = 0x60;
447 tx_info.crc16[1] = 0x8e;
448 /*long preamble*/
449 tx_info.is_short_preamble = false;
450 tx_info.sfd = 0xf3a0;
451 } else if (tx_info.tx_rate == ODM_RATE6M) {
452 /*l-sig[3:0] = rate = 6M = 0xb*/
453 /*l-sig[16:5] = length = 1000 bytes*/
454 /*l-sig[17] = parity = 1*/
455 tx_info.lsig[0] = 0xb;
456 tx_info.lsig[1] = 0x7d;
457 tx_info.lsig[2] = 0x2;
458 }
459 phydm_print_rate_2_buff(dm, tx_info.tx_rate, dbg_buf,
460 PHYDM_SNPRINT_SIZE);
461 PDM_SNPF(out_len, used, output + used, out_len - used,
462 "rate=%s, count=%d, pkt_interval=500(us), length=1000(bytes)\n",
463 dbg_buf, tx_info.packet_count);
464
465 if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
466 PDM_SNPF(out_len, used, output + used, out_len - used,
467 "check trx idle failed, please try again.\n");
468 return;
469 }
470
471 phydm_reset_bb_hw_cnt(dm);
472 phydm_set_pmac_tx_jgr3(dm, &tx_info, RF_PATH_A);
473
474 PDM_SNPF(out_len, used, output + used, out_len - used,
475 "pmac_tx enabled, please wait for tx_cnt = %d\n",
476 tx_info.packet_count);
477 while (1) {
478 if (phydm_is_cck_rate(dm, tx_info.tx_rate))
479 tx_cnt = odm_get_bb_reg(dm, R_0x2de4,
480 MASKLWORD);
481 else
482 tx_cnt = odm_get_bb_reg(dm, R_0x2de0,
483 MASKLWORD);
484
485 if (tx_cnt >= tx_info.packet_count || poll_cnt >= 10)
486 break;
487
488 ODM_delay_ms(100);
489 poll_cnt++;
490 }
491
492 if (tx_cnt < tx_info.packet_count)
493 PDM_SNPF(out_len, used, output + used, out_len - used,
494 "polling time out(1s), tx_cnt = %d\n", tx_cnt);
495 else
496 PDM_SNPF(out_len, used, output + used, out_len - used,
497 "pmac_tx finished, poll_cnt = %d\n", poll_cnt);
498
499 tx_info.en_pmac_tx = false;
500 phydm_set_pmac_tx(dm, &tx_info, RF_PATH_A);
501 phydm_set_tmac_tx(dm);
502 PDM_SNPF(out_len, used, output + used, out_len - used,
503 "Stop pmac_tx and turn on true mac mode.\n");
504
505 phydm_stop_ic_trx(dm, PHYDM_REVERT);
506 }
507 *_used = used;
508 *_out_len = out_len;
509 }
510 #endif