1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __PHYDM_API_H__ 27 #define __PHYDM_API_H__ 28 29 /* 2019.10.22 Add get/shift rxagc API for 8822C*/ 30 #define PHYDM_API_VERSION "2.3" 31 32 /* @1 ============================================================ 33 * 1 Definition 34 * 1 ============================================================ 35 */ 36 #define N_IC_TX_OFFEST_5_BIT (ODM_RTL8188E | ODM_RTL8192E) 37 38 #define N_IC_TX_OFFEST_6_BIT (ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B |\ 39 ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8195A |\ 40 ODM_RTL8188F) 41 42 #define N_IC_TX_OFFEST_7_BIT (ODM_RTL8721D | ODM_RTL8710C) 43 44 #define CN_CNT_MAX 10 /*@max condition number threshold*/ 45 46 #define FUNC_ENABLE 1 47 #define FUNC_DISABLE 2 48 49 /*@NBI API------------------------------------*/ 50 #define NBI_128TONE 27 /*register table size*/ 51 #define NBI_256TONE 59 /*register table size*/ 52 53 #define NUM_START_CH_80M 7 54 #define NUM_START_CH_40M 14 55 56 #define CH_OFFSET_40M 2 57 #define CH_OFFSET_80M 6 58 59 #define FFT_128_TYPE 1 60 #define FFT_256_TYPE 2 61 62 #define FREQ_POSITIVE 1 63 #define FREQ_NEGATIVE 2 64 /*@------------------------------------------------*/ 65 66 enum phystat_rpt { 67 PHY_PWDB = 0, 68 PHY_EVM = 1, 69 PHY_CFO = 2, 70 PHY_RXSNR = 3, 71 PHY_LGAIN = 4, 72 PHY_HT_AAGC_GAIN = 5, 73 }; 74 75 #ifndef PHYDM_COMMON_API_SUPPORT 76 #define INVALID_RF_DATA 0xffffffff 77 #define INVALID_TXAGC_DATA 0xff 78 #endif 79 80 /* @1 ============================================================ 81 * 1 structure 82 * 1 ============================================================ 83 */ 84 85 struct phydm_api_stuc { 86 u32 rxiqc_reg1; /*N-mode: for pathA REG0xc14*/ 87 u32 rxiqc_reg2; /*N-mode: for pathB REG0xc1c*/ 88 u8 tx_queue_bitmap; /*REG0x520[23:16]*/ 89 u8 ccktx_path; 90 u8 pri_ch_idx; 91 }; 92 93 /* @1 ============================================================ 94 * 1 enumeration 95 * 1 ============================================================ 96 */ 97 98 /* @1 ============================================================ 99 * 1 function prototype 100 * 1 ============================================================ 101 */ 102 enum channel_width phydm_rxsc_2_bw(void *dm_void, u8 rxsc); 103 104 void phydm_reset_bb_hw_cnt(void *dm_void); 105 106 void phydm_dynamic_ant_weighting(void *dm_void); 107 108 #ifdef DYN_ANT_WEIGHTING_SUPPORT 109 void phydm_ant_weight_dbg(void *dm_void, char input[][16], u32 *_used, 110 char *output, u32 *_out_len); 111 #endif 112 113 void phydm_trx_antenna_setting_init(void *dm_void, u8 num_rf_path); 114 115 void phydm_config_ofdm_rx_path(void *dm_void, enum bb_path path); 116 117 void phydm_config_cck_rx_path(void *dm_void, enum bb_path path); 118 119 void phydm_config_cck_rx_antenna_init(void *dm_void); 120 121 void phydm_config_trx_path(void *dm_void, char input[][16], u32 *_used, 122 char *output, u32 *_out_len); 123 124 void phydm_config_ofdm_tx_path(void *dm_void, enum bb_path path); 125 126 void phydm_config_cck_tx_path(void *dm_void, enum bb_path path); 127 128 void phydm_tx_2path(void *dm_void); 129 130 void phydm_stop_3_wire(void *dm_void, u8 set_type); 131 132 u8 phydm_stop_ic_trx(void *dm_void, u8 set_type); 133 134 void phydm_dis_cck_trx(void *dm_void, u8 set_type); 135 136 void phydm_bw_fixed_enable(void *dm_void, boolean enable); 137 138 void phydm_bw_fixed_setting(void *dm_void); 139 140 void phydm_set_ext_switch(void *dm_void, u32 ext_ant_switch); 141 142 void phydm_nbi_enable(void *dm_void, u32 enable); 143 144 u8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf, 145 u32 sec_ch); 146 147 u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf, 148 u32 sec_ch); 149 150 void phydm_nbi_debug(void *dm_void, char input[][16], u32 *_used, 151 char *output, u32 *_out_len); 152 153 void phydm_csi_debug(void *dm_void, char input[][16], u32 *_used, 154 char *output, u32 *_out_len); 155 156 void phydm_stop_ck320(void *dm_void, u8 enable); 157 158 boolean 159 phydm_set_bb_txagc_offset(void *dm_void, s8 power_offset, u8 add_half_db); 160 161 boolean phydm_spur_case_mapping(void *dm_void); 162 163 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT 164 u32 phydm_rf_psd_jgr3(void *dm_void, u8 path, u32 tone_idx); 165 166 u8 phydm_csi_mask_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, 167 u32 f_intf, u32 sec_ch, u8 wgt); 168 169 void phydm_set_csi_mask_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction, 170 u8 wgt); 171 172 u8 phydm_nbi_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf, 173 u32 sec_ch, u8 path); 174 175 void phydm_set_nbi_reg_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction, 176 u8 path); 177 178 void phydm_nbi_enable_jgr3(void *dm_void, u32 enable, u8 path); 179 180 u8 phydm_phystat_rpt_jgr3(void *dm_void, enum phystat_rpt info, 181 enum rf_path ant_path); 182 void phydm_user_position_for_sniffer(void *dm_void, u8 user_position); 183 184 #endif 185 186 #ifdef PHYDM_COMMON_API_SUPPORT 187 void phydm_reset_txagc(void *dm_void); 188 189 boolean 190 phydm_api_shift_txagc(void *dm_void, u32 pwr_offset, enum rf_path path, 191 boolean is_positive); 192 boolean 193 phydm_api_set_txagc(void *dm_void, u32 power_index, enum rf_path path, 194 u8 hw_rate, boolean is_single_rate); 195 196 u8 phydm_api_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate); 197 198 #if (RTL8822C_SUPPORT) 199 void phydm_shift_rxagc_table(void *dm_void, boolean shift_up, u8 shift); 200 #endif 201 202 boolean 203 phydm_api_switch_bw_channel(void *dm_void, u8 central_ch, u8 primary_ch_idx, 204 enum channel_width bandwidth); 205 206 boolean 207 phydm_api_trx_mode(void *dm_void, enum bb_path tx_path, enum bb_path rx_path, 208 enum bb_path tx_path_ctrl); 209 210 #endif 211 212 #ifdef PHYDM_COMMON_API_NOT_SUPPORT 213 u8 config_phydm_read_txagc_n(void *dm_void, enum rf_path path, u8 hw_rate); 214 #endif 215 216 #ifdef CONFIG_MCC_DM 217 #ifdef DYN_ANT_WEIGHTING_SUPPORT 218 void phydm_dynamic_ant_weighting_mcc_8822b(void *dm_void); 219 #endif /*#ifdef DYN_ANT_WEIGHTING_SUPPORT*/ 220 void phydm_fill_mcccmd(void *dm_void, u8 regid, u16 reg_add, 221 u8 val0, u8 val1); 222 u8 phydm_check(void *dm_void); 223 void phydm_mcc_init(void *dm_void); 224 void phydm_mcc_switch(void *dm_void); 225 #endif /*#ifdef CONFIG_MCC_DM*/ 226 227 #endif 228