1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 ************************************************************/
29 #include "mp_precomp.h"
30 #include "phydm_precomp.h"
31
32 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
33 #if WPP_SOFTWARE_TRACE
34 #include "PhyDM_Adaptivity.tmh"
35 #endif
36 #endif
37 #ifdef PHYDM_SUPPORT_ADAPTIVITY
38 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
39 boolean
phydm_check_channel_plan(void * dm_void)40 phydm_check_channel_plan(void *dm_void)
41 {
42 struct dm_struct *dm = (struct dm_struct *)dm_void;
43 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
44 void *adapter = dm->adapter;
45 PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
46
47 if (mgnt_info->RegEnableAdaptivity != 2)
48 return false;
49
50 if (!dm->carrier_sense_enable) { /*@check domain Code for adaptivity or CarrierSense*/
51 if ((*dm->band_type == ODM_BAND_5G) &&
52 !(adapt->regulation_5g == REGULATION_ETSI || adapt->regulation_5g == REGULATION_WW)) {
53 PHYDM_DBG(dm, DBG_ADPTVTY,
54 "adaptivity skip 5G domain code : %d\n",
55 adapt->regulation_5g);
56 return true;
57 } else if ((*dm->band_type == ODM_BAND_2_4G) &&
58 !(adapt->regulation_2g == REGULATION_ETSI || adapt->regulation_2g == REGULATION_WW)) {
59 PHYDM_DBG(dm, DBG_ADPTVTY,
60 "adaptivity skip 2.4G domain code : %d\n",
61 adapt->regulation_2g);
62 return true;
63 } else if ((*dm->band_type != ODM_BAND_2_4G) && (*dm->band_type != ODM_BAND_5G)) {
64 PHYDM_DBG(dm, DBG_ADPTVTY,
65 "adaptivity neither 2G nor 5G band, return\n");
66 return true;
67 }
68 } else {
69 if ((*dm->band_type == ODM_BAND_5G) &&
70 !(adapt->regulation_5g == REGULATION_MKK || adapt->regulation_5g == REGULATION_WW)) {
71 PHYDM_DBG(dm, DBG_ADPTVTY,
72 "CarrierSense skip 5G domain code : %d\n",
73 adapt->regulation_5g);
74 return true;
75 } else if ((*dm->band_type == ODM_BAND_2_4G) &&
76 !(adapt->regulation_2g == REGULATION_MKK || adapt->regulation_2g == REGULATION_WW)) {
77 PHYDM_DBG(dm, DBG_ADPTVTY,
78 "CarrierSense skip 2.4G domain code : %d\n",
79 adapt->regulation_2g);
80 return true;
81 } else if ((*dm->band_type != ODM_BAND_2_4G) && (*dm->band_type != ODM_BAND_5G)) {
82 PHYDM_DBG(dm, DBG_ADPTVTY,
83 "CarrierSense neither 2G nor 5G band, return\n");
84 return true;
85 }
86 }
87
88 return false;
89 }
90
91 boolean
phydm_soft_ap_special_set(void * dm_void)92 phydm_soft_ap_special_set(void *dm_void)
93 {
94 struct dm_struct *dm = (struct dm_struct *)dm_void;
95 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
96 boolean disable_ap_adapt_setting = false;
97
98 if (dm->soft_ap_mode != NULL) {
99 if (*dm->soft_ap_mode != 0 &&
100 (dm->soft_ap_special_setting & BIT(0)))
101 disable_ap_adapt_setting = true;
102 else
103 disable_ap_adapt_setting = false;
104 PHYDM_DBG(dm, DBG_ADPTVTY,
105 "soft_ap_setting = %x, soft_ap = %d, dis_ap_adapt = %d\n",
106 dm->soft_ap_special_setting, *dm->soft_ap_mode,
107 disable_ap_adapt_setting);
108 }
109
110 return disable_ap_adapt_setting;
111 }
112
113 boolean
phydm_ap_num_check(void * dm_void)114 phydm_ap_num_check(void *dm_void)
115 {
116 struct dm_struct *dm = (struct dm_struct *)dm_void;
117 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
118 boolean dis_adapt = false;
119
120 if (dm->ap_total_num > adapt->ap_num_th)
121 dis_adapt = true;
122 else
123 dis_adapt = false;
124
125 PHYDM_DBG(dm, DBG_ADPTVTY, "AP total num = %d, AP num threshold = %d\n",
126 dm->ap_total_num, adapt->ap_num_th);
127 return dis_adapt;
128 }
129
phydm_check_adaptivity(void * dm_void)130 void phydm_check_adaptivity(void *dm_void)
131 {
132 struct dm_struct *dm = (struct dm_struct *)dm_void;
133 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
134 boolean disable_adapt = false;
135
136 if (!adapt->mode_cvrt_en)
137 return;
138
139 if (phydm_check_channel_plan(dm) || phydm_ap_num_check(dm) ||
140 phydm_soft_ap_special_set(dm))
141 disable_adapt = true;
142
143 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE && disable_adapt)
144 *dm->edcca_mode = PHYDM_EDCCA_NORMAL_MODE;
145 else if (*dm->edcca_mode == PHYDM_EDCCA_NORMAL_MODE && !disable_adapt)
146 *dm->edcca_mode = PHYDM_EDCCA_ADAPT_MODE;
147 }
148
phydm_set_l2h_th_ini_win(void * dm_void)149 void phydm_set_l2h_th_ini_win(void *dm_void)
150 {
151 struct dm_struct *dm = (struct dm_struct *)dm_void;
152
153 /*@ [New Format: JGR3]IGI-idx:45 = RSSI:35 = -65dBm*/
154 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
155 if (dm->support_ic_type & ODM_RTL8822C)
156 dm->th_l2h_ini = 45;
157 else if (dm->support_ic_type & ODM_RTL8814B)
158 dm->th_l2h_ini = 49;
159 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
160 /*@ [Old Format] -11+base(50) = IGI_idx:39 = RSSI:29 = -71dBm*/
161 if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812)) {
162 dm->th_l2h_ini = -17;
163 } else {
164 if (*dm->band_type == ODM_BAND_5G)
165 dm->th_l2h_ini = -14;
166 else if (*dm->band_type == ODM_BAND_2_4G)
167 dm->th_l2h_ini = -9;
168 }
169 } else { /*ODM_IC_11N_SERIES*/
170 dm->th_l2h_ini = -9;
171 }
172 }
173 #endif
174
phydm_dig_up_bound_lmt_en(void * dm_void)175 void phydm_dig_up_bound_lmt_en(void *dm_void)
176 {
177 struct dm_struct *dm = (struct dm_struct *)dm_void;
178 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
179
180 if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE ||
181 !dm->is_linked) {
182 adapt->igi_up_bound_lmt_cnt = 0;
183 adapt->igi_lmt_en = false;
184 return;
185 }
186
187 if (dm->total_tp > 1) {
188 adapt->igi_lmt_en = true;
189 adapt->igi_up_bound_lmt_cnt = adapt->igi_up_bound_lmt_val;
190 PHYDM_DBG(dm, DBG_ADPTVTY,
191 "TP >1, Start limit IGI upper bound\n");
192 } else {
193 if (adapt->igi_up_bound_lmt_cnt == 0)
194 adapt->igi_lmt_en = false;
195 else
196 adapt->igi_up_bound_lmt_cnt--;
197 }
198
199 PHYDM_DBG(dm, DBG_ADPTVTY, "IGI_lmt_cnt = %d\n",
200 adapt->igi_up_bound_lmt_cnt);
201 }
202
phydm_set_edcca_threshold(void * dm_void,s8 H2L,s8 L2H)203 void phydm_set_edcca_threshold(void *dm_void, s8 H2L, s8 L2H)
204 {
205 struct dm_struct *dm = (struct dm_struct *)dm_void;
206
207 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
208 odm_set_bb_reg(dm, R_0x84c, MASKBYTE2, (u8)L2H + 0x80);
209 odm_set_bb_reg(dm, R_0x84c, MASKBYTE3, (u8)H2L + 0x80);
210 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
211 odm_set_bb_reg(dm, R_0xc4c, MASKBYTE0, (u8)L2H);
212 odm_set_bb_reg(dm, R_0xc4c, MASKBYTE2, (u8)H2L);
213 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
214 odm_set_bb_reg(dm, R_0x8a4, MASKBYTE0, (u8)L2H);
215 odm_set_bb_reg(dm, R_0x8a4, MASKBYTE1, (u8)H2L);
216 }
217 }
218
phydm_mac_edcca_state(void * dm_void,enum phydm_mac_edcca_type state)219 void phydm_mac_edcca_state(void *dm_void, enum phydm_mac_edcca_type state)
220 {
221 struct dm_struct *dm = (struct dm_struct *)dm_void;
222
223 if (state == PHYDM_IGNORE_EDCCA) {
224 /*@ignore EDCCA*/
225 odm_set_mac_reg(dm, R_0x520, BIT(15), 1);
226 /*@enable EDCCA count down*/
227 odm_set_mac_reg(dm, R_0x524, BIT(11), 0);
228 } else { /*@don't set MAC ignore EDCCA signal*/
229 /*@don't ignore EDCCA*/
230 odm_set_mac_reg(dm, R_0x520, BIT(15), 0);
231 /*@disable EDCCA count down*/
232 odm_set_mac_reg(dm, R_0x524, BIT(11), 1);
233 }
234 PHYDM_DBG(dm, DBG_ADPTVTY, "EDCCA enable state = %d\n", state);
235 }
236
phydm_search_pwdb_lower_bound(void * dm_void)237 void phydm_search_pwdb_lower_bound(void *dm_void)
238 {
239 struct dm_struct *dm = (struct dm_struct *)dm_void;
240 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
241 u32 value32 = 0, reg_value32 = 0;
242 u8 cnt = 0, try_count = 0;
243 u8 tx_edcca1 = 0;
244 boolean is_adjust = true;
245 s8 th_l2h, th_h2l, igi_target_dc = 0x32;
246 s8 diff = 0;
247 s8 IGI = adapt->igi_base + 30 + dm->th_l2h_ini - dm->th_edcca_hl_diff;
248
249 halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);
250 diff = igi_target_dc - IGI;
251 th_l2h = dm->th_l2h_ini + diff;
252 if (th_l2h > 10)
253 th_l2h = 10;
254
255 th_h2l = th_l2h - dm->th_edcca_hl_diff;
256 phydm_set_edcca_threshold(dm, th_h2l, th_l2h);
257 ODM_delay_ms(30);
258
259 while (is_adjust) {
260 /*@check CCA status*/
261 /*set debug port to 0x0*/
262 if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x0)) {
263 reg_value32 = phydm_get_bb_dbg_port_val(dm);
264
265 while (reg_value32 & BIT(3) && try_count < 3) {
266 ODM_delay_ms(3);
267 try_count = try_count + 1;
268 reg_value32 = phydm_get_bb_dbg_port_val(dm);
269 }
270 phydm_release_bb_dbg_port(dm);
271 try_count = 0;
272 }
273
274 /*@count EDCCA signal = 1 times*/
275 for (cnt = 0; cnt < 20; cnt++) {
276 if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1,
277 adapt->adaptivity_dbg_port)) {
278 value32 = phydm_get_bb_dbg_port_val(dm);
279 phydm_release_bb_dbg_port(dm);
280 }
281
282 if (value32 & BIT(30) && dm->support_ic_type &
283 (ODM_RTL8723B | ODM_RTL8188E))
284 tx_edcca1 = tx_edcca1 + 1;
285 else if (value32 & BIT(29))
286 tx_edcca1 = tx_edcca1 + 1;
287 }
288
289 if (tx_edcca1 > 1) {
290 IGI = IGI - 1;
291 th_l2h = th_l2h + 1;
292 if (th_l2h > 10)
293 th_l2h = 10;
294
295 th_h2l = th_l2h - dm->th_edcca_hl_diff;
296 phydm_set_edcca_threshold(dm, th_h2l, th_l2h);
297 tx_edcca1 = 0;
298 if (th_l2h == 10)
299 is_adjust = false;
300
301 } else {
302 is_adjust = false;
303 }
304 }
305
306 adapt->adapt_igi_up = IGI - ADAPT_DC_BACKOFF;
307 adapt->h2l_lb = th_h2l + ADAPT_DC_BACKOFF;
308 adapt->l2h_lb = th_l2h + ADAPT_DC_BACKOFF;
309
310 halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);
311 phydm_set_edcca_threshold(dm, 0x7f, 0x7f); /*resume to no link state*/
312 }
313
phydm_re_search_condition(void * dm_void)314 boolean phydm_re_search_condition(void *dm_void)
315 {
316 struct dm_struct *dm = (struct dm_struct *)dm_void;
317 struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
318 u8 adaptivity_igi_upper = adaptivity->adapt_igi_up + ADAPT_DC_BACKOFF;
319
320 if (adaptivity_igi_upper <= 0x26)
321 return true;
322 else
323 return false;
324 }
325
phydm_set_l2h_th_ini(void * dm_void)326 void phydm_set_l2h_th_ini(void *dm_void)
327 {
328 struct dm_struct *dm = (struct dm_struct *)dm_void;
329
330 /*@ [New Format: JGR3]IGI-idx:45 = RSSI:35 = -65dBm*/
331 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
332 if (dm->support_ic_type & ODM_RTL8822C)
333 dm->th_l2h_ini = 45;
334 else if (dm->support_ic_type & ODM_RTL8814B)
335 dm->th_l2h_ini = 49;
336 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
337 /*@ [Old Format] -11+base(50) = IGI_idx:39 = RSSI:29 = -71dBm*/
338 if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812))
339 dm->th_l2h_ini = -17;
340 else
341 dm->th_l2h_ini = -14;
342 } else { /*ODM_IC_11N_SERIES*/
343 if (dm->support_ic_type & ODM_RTL8721D)
344 dm->th_l2h_ini = -14;
345 else
346 dm->th_l2h_ini = -11;
347 }
348 }
349
phydm_set_l2h_th_ini_carrier_sense(void * dm_void)350 void phydm_set_l2h_th_ini_carrier_sense(void *dm_void)
351 {
352 struct dm_struct *dm = (struct dm_struct *)dm_void;
353
354 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
355 dm->th_l2h_ini = 60; /*@ -50dBm*/
356 else
357 dm->th_l2h_ini = 10; /*@ -50dBm*/
358 }
359
phydm_set_forgetting_factor(void * dm_void)360 void phydm_set_forgetting_factor(void *dm_void)
361 {
362 struct dm_struct *dm = (struct dm_struct *)dm_void;
363
364 if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
365 return;
366
367 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A |
368 ODM_RTL8195B))
369 odm_set_bb_reg(dm, R_0x8a0, BIT(1) | BIT(0), 0);
370 }
371
phydm_edcca_decision_opt(void * dm_void)372 void phydm_edcca_decision_opt(void *dm_void)
373 {
374 struct dm_struct *dm = (struct dm_struct *)dm_void;
375
376 if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
377 return;
378
379 if (dm->support_ic_type & ODM_RTL8822B)
380 odm_set_bb_reg(dm, R_0x8dc, BIT(5), 0x1);
381 else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
382 odm_set_bb_reg(dm, R_0xce8, BIT(13), 0x1);
383 else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
384 odm_set_bb_reg(dm, R_0x844, BIT(30) | BIT(29), 0x0);
385 }
386
phydm_adaptivity_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)387 void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used,
388 char *output, u32 *_out_len)
389 {
390 struct dm_struct *dm = (struct dm_struct *)dm_void;
391 struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
392 u32 used = *_used;
393 u32 out_len = *_out_len;
394 char help[] = "-h";
395 u32 dm_value[10] = {0};
396 u8 i = 0, input_idx = 0;
397 u32 reg_value32 = 0;
398 s8 h2l_diff = 0;
399
400 for (i = 0; i < 5; i++) {
401 if (input[i + 1]) {
402 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
403 input_idx++;
404 }
405 }
406 if (strcmp(input[1], help) == 0) {
407 PDM_SNPF(out_len, used, output + used, out_len - used,
408 "Show adaptivity message: {0}\n");
409 PDM_SNPF(out_len, used, output + used, out_len - used,
410 "Enter debug mode: {1} {th_l2h_ini} {th_edcca_hl_diff}\n");
411 PDM_SNPF(out_len, used, output + used, out_len - used,
412 "Leave debug mode: {2}\n");
413 goto out;
414 }
415
416 if (input_idx == 0)
417 return;
418
419 if (dm_value[0] == PHYDM_ADAPT_DEBUG) {
420 adaptivity->debug_mode = true;
421 if (dm_value[1] != 0)
422 dm->th_l2h_ini = (s8)dm_value[1];
423 if (dm_value[2] != 0)
424 dm->th_edcca_hl_diff = (s8)dm_value[2];
425 PDM_SNPF(out_len, used, output + used, out_len - used,
426 "th_l2h_ini = %d, th_edcca_hl_diff = %d\n",
427 dm->th_l2h_ini, dm->th_edcca_hl_diff);
428 } else if (dm_value[0] == PHYDM_ADAPT_RESUME) {
429 adaptivity->debug_mode = false;
430 dm->th_l2h_ini = adaptivity->th_l2h_ini_backup;
431 dm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup;
432 } else if (dm_value[0] == PHYDM_ADAPT_MSG) {
433 PDM_SNPF(out_len, used, output + used, out_len - used,
434 "debug_mode = %s, th_l2h_ini = %d\n",
435 (adaptivity->debug_mode ? "TRUE" : "FALSE"),
436 dm->th_l2h_ini);
437 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
438 reg_value32 = odm_get_bb_reg(dm, R_0x84c, MASKDWORD);
439 h2l_diff = (s8)((0x00ff0000 & reg_value32) >> 16) -
440 (s8)((0xff000000 & reg_value32) >> 24);
441 } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
442 reg_value32 = odm_get_bb_reg(dm, R_0xc4c, MASKDWORD);
443 h2l_diff = (s8)(0x000000ff & reg_value32) -
444 (s8)((0x00ff0000 & reg_value32) >> 16);
445 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
446 reg_value32 = odm_get_bb_reg(dm, R_0x8a4, MASKDWORD);
447 h2l_diff = (s8)(0x000000ff & reg_value32) -
448 (s8)((0x0000ff00 & reg_value32) >> 8);
449 }
450
451 if (h2l_diff == 7)
452 PDM_SNPF(out_len, used, output + used, out_len - used,
453 "adaptivity enable\n");
454 else
455 PDM_SNPF(out_len, used, output + used, out_len - used,
456 "adaptivity disable\n");
457 }
458
459 out:
460 *_used = used;
461 *_out_len = out_len;
462 }
463
phydm_set_edcca_val(void * dm_void,u32 * val_buf,u8 val_len)464 void phydm_set_edcca_val(void *dm_void, u32 *val_buf, u8 val_len)
465 {
466 struct dm_struct *dm = (struct dm_struct *)dm_void;
467
468 if (val_len != 2) {
469 PHYDM_DBG(dm, ODM_COMP_API,
470 "[Error][adaptivity]Need val_len = 2\n");
471 return;
472 }
473 phydm_set_edcca_threshold(dm, (s8)val_buf[1], (s8)val_buf[0]);
474 }
475
phydm_edcca_abort(void * dm_void)476 boolean phydm_edcca_abort(void *dm_void)
477 {
478 struct dm_struct *dm = (struct dm_struct *)dm_void;
479 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
480 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
481 void *adapter = dm->adapter;
482 u32 is_fw_in_psmode = false;
483 #endif
484
485 if (!(dm->support_ability & ODM_BB_ADAPTIVITY)) {
486 PHYDM_DBG(dm, DBG_ADPTVTY, "adaptivity disable\n");
487 return true;
488 }
489
490 if (dm->pause_ability & ODM_BB_ADAPTIVITY) {
491 PHYDM_DBG(dm, DBG_ADPTVTY, "Return: Pause ADPTVTY in LV=%d\n",
492 dm->pause_lv_table.lv_adapt);
493 return true;
494 }
495
496 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
497 ((PADAPTER)adapter)->HalFunc.GetHwRegHandler(adapter,
498 HW_VAR_FW_PSMODE_STATUS,
499 (u8 *)(&is_fw_in_psmode));
500
501 /*@Disable EDCCA while under LPS mode, added by Roger, 2012.09.14.*/
502 if (is_fw_in_psmode)
503 return true;
504 #endif
505
506 return false;
507 }
508
phydm_edcca_thre_calc_jgr3(void * dm_void)509 void phydm_edcca_thre_calc_jgr3(void *dm_void)
510 {
511 struct dm_struct *dm = (struct dm_struct *)dm_void;
512 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
513 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
514 u8 igi = dig_t->cur_ig_value;
515 s8 th_l2h = 0, th_h2l = 0;
516
517 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) {
518 /*prevent pwdB clipping and result in Miss Detection*/
519 adapt->l2h_dyn_min = (u8)(dm->th_l2h_ini - ADC_BACKOFF);
520
521 if (igi < adapt->l2h_dyn_min)
522 th_l2h = igi + ADC_BACKOFF;
523 else
524 th_l2h = dm->th_l2h_ini;
525
526 th_h2l = th_l2h - dm->th_edcca_hl_diff;
527 } else {
528 th_l2h = MAX_2(igi + TH_L2H_DIFF_IGI, EDCCA_TH_L2H_LB);
529 th_h2l = th_l2h - EDCCA_HL_DIFF_NORMAL;
530 }
531 adapt->th_l2h = th_l2h;
532 adapt->th_h2l = th_h2l;
533
534 phydm_set_edcca_threshold(dm, adapt->th_h2l, adapt->th_l2h);
535 }
536
phydm_edcca_thre_calc(void * dm_void)537 void phydm_edcca_thre_calc(void *dm_void)
538 {
539 struct dm_struct *dm = (struct dm_struct *)dm_void;
540 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
541 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
542 u8 igi = dig_t->cur_ig_value;
543 s8 th_l2h = 0, th_h2l = 0;
544 s8 diff = 0, igi_target = adapt->igi_base;
545
546 if (dm->support_ic_type & ODM_IC_PWDB_EDCCA) {
547 /*@fix EDCCA hang issue*/
548 if (dm->support_ic_type & ODM_RTL8812) {
549 /*@ADC_mask disable*/
550 odm_set_bb_reg(dm, R_0x800, BIT(10), 1);
551 /*@ADC_mask enable*/
552 odm_set_bb_reg(dm, R_0x800, BIT(10), 0);
553 }
554
555 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) {
556 /*@Limit IGI upper bound for adaptivity*/
557 phydm_dig_up_bound_lmt_en(dm);
558 diff = igi_target - (s8)igi;
559 th_l2h = dm->th_l2h_ini + diff;
560 if (th_l2h > 10)
561 th_l2h = 10;
562
563 th_h2l = th_l2h - dm->th_edcca_hl_diff;
564 } else {
565 th_l2h = 70 - igi;
566 th_h2l = th_l2h - EDCCA_HL_DIFF_NORMAL;
567 }
568 /*replace lower bound to prevent EDCCA always equal 1*/
569 if (th_h2l < adapt->h2l_lb)
570 th_h2l = adapt->h2l_lb;
571 if (th_l2h < adapt->l2h_lb)
572 th_l2h = adapt->l2h_lb;
573 PHYDM_DBG(dm, DBG_ADPTVTY,
574 "adapt_igi_up=0x%x, l2h_lb = %d dBm, h2l_lb = %d dBm\n",
575 adapt->adapt_igi_up,
576 IGI_2_DBM(adapt->l2h_lb + adapt->adapt_igi_up),
577 IGI_2_DBM(adapt->h2l_lb + adapt->adapt_igi_up));
578 } else { /* < JGR2 & N*/
579 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) {
580 /*need to consider PwdB upper bound for 8814 later IC*/
581 adapt->l2h_dyn_min = (u8)(dm->th_l2h_ini + igi_target);
582
583 if (igi < adapt->l2h_dyn_min)
584 th_l2h = igi;
585 else
586 th_l2h = adapt->l2h_dyn_min;
587
588 th_h2l = th_l2h - dm->th_edcca_hl_diff;
589 } else {
590 th_l2h = MAX_2(igi + TH_L2H_DIFF_IGI, EDCCA_TH_L2H_LB);
591 th_h2l = th_l2h - EDCCA_HL_DIFF_NORMAL;
592 }
593 }
594
595 adapt->th_l2h = th_l2h;
596 adapt->th_h2l = th_h2l;
597
598 phydm_set_edcca_threshold(dm, adapt->th_h2l, adapt->th_l2h);
599 }
600 #endif
601
phydm_set_edcca_threshold_api(void * dm_void)602 void phydm_set_edcca_threshold_api(void *dm_void)
603 {
604 #ifdef PHYDM_SUPPORT_ADAPTIVITY
605 struct dm_struct *dm = (struct dm_struct *)dm_void;
606 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
607
608 if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
609 return;
610
611 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
612 phydm_edcca_thre_calc_jgr3(dm);
613 else
614 phydm_edcca_thre_calc(dm);
615
616 PHYDM_DBG(dm, DBG_ADPTVTY,
617 "API :IGI = 0x%x, th_l2h = %d, th_h2l = %d\n",
618 dm->dm_dig_table.cur_ig_value, adapt->th_l2h, adapt->th_h2l);
619 #endif
620 }
621
phydm_adaptivity_info_init(void * dm_void,enum phydm_adapinfo cmn_info,u32 value)622 void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,
623 u32 value)
624 {
625 struct dm_struct *dm = (struct dm_struct *)dm_void;
626 struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
627
628 switch (cmn_info) {
629 case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE:
630 dm->carrier_sense_enable = (boolean)value;
631 break;
632 case PHYDM_ADAPINFO_TH_L2H_INI:
633 dm->th_l2h_ini = (s8)value;
634 break;
635 case PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF:
636 dm->th_edcca_hl_diff = (s8)value;
637 break;
638 case PHYDM_ADAPINFO_AP_NUM_TH:
639 adaptivity->ap_num_th = (u8)value;
640 break;
641 case PHYDM_ADAPINFO_SWITCH_TH_L2H_INI_IN_BAND:
642 adaptivity->switch_th_l2h_ini_in_band = (u8)value;
643 break;
644 default:
645 break;
646 }
647 }
648
phydm_adaptivity_info_update(void * dm_void,enum phydm_adapinfo cmn_info,u32 value)649 void phydm_adaptivity_info_update(void *dm_void, enum phydm_adapinfo cmn_info,
650 u32 value)
651 {
652 struct dm_struct *dm = (struct dm_struct *)dm_void;
653 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
654
655 /*This init variable may be changed in run time.*/
656 switch (cmn_info) {
657 case PHYDM_ADAPINFO_DOMAIN_CODE_2G:
658 adapt->regulation_2g = (u8)value;
659 break;
660 case PHYDM_ADAPINFO_DOMAIN_CODE_5G:
661 adapt->regulation_5g = (u8)value;
662 break;
663 default:
664 break;
665 }
666 }
667
phydm_adaptivity_init(void * dm_void)668 void phydm_adaptivity_init(void *dm_void)
669 {
670 #ifdef PHYDM_SUPPORT_ADAPTIVITY
671 struct dm_struct *dm = (struct dm_struct *)dm_void;
672 struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
673
674 /* @[Config Adaptivity]*/
675 if (!dm->edcca_mode) {
676 pr_debug("[%s] warning!\n", __func__);
677 dm->edcca_mode = &dm->u8_dummy;
678 dm->support_ability &= ~ODM_BB_ADAPTIVITY;
679 return;
680 }
681
682 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
683 if (!dm->carrier_sense_enable) {
684 if (dm->th_l2h_ini == 0 &&
685 !adaptivity->switch_th_l2h_ini_in_band)
686 phydm_set_l2h_th_ini(dm);
687 } else {
688 phydm_set_l2h_th_ini_carrier_sense(dm);
689 }
690
691 if (dm->th_edcca_hl_diff == 0)
692 dm->th_edcca_hl_diff = 7;
693
694 if (dm->wifi_test & RT_WIFI_LOGO)
695 dm->support_ability &= ~ODM_BB_ADAPTIVITY;
696
697 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE)
698 adaptivity->mode_cvrt_en = true;
699 else
700 adaptivity->mode_cvrt_en = false;
701 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
702 if (!dm->carrier_sense_enable) {
703 if (dm->th_l2h_ini == 0)
704 phydm_set_l2h_th_ini(dm);
705 } else {
706 phydm_set_l2h_th_ini_carrier_sense(dm);
707 }
708
709 if (dm->th_edcca_hl_diff == 0)
710 dm->th_edcca_hl_diff = 7;
711
712 if (dm->wifi_test || *dm->mp_mode)
713 dm->support_ability &= ~ODM_BB_ADAPTIVITY;
714 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
715 if (dm->carrier_sense_enable) {
716 phydm_set_l2h_th_ini_carrier_sense(dm);
717 dm->th_edcca_hl_diff = 7;
718 } else {
719 dm->th_l2h_ini = dm->TH_L2H_default; /*set by mib*/
720 dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_default;
721 }
722 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
723 if (!dm->carrier_sense_enable) {
724 if (dm->th_l2h_ini == 0)
725 phydm_set_l2h_th_ini(dm);
726 } else {
727 phydm_set_l2h_th_ini_carrier_sense(dm);
728 }
729
730 if (dm->th_edcca_hl_diff == 0)
731 dm->th_edcca_hl_diff = 7;
732 #endif
733
734 adaptivity->debug_mode = false;
735 adaptivity->th_l2h_ini_backup = dm->th_l2h_ini;
736 adaptivity->th_edcca_hl_diff_backup = dm->th_edcca_hl_diff;
737 adaptivity->igi_base = 0x32;
738 adaptivity->adapt_igi_up = 0;
739 adaptivity->h2l_lb = 0;
740 adaptivity->l2h_lb = 0;
741 adaptivity->l2h_dyn_min = 0;
742 adaptivity->th_l2h = 0x7f;
743 adaptivity->th_h2l = 0x7f;
744
745 if (dm->support_ic_type & ODM_IC_11N_SERIES)
746 adaptivity->adaptivity_dbg_port = 0x208;
747 else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
748 adaptivity->adaptivity_dbg_port = 0x209;
749
750 if (dm->support_ic_type & ODM_IC_11N_SERIES &&
751 !(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
752 if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) {
753 /*set to page B1*/
754 odm_set_bb_reg(dm, R_0xe28, BIT(30), 0x1);
755 /*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
756 odm_set_bb_reg(dm, R_0xbc0, BIT(27) | BIT(26), 0x1);
757 odm_set_bb_reg(dm, R_0xe28, BIT(30), 0x0);
758 } else {
759 /*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
760 odm_set_bb_reg(dm, R_0xe24, BIT(21) | BIT(20), 0x1);
761 }
762 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES &&
763 !(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
764 /*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
765 odm_set_bb_reg(dm, R_0x944, BIT(29) | BIT(28), 0x1);
766 }
767
768 if (dm->support_ic_type & ODM_IC_PWDB_EDCCA) {
769 phydm_search_pwdb_lower_bound(dm);
770 if (phydm_re_search_condition(dm))
771 phydm_search_pwdb_lower_bound(dm);
772 } else {
773 /*resume to no link state*/
774 phydm_set_edcca_threshold(dm, 0x7f, 0x7f);
775 }
776
777 /*@whether to ignore EDCCA*/
778 phydm_mac_edcca_state(dm, PHYDM_DONT_IGNORE_EDCCA);
779
780 /*@forgetting factor setting*/
781 phydm_set_forgetting_factor(dm);
782
783 /*@EDCCA behavior based on maximum or mean power*/
784 phydm_edcca_decision_opt(dm);
785
786 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
787 adaptivity->igi_up_bound_lmt_val = 180;
788 #else
789 adaptivity->igi_up_bound_lmt_val = 90;
790 #endif
791 adaptivity->igi_up_bound_lmt_cnt = 0;
792 adaptivity->igi_lmt_en = false;
793 #endif
794 }
795
phydm_adaptivity(void * dm_void)796 void phydm_adaptivity(void *dm_void)
797 {
798 #ifdef PHYDM_SUPPORT_ADAPTIVITY
799 struct dm_struct *dm = (struct dm_struct *)dm_void;
800 struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
801 struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
802
803 if (phydm_edcca_abort(dm))
804 return;
805
806 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
807 phydm_check_adaptivity(dm); /*@Check adaptivity enable*/
808
809 if (!dm->carrier_sense_enable &&
810 !adapt->debug_mode &&
811 adapt->switch_th_l2h_ini_in_band)
812 phydm_set_l2h_th_ini_win(dm);
813 #endif
814
815 PHYDM_DBG(dm, DBG_ADPTVTY, "%s ====>\n", __func__);
816 PHYDM_DBG(dm, DBG_ADPTVTY, "mode = %s, debug_mode = %d\n",
817 (*dm->edcca_mode ?
818 (dm->carrier_sense_enable ?
819 "CARRIER SENSE" :
820 "ADAPTIVITY") :
821 "NORMAL"),
822 adapt->debug_mode);
823
824 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
825 phydm_edcca_thre_calc_jgr3(dm);
826 else
827 phydm_edcca_thre_calc(dm);
828
829 if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE)
830 PHYDM_DBG(dm, DBG_ADPTVTY,
831 "th_l2h_ini = %d, th_edcca_hl_diff = %d\n",
832 dm->th_l2h_ini, dm->th_edcca_hl_diff);
833 if (dm->support_ic_type & ODM_IC_PWDB_EDCCA)
834 PHYDM_DBG(dm, DBG_ADPTVTY,
835 "IGI = 0x%x, th_l2h = %d dBm, th_h2l = %d dBm\n",
836 dig_t->cur_ig_value,
837 IGI_2_DBM(adapt->th_l2h + dig_t->cur_ig_value),
838 IGI_2_DBM(adapt->th_h2l + dig_t->cur_ig_value));
839 else
840 PHYDM_DBG(dm, DBG_ADPTVTY,
841 "IGI = 0x%x, th_l2h = %d dBm, th_h2l = %d dBm\n",
842 dig_t->cur_ig_value,
843 IGI_2_DBM(adapt->th_l2h),
844 IGI_2_DBM(adapt->th_h2l));
845 #endif
846 }
847
848