1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _HAL_MP_C_
16
17 #include <drv_types.h>
18
19 #ifdef CONFIG_MP_INCLUDED
20
21 #ifdef RTW_HALMAC
22 #include <hal_data.h> /* struct HAL_DATA_TYPE, RF register definition and etc. */
23 #else /* !RTW_HALMAC */
24 #ifdef CONFIG_RTL8188E
25 #include <rtl8188e_hal.h>
26 #endif
27 #ifdef CONFIG_RTL8723B
28 #include <rtl8723b_hal.h>
29 #endif
30 #ifdef CONFIG_RTL8192E
31 #include <rtl8192e_hal.h>
32 #endif
33 #ifdef CONFIG_RTL8814A
34 #include <rtl8814a_hal.h>
35 #endif
36 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
37 #include <rtl8812a_hal.h>
38 #endif
39 #ifdef CONFIG_RTL8703B
40 #include <rtl8703b_hal.h>
41 #endif
42 #ifdef CONFIG_RTL8723D
43 #include <rtl8723d_hal.h>
44 #endif
45 #ifdef CONFIG_RTL8710B
46 #include <rtl8710b_hal.h>
47 #endif
48 #ifdef CONFIG_RTL8188F
49 #include <rtl8188f_hal.h>
50 #endif
51 #ifdef CONFIG_RTL8188GTV
52 #include <rtl8188gtv_hal.h>
53 #endif
54 #ifdef CONFIG_RTL8192F
55 #include <rtl8192f_hal.h>
56 #endif
57 #endif /* !RTW_HALMAC */
58
59
MgntQuery_NssTxRate(u16 Rate)60 u8 MgntQuery_NssTxRate(u16 Rate)
61 {
62 u8 NssNum = RF_TX_NUM_NONIMPLEMENT;
63
64 if ((Rate >= MGN_MCS8 && Rate <= MGN_MCS15) ||
65 (Rate >= MGN_VHT2SS_MCS0 && Rate <= MGN_VHT2SS_MCS9))
66 NssNum = RF_2TX;
67 else if ((Rate >= MGN_MCS16 && Rate <= MGN_MCS23) ||
68 (Rate >= MGN_VHT3SS_MCS0 && Rate <= MGN_VHT3SS_MCS9))
69 NssNum = RF_3TX;
70 else if ((Rate >= MGN_MCS24 && Rate <= MGN_MCS31) ||
71 (Rate >= MGN_VHT4SS_MCS0 && Rate <= MGN_VHT4SS_MCS9))
72 NssNum = RF_4TX;
73 else
74 NssNum = RF_1TX;
75
76 return NssNum;
77 }
78
hal_mpt_SwitchRfSetting(PADAPTER pAdapter)79 void hal_mpt_SwitchRfSetting(PADAPTER pAdapter)
80 {
81 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
82 u8 ChannelToSw = pMptCtx->MptChannelToSw;
83 u32 ulRateIdx = pMptCtx->mpt_rate_index;
84 u32 ulbandwidth = pMptCtx->MptBandWidth;
85
86 /* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/
87 if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&
88 (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) {
89 pMptCtx->backup0x52_RF_A = (u8)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
90 pMptCtx->backup0x52_RF_B = (u8)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
91
92 if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) {
93 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB);
94 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB);
95 } else {
96 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD);
97 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD);
98 }
99 } else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/
100 if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) {
101 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
102 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
103 } else {
104 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
105 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
106 }
107 } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
108 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A);
109 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B);
110 }
111 }
112
hal_mpt_SetPowerTracking(PADAPTER padapter,u8 enable)113 s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable)
114 {
115 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
116 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
117
118
119 if (!netif_running(padapter->pnetdev)) {
120 return _FAIL;
121 }
122
123 if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
124 return _FAIL;
125 }
126 if (enable)
127 pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE;
128 else
129 pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
130
131 return _SUCCESS;
132 }
133
hal_mpt_GetPowerTracking(PADAPTER padapter,u8 * enable)134 void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable)
135 {
136 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
137 struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
138
139
140 *enable = pDM_Odm->rf_calibrate_info.txpowertrack_control;
141 }
142
143
hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter,BOOLEAN bInCH14)144 void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
145 {
146 u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0;
147 u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12;
148 u8 i;
149 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
150 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
151 u8 u1Channel = pHalData->current_channel;
152 u32 ulRateIdx = pMptCtx->mpt_rate_index;
153 u8 DataRate = 0xFF;
154
155 /* Do not modify CCK TX filter parameters for 8822B*/
156 if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) ||
157 IS_HARDWARE_TYPE_8723D(Adapter) || IS_HARDWARE_TYPE_8192F(Adapter) || IS_HARDWARE_TYPE_8822C(Adapter))
158 return;
159
160 DataRate = mpt_to_mgnt_rate(ulRateIdx);
161
162 if (u1Channel == 14 && IS_CCK_RATE(DataRate))
163 pHalData->bCCKinCH14 = TRUE;
164 else
165 pHalData->bCCKinCH14 = FALSE;
166
167 if (IS_HARDWARE_TYPE_8703B(Adapter)) {
168 if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) {
169 /* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */
170 phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0);
171 phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskLWord, 0);
172
173 } else {
174 /* Normal setting for 8703B, just recover to the default setting. */
175 /* This hardcore values reference from the parameter which BB team gave. */
176 for (i = 0 ; i < 2 ; ++i)
177 phy_set_bb_reg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);
178
179 }
180 } else if (IS_HARDWARE_TYPE_8723D(Adapter)) {
181 /* 2.4G CCK TX DFIR */
182 /* 2016.01.20 Suggest from RS BB mingzhi*/
183 if ((u1Channel == 14)) {
184 phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C);
185 phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000000);
186 phy_set_bb_reg(Adapter, 0xAAC, bMaskDWord, 0x00003667);
187 } else {
188 for (i = 0 ; i < 3 ; ++i) {
189 phy_set_bb_reg(Adapter,
190 pHalData->RegForRecover[i].offset,
191 bMaskDWord,
192 pHalData->RegForRecover[i].value);
193 }
194 }
195 } else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) {
196 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
197 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
198 CCKSwingIndex = 20; /* default index */
199
200 if (!pHalData->bCCKinCH14) {
201 /* Readback the current bb cck swing value and compare with the table to */
202 /* get the current swing index */
203 for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
204 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13_88f[i][0]) &&
205 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13_88f[i][1])) {
206 CCKSwingIndex = i;
207 break;
208 }
209 }
210 write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][0]);
211 write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][1]);
212 write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][2]);
213 write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][3]);
214 write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][4]);
215 write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][5]);
216 write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][6]);
217 write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][7]);
218 write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][8]);
219 write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][9]);
220 write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][10]);
221 write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][11]);
222 write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][12]);
223 write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][13]);
224 write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][14]);
225 write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][15]);
226 RTW_INFO("%s , cck_swing_table_ch1_ch13_88f[%d]\n", __func__, CCKSwingIndex);
227 } else {
228 for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
229 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14_88f[i][0]) &&
230 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14_88f[i][1])) {
231 CCKSwingIndex = i;
232 break;
233 }
234 }
235 write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][0]);
236 write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][1]);
237 write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][2]);
238 write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][3]);
239 write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][4]);
240 write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][5]);
241 write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][6]);
242 write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][7]);
243 write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][8]);
244 write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][9]);
245 write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][10]);
246 write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][11]);
247 write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][12]);
248 write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][13]);
249 write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][14]);
250 write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][15]);
251 RTW_INFO("%s , cck_swing_table_ch14_88f[%d]\n", __func__, CCKSwingIndex);
252 }
253 } else {
254
255 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
256 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
257
258 if (!pHalData->bCCKinCH14) {
259 /* Readback the current bb cck swing value and compare with the table to */
260 /* get the current swing index */
261 for (i = 0; i < CCK_TABLE_SIZE; i++) {
262 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13[i][0]) &&
263 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13[i][1])) {
264 CCKSwingIndex = i;
265 break;
266 }
267 }
268
269 /*Write 0xa22 0xa23*/
270 TempVal = cck_swing_table_ch1_ch13[CCKSwingIndex][0] +
271 (cck_swing_table_ch1_ch13[CCKSwingIndex][1] << 8);
272
273
274 /*Write 0xa24 ~ 0xa27*/
275 TempVal2 = 0;
276 TempVal2 = cck_swing_table_ch1_ch13[CCKSwingIndex][2] +
277 (cck_swing_table_ch1_ch13[CCKSwingIndex][3] << 8) +
278 (cck_swing_table_ch1_ch13[CCKSwingIndex][4] << 16) +
279 (cck_swing_table_ch1_ch13[CCKSwingIndex][5] << 24);
280
281 /*Write 0xa28 0xa29*/
282 TempVal3 = 0;
283 TempVal3 = cck_swing_table_ch1_ch13[CCKSwingIndex][6] +
284 (cck_swing_table_ch1_ch13[CCKSwingIndex][7] << 8);
285 } else {
286 for (i = 0; i < CCK_TABLE_SIZE; i++) {
287 if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14[i][0]) &&
288 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14[i][1])) {
289 CCKSwingIndex = i;
290 break;
291 }
292 }
293
294 /*Write 0xa22 0xa23*/
295 TempVal = cck_swing_table_ch14[CCKSwingIndex][0] +
296 (cck_swing_table_ch14[CCKSwingIndex][1] << 8);
297
298 /*Write 0xa24 ~ 0xa27*/
299 TempVal2 = 0;
300 TempVal2 = cck_swing_table_ch14[CCKSwingIndex][2] +
301 (cck_swing_table_ch14[CCKSwingIndex][3] << 8) +
302 (cck_swing_table_ch14[CCKSwingIndex][4] << 16) +
303 (cck_swing_table_ch14[CCKSwingIndex][5] << 24);
304
305 /*Write 0xa28 0xa29*/
306 TempVal3 = 0;
307 TempVal3 = cck_swing_table_ch14[CCKSwingIndex][6] +
308 (cck_swing_table_ch14[CCKSwingIndex][7] << 8);
309 }
310
311 write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
312 write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
313 write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
314 }
315
316 }
317
hal_mpt_SetChannel(PADAPTER pAdapter)318 void hal_mpt_SetChannel(PADAPTER pAdapter)
319 {
320 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
321 struct mp_priv *pmp = &pAdapter->mppriv;
322 u8 channel = pmp->channel;
323 u8 bandwidth = pmp->bandwidth;
324
325 hal_mpt_SwitchRfSetting(pAdapter);
326
327 pHalData->bSwChnl = _TRUE;
328 pHalData->bSetChnlBW = _TRUE;
329
330 if (bandwidth == 2) {
331 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
332 } else if (bandwidth == 1) {
333 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
334 } else
335 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
336
337 hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
338 rtw_btcoex_wifionly_scan_notify(pAdapter);
339
340 }
341
342 /*
343 * Notice
344 * Switch bandwitdth may change center frequency(channel)
345 */
hal_mpt_SetBandwidth(PADAPTER pAdapter)346 void hal_mpt_SetBandwidth(PADAPTER pAdapter)
347 {
348 struct mp_priv *pmp = &pAdapter->mppriv;
349 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
350
351 u8 channel = pmp->channel;
352 u8 bandwidth = pmp->bandwidth;
353
354 pHalData->bSwChnl = _TRUE;
355 pHalData->bSetChnlBW = _TRUE;
356
357 if (bandwidth == 2) {
358 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
359 } else if (bandwidth == 1) {
360 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
361 } else
362 rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
363
364 hal_mpt_SwitchRfSetting(pAdapter);
365 rtw_btcoex_wifionly_scan_notify(pAdapter);
366
367 }
368
mpt_SetTxPower_Old(PADAPTER pAdapter,MPT_TXPWR_DEF Rate,u8 * pTxPower)369 void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)
370 {
371 switch (Rate) {
372 case MPT_CCK: {
373 u32 TxAGC = 0, pwr = 0;
374
375 pwr = pTxPower[RF_PATH_A];
376 if (pwr < 0x3f) {
377 TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
378 phy_set_bb_reg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[RF_PATH_A]);
379 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);
380 }
381 pwr = pTxPower[RF_PATH_B];
382 if (pwr < 0x3f) {
383 TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
384 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[RF_PATH_B]);
385 phy_set_bb_reg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC);
386 }
387 }
388 break;
389
390 case MPT_OFDM_AND_HT: {
391 u32 TxAGC = 0;
392 u8 pwr = 0;
393
394 pwr = pTxPower[0];
395 if (pwr < 0x3f) {
396 TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
397 RTW_INFO("HT Tx-rf(A) Power = 0x%x\n", TxAGC);
398 phy_set_bb_reg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
399 phy_set_bb_reg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
400 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
401 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
402 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
403 phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
404 }
405 TxAGC = 0;
406 pwr = pTxPower[1];
407 if (pwr < 0x3f) {
408 TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
409 RTW_INFO("HT Tx-rf(B) Power = 0x%x\n", TxAGC);
410 phy_set_bb_reg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
411 phy_set_bb_reg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
412 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
413 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
414 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
415 phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
416 }
417 }
418 break;
419
420 default:
421 break;
422 }
423 RTW_INFO("<===mpt_SetTxPower_Old()\n");
424 }
425
426 void
mpt_SetTxPower(PADAPTER pAdapter,MPT_TXPWR_DEF Rate,u8 * pTxPower)427 mpt_SetTxPower(
428 PADAPTER pAdapter,
429 MPT_TXPWR_DEF Rate,
430 u8 *pTxPower
431 )
432 {
433 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
434
435 u8 path = 0 , i = 0, MaxRate = MGN_6M;
436 u8 StartPath = RF_PATH_A, EndPath = RF_PATH_B;
437
438 if (IS_HARDWARE_TYPE_8814A(pAdapter) || IS_HARDWARE_TYPE_8814B(pAdapter))
439 EndPath = RF_PATH_D;
440 else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)
441 || IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter))
442 EndPath = RF_PATH_A;
443
444 switch (Rate) {
445 case MPT_CCK: {
446 u8 rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
447
448 for (path = StartPath; path <= EndPath; path++)
449 for (i = 0; i < sizeof(rate); ++i)
450 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
451 }
452 break;
453 case MPT_OFDM: {
454 u8 rate[] = {
455 MGN_6M, MGN_9M, MGN_12M, MGN_18M,
456 MGN_24M, MGN_36M, MGN_48M, MGN_54M,
457 };
458
459 for (path = StartPath; path <= EndPath; path++)
460 for (i = 0; i < sizeof(rate); ++i)
461 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
462 }
463 break;
464 case MPT_HT: {
465 u8 rate[] = {
466 MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4,
467 MGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9,
468 MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14,
469 MGN_MCS15, MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19,
470 MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23, MGN_MCS24,
471 MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29,
472 MGN_MCS30, MGN_MCS31,
473 };
474 if (pHalData->rf_type == RF_4T4R)
475 MaxRate = MGN_MCS31;
476 else if (pHalData->rf_type == RF_3T3R)
477 MaxRate = MGN_MCS23;
478 else if (pHalData->rf_type == RF_2T2R)
479 MaxRate = MGN_MCS15;
480 else
481 MaxRate = MGN_MCS7;
482 for (path = StartPath; path <= EndPath; path++) {
483 for (i = 0; i < sizeof(rate); ++i) {
484 if (rate[i] > MaxRate)
485 break;
486 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
487 }
488 }
489 }
490 break;
491 case MPT_VHT: {
492 u8 rate[] = {
493 MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
494 MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9,
495 MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
496 MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9,
497 MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
498 MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9,
499 MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,
500 MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9,
501 };
502 if (pHalData->rf_type == RF_4T4R)
503 MaxRate = MGN_VHT4SS_MCS9;
504 else if (pHalData->rf_type == RF_3T3R)
505 MaxRate = MGN_VHT3SS_MCS9;
506 else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
507 MaxRate = MGN_VHT2SS_MCS9;
508 else
509 MaxRate = MGN_VHT1SS_MCS9;
510
511 for (path = StartPath; path <= EndPath; path++) {
512 for (i = 0; i < sizeof(rate); ++i) {
513 if (rate[i] > MaxRate)
514 break;
515 PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
516 }
517 }
518 }
519 break;
520 default:
521 RTW_INFO("<===mpt_SetTxPower: Illegal channel!!\n");
522 break;
523 }
524 }
525
hal_mpt_SetTxPower(PADAPTER pAdapter)526 void hal_mpt_SetTxPower(PADAPTER pAdapter)
527 {
528 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
529 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
530 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
531
532 if (pHalData->rf_chip < RF_CHIP_MAX) {
533 if (IS_HARDWARE_TYPE_8188E(pAdapter) ||
534 IS_HARDWARE_TYPE_8723B(pAdapter) ||
535 IS_HARDWARE_TYPE_8192E(pAdapter) ||
536 IS_HARDWARE_TYPE_8703B(pAdapter) ||
537 IS_HARDWARE_TYPE_8188F(pAdapter) ||
538 IS_HARDWARE_TYPE_8188GTV(pAdapter)
539 ) {
540
541 RTW_INFO("===> MPT_ProSetTxPower: Old\n");
542
543 mpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
544 mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel);
545
546 } else {
547
548 mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
549 mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);
550 mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel);
551 if(IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
552 RTW_INFO("===> MPT_ProSetTxPower: Jaguar/Jaguar2\n");
553 mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);
554 }
555 }
556
557 rtw_hal_set_txpwr_done(pAdapter);
558 } else
559 RTW_INFO("RFChipID < RF_CHIP_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
560
561 odm_clear_txpowertracking_state(pDM_Odm);
562 }
563
hal_mpt_SetDataRate(PADAPTER pAdapter)564 void hal_mpt_SetDataRate(PADAPTER pAdapter)
565 {
566 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
567 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
568 u32 DataRate;
569
570 DataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
571
572 hal_mpt_SwitchRfSetting(pAdapter);
573
574 hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
575 #ifdef CONFIG_RTL8723B
576 if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
577 if (IS_CCK_RATE(DataRate)) {
578 if (pMptCtx->mpt_rf_path == RF_PATH_A)
579 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0x6);
580 else
581 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0x6);
582 } else {
583 if (pMptCtx->mpt_rf_path == RF_PATH_A)
584 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
585 else
586 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
587 }
588 }
589
590 if ((IS_HARDWARE_TYPE_8723BS(pAdapter) &&
591 ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) {
592 if (pMptCtx->mpt_rf_path == RF_PATH_A)
593 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
594 else
595 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
596 }
597 #endif
598 }
599
600 #define RF_PATH_AB 22
601
602 #ifdef CONFIG_RTL8814A
mpt_ToggleIG_8814A(PADAPTER pAdapter)603 void mpt_ToggleIG_8814A(PADAPTER pAdapter)
604 {
605 u8 Path;
606 u32 IGReg = rA_IGI_Jaguar, IGvalue = 0;
607
608 for (Path = 0; Path <= RF_PATH_D; Path++) {
609 switch (Path) {
610 case RF_PATH_B:
611 IGReg = rB_IGI_Jaguar;
612 break;
613 case RF_PATH_C:
614 IGReg = rC_IGI_Jaguar2;
615 break;
616 case RF_PATH_D:
617 IGReg = rD_IGI_Jaguar2;
618 break;
619 default:
620 IGReg = rA_IGI_Jaguar;
621 break;
622 }
623
624 IGvalue = phy_query_bb_reg(pAdapter, IGReg, bMaskByte0);
625 phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue + 2);
626 phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue);
627 }
628 }
629
mpt_SetRFPath_8814A(PADAPTER pAdapter)630 void mpt_SetRFPath_8814A(PADAPTER pAdapter)
631 {
632
633 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
634 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
635 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
636 R_ANTENNA_SELECT_CCK *p_cck_txrx;
637 u8 ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
638 /*/PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo);*/
639 /*/PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pMgntInfo);*/
640
641 u32 ulAntennaTx = pHalData->antenna_tx_path;
642 u32 ulAntennaRx = pHalData->AntennaRxPath;
643 u8 NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
644
645 if (NssforRate == RF_3TX) {
646 RTW_INFO("===> SetAntenna 3T Rate ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
647
648 switch (ulAntennaTx) {
649 case ANTENNA_BCD:
650 pMptCtx->mpt_rf_path = RF_PATH_BCD;
651 /*pHalData->ValidTxPath = 0x0e;*/
652 phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e); /*/ 0x940[27:16]=12'b0010_0100_0111*/
653 break;
654
655 case ANTENNA_ABC:
656 default:
657 pMptCtx->mpt_rf_path = RF_PATH_ABC;
658 /*pHalData->ValidTxPath = 0x0d;*/
659 phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247); /*/ 0x940[27:16]=12'b0010_0100_0111*/
660 break;
661 }
662
663 } else { /*/if(NssforRate == RF_1TX)*/
664 RTW_INFO("===> SetAntenna for 1T/2T Rate, ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
665 switch (ulAntennaTx) {
666 case ANTENNA_BCD:
667 pMptCtx->mpt_rf_path = RF_PATH_BCD;
668 /*pHalData->ValidTxPath = 0x0e;*/
669 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7);
670 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe);
671 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0xe);
672 break;
673
674 case ANTENNA_BC:
675 pMptCtx->mpt_rf_path = RF_PATH_BC;
676 /*pHalData->ValidTxPath = 0x06;*/
677 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6);
678 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6);
679 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6);
680 break;
681 case ANTENNA_B:
682 pMptCtx->mpt_rf_path = RF_PATH_B;
683 /*pHalData->ValidTxPath = 0x02;*/
684 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4); /*/ 0xa07[7:4] = 4'b0100*/
685 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002); /*/ 0x93C[31:20]=12'b0000_0000_0010*/
686 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2); /* 0x80C[7:4] = 4'b0010*/
687 break;
688
689 case ANTENNA_C:
690 pMptCtx->mpt_rf_path = RF_PATH_C;
691 /*pHalData->ValidTxPath = 0x04;*/
692 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2); /*/ 0xa07[7:4] = 4'b0010*/
693 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004); /*/ 0x93C[31:20]=12'b0000_0000_0100*/
694 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4); /*/ 0x80C[7:4] = 4'b0100*/
695 break;
696
697 case ANTENNA_D:
698 pMptCtx->mpt_rf_path = RF_PATH_D;
699 /*pHalData->ValidTxPath = 0x08;*/
700 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1); /*/ 0xa07[7:4] = 4'b0001*/
701 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008); /*/ 0x93C[31:20]=12'b0000_0000_1000*/
702 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8); /*/ 0x80C[7:4] = 4'b1000*/
703 break;
704
705 case ANTENNA_A:
706 default:
707 pMptCtx->mpt_rf_path = RF_PATH_A;
708 /*pHalData->ValidTxPath = 0x01;*/
709 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8); /*/ 0xa07[7:4] = 4'b1000*/
710 phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001); /*/ 0x93C[31:20]=12'b0000_0000_0001*/
711 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1); /*/ 0x80C[7:4] = 4'b0001*/
712 break;
713 }
714 }
715
716 switch (ulAntennaRx) {
717 case ANTENNA_A:
718 /*pHalData->ValidRxPath = 0x01;*/
719 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
720 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
721 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
722 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
723 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
724 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0);
725 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
726 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
727 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
728 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
729 /*/ CCA related PD_delay_th*/
730 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
731 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
732 break;
733
734 case ANTENNA_B:
735 /*pHalData->ValidRxPath = 0x02;*/
736 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
737 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
738 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
739 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
740 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
741 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1);
742 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
743 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
744 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
745 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
746 /*/ CCA related PD_delay_th*/
747 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
748 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
749 break;
750
751 case ANTENNA_C:
752 /*pHalData->ValidRxPath = 0x04;*/
753 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
754 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
755 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44);
756 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
757 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
758 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2);
759 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
760 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
761 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
762 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
763 /*/ CCA related PD_delay_th*/
764 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
765 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
766 break;
767
768 case ANTENNA_D:
769 /*pHalData->ValidRxPath = 0x08;*/
770 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
771 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
772 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88);
773 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
774 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
775 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3);
776 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
777 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
778 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
779 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
780 /*/ CCA related PD_delay_th*/
781 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
782 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
783 break;
784
785 case ANTENNA_BC:
786 /*pHalData->ValidRxPath = 0x06;*/
787 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
788 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
789 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66);
790 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
791 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
792 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
793 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
794 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
795 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
796 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
797 /*/ CCA related PD_delay_th*/
798 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
799 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
800 break;
801
802 case ANTENNA_CD:
803 /*pHalData->ValidRxPath = 0x0C;*/
804 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
805 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
806 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc);
807 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
808 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
809 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB);
810 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
811 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
812 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
813 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
814 /*/ CCA related PD_delay_th*/
815 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
816 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
817 break;
818
819 case ANTENNA_BCD:
820 /*pHalData->ValidRxPath = 0x0e;*/
821 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
822 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
823 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee);
824 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
825 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
826 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
827 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
828 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
829 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
830 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/
831 /*/ CCA related PD_delay_th*/
832 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
833 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
834 break;
835
836 case ANTENNA_ABCD:
837 /*pHalData->ValidRxPath = 0x0f;*/
838 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
839 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
840 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff);
841 phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
842 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
843 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1);
844 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
845 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
846 phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
847 phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
848 /*/ CCA related PD_delay_th*/
849 phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
850 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
851 break;
852
853 default:
854 break;
855 }
856
857 PHY_Set_SecCCATH_by_RXANT_8814A(pAdapter, ulAntennaRx);
858
859 mpt_ToggleIG_8814A(pAdapter);
860 }
861
862 #endif /* CONFIG_RTL8814A */
863 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
864 void
mpt_SetSingleTone_8814A(PADAPTER pAdapter,BOOLEAN bSingleTone,BOOLEAN bEnPMacTx)865 mpt_SetSingleTone_8814A(
866 PADAPTER pAdapter,
867 BOOLEAN bSingleTone,
868 BOOLEAN bEnPMacTx)
869 {
870
871 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
872 u8 StartPath = RF_PATH_A, EndPath = RF_PATH_A, path;
873 static u32 regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0;
874
875 if (bSingleTone) {
876 regIG0 = phy_query_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord); /*/ 0xC1C[31:21]*/
877 regIG1 = phy_query_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord); /*/ 0xE1C[31:21]*/
878 regIG2 = phy_query_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord); /*/ 0x181C[31:21]*/
879 regIG3 = phy_query_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord); /*/ 0x1A1C[31:21]*/
880
881 switch (pMptCtx->mpt_rf_path) {
882 case RF_PATH_A:
883 case RF_PATH_B:
884 case RF_PATH_C:
885 case RF_PATH_D:
886 StartPath = pMptCtx->mpt_rf_path;
887 EndPath = pMptCtx->mpt_rf_path;
888 break;
889 case RF_PATH_AB:
890 EndPath = RF_PATH_B;
891 break;
892 case RF_PATH_BC:
893 StartPath = RF_PATH_B;
894 EndPath = RF_PATH_C;
895 break;
896 case RF_PATH_ABC:
897 EndPath = RF_PATH_C;
898 break;
899 case RF_PATH_BCD:
900 StartPath = RF_PATH_B;
901 EndPath = RF_PATH_D;
902 break;
903 case RF_PATH_ABCD:
904 EndPath = RF_PATH_D;
905 break;
906 }
907
908 if (bEnPMacTx == FALSE) {
909 hal_mpt_SetContinuousTx(pAdapter, _TRUE);
910 issue_nulldata(pAdapter, NULL, 1, 3, 500);
911 }
912
913 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/
914
915 for (path = StartPath; path <= EndPath; path++) {
916 phy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
917 phy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
918
919 phy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
920 }
921
922 phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/
923 phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/
924 phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/
925 phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/
926 } else {
927 switch (pMptCtx->mpt_rf_path) {
928 case RF_PATH_A:
929 case RF_PATH_B:
930 case RF_PATH_C:
931 case RF_PATH_D:
932 StartPath = pMptCtx->mpt_rf_path;
933 EndPath = pMptCtx->mpt_rf_path;
934 break;
935 case RF_PATH_AB:
936 EndPath = RF_PATH_B;
937 break;
938 case RF_PATH_BC:
939 StartPath = RF_PATH_B;
940 EndPath = RF_PATH_C;
941 break;
942 case RF_PATH_ABC:
943 EndPath = RF_PATH_C;
944 break;
945 case RF_PATH_BCD:
946 StartPath = RF_PATH_B;
947 EndPath = RF_PATH_D;
948 break;
949 case RF_PATH_ABCD:
950 EndPath = RF_PATH_D;
951 break;
952 }
953 for (path = StartPath; path <= EndPath; path++)
954 phy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x0); /* RF LO disabled */
955
956 phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/
957
958 if (bEnPMacTx == FALSE) {
959 if(IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
960 #ifdef PHYDM_MP_SUPPORT
961 phydm_stop_ofdm_cont_tx(pAdapter);
962 pMptCtx->bCckContTx = FALSE;
963 pMptCtx->bOfdmContTx = FALSE;
964 #endif
965 } else
966 hal_mpt_SetContinuousTx(pAdapter, _FALSE);
967 }
968
969 phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/
970 phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/
971 phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/
972 phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/
973 }
974 }
975
976 #endif
977
978 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
mpt_SetRFPath_8812A(PADAPTER pAdapter)979 void mpt_SetRFPath_8812A(PADAPTER pAdapter)
980 {
981 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
982 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
983 struct mp_priv *pmp = &pAdapter->mppriv;
984 u8 channel = pmp->channel;
985 u8 bandwidth = pmp->bandwidth;
986 u8 eLNA_2g = pHalData->ExternalLNA_2G;
987 u32 ulAntennaTx, ulAntennaRx;
988 u32 reg0xC50 = 0;
989
990 ulAntennaTx = pHalData->antenna_tx_path;
991 ulAntennaRx = pHalData->AntennaRxPath;
992
993 switch (ulAntennaTx) {
994 case ANTENNA_A:
995 pMptCtx->mpt_rf_path = RF_PATH_A;
996 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
997 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
998 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
999 break;
1000 case ANTENNA_B:
1001 pMptCtx->mpt_rf_path = RF_PATH_B;
1002 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222);
1003 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
1004 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1);
1005 break;
1006 case ANTENNA_AB:
1007 pMptCtx->mpt_rf_path = RF_PATH_AB;
1008 phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333);
1009 if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
1010 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
1011 break;
1012 default:
1013 pMptCtx->mpt_rf_path = RF_PATH_AB;
1014 RTW_INFO("Unknown Tx antenna.\n");
1015 break;
1016 }
1017
1018 switch (ulAntennaRx) {
1019 case ANTENNA_A:
1020 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
1021 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
1022 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
1023 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
1024
1025 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
1026 reg0xC50 = phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
1027 phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
1028 phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50);
1029
1030 /* set PWED_TH for BB Yn user guide R29 */
1031 if (IS_HARDWARE_TYPE_8812(pAdapter)) {
1032 if (channel <= 14) { /* 2.4G */
1033 if (bandwidth == CHANNEL_WIDTH_20
1034 && eLNA_2g == 0) {
1035 /* 0x830[3:1]=3'b010 */
1036 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
1037 } else
1038 /* 0x830[3:1]=3'b100 */
1039 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1040 } else
1041 /* 0x830[3:1]=3'b100 for 5G */
1042 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1043 }
1044 break;
1045 case ANTENNA_B:
1046 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
1047 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */
1048 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1);
1049 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
1050
1051 /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
1052 reg0xC50 = phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
1053 phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
1054 phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50);
1055
1056 /* set PWED_TH for BB Yn user guide R29 */
1057 if (IS_HARDWARE_TYPE_8812(pAdapter)) {
1058 if (channel <= 14) {
1059 if (bandwidth == CHANNEL_WIDTH_20
1060 && eLNA_2g == 0) {
1061 /* 0x830[3:1]=3'b010 */
1062 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
1063 } else
1064 /* 0x830[3:1]=3'b100 */
1065 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1066 } else
1067 /* 0x830[3:1]=3'b100 for 5G */
1068 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1069 }
1070 break;
1071 case ANTENNA_AB:
1072 phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33);
1073 phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/
1074 phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
1075 /* set PWED_TH for BB Yn user guide R29 */
1076 phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
1077 break;
1078 default:
1079 RTW_INFO("Unknown Rx antenna.\n");
1080 break;
1081 }
1082
1083 if (pHalData->rfe_type == 5 || pHalData->rfe_type == 1) {
1084 if (ulAntennaTx == ANTENNA_A || ulAntennaTx == ANTENNA_AB) {
1085 /* WiFi */
1086 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x2);
1087 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
1088 } else {
1089 /* BT */
1090 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x1);
1091 phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
1092 }
1093 }
1094 }
1095 #endif
1096
1097 #ifdef CONFIG_RTL8723B
mpt_SetRFPath_8723B(PADAPTER pAdapter)1098 void mpt_SetRFPath_8723B(PADAPTER pAdapter)
1099 {
1100 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1101 u32 ulAntennaTx, ulAntennaRx;
1102 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1103 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1104 struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1105 u8 i;
1106
1107 ulAntennaTx = pHalData->antenna_tx_path;
1108 ulAntennaRx = pHalData->AntennaRxPath;
1109
1110 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1111 RTW_INFO("This RF chip ID is not supported\n");
1112 return;
1113 }
1114
1115 switch (pAdapter->mppriv.antenna_tx) {
1116 case ANTENNA_A: { /*/ Actually path S1 (Wi-Fi)*/
1117 pMptCtx->mpt_rf_path = RF_PATH_A;
1118 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1119 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1120
1121 for (i = 0; i < 3; ++i) {
1122 u32 offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
1123 u32 data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][1];
1124
1125 if (offset != 0) {
1126 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1127 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1128 }
1129 }
1130 for (i = 0; i < 2; ++i) {
1131 u32 offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
1132 u32 data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][1];
1133
1134 if (offset != 0) {
1135 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1136 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1137 }
1138 }
1139 }
1140 break;
1141 case ANTENNA_B: { /*/ Actually path S0 (BT)*/
1142 u32 offset;
1143 u32 data;
1144
1145 pMptCtx->mpt_rf_path = RF_PATH_B;
1146 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1147 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/
1148
1149 for (i = 0; i < 3; ++i) {
1150 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1151 offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
1152 data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][1];
1153 if (pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][0] != 0) {
1154 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1155 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1156 }
1157 }
1158 /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
1159 for (i = 0; i < 2; ++i) {
1160 offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
1161 data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][1];
1162 if (pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][0] != 0) {
1163 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1164 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1165 }
1166 }
1167 }
1168 break;
1169 default:
1170 pMptCtx->mpt_rf_path = RF_PATH_AB;
1171 break;
1172 }
1173 }
1174 #endif
1175
1176 #ifdef CONFIG_RTL8703B
mpt_SetRFPath_8703B(PADAPTER pAdapter)1177 void mpt_SetRFPath_8703B(PADAPTER pAdapter)
1178 {
1179 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1180 u32 ulAntennaTx, ulAntennaRx;
1181 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1182 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1183 struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1184 u8 i;
1185
1186 ulAntennaTx = pHalData->antenna_tx_path;
1187 ulAntennaRx = pHalData->AntennaRxPath;
1188
1189 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1190 RTW_INFO("This RF chip ID is not supported\n");
1191 return;
1192 }
1193
1194 switch (pAdapter->mppriv.antenna_tx) {
1195 case ANTENNA_A: { /* Actually path S1 (Wi-Fi) */
1196 pMptCtx->mpt_rf_path = RF_PATH_A;
1197 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
1198 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
1199
1200 for (i = 0; i < 3; ++i) {
1201 u32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
1202 u32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
1203
1204 if (offset != 0) {
1205 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1206 RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
1207 }
1208
1209 }
1210 for (i = 0; i < 2; ++i) {
1211 u32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
1212 u32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
1213
1214 if (offset != 0) {
1215 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1216 RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1217 }
1218 }
1219 }
1220 break;
1221 case ANTENNA_B: { /* Actually path S0 (BT)*/
1222 pMptCtx->mpt_rf_path = RF_PATH_B;
1223 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
1224 phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */
1225
1226 for (i = 0; i < 3; ++i) {
1227 u32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
1228 u32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
1229
1230 if (pRFCalibrateInfo->tx_iqc_8703b[i][0] != 0) {
1231 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1232 RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1233 }
1234 }
1235 for (i = 0; i < 2; ++i) {
1236 u32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
1237 u32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
1238
1239 if (pRFCalibrateInfo->rx_iqc_8703b[i][0] != 0) {
1240 phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
1241 RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
1242 }
1243 }
1244 }
1245 break;
1246 default:
1247 pMptCtx->mpt_rf_path = RF_PATH_AB;
1248 break;
1249 }
1250
1251 }
1252 #endif
1253
1254 #ifdef CONFIG_RTL8723D
mpt_SetRFPath_8723D(PADAPTER pAdapter)1255 void mpt_SetRFPath_8723D(PADAPTER pAdapter)
1256 {
1257 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1258 u8 p = 0, i = 0;
1259 u32 ulAntennaTx, ulAntennaRx, offset = 0, data = 0, val32 = 0;
1260 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1261 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1262 struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
1263
1264 ulAntennaTx = pHalData->antenna_tx_path;
1265 ulAntennaRx = pHalData->AntennaRxPath;
1266
1267 if (pHalData->rf_chip >= RF_CHIP_MAX) {
1268 RTW_INFO("This RF chip ID is not supported\n");
1269 return;
1270 }
1271
1272 switch (pAdapter->mppriv.antenna_tx) {
1273 /* Actually path S1 (Wi-Fi) */
1274 case ANTENNA_A: {
1275 pMptCtx->mpt_rf_path = RF_PATH_A;
1276 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0);
1277 }
1278 break;
1279 /* Actually path S0 (BT) */
1280 case ANTENNA_B: {
1281 pMptCtx->mpt_rf_path = RF_PATH_B;
1282 phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0xA);
1283
1284 }
1285 break;
1286 default:
1287 pMptCtx->mpt_rf_path = RF_PATH_AB;
1288 break;
1289 }
1290 }
1291 #endif
1292
mpt_SetRFPath_819X(PADAPTER pAdapter)1293 void mpt_SetRFPath_819X(PADAPTER pAdapter)
1294 {
1295 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1296 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1297 u32 ulAntennaTx, ulAntennaRx;
1298 R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
1299 R_ANTENNA_SELECT_CCK *p_cck_txrx;
1300 u8 r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
1301 u8 chgTx = 0, chgRx = 0;
1302 u32 r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
1303
1304 ulAntennaTx = pHalData->antenna_tx_path;
1305 ulAntennaRx = pHalData->AntennaRxPath;
1306
1307 p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;
1308 p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
1309
1310 p_ofdm_tx->r_ant_ht1 = 0x1;
1311 p_ofdm_tx->r_ant_ht2 = 0x2;/*Second TX RF path is A*/
1312 p_ofdm_tx->r_ant_non_ht = 0x3;/*/ 0x1+0x2=0x3 */
1313
1314 switch (ulAntennaTx) {
1315 case ANTENNA_A:
1316 p_ofdm_tx->r_tx_antenna = 0x1;
1317 r_ofdm_tx_en_val = 0x1;
1318 p_ofdm_tx->r_ant_l = 0x1;
1319 p_ofdm_tx->r_ant_ht_s1 = 0x1;
1320 p_ofdm_tx->r_ant_non_ht_s1 = 0x1;
1321 p_cck_txrx->r_ccktx_enable = 0x8;
1322 chgTx = 1;
1323 /*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
1324 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1325 {
1326 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1327 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
1328 r_ofdm_tx_en_val = 0x3;
1329 /*/ Power save*/
1330 /*/cosa r_ant_select_ofdm_val = 0x11111111;*/
1331 /*/ We need to close RFB by SW control*/
1332 if (pHalData->rf_type == RF_2T2R) {
1333 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1334 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
1335 phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
1336 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1337 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
1338 }
1339 }
1340 pMptCtx->mpt_rf_path = RF_PATH_A;
1341 break;
1342 case ANTENNA_B:
1343 p_ofdm_tx->r_tx_antenna = 0x2;
1344 r_ofdm_tx_en_val = 0x2;
1345 p_ofdm_tx->r_ant_l = 0x2;
1346 p_ofdm_tx->r_ant_ht_s1 = 0x2;
1347 p_ofdm_tx->r_ant_non_ht_s1 = 0x2;
1348 p_cck_txrx->r_ccktx_enable = 0x4;
1349 chgTx = 1;
1350 /*/ From SD3 Willis suggestion !!! Set RF A as standby*/
1351 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1352 {
1353 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
1354 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1355
1356 /*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/
1357 /*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/
1358 if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
1359 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
1360 phy_set_bb_reg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
1361 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1362 /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1363 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
1364 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1365 }
1366 }
1367 pMptCtx->mpt_rf_path = RF_PATH_B;
1368 break;
1369 case ANTENNA_AB:/*/ For 8192S*/
1370 p_ofdm_tx->r_tx_antenna = 0x3;
1371 r_ofdm_tx_en_val = 0x3;
1372 p_ofdm_tx->r_ant_l = 0x3;
1373 p_ofdm_tx->r_ant_ht_s1 = 0x3;
1374 p_ofdm_tx->r_ant_non_ht_s1 = 0x3;
1375 p_cck_txrx->r_ccktx_enable = 0xC;
1376 chgTx = 1;
1377 /*/ From SD3Willis suggestion !!! Set RF B as standby*/
1378 /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
1379 {
1380 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
1381 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
1382 /* Disable Power save*/
1383 /*cosa r_ant_select_ofdm_val = 0x3321333;*/
1384 /* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/
1385 if (pHalData->rf_type == RF_2T2R) {
1386 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
1387
1388 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
1389 /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
1390 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
1391 phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
1392 }
1393 }
1394 pMptCtx->mpt_rf_path = RF_PATH_AB;
1395 break;
1396 default:
1397 break;
1398 }
1399 #if 0
1400 /* r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
1401 /* r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
1402 /* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D */
1403 #endif
1404 switch (ulAntennaRx) {
1405 case ANTENNA_A:
1406 r_rx_antenna_ofdm = 0x1; /* A*/
1407 p_cck_txrx->r_cckrx_enable = 0x0; /* default: A*/
1408 p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A*/
1409 chgRx = 1;
1410 break;
1411 case ANTENNA_B:
1412 r_rx_antenna_ofdm = 0x2; /*/ B*/
1413 p_cck_txrx->r_cckrx_enable = 0x1; /*/ default: B*/
1414 p_cck_txrx->r_cckrx_enable_2 = 0x1; /*/ option: B*/
1415 chgRx = 1;
1416 break;
1417 case ANTENNA_AB:/*/ For 8192S and 8192E/U...*/
1418 r_rx_antenna_ofdm = 0x3;/*/ AB*/
1419 p_cck_txrx->r_cckrx_enable = 0x0;/*/ default:A*/
1420 p_cck_txrx->r_cckrx_enable_2 = 0x1;/*/ option:B*/
1421 chgRx = 1;
1422 break;
1423 default:
1424 break;
1425 }
1426
1427
1428 if (chgTx && chgRx) {
1429 switch (pHalData->rf_chip) {
1430 case RF_8225:
1431 case RF_8256:
1432 case RF_6052:
1433 /*/r_ant_sel_cck_val = r_ant_select_cck_val;*/
1434 phy_set_bb_reg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); /*/OFDM Tx*/
1435 phy_set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /*/OFDM Tx*/
1436 phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
1437 phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
1438 if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1439 phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
1440 phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
1441 }
1442 phy_set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/
1443 break;
1444
1445 default:
1446 RTW_INFO("Unsupported RFChipID for switching antenna.\n");
1447 break;
1448 }
1449 }
1450 } /* MPT_ProSetRFPath */
1451
1452 #ifdef CONFIG_RTL8192F
1453
mpt_set_rfpath_8192f(PADAPTER pAdapter)1454 void mpt_set_rfpath_8192f(PADAPTER pAdapter)
1455 {
1456 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1457 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1458
1459 u16 ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
1460 u8 NssforRate, odmNssforRate;
1461 u32 ulAntennaTx, ulAntennaRx;
1462 enum bb_path RxAntToPhyDm;
1463 enum bb_path TxAntToPhyDm;
1464
1465 ulAntennaTx = pHalData->antenna_tx_path;
1466 ulAntennaRx = pHalData->AntennaRxPath;
1467 NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
1468
1469 if (pHalData->rf_chip >= RF_TYPE_MAX)
1470 RTW_INFO("This RF chip ID is not supported\n");
1471
1472 switch (ulAntennaTx) {
1473 case ANTENNA_A:
1474 pMptCtx->mpt_rf_path = RF_PATH_A;
1475 TxAntToPhyDm = BB_PATH_A;
1476 break;
1477 case ANTENNA_B:
1478 pMptCtx->mpt_rf_path = RF_PATH_B;
1479 TxAntToPhyDm = BB_PATH_B;
1480 break;
1481 case ANTENNA_AB:
1482 pMptCtx->mpt_rf_path = RF_PATH_AB;
1483 TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1484 break;
1485 default:
1486 pMptCtx->mpt_rf_path = RF_PATH_AB;
1487 TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1488 break;
1489 }
1490
1491 switch (ulAntennaRx) {
1492 case ANTENNA_A:
1493 RxAntToPhyDm = BB_PATH_A;
1494 break;
1495 case ANTENNA_B:
1496 RxAntToPhyDm = BB_PATH_B;
1497 break;
1498 case ANTENNA_AB:
1499 RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1500 break;
1501 default:
1502 RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
1503 break;
1504 }
1505
1506 phydm_api_trx_mode(GET_PDM_ODM(pAdapter), TxAntToPhyDm, RxAntToPhyDm, TxAntToPhyDm);
1507
1508 }
1509
1510 #endif
1511
hal_mpt_SetAntenna(PADAPTER pAdapter)1512 void hal_mpt_SetAntenna(PADAPTER pAdapter)
1513 {
1514 PHAL_DATA_TYPE hal;
1515 ANTENNA_PATH anttx;
1516 enum bb_path bb_tx = 0;
1517
1518
1519 hal = GET_HAL_DATA(pAdapter);
1520 anttx = hal->antenna_tx_path;
1521
1522 switch (anttx) {
1523 case ANTENNA_A:
1524 bb_tx = BB_PATH_A;
1525 break;
1526 case ANTENNA_B:
1527 bb_tx = BB_PATH_B;
1528 break;
1529 case ANTENNA_C:
1530 bb_tx = BB_PATH_C;
1531 break;
1532 case ANTENNA_D:
1533 bb_tx = BB_PATH_D;
1534 break;
1535 case ANTENNA_AB:
1536 bb_tx = BB_PATH_AB;
1537 break;
1538 case ANTENNA_AC:
1539 bb_tx = BB_PATH_AC;
1540 break;
1541 case ANTENNA_AD:
1542 bb_tx = BB_PATH_AD;
1543 break;
1544 case ANTENNA_BC:
1545 bb_tx = BB_PATH_BC;
1546 break;
1547 case ANTENNA_BD:
1548 bb_tx = BB_PATH_BD;
1549 break;
1550 case ANTENNA_CD:
1551 bb_tx = BB_PATH_CD;
1552 break;
1553 case ANTENNA_ABC:
1554 bb_tx = BB_PATH_ABC;
1555 break;
1556 case ANTENNA_BCD:
1557 bb_tx = BB_PATH_BCD;
1558 break;
1559 case ANTENNA_ABD:
1560 bb_tx = BB_PATH_ABD;
1561 break;
1562 case ANTENNA_ACD:
1563 bb_tx = BB_PATH_ACD;
1564 break;
1565 case ANTENNA_ABCD:
1566 bb_tx = BB_PATH_ABCD;
1567 break;
1568 default:
1569 bb_tx = BB_PATH_A;
1570 break;
1571 }
1572 tx_path_nss_set_full_tx(hal->txpath_nss, hal->txpath_num_nss, bb_tx);
1573 RTW_INFO("%s ,ant idx %d, tx path_num_nss = %d\n", __func__, anttx, hal->txpath_num_nss[0]);
1574
1575 #ifdef CONFIG_RTL8822C
1576 if (IS_HARDWARE_TYPE_8822C(pAdapter)) {
1577 rtl8822c_mp_config_rfpath(pAdapter);
1578 return;
1579 }
1580 #endif
1581 #ifdef CONFIG_RTL8814A
1582 if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
1583 mpt_SetRFPath_8814A(pAdapter);
1584 return;
1585 }
1586 #endif
1587 #ifdef CONFIG_RTL8822B
1588 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1589 rtl8822b_mp_config_rfpath(pAdapter);
1590 return;
1591 }
1592 #endif
1593 #ifdef CONFIG_RTL8821C
1594 if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
1595 rtl8821c_mp_config_rfpath(pAdapter);
1596 return;
1597 }
1598 #endif
1599 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1600 if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
1601 mpt_SetRFPath_8812A(pAdapter);
1602 return;
1603 }
1604 #endif
1605 #ifdef CONFIG_RTL8723B
1606 if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1607 mpt_SetRFPath_8723B(pAdapter);
1608 return;
1609 }
1610 #endif
1611
1612 #ifdef CONFIG_RTL8703B
1613 if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1614 mpt_SetRFPath_8703B(pAdapter);
1615 return;
1616 }
1617 #endif
1618
1619 #ifdef CONFIG_RTL8723D
1620 if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1621 mpt_SetRFPath_8723D(pAdapter);
1622 return;
1623 }
1624 #endif
1625
1626 #ifdef CONFIG_RTL8192F
1627 if (IS_HARDWARE_TYPE_8192F(pAdapter)) {
1628 mpt_set_rfpath_8192f(pAdapter);
1629 return;
1630 }
1631 #endif
1632
1633 #ifdef CONFIG_RTL8814B
1634 if (IS_HARDWARE_TYPE_8814B(pAdapter)) {
1635 rtl8814b_mp_config_rfpath(pAdapter);
1636 return;
1637 }
1638 #endif
1639
1640 /* else if (IS_HARDWARE_TYPE_8821B(pAdapter))
1641 mpt_SetRFPath_8821B(pAdapter);
1642 Prepare for 8822B
1643 else if (IS_HARDWARE_TYPE_8822B(Context))
1644 mpt_SetRFPath_8822B(Context);
1645 */
1646 mpt_SetRFPath_819X(pAdapter);
1647 RTW_INFO("mpt_SetRFPath_819X Do %s\n", __func__);
1648 }
1649
hal_mpt_SetThermalMeter(PADAPTER pAdapter,u8 target_ther)1650 s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
1651 {
1652 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1653
1654 if (!netif_running(pAdapter->pnetdev)) {
1655 return _FAIL;
1656 }
1657
1658
1659 if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
1660 return _FAIL;
1661 }
1662
1663 target_ther &= 0xff;
1664
1665 pHalData->eeprom_thermal_meter = target_ther;
1666
1667 return _SUCCESS;
1668 }
1669
1670
hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)1671 void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)
1672 {
1673 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
1674 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);
1675 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x0);
1676 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);
1677 } else
1678 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);
1679
1680 }
1681
1682
hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter,u8 rf_path)1683 u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter, u8 rf_path)
1684
1685 {
1686 struct dm_struct *p_dm_odm = adapter_to_phydm(pAdapter);
1687
1688 u32 ThermalValue = 0;
1689 s32 thermal_value_temp = 0;
1690 s8 thermal_offset = 0;
1691 u32 thermal_reg_mask = 0;
1692
1693 if (IS_8822C_SERIES(GET_HAL_DATA(pAdapter)->version_id))
1694 thermal_reg_mask = 0x007e; /*0x42: RF Reg[6:1], 35332(themal K & bias k & power trim) & 35325(tssi )*/
1695 else
1696 thermal_reg_mask = 0xfc00; /*0x42: RF Reg[15:10]*/
1697
1698 ThermalValue = (u8)phy_query_rf_reg(pAdapter, rf_path, 0x42, thermal_reg_mask);
1699
1700 thermal_offset = phydm_get_thermal_offset(p_dm_odm);
1701
1702 thermal_value_temp = ThermalValue + thermal_offset;
1703
1704 if (thermal_value_temp > 63)
1705 ThermalValue = 63;
1706 else if (thermal_value_temp < 0)
1707 ThermalValue = 0;
1708 else
1709 ThermalValue = thermal_value_temp;
1710
1711 return (u8)ThermalValue;
1712 }
1713
1714
hal_mpt_GetThermalMeter(PADAPTER pAdapter,u8 rfpath,u8 * value)1715 void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 rfpath, u8 *value)
1716 {
1717 #if 0
1718 fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
1719 rtw_msleep_os(1000);
1720 fw_cmd_data(pAdapter, value, 1);
1721 *value &= 0xFF;
1722 #else
1723 hal_mpt_TriggerRFThermalMeter(pAdapter);
1724 rtw_msleep_os(1000);
1725 *value = hal_mpt_ReadRFThermalMeter(pAdapter, rfpath);
1726 #endif
1727
1728 }
1729
1730
hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter,u8 bStart)1731 void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
1732 {
1733 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1734
1735 pAdapter->mppriv.mpt_ctx.bSingleCarrier = bStart;
1736
1737 if (bStart) {/*/ Start Single Carrier.*/
1738 /*/ Start Single Carrier.*/
1739 /*/ 1. if OFDM block on?*/
1740 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
1741 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/
1742
1743 /*/ 2. set CCK test mode off, set to CCK normal mode*/
1744 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
1745
1746 /*/ 3. turn on scramble setting*/
1747 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
1748
1749 /*/ 4. Turn On Continue Tx and turn off the other test modes.*/
1750 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1751 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
1752 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_SingleCarrier);
1753 else
1754 #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1755 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleCarrier);
1756
1757 } else {
1758 /*/ Stop Single Carrier.*/
1759 /*/ Stop Single Carrier.*/
1760 /*/ Turn off all test modes.*/
1761 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1762 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
1763 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
1764 else
1765 #endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
1766 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
1767
1768 rtw_msleep_os(10);
1769 /*/BB Reset*/
1770 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
1771 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
1772 }
1773 }
1774
1775
hal_mpt_SetSingleToneTx(PADAPTER pAdapter,u8 bStart)1776 void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
1777 {
1778 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1779 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
1780 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
1781 u32 ulAntennaTx = pHalData->antenna_tx_path;
1782 static u32 regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0;
1783 u8 rfPath;
1784
1785 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
1786 #ifdef PHYDM_MP_SUPPORT
1787 #ifdef CONFIG_RTL8814B
1788 if(pHalData->current_channel_bw == CHANNEL_WIDTH_80_80)
1789 {
1790 /* @Tx mode: RF0x00[19:16]=4'b0010 */
1791 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x0, 0xF0000, 0x2);
1792 /* @Lowest RF gain index: RF_0x0[4:0] = 0*/
1793 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x0, 0x1F, 0x0);
1794 /* @RF LO enabled */
1795 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x58, BIT(1), 0x1);
1796 /* @SYN1 */
1797 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x0, 0xF0000, 0x2);
1798 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x0, 0x1F, 0x0);
1799 config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x58, BIT(1), 0x1);
1800 }
1801 #endif
1802 phydm_mp_set_single_tone(pDM_Odm, bStart, pMptCtx->mpt_rf_path);
1803 #endif
1804 return;
1805 }
1806
1807 switch (ulAntennaTx) {
1808 case ANTENNA_B:
1809 rfPath = RF_PATH_B;
1810 break;
1811 case ANTENNA_C:
1812 rfPath = RF_PATH_C;
1813 break;
1814 case ANTENNA_D:
1815 rfPath = RF_PATH_D;
1816 break;
1817 case ANTENNA_A:
1818 default:
1819 rfPath = RF_PATH_A;
1820 break;
1821 }
1822
1823 pAdapter->mppriv.mpt_ctx.is_single_tone = bStart;
1824 if (bStart) {
1825 /*/ Start Single Tone.*/
1826 /*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/
1827 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1828 regRF = phy_query_rf_reg(pAdapter, rfPath, lna_low_gain_3, bRFRegOffsetMask);
1829 phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1830 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
1831 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
1832 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
1833 /*/Set MAC REG 88C: Prevent SingleTone Fail*/
1834 phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0xF);
1835 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO disabled*/
1836 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1837 } else if (IS_HARDWARE_TYPE_8192F(pAdapter)) { /* USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
1838 #ifdef CONFIG_RTL8192F
1839 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x1);
1840 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x1);
1841 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x1);
1842 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x1);
1843 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x1);
1844 phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x1);
1845 phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0xF);
1846 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x1); /* RF LO disabled*/
1847 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /* Tx mode*/
1848 #endif
1849 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1850 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1851 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1852 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/
1853 } else {
1854 /*/ S0/S1 both use PATH A to configure*/
1855 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
1856 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/
1857 }
1858 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1859 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1860 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */
1861 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */
1862 }
1863 } else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
1864 /*Set BB REG 88C: Prevent SingleTone Fail*/
1865 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF);
1866 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1);
1867 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2);
1868
1869 } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1870 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1871 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1872 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
1873 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x1);
1874 } else {/* S0/S1 both use PATH A to configure */
1875 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
1876 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
1877 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x1);
1878 }
1879 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
1880 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
1881 u8 p = RF_PATH_A;
1882
1883 regRF = phy_query_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);
1884 regBB0 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);
1885 regBB1 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);
1886 regBB2 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1887 regBB3 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord);
1888
1889 phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x0); /*/ Disable CCK and OFDM*/
1890
1891 if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
1892 for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
1893 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1894 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1895 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1896 }
1897 } else {
1898 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
1899 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
1900 #ifdef CONFIG_RTL8821C
1901 if (IS_HARDWARE_TYPE_8821C(pAdapter) && pDM_Odm->current_rf_set_8821c == SWITCH_TO_BTG)
1902 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x75, BIT16, 0x1); /* RF LO (for BTG) enabled */
1903 else
1904 #endif
1905 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
1906 }
1907 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
1908 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777); /* 0xCB0=0x77777777*/
1909 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777); /* 0xEB0=0x77777777*/
1910 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777); /* 0xCB4[15:0] = 0x7777*/
1911 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777); /* 0xEB4[15:0] = 0x7777*/
1912 phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xFFF, 0xb); /* 0xCBC[23:16] = 0x12*/
1913 phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xFFF, 0x830); /* 0xEBC[23:16] = 0x12*/
1914 } else if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
1915 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xF0F0, 0x707); /* 0xCB0[[15:12, 7:4] = 0x707*/
1916
1917 if (pHalData->external_pa_5g)
1918 {
1919 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
1920 }
1921 else if (pHalData->ExternalPA_2G)
1922 {
1923 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
1924 }
1925 } else {
1926 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1927 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
1928
1929 if (pHalData->external_pa_5g) {
1930 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/
1931 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/
1932 } else if (pHalData->ExternalPA_2G) {
1933 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/
1934 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/
1935 }
1936 }
1937 #endif
1938 }
1939 #if defined(CONFIG_RTL8814A)
1940 else if (IS_HARDWARE_TYPE_8814A(pAdapter))
1941 mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE);
1942 #endif
1943 else /*/ Turn On SingleTone and turn off the other test modes.*/
1944 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone);
1945
1946 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
1947 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
1948
1949 } else {/*/ Stop Single Ton e.*/
1950
1951 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
1952 phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, bRFRegOffsetMask, regRF);
1953 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1954 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1955 } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
1956 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/
1957 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0);/*/ RF LO disabled */
1958 /*/ RESTORE MAC REG 88C: Enable RF Functions*/
1959 phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0x0);
1960 } else if (IS_HARDWARE_TYPE_8192F(pAdapter)){
1961 #ifdef CONFIG_RTL8192F
1962 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x0);
1963 phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x0);
1964 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x0);
1965 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x0);
1966 phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x0);
1967 phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x0);
1968 phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0x0);
1969 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x0); /* RF LO disabled*/
1970 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /* Rx mode*/
1971 #endif
1972 } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
1973 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1974 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1975 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/
1976 } else {
1977 /*/ S0/S1 both use PATH A to configure*/
1978 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
1979 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/
1980 }
1981 } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
1982 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1983 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */
1984 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */
1985 }
1986 } else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
1987 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /*Tx mode*/
1988 phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0); /*RF LO disabled*/
1989 /*Set BB REG 88C: Prevent SingleTone Fail*/
1990 phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc);
1991 } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
1992 if (pMptCtx->mpt_rf_path == RF_PATH_A) {
1993 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
1994 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
1995 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x0);
1996 } else { /* S0/S1 both use PATH A to configure */
1997 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
1998 phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
1999 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x0);
2000 }
2001 } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
2002 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
2003 u8 p = RF_PATH_A;
2004
2005 phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/
2006
2007 if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
2008 for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
2009 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
2010 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
2011 }
2012 } else {
2013 p = pMptCtx->mpt_rf_path;
2014 phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
2015
2016 if (IS_HARDWARE_TYPE_8821C(pAdapter))
2017 phy_set_rf_reg(pAdapter, p, 0x75, BIT16, 0x0); /* RF LO (for BTG) disabled */
2018
2019 phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
2020 }
2021
2022 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0);
2023 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1);
2024 phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB2);
2025 phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB3);
2026
2027 if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
2028 RTW_INFO("Restore RFE control Pin cbc\n");
2029 phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xfff, 0x0);
2030 phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xfff, 0x0);
2031 }
2032 #endif
2033 }
2034 #if defined(CONFIG_RTL8814A)
2035 else if (IS_HARDWARE_TYPE_8814A(pAdapter))
2036 mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE);
2037
2038 else/*/ Turn off all test modes.*/
2039 phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2040 #endif
2041 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2042 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2043
2044 }
2045 }
2046
hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter,u8 bStart)2047 void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
2048 {
2049 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2050 struct dm_struct *pdm_odm = &pHalData->odmpriv;
2051 u8 Rate;
2052
2053 pAdapter->mppriv.mpt_ctx.is_carrier_suppression = bStart;
2054
2055 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
2056 #ifdef PHYDM_MP_SUPPORT
2057 phydm_mp_set_carrier_supp(pdm_odm, bStart, pAdapter->mppriv.rateidx);
2058 #endif
2059 return;
2060 }
2061
2062 Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
2063 if (bStart) {/* Start Carrier Suppression.*/
2064 if (Rate <= MPT_RATE_11M) {
2065 /*/ 1. if CCK block on?*/
2066 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
2067 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
2068
2069 /*/Turn Off All Test Mode*/
2070 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
2071 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/
2072 else
2073 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2074
2075 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/
2076 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); /*/turn off scramble setting*/
2077
2078 /*/Set CCK Tx Test Rate*/
2079 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); /*/Set FTxRate to 1Mbps*/
2080 }
2081
2082 /*Set for dynamic set Power index*/
2083 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2084 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2085
2086 } else {/* Stop Carrier Suppression.*/
2087
2088 if (Rate <= MPT_RATE_11M) {
2089 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
2090 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2091
2092 /*BB Reset*/
2093 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2094 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2095 }
2096 /*Stop for dynamic set Power index*/
2097 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2098 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2099 }
2100 RTW_INFO("\n MPT_ProSetCarrierSupp() is finished.\n");
2101 }
2102
hal_mpt_query_phytxok(PADAPTER pAdapter)2103 u32 hal_mpt_query_phytxok(PADAPTER pAdapter)
2104 {
2105 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2106 RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
2107 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2108 u16 count = 0;
2109
2110 #ifdef PHYDM_MP_SUPPORT
2111 struct dm_struct *dm = (struct dm_struct *)&pHalData->odmpriv;
2112 struct phydm_mp *mp = &dm->dm_mp_table;
2113
2114 if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
2115 phydm_mp_get_tx_ok(&pHalData->odmpriv, pAdapter->mppriv.rateidx);
2116 count = mp->tx_phy_ok_cnt;
2117
2118 } else
2119 #endif
2120 {
2121
2122 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2123 count = phy_query_bb_reg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/
2124 else
2125 count = phy_query_bb_reg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/
2126 }
2127
2128 if (count > 50000) {
2129 rtw_reset_phy_trx_ok_counters(pAdapter);
2130 pAdapter->mppriv.tx.sended += count;
2131 count = 0;
2132 }
2133
2134 return pAdapter->mppriv.tx.sended + count;
2135
2136 }
2137
mpt_StopCckContTx(PADAPTER pAdapter)2138 static void mpt_StopCckContTx(
2139 PADAPTER pAdapter
2140 )
2141 {
2142 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2143 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2144 u8 u1bReg;
2145
2146 pMptCtx->bCckContTx = FALSE;
2147 pMptCtx->bOfdmContTx = FALSE;
2148
2149 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
2150 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2151
2152 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2153 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 2b00*/
2154 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
2155
2156 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
2157 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 0);
2158 phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 0);
2159 }
2160
2161 /*BB Reset*/
2162 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2163 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2164
2165 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2166 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2167 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2168 }
2169
2170 if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) ||
2171 IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) ||
2172 IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) ||
2173 IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
2174 phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);/* patch Count CCK adjust Rate*/
2175 }
2176
2177 } /* mpt_StopCckContTx */
2178
2179
mpt_StopOfdmContTx(PADAPTER pAdapter)2180 static void mpt_StopOfdmContTx(
2181 PADAPTER pAdapter
2182 )
2183 {
2184 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2185 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2186 u8 u1bReg;
2187 u32 data;
2188
2189 pMptCtx->bCckContTx = FALSE;
2190 pMptCtx->bOfdmContTx = FALSE;
2191
2192 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
2193 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2194 else
2195 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2196
2197 rtw_mdelay_os(10);
2198
2199 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)){
2200 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 0*/
2201 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
2202 }
2203
2204 /*BB Reset*/
2205 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
2206 phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
2207
2208 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2209 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
2210 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
2211 }
2212 } /* mpt_StopOfdmContTx */
2213
2214
mpt_StartCckContTx(PADAPTER pAdapter)2215 static void mpt_StartCckContTx(
2216 PADAPTER pAdapter
2217 )
2218 {
2219 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2220 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2221 u32 cckrate;
2222
2223 /* 1. if CCK block on */
2224 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn))
2225 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/
2226
2227 /*Turn Off All Test Mode*/
2228 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
2229 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
2230 else
2231 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
2232
2233 cckrate = pAdapter->mppriv.rateidx;
2234
2235 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
2236
2237 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*transmit mode*/
2238 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
2239
2240 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2241 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 11 force cck rxiq = 0*/
2242 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
2243 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
2244 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 1);
2245 phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 1);
2246 }
2247
2248 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2249 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2250 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2251 }
2252
2253 if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) ||
2254 IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) ||
2255 IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) ||
2256 IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
2257 if (pAdapter->mppriv.rateidx == MPT_RATE_1M) /* patch Count CCK adjust Rate*/
2258 phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);
2259 else
2260 phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bEnable);
2261 }
2262
2263 pMptCtx->bCckContTx = TRUE;
2264 pMptCtx->bOfdmContTx = FALSE;
2265
2266 } /* mpt_StartCckContTx */
2267
2268
mpt_StartOfdmContTx(PADAPTER pAdapter)2269 static void mpt_StartOfdmContTx(
2270 PADAPTER pAdapter
2271 )
2272 {
2273 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2274 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
2275
2276 /* 1. if OFDM block on?*/
2277 if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
2278 phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/
2279
2280 /* 2. set CCK test mode off, set to CCK normal mode*/
2281 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
2282
2283 /* 3. turn on scramble setting*/
2284 phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
2285
2286 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2287 phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 2b'11*/
2288 phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/
2289 }
2290
2291 /* 4. Turn On Continue Tx and turn off the other test modes.*/
2292 if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
2293 phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx);
2294 else
2295 phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);
2296
2297 if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
2298 phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
2299 phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
2300 }
2301
2302 pMptCtx->bCckContTx = FALSE;
2303 pMptCtx->bOfdmContTx = TRUE;
2304 } /* mpt_StartOfdmContTx */
2305
2306 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
2307 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
mpt_convert_phydm_txinfo_for_jaguar3(RT_PMAC_TX_INFO * pMacTxInfo,struct phydm_pmac_info * phydmtxinfo)2308 static void mpt_convert_phydm_txinfo_for_jaguar3(
2309 RT_PMAC_TX_INFO *pMacTxInfo, struct phydm_pmac_info *phydmtxinfo)
2310 {
2311 phydmtxinfo->en_pmac_tx = pMacTxInfo->bEnPMacTx;
2312 phydmtxinfo->mode = pMacTxInfo->Mode;
2313 phydmtxinfo->tx_rate = MRateToHwRate(mpt_to_mgnt_rate(pMacTxInfo->TX_RATE));
2314 phydmtxinfo->tx_sc = pMacTxInfo->TX_SC;
2315 phydmtxinfo->is_short_preamble = pMacTxInfo->bSPreamble;
2316 phydmtxinfo->ndp_sound = pMacTxInfo->NDP_sound;
2317 phydmtxinfo->bw = pMacTxInfo->BandWidth;
2318 phydmtxinfo->m_stbc = pMacTxInfo->m_STBC;
2319 phydmtxinfo->packet_period = pMacTxInfo->PacketPeriod;
2320 phydmtxinfo->packet_count = pMacTxInfo->PacketCount;
2321 phydmtxinfo->packet_pattern = pMacTxInfo->PacketPattern;
2322 phydmtxinfo->sfd = pMacTxInfo->SFD;
2323 phydmtxinfo->signal_field = pMacTxInfo->SignalField;
2324 phydmtxinfo->service_field = pMacTxInfo->ServiceField;
2325 phydmtxinfo->length = pMacTxInfo->LENGTH;
2326 _rtw_memcpy(&phydmtxinfo->crc16,pMacTxInfo->CRC16, 2);
2327 _rtw_memcpy(&phydmtxinfo->lsig , pMacTxInfo->LSIG,3);
2328 _rtw_memcpy(&phydmtxinfo->ht_sig , pMacTxInfo->HT_SIG,6);
2329 _rtw_memcpy(&phydmtxinfo->vht_sig_a , pMacTxInfo->VHT_SIG_A,6);
2330 _rtw_memcpy(&phydmtxinfo->vht_sig_b , pMacTxInfo->VHT_SIG_B,4);
2331 phydmtxinfo->vht_sig_b_crc = pMacTxInfo->VHT_SIG_B_CRC;
2332 _rtw_memcpy(&phydmtxinfo->vht_delimiter,pMacTxInfo->VHT_Delimiter,4);
2333 }
2334 #endif
2335
2336 /* for HW TX mode */
mpt_ProSetPMacTx(PADAPTER Adapter)2337 u8 mpt_ProSetPMacTx(PADAPTER Adapter)
2338 {
2339 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2340 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
2341 struct mp_priv *pmppriv = &Adapter->mppriv;
2342 struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
2343 RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
2344 struct dm_struct *p_dm_odm;
2345 u32 u4bTmp;
2346 u8 status = _TRUE;
2347
2348 p_dm_odm = &pHalData->odmpriv;
2349
2350 #if 0
2351 PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3);
2352 PRINT_DATA("HT_SIG", PMacTxInfo.HT_SIG, 6);
2353 PRINT_DATA("VHT_SIG_A", PMacTxInfo.VHT_SIG_A, 6);
2354 PRINT_DATA("VHT_SIG_B", PMacTxInfo.VHT_SIG_B, 4);
2355 dbg_print("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC);
2356 PRINT_DATA("VHT_Delimiter", PMacTxInfo.VHT_Delimiter, 4);
2357
2358 PRINT_DATA("Src Address", Adapter->mac_addr, ETH_ALEN);
2359 PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, ETH_ALEN);
2360 #endif
2361 if (pmppriv->pktInterval != 0)
2362 PMacTxInfo.PacketPeriod = pmppriv->pktInterval;
2363
2364 if (pmppriv->tx.count != 0)
2365 PMacTxInfo.PacketCount = pmppriv->tx.count;
2366
2367 RTW_INFO("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound);
2368 RTW_INFO("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount,
2369 PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern);
2370
2371 if (hal_spec->tx_nss_num < 2 && MPT_IS_2SS_RATE(PMacTxInfo.TX_RATE))
2372 return _FALSE;
2373 if (hal_spec->tx_nss_num < 3 && MPT_IS_3SS_RATE(PMacTxInfo.TX_RATE))
2374 return _FALSE;
2375 if (hal_spec->tx_nss_num < 4 && MPT_IS_4SS_RATE(PMacTxInfo.TX_RATE))
2376 return _FALSE;
2377 if (!is_supported_vht(Adapter->registrypriv.wireless_mode) && MPT_IS_VHT_RATE(PMacTxInfo.TX_RATE))
2378 return _FALSE;
2379 if (!is_supported_ht(Adapter->registrypriv.wireless_mode) && MPT_IS_HT_RATE(PMacTxInfo.TX_RATE))
2380 return _FALSE;
2381
2382 if (PMacTxInfo.BandWidth == 1 && hal_chk_bw_cap(Adapter, BW_CAP_40M))
2383 PMacTxInfo.BandWidth = CHANNEL_WIDTH_40;
2384 else if (PMacTxInfo.BandWidth == 2 && hal_chk_bw_cap(Adapter, BW_CAP_80M))
2385 PMacTxInfo.BandWidth = CHANNEL_WIDTH_80;
2386 else
2387 PMacTxInfo.BandWidth = CHANNEL_WIDTH_20;
2388
2389 if (IS_HARDWARE_TYPE_JAGUAR3(Adapter)) {
2390 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
2391 struct phydm_pmac_info phydm_mactxinfo;
2392
2393 if (PMacTxInfo.bEnPMacTx == TRUE) {
2394 pMptCtx->HWTxmode = PMacTxInfo.Mode;
2395 pMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE;
2396 if (PMacTxInfo.Mode == CONTINUOUS_TX)
2397 hal_mpt_SetTxPower(Adapter);
2398 } else {
2399 PMacTxInfo.Mode = pMptCtx->HWTxmode;
2400 PMacTxInfo.TX_RATE = pMptCtx->mpt_rate_index;
2401 pMptCtx->HWTxmode = TEST_NONE;
2402 }
2403 mpt_convert_phydm_txinfo_for_jaguar3(&PMacTxInfo, &phydm_mactxinfo);
2404 phydm_set_pmac_tx(p_dm_odm, &phydm_mactxinfo, pMptCtx->mpt_rf_path);
2405 #endif
2406 return status;
2407 }
2408
2409 if (PMacTxInfo.bEnPMacTx == FALSE) {
2410 if (pMptCtx->HWTxmode == CONTINUOUS_TX) {
2411 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
2412 if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
2413 mpt_StopCckContTx(Adapter);
2414 else
2415 mpt_StopOfdmContTx(Adapter);
2416 } else if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index)) {
2417 u4bTmp = phy_query_bb_reg(Adapter, 0xf50, bMaskLWord);
2418 phy_set_bb_reg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50);
2419 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /*TX Stop*/
2420 } else
2421 phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
2422
2423 if (pMptCtx->HWTxmode == OFDM_Single_Tone_TX) {
2424 /* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/
2425 if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
2426 mpt_StopCckContTx(Adapter);
2427 else
2428 mpt_StopOfdmContTx(Adapter);
2429
2430 mpt_SetSingleTone_8814A(Adapter, FALSE, TRUE);
2431 }
2432 pMptCtx->HWTxmode = TEST_NONE;
2433 return status;
2434 }
2435
2436 pMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE;
2437
2438 if (PMacTxInfo.Mode == CONTINUOUS_TX) {
2439 pMptCtx->HWTxmode = CONTINUOUS_TX;
2440 PMacTxInfo.PacketCount = 1;
2441
2442 hal_mpt_SetTxPower(Adapter);
2443
2444 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2445 mpt_StartCckContTx(Adapter);
2446 else
2447 mpt_StartOfdmContTx(Adapter);
2448 } else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
2449 /* Continuous TX -> HW TX -> RF Setting */
2450 pMptCtx->HWTxmode = OFDM_Single_Tone_TX;
2451 PMacTxInfo.PacketCount = 1;
2452
2453 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
2454 mpt_StartCckContTx(Adapter);
2455 else
2456 mpt_StartOfdmContTx(Adapter);
2457 } else if (PMacTxInfo.Mode == PACKETS_TX) {
2458 pMptCtx->HWTxmode = PACKETS_TX;
2459 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0)
2460 PMacTxInfo.PacketCount = 0xffff;
2461 }
2462
2463 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2464 /* 0xb1c[0:15] TX packet count 0xb1C[31:16] SFD*/
2465 u4bTmp = PMacTxInfo.PacketCount | (PMacTxInfo.SFD << 16);
2466 phy_set_bb_reg(Adapter, 0xb1c, bMaskDWord, u4bTmp);
2467 /* 0xb40 7:0 SIGNAL 15:8 SERVICE 31:16 LENGTH*/
2468 u4bTmp = PMacTxInfo.SignalField | (PMacTxInfo.ServiceField << 8) | (PMacTxInfo.LENGTH << 16);
2469 phy_set_bb_reg(Adapter, 0xb40, bMaskDWord, u4bTmp);
2470 u4bTmp = PMacTxInfo.CRC16[0] | (PMacTxInfo.CRC16[1] << 8);
2471 phy_set_bb_reg(Adapter, 0xb44, bMaskLWord, u4bTmp);
2472
2473 if (PMacTxInfo.bSPreamble)
2474 phy_set_bb_reg(Adapter, 0xb0c, BIT27, 0);
2475 else
2476 phy_set_bb_reg(Adapter, 0xb0c, BIT27, 1);
2477 } else {
2478 phy_set_bb_reg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount);
2479
2480 u4bTmp = PMacTxInfo.LSIG[0] | ((PMacTxInfo.LSIG[1]) << 8) | ((PMacTxInfo.LSIG[2]) << 16) | ((PMacTxInfo.PacketPattern) << 24);
2481 phy_set_bb_reg(Adapter, 0xb08, bMaskDWord, u4bTmp); /* Set 0xb08[23:0] = LSIG, 0xb08[31:24] = Data init octet*/
2482
2483 if (PMacTxInfo.PacketPattern == 0x12)
2484 u4bTmp = 0x3000000;
2485 else
2486 u4bTmp = 0;
2487 }
2488
2489 if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) {
2490 u4bTmp |= PMacTxInfo.HT_SIG[0] | ((PMacTxInfo.HT_SIG[1]) << 8) | ((PMacTxInfo.HT_SIG[2]) << 16);
2491 phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2492 u4bTmp = PMacTxInfo.HT_SIG[3] | ((PMacTxInfo.HT_SIG[4]) << 8) | ((PMacTxInfo.HT_SIG[5]) << 16);
2493 phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
2494 } else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2495 u4bTmp |= PMacTxInfo.VHT_SIG_A[0] | ((PMacTxInfo.VHT_SIG_A[1]) << 8) | ((PMacTxInfo.VHT_SIG_A[2]) << 16);
2496 phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
2497 u4bTmp = PMacTxInfo.VHT_SIG_A[3] | ((PMacTxInfo.VHT_SIG_A[4]) << 8) | ((PMacTxInfo.VHT_SIG_A[5]) << 16);
2498 phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
2499
2500 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_SIG_B, 4);
2501 phy_set_bb_reg(Adapter, 0xb14, bMaskDWord, u4bTmp);
2502 }
2503
2504 if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
2505 u4bTmp = (PMacTxInfo.VHT_SIG_B_CRC << 24) | PMacTxInfo.PacketPeriod; /* for TX interval */
2506 phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, u4bTmp);
2507
2508 _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_Delimiter, 4);
2509 phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, u4bTmp);
2510
2511 /* 0xb28 - 0xb34 24 byte Probe Request MAC Header*/
2512 /*& Duration & Frame control*/
2513 phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, 0x00000040);
2514
2515 /* Address1 [0:3]*/
2516 u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2517 phy_set_bb_reg(Adapter, 0xb2C, bMaskDWord, u4bTmp);
2518
2519 /* Address3 [3:0]*/
2520 phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2521
2522 /* Address2[0:1] & Address1 [5:4]*/
2523 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2524 phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2525
2526 /* Address2 [5:2]*/
2527 u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2528 phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2529
2530 /* Sequence Control & Address3 [5:4]*/
2531 /*u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8) ;*/
2532 /*phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/
2533 } else {
2534 phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod); /* for TX interval*/
2535 /* & Duration & Frame control */
2536 phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, 0x00000040);
2537
2538 /* 0xb24 - 0xb38 24 byte Probe Request MAC Header*/
2539 /* Address1 [0:3]*/
2540 u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
2541 phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, u4bTmp);
2542
2543 /* Address3 [3:0]*/
2544 phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
2545
2546 /* Address2[0:1] & Address1 [5:4]*/
2547 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
2548 phy_set_bb_reg(Adapter, 0xb2c, bMaskDWord, u4bTmp);
2549
2550 /* Address2 [5:2] */
2551 u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
2552 phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
2553
2554 /* Sequence Control & Address3 [5:4]*/
2555 u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8);
2556 phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
2557 }
2558
2559 phy_set_bb_reg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX);
2560
2561 /* 0xb4c 3:0 TXSC 5:4 BW 7:6 m_STBC 8 NDP_Sound*/
2562 u4bTmp = (PMacTxInfo.TX_SC) | ((PMacTxInfo.BandWidth) << 4) | ((PMacTxInfo.m_STBC - 1) << 6) | ((PMacTxInfo.NDP_sound) << 8);
2563 phy_set_bb_reg(Adapter, 0xb4c, 0x1ff, u4bTmp);
2564
2565 if (IS_HARDWARE_TYPE_JAGUAR2(Adapter)) {
2566 u32 offset = 0xb44;
2567
2568 if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
2569 phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
2570 else if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
2571 phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
2572 else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
2573 phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
2574
2575 } else if(IS_HARDWARE_TYPE_JAGUAR(Adapter)) {
2576 u32 offset = 0xb4c;
2577
2578 if(IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
2579 phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
2580 else if(IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
2581 phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
2582 else if(IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
2583 phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
2584 }
2585
2586 phy_set_bb_reg(Adapter, 0xb00, BIT8, 1); /* Turn on PMAC*/
2587 /* phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); */ /* TX Stop */
2588 if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
2589 phy_set_bb_reg(Adapter, 0xb04, 0xf, 8); /*TX CCK ON*/
2590 phy_set_bb_reg(Adapter, 0xA84, BIT31, 0);
2591 } else
2592 phy_set_bb_reg(Adapter, 0xb04, 0xf, 4); /* TX Ofdm ON */
2593
2594 if (PMacTxInfo.Mode == OFDM_Single_Tone_TX)
2595 mpt_SetSingleTone_8814A(Adapter, TRUE, TRUE);
2596
2597 return status;
2598 }
2599
2600 #endif
2601
hal_mpt_SetContinuousTx(PADAPTER pAdapter,u8 bStart)2602 void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
2603 {
2604 u8 Rate;
2605
2606 RTW_INFO("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx);
2607 Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
2608 pAdapter->mppriv.mpt_ctx.is_start_cont_tx = bStart;
2609
2610 if (Rate <= MPT_RATE_11M) {
2611 if (bStart)
2612 mpt_StartCckContTx(pAdapter);
2613 else
2614 mpt_StopCckContTx(pAdapter);
2615
2616 } else if (Rate >= MPT_RATE_6M) {
2617 if (bStart)
2618 mpt_StartOfdmContTx(pAdapter);
2619 else
2620 mpt_StopOfdmContTx(pAdapter);
2621 }
2622 }
2623
mpt_trigger_tssi_tracking(PADAPTER pAdapter,u8 rf_path)2624 void mpt_trigger_tssi_tracking(PADAPTER pAdapter, u8 rf_path)
2625 {
2626 #ifdef CONFIG_RTL8814B
2627 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2628 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
2629
2630 halrf_do_tssi_8814b(pDM_Odm, rf_path);
2631 #endif
2632 }
2633
2634 #endif /* CONFIG_MP_INCLUDE*/
2635