1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15
16 #define _HAL_INTF_C_
17
18 #include <drv_types.h>
19 #include <hal_data.h>
20
21 const u32 _chip_type_to_odm_ic_type[] = {
22 0,
23 ODM_RTL8188E,
24 ODM_RTL8192E,
25 ODM_RTL8812,
26 ODM_RTL8821,
27 ODM_RTL8723B,
28 ODM_RTL8814A,
29 ODM_RTL8703B,
30 ODM_RTL8188F,
31 ODM_RTL8188F,
32 ODM_RTL8822B,
33 ODM_RTL8723D,
34 ODM_RTL8821C,
35 ODM_RTL8710B,
36 ODM_RTL8192F,
37 ODM_RTL8822C,
38 ODM_RTL8814B,
39 0,
40 };
41
rtw_hal_chip_configure(_adapter * padapter)42 void rtw_hal_chip_configure(_adapter *padapter)
43 {
44 padapter->hal_func.intf_chip_configure(padapter);
45 }
46
47 /*
48 * Description:
49 * Read chip internal ROM data
50 *
51 * Return:
52 * _SUCCESS success
53 * _FAIL fail
54 */
rtw_hal_read_chip_info(_adapter * padapter)55 u8 rtw_hal_read_chip_info(_adapter *padapter)
56 {
57 u8 rtn = _SUCCESS;
58 u8 hci_type = rtw_get_intf_type(padapter);
59 systime start = rtw_get_current_time();
60
61 /* before access eFuse, make sure card enable has been called */
62 if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI)
63 && !rtw_is_hw_init_completed(padapter))
64 rtw_hal_power_on(padapter);
65
66 rtn = padapter->hal_func.read_adapter_info(padapter);
67
68 if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI)
69 && !rtw_is_hw_init_completed(padapter))
70 rtw_hal_power_off(padapter);
71
72 RTW_INFO("%s in %d ms\n", __func__, rtw_get_passing_time_ms(start));
73
74 return rtn;
75 }
76
rtw_hal_read_chip_version(_adapter * padapter)77 void rtw_hal_read_chip_version(_adapter *padapter)
78 {
79 padapter->hal_func.read_chip_version(padapter);
80 rtw_odm_init_ic_type(padapter);
81 }
82
rtw_init_wireless_mode(_adapter * padapter)83 static void rtw_init_wireless_mode(_adapter *padapter)
84 {
85 u8 proto_wireless_mode = 0;
86 struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
87 if(hal_spec->proto_cap & PROTO_CAP_11B)
88 proto_wireless_mode |= WIRELESS_11B;
89
90 if(hal_spec->proto_cap & PROTO_CAP_11G)
91 proto_wireless_mode |= WIRELESS_11G;
92 #ifdef CONFIG_80211AC_VHT
93 if(hal_spec->band_cap & BAND_CAP_5G)
94 proto_wireless_mode |= WIRELESS_11A;
95 #endif
96
97 #ifdef CONFIG_80211N_HT
98 if(hal_spec->proto_cap & PROTO_CAP_11N) {
99
100 if(hal_spec->band_cap & BAND_CAP_2G)
101 proto_wireless_mode |= WIRELESS_11_24N;
102 if(hal_spec->band_cap & BAND_CAP_5G)
103 proto_wireless_mode |= WIRELESS_11_5N;
104 }
105 #endif
106
107 #ifdef CONFIG_80211AC_VHT
108 if(hal_spec->proto_cap & PROTO_CAP_11AC)
109 proto_wireless_mode |= WIRELESS_11AC;
110 #endif
111 padapter->registrypriv.wireless_mode &= proto_wireless_mode;
112 }
113
rtw_hal_def_value_init(_adapter * padapter)114 void rtw_hal_def_value_init(_adapter *padapter)
115 {
116 if (is_primary_adapter(padapter)) {
117 /*init fw_psmode_iface_id*/
118 adapter_to_pwrctl(padapter)->fw_psmode_iface_id = 0xff;
119 /*wireless_mode*/
120 rtw_init_wireless_mode(padapter);
121 padapter->hal_func.init_default_value(padapter);
122
123 rtw_init_hal_com_default_value(padapter);
124
125 #ifdef CONFIG_FW_MULTI_PORT_SUPPORT
126 adapter_to_dvobj(padapter)->dft.port_id = 0xFF;
127 adapter_to_dvobj(padapter)->dft.mac_id = 0xFF;
128 #endif
129 #ifdef CONFIG_HW_P0_TSF_SYNC
130 adapter_to_dvobj(padapter)->p0_tsf.sync_port = MAX_HW_PORT;
131 adapter_to_dvobj(padapter)->p0_tsf.offset = 0;
132 #endif
133
134 GET_HAL_DATA(padapter)->rx_tsf_addr_filter_config = 0;
135 }
136 }
137
rtw_hal_data_init(_adapter * padapter)138 u8 rtw_hal_data_init(_adapter *padapter)
139 {
140 if (is_primary_adapter(padapter)) {
141 padapter->hal_data_sz = sizeof(HAL_DATA_TYPE);
142 padapter->HalData = rtw_zvmalloc(padapter->hal_data_sz);
143 if (padapter->HalData == NULL) {
144 RTW_INFO("cant not alloc memory for HAL DATA\n");
145 return _FAIL;
146 }
147 rtw_phydm_priv_init(padapter);
148 }
149 return _SUCCESS;
150 }
151
rtw_hal_data_deinit(_adapter * padapter)152 void rtw_hal_data_deinit(_adapter *padapter)
153 {
154 if (is_primary_adapter(padapter)) {
155 if (padapter->HalData) {
156 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
157 phy_free_filebuf(padapter);
158 #endif
159 rtw_vmfree(padapter->HalData, padapter->hal_data_sz);
160 padapter->HalData = NULL;
161 padapter->hal_data_sz = 0;
162 }
163 }
164 }
165
rtw_hal_free_data(_adapter * padapter)166 void rtw_hal_free_data(_adapter *padapter)
167 {
168 /* free HAL Data */
169 rtw_hal_data_deinit(padapter);
170 }
rtw_hal_dm_init(_adapter * padapter)171 void rtw_hal_dm_init(_adapter *padapter)
172 {
173 if (is_primary_adapter(padapter)) {
174 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
175
176 padapter->hal_func.dm_init(padapter);
177
178 _rtw_spinlock_init(&pHalData->IQKSpinLock);
179
180 #ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
181 if (pHalData->txpwr_pg_mode == TXPWR_PG_WITH_PWR_IDX)
182 hal_load_txpwr_info(padapter);
183 #endif
184 phy_load_tx_power_ext_info(padapter, 1);
185 }
186 }
rtw_hal_dm_deinit(_adapter * padapter)187 void rtw_hal_dm_deinit(_adapter *padapter)
188 {
189 if (is_primary_adapter(padapter)) {
190 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
191
192 padapter->hal_func.dm_deinit(padapter);
193
194 _rtw_spinlock_free(&pHalData->IQKSpinLock);
195 }
196 }
197
rtw_chip_rftype_to_hal_rftype(_adapter * adapter,u8 limit)198 enum rf_type rtw_chip_rftype_to_hal_rftype(_adapter *adapter, u8 limit)
199 {
200 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
201 u8 tx_num = 0, rx_num = 0;
202
203 /*get RF PATH from version_id.RF_TYPE */
204 if (IS_1T1R(hal_data->version_id)) {
205 tx_num = 1;
206 rx_num = 1;
207 } else if (IS_1T2R(hal_data->version_id)) {
208 tx_num = 1;
209 rx_num = 2;
210 } else if (IS_2T2R(hal_data->version_id)) {
211 tx_num = 2;
212 rx_num = 2;
213 } else if (IS_2T3R(hal_data->version_id)) {
214 tx_num = 2;
215 rx_num = 3;
216 } else if (IS_2T4R(hal_data->version_id)) {
217 tx_num = 2;
218 rx_num = 4;
219 } else if (IS_3T3R(hal_data->version_id)) {
220 tx_num = 3;
221 rx_num = 3;
222 } else if (IS_3T4R(hal_data->version_id)) {
223 tx_num = 3;
224 rx_num = 4;
225 } else if (IS_4T4R(hal_data->version_id)) {
226 tx_num = 4;
227 rx_num = 4;
228 }
229
230 if (limit) {
231 tx_num = rtw_min(tx_num, limit);
232 rx_num = rtw_min(rx_num, limit);
233 }
234
235 return trx_num_to_rf_type(tx_num, rx_num);
236 }
237
dump_hal_runtime_trx_mode(void * sel,_adapter * adapter)238 void dump_hal_runtime_trx_mode(void *sel, _adapter *adapter)
239 {
240 struct registry_priv *regpriv = &adapter->registrypriv;
241 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
242 int i;
243
244 RTW_PRINT_SEL(sel, "txpath=0x%x, rxpath=0x%x\n", hal_data->txpath, hal_data->rxpath);
245 for (i = 0; i < hal_data->tx_nss; i++)
246 RTW_PRINT_SEL(sel, "txpath_%uss:0x%x, num:%u\n"
247 , i + 1, hal_data->txpath_nss[i]
248 , hal_data->txpath_num_nss[i]);
249 }
250
dump_hal_trx_mode(void * sel,_adapter * adapter)251 void dump_hal_trx_mode(void *sel, _adapter *adapter)
252 {
253 struct registry_priv *regpriv = &adapter->registrypriv;
254 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
255
256 RTW_PRINT_SEL(sel, "trx_path_bmp:0x%02x(%s), NumTotalRFPath:%u, max_tx_cnt:%u\n"
257 , hal_data->trx_path_bmp
258 , rf_type_to_rfpath_str(hal_data->rf_type)
259 , hal_data->NumTotalRFPath
260 , hal_data->max_tx_cnt
261 );
262 RTW_PRINT_SEL(sel, "tx_nss:%u, rx_nss:%u\n"
263 , hal_data->tx_nss, hal_data->rx_nss);
264 RTW_PRINT_SEL(sel, "\n");
265
266 dump_hal_runtime_trx_mode(sel, adapter);
267 }
268
_dump_rf_path(void * sel,_adapter * adapter)269 void _dump_rf_path(void *sel, _adapter *adapter)
270 {
271 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
272 struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
273 struct registry_priv *regsty = adapter_to_regsty(adapter);
274
275 RTW_PRINT_SEL(sel, "[RF_PATH] ver_id.RF_TYPE:%s\n"
276 , rf_type_to_rfpath_str(rtw_chip_rftype_to_hal_rftype(adapter, 0)));
277 RTW_PRINT_SEL(sel, "[RF_PATH] HALSPEC's rf_reg_trx_path_bmp:0x%02x, rf_reg_path_avail_num:%u, max_tx_cnt:%u\n"
278 , hal_spec->rf_reg_trx_path_bmp, hal_spec->rf_reg_path_avail_num, hal_spec->max_tx_cnt);
279 RTW_PRINT_SEL(sel, "[RF_PATH] PG's trx_path_bmp:0x%02x, max_tx_cnt:%u\n"
280 , hal_data->eeprom_trx_path_bmp, hal_data->eeprom_max_tx_cnt);
281 RTW_PRINT_SEL(sel, "[RF_PATH] Registry's trx_path_bmp:0x%02x, tx_path_lmt:%u, rx_path_lmt:%u\n"
282 , regsty->trx_path_bmp, regsty->tx_path_lmt, regsty->rx_path_lmt);
283 RTW_PRINT_SEL(sel, "[RF_PATH] HALDATA's trx_path_bmp:0x%02x, max_tx_cnt:%u\n"
284 , hal_data->trx_path_bmp, hal_data->max_tx_cnt);
285 RTW_PRINT_SEL(sel, "[RF_PATH] HALDATA's rf_type:%s, NumTotalRFPath:%d\n"
286 , rf_type_to_rfpath_str(hal_data->rf_type), hal_data->NumTotalRFPath);
287 }
288
289 #ifdef CONFIG_RTL8814A
290 extern enum rf_type rtl8814a_rfpath_decision(_adapter *adapter);
291 #endif
292
rtw_hal_rfpath_init(_adapter * adapter)293 u8 rtw_hal_rfpath_init(_adapter *adapter)
294 {
295 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
296 struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
297
298 #ifdef CONFIG_RTL8814A
299 if (IS_HARDWARE_TYPE_8814A(adapter)) {
300 enum bb_path tx_bmp, rx_bmp;
301 hal_data->rf_type = rtl8814a_rfpath_decision(adapter);
302 rf_type_to_default_trx_bmp(hal_data->rf_type, &tx_bmp, &rx_bmp);
303 hal_data->trx_path_bmp = (tx_bmp << 4) | rx_bmp;
304 hal_data->NumTotalRFPath = 4;
305 hal_data->max_tx_cnt = hal_spec->max_tx_cnt;
306 hal_data->max_tx_cnt = rtw_min(hal_data->max_tx_cnt, rf_type_to_rf_tx_cnt(hal_data->rf_type));
307 } else
308 #endif
309 {
310 struct registry_priv *regsty = adapter_to_regsty(adapter);
311 u8 trx_path_bmp;
312 u8 tx_path_num;
313 u8 rx_path_num;
314 int i;
315
316 trx_path_bmp = hal_spec->rf_reg_trx_path_bmp;
317
318 if (regsty->trx_path_bmp != 0x00) {
319 /* restrict trx_path_bmp with regsty.trx_path_bmp */
320 trx_path_bmp &= regsty->trx_path_bmp;
321 if (!trx_path_bmp) {
322 RTW_ERR("%s hal_spec.rf_reg_trx_path_bmp:0x%02x, regsty->trx_path_bmp:0x%02x no intersection\n"
323 , __func__, hal_spec->rf_reg_trx_path_bmp, regsty->trx_path_bmp);
324 return _FAIL;
325 }
326 } else if (hal_data->eeprom_trx_path_bmp != 0x00) {
327 /* restrict trx_path_bmp with eeprom_trx_path_bmp */
328 trx_path_bmp &= hal_data->eeprom_trx_path_bmp;
329 if (!trx_path_bmp) {
330 RTW_ERR("%s hal_spec.rf_reg_trx_path_bmp:0x%02x, hal_data->eeprom_trx_path_bmp:0x%02x no intersection\n"
331 , __func__, hal_spec->rf_reg_trx_path_bmp, hal_data->eeprom_trx_path_bmp);
332 return _FAIL;
333 }
334 }
335
336 /* restrict trx_path_bmp with TX and RX num limit */
337 trx_path_bmp = rtw_restrict_trx_path_bmp_by_trx_num_lmt(trx_path_bmp
338 , regsty->tx_path_lmt, regsty->rx_path_lmt, &tx_path_num, &rx_path_num);
339 if (!trx_path_bmp) {
340 RTW_ERR("%s rtw_restrict_trx_path_bmp_by_trx_num_lmt(0x%02x, %u, %u) failed\n"
341 , __func__, trx_path_bmp, regsty->tx_path_lmt, regsty->rx_path_lmt);
342 return _FAIL;
343 }
344 hal_data->trx_path_bmp = trx_path_bmp;
345 hal_data->rf_type = trx_bmp_to_rf_type((trx_path_bmp & 0xF0) >> 4, trx_path_bmp & 0x0F);
346 hal_data->NumTotalRFPath = rtw_max(tx_path_num, rx_path_num);
347
348 hal_data->max_tx_cnt = hal_spec->max_tx_cnt;
349 hal_data->max_tx_cnt = rtw_min(hal_data->max_tx_cnt, tx_path_num);
350 if (hal_data->eeprom_max_tx_cnt)
351 hal_data->max_tx_cnt = rtw_min(hal_data->max_tx_cnt, hal_data->eeprom_max_tx_cnt);
352
353 if (1)
354 _dump_rf_path(RTW_DBGDUMP, adapter);
355 }
356
357 RTW_INFO("%s trx_path_bmp:0x%02x(%s), NumTotalRFPath:%u, max_tx_cnt:%u\n"
358 , __func__
359 , hal_data->trx_path_bmp
360 , rf_type_to_rfpath_str(hal_data->rf_type)
361 , hal_data->NumTotalRFPath
362 , hal_data->max_tx_cnt);
363
364 return _SUCCESS;
365 }
366
_dump_trx_nss(void * sel,_adapter * adapter)367 void _dump_trx_nss(void *sel, _adapter *adapter)
368 {
369 struct registry_priv *regpriv = &adapter->registrypriv;
370 struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
371
372 RTW_PRINT_SEL(sel, "[TRX_Nss] HALSPEC - tx_nss:%d, rx_nss:%d\n", hal_spec->tx_nss_num, hal_spec->rx_nss_num);
373 RTW_PRINT_SEL(sel, "[TRX_Nss] Registry - tx_nss:%d, rx_nss:%d\n", regpriv->tx_nss, regpriv->rx_nss);
374 RTW_PRINT_SEL(sel, "[TRX_Nss] HALDATA - tx_nss:%d, rx_nss:%d\n", GET_HAL_TX_NSS(adapter), GET_HAL_RX_NSS(adapter));
375
376 }
377 #define NSS_VALID(nss) (nss > 0)
378
rtw_hal_trxnss_init(_adapter * adapter)379 u8 rtw_hal_trxnss_init(_adapter *adapter)
380 {
381 struct registry_priv *regpriv = &adapter->registrypriv;
382 struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
383 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
384 enum rf_type rf_path = GET_HAL_RFPATH(adapter);
385
386 hal_data->tx_nss = hal_spec->tx_nss_num;
387 hal_data->rx_nss = hal_spec->rx_nss_num;
388
389 if (NSS_VALID(regpriv->tx_nss))
390 hal_data->tx_nss = rtw_min(hal_data->tx_nss, regpriv->tx_nss);
391 hal_data->tx_nss = rtw_min(hal_data->tx_nss, hal_data->max_tx_cnt);
392 if (NSS_VALID(regpriv->rx_nss))
393 hal_data->rx_nss = rtw_min(hal_data->rx_nss, regpriv->rx_nss);
394 hal_data->rx_nss = rtw_min(hal_data->rx_nss, rf_type_to_rf_rx_cnt(rf_path));
395
396 if (1)
397 _dump_trx_nss(RTW_DBGDUMP, adapter);
398
399 RTW_INFO("%s tx_nss:%u, rx_nss:%u\n", __func__
400 , hal_data->tx_nss, hal_data->rx_nss);
401
402 return _SUCCESS;
403 }
404
405 #ifdef CONFIG_RTW_SW_LED
rtw_hal_sw_led_init(_adapter * padapter)406 void rtw_hal_sw_led_init(_adapter *padapter)
407 {
408 struct led_priv *ledpriv = adapter_to_led(padapter);
409
410 if (ledpriv->bRegUseLed == _FALSE)
411 return;
412
413 if (!is_primary_adapter(padapter))
414 return;
415
416 if (padapter->hal_func.InitSwLeds) {
417 padapter->hal_func.InitSwLeds(padapter);
418 rtw_led_set_ctl_en_mask_primary(padapter);
419 rtw_led_set_iface_en(padapter, 1);
420 }
421 }
422
rtw_hal_sw_led_deinit(_adapter * padapter)423 void rtw_hal_sw_led_deinit(_adapter *padapter)
424 {
425 struct led_priv *ledpriv = adapter_to_led(padapter);
426
427 if (ledpriv->bRegUseLed == _FALSE)
428 return;
429
430 if (!is_primary_adapter(padapter))
431 return;
432
433 if (padapter->hal_func.DeInitSwLeds)
434 padapter->hal_func.DeInitSwLeds(padapter);
435 }
436 #endif
437
rtw_hal_power_on(_adapter * padapter)438 u32 rtw_hal_power_on(_adapter *padapter)
439 {
440 u32 ret = 0;
441 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
442
443 ret = padapter->hal_func.hal_power_on(padapter);
444
445 #ifdef CONFIG_BT_COEXIST
446 if ((ret == _SUCCESS) && (pHalData->EEPROMBluetoothCoexist == _TRUE))
447 rtw_btcoex_PowerOnSetting(padapter);
448 #endif
449
450 return ret;
451 }
rtw_hal_power_off(_adapter * padapter)452 void rtw_hal_power_off(_adapter *padapter)
453 {
454 struct macid_ctl_t *macid_ctl = &padapter->dvobj->macid_ctl;
455
456 _rtw_memset(macid_ctl->h2c_msr, 0, MACID_NUM_SW_LIMIT);
457 _rtw_memset(macid_ctl->op_num, 0, H2C_MSR_ROLE_MAX);
458
459 #ifdef CONFIG_LPS_1T1R
460 GET_HAL_DATA(padapter)->lps_1t1r = 0;
461 #endif
462
463 #ifdef CONFIG_BT_COEXIST
464 rtw_btcoex_PowerOffSetting(padapter);
465 #endif
466
467 padapter->hal_func.hal_power_off(padapter);
468 }
469
470
rtw_hal_init_opmode(_adapter * padapter)471 void rtw_hal_init_opmode(_adapter *padapter)
472 {
473 NDIS_802_11_NETWORK_INFRASTRUCTURE networkType = Ndis802_11InfrastructureMax;
474 struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
475 sint fw_state;
476
477 fw_state = get_fwstate(pmlmepriv);
478
479 if (fw_state & WIFI_ADHOC_STATE)
480 networkType = Ndis802_11IBSS;
481 else if (fw_state & WIFI_STATION_STATE)
482 networkType = Ndis802_11Infrastructure;
483 #ifdef CONFIG_AP_MODE
484 else if (fw_state & WIFI_AP_STATE)
485 networkType = Ndis802_11APMode;
486 #endif
487 #ifdef CONFIG_RTW_MESH
488 else if (fw_state & WIFI_MESH_STATE)
489 networkType = Ndis802_11_mesh;
490 #endif
491 else
492 return;
493
494 rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_DIRECTLY);
495 }
496
497 #ifdef CONFIG_NEW_NETDEV_HDL
rtw_hal_iface_init(_adapter * adapter)498 uint rtw_hal_iface_init(_adapter *adapter)
499 {
500 uint status = _SUCCESS;
501
502 rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter_mac_addr(adapter));
503 #ifdef RTW_HALMAC
504 rtw_hal_hw_port_enable(adapter);
505 #endif
506 rtw_sec_restore_wep_key(adapter);
507 rtw_hal_init_opmode(adapter);
508 rtw_hal_start_thread(adapter);
509 return status;
510 }
rtw_hal_init(_adapter * padapter)511 uint rtw_hal_init(_adapter *padapter)
512 {
513 uint status = _SUCCESS;
514 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
515
516 halrf_set_rfsupportability(adapter_to_phydm(padapter));
517
518 status = padapter->hal_func.hal_init(padapter);
519
520 if(pHalData ->phydm_init_result) {
521
522 status = _FAIL;
523 RTW_ERR("%s phydm init fail reason=%u \n",
524 __func__,
525 pHalData ->phydm_init_result);
526 }
527
528 if (status == _SUCCESS) {
529 rtw_set_hw_init_completed(padapter, _TRUE);
530 if (padapter->registrypriv.notch_filter == 1)
531 rtw_hal_notch_filter(padapter, 1);
532 rtw_led_control(padapter, LED_CTL_POWER_ON);
533 init_hw_mlme_ext(padapter);
534 #ifdef CONFIG_RF_POWER_TRIM
535 rtw_bb_rf_gain_offset(padapter);
536 #endif /*CONFIG_RF_POWER_TRIM*/
537 GET_PRIMARY_ADAPTER(padapter)->bup = _TRUE; /*temporary*/
538 #ifdef CONFIG_MI_WITH_MBSSID_CAM
539 rtw_mi_set_mbid_cam(padapter);
540 #endif
541 #ifdef CONFIG_SUPPORT_MULTI_BCN
542 rtw_ap_multi_bcn_cfg(padapter);
543 #endif
544 #if (RTL8822B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)
545 #ifdef CONFIG_DYNAMIC_SOML
546 rtw_dyn_soml_config(padapter);
547 #endif
548 #endif
549 #ifdef CONFIG_TDMADIG
550 rtw_phydm_tdmadig(padapter, TDMADIG_INIT);
551 #endif/*CONFIG_TDMADIG*/
552 rtw_phydm_dyn_rrsr_en(padapter,padapter->registrypriv.en_dyn_rrsr);
553 #ifdef RTW_HALMAC
554 RTW_INFO("%s: padapter->registrypriv.set_rrsr_value=0x%x\n", __func__,padapter->registrypriv.set_rrsr_value);
555 if(padapter->registrypriv.set_rrsr_value != 0xFFFFFFFF)
556 rtw_phydm_set_rrsr(padapter, padapter->registrypriv.set_rrsr_value, TRUE);
557 #endif
558 } else {
559 rtw_set_hw_init_completed(padapter, _FALSE);
560 RTW_ERR("%s: hal_init fail\n", __func__);
561 }
562 return status;
563 }
564 #else
rtw_hal_init(_adapter * padapter)565 uint rtw_hal_init(_adapter *padapter)
566 {
567 uint status = _SUCCESS;
568 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
569 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
570 int i;
571
572 halrf_set_rfsupportability(adapter_to_phydm(padapter));
573
574 status = padapter->hal_func.hal_init(padapter);
575
576 if(pHalData ->phydm_init_result) {
577
578 status = _FAIL;
579 RTW_ERR("%s phydm init fail reason=%u \n",
580 __func__,
581 pHalData->phydm_init_result);
582 }
583
584 if (status == _SUCCESS) {
585 rtw_set_hw_init_completed(padapter, _TRUE);
586 rtw_mi_set_mac_addr(padapter);/*set mac addr of all ifaces*/
587 #ifdef RTW_HALMAC
588 rtw_restore_hw_port_cfg(padapter);
589 #endif
590 if (padapter->registrypriv.notch_filter == 1)
591 rtw_hal_notch_filter(padapter, 1);
592
593 for (i = 0; i < dvobj->iface_nums; i++)
594 rtw_sec_restore_wep_key(dvobj->padapters[i]);
595
596 rtw_led_control(padapter, LED_CTL_POWER_ON);
597
598 init_hw_mlme_ext(padapter);
599
600 rtw_hal_init_opmode(padapter);
601
602 #ifdef CONFIG_RF_POWER_TRIM
603 rtw_bb_rf_gain_offset(padapter);
604 #endif /*CONFIG_RF_POWER_TRIM*/
605
606 #ifdef CONFIG_SUPPORT_MULTI_BCN
607 rtw_ap_multi_bcn_cfg(padapter);
608 #endif
609
610 #if (RTL8822B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)
611 #ifdef CONFIG_DYNAMIC_SOML
612 rtw_dyn_soml_config(padapter);
613 #endif
614 #endif
615 #ifdef CONFIG_TDMADIG
616 rtw_phydm_tdmadig(padapter, TDMADIG_INIT);
617 #endif/*CONFIG_TDMADIG*/
618
619 rtw_phydm_dyn_rrsr_en(padapter,padapter->registrypriv.en_dyn_rrsr);
620 #ifdef RTW_HALMAC
621 RTW_INFO("%s: padapter->registrypriv.set_rrsr_value=0x%x\n", __func__,padapter->registrypriv.set_rrsr_value);
622 if(padapter->registrypriv.set_rrsr_value != 0xFFFFFFFF)
623 rtw_phydm_set_rrsr(padapter, padapter->registrypriv.set_rrsr_value, TRUE);
624 #endif
625
626 } else {
627 rtw_set_hw_init_completed(padapter, _FALSE);
628 RTW_ERR("%s: fail\n", __func__);
629 }
630
631
632 return status;
633
634 }
635 #endif
636
rtw_hal_deinit(_adapter * padapter)637 uint rtw_hal_deinit(_adapter *padapter)
638 {
639 uint status = _SUCCESS;
640
641 status = padapter->hal_func.hal_deinit(padapter);
642
643 if (status == _SUCCESS) {
644 rtw_led_control(padapter, LED_CTL_POWER_OFF);
645 rtw_set_hw_init_completed(padapter, _FALSE);
646 } else
647 RTW_INFO("\n rtw_hal_deinit: hal_init fail\n");
648
649
650 return status;
651 }
652
rtw_hal_set_hwreg(_adapter * padapter,u8 variable,u8 * val)653 u8 rtw_hal_set_hwreg(_adapter *padapter, u8 variable, u8 *val)
654 {
655 return padapter->hal_func.set_hw_reg_handler(padapter, variable, val);
656 }
657
rtw_hal_get_hwreg(_adapter * padapter,u8 variable,u8 * val)658 void rtw_hal_get_hwreg(_adapter *padapter, u8 variable, u8 *val)
659 {
660 padapter->hal_func.GetHwRegHandler(padapter, variable, val);
661 }
662
rtw_hal_set_def_var(_adapter * padapter,HAL_DEF_VARIABLE eVariable,void * pValue)663 u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue)
664 {
665 return padapter->hal_func.SetHalDefVarHandler(padapter, eVariable, pValue);
666 }
rtw_hal_get_def_var(_adapter * padapter,HAL_DEF_VARIABLE eVariable,void * pValue)667 u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue)
668 {
669 return padapter->hal_func.get_hal_def_var_handler(padapter, eVariable, pValue);
670 }
671
rtw_hal_set_odm_var(_adapter * padapter,HAL_ODM_VARIABLE eVariable,void * pValue1,BOOLEAN bSet)672 void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, BOOLEAN bSet)
673 {
674 padapter->hal_func.SetHalODMVarHandler(padapter, eVariable, pValue1, bSet);
675 }
rtw_hal_get_odm_var(_adapter * padapter,HAL_ODM_VARIABLE eVariable,void * pValue1,void * pValue2)676 void rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2)
677 {
678 padapter->hal_func.GetHalODMVarHandler(padapter, eVariable, pValue1, pValue2);
679 }
680
681 /* FOR SDIO & PCIE */
rtw_hal_enable_interrupt(_adapter * padapter)682 void rtw_hal_enable_interrupt(_adapter *padapter)
683 {
684 #if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
685 padapter->hal_func.enable_interrupt(padapter);
686 #endif /* #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
687 }
688
689 /* FOR SDIO & PCIE */
rtw_hal_disable_interrupt(_adapter * padapter)690 void rtw_hal_disable_interrupt(_adapter *padapter)
691 {
692 #if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
693 padapter->hal_func.disable_interrupt(padapter);
694 #endif /* #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
695 }
696
697
rtw_hal_check_ips_status(_adapter * padapter)698 u8 rtw_hal_check_ips_status(_adapter *padapter)
699 {
700 u8 val = _FALSE;
701 if (padapter->hal_func.check_ips_status)
702 val = padapter->hal_func.check_ips_status(padapter);
703 else
704 RTW_INFO("%s: hal_func.check_ips_status is NULL!\n", __FUNCTION__);
705
706 return val;
707 }
708
rtw_hal_fw_dl(_adapter * padapter,u8 wowlan)709 s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan)
710 {
711 s32 ret;
712
713 ret = padapter->hal_func.fw_dl(padapter, wowlan);
714
715 #ifdef CONFIG_LPS_1T1R
716 GET_HAL_DATA(padapter)->lps_1t1r = 0;
717 #endif
718
719 return ret;
720 }
721
722 #ifdef RTW_HALMAC
rtw_hal_fw_mem_dl(_adapter * padapter,enum fw_mem mem)723 s32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem)
724 {
725 systime dlfw_start_time = rtw_get_current_time();
726 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
727 struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
728 s32 rst = _FALSE;
729
730 rst = padapter->hal_func.fw_mem_dl(padapter, mem);
731 RTW_INFO("%s in %dms\n", __func__, rtw_get_passing_time_ms(dlfw_start_time));
732
733 if (rst == _FALSE)
734 pdbgpriv->dbg_fw_mem_dl_error_cnt++;
735 if (1)
736 RTW_INFO("%s dbg_fw_mem_dl_error_cnt:%d\n", __func__, pdbgpriv->dbg_fw_mem_dl_error_cnt);
737 return rst;
738 }
739 #endif
740
741 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
rtw_hal_clear_interrupt(_adapter * padapter)742 void rtw_hal_clear_interrupt(_adapter *padapter)
743 {
744 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
745 padapter->hal_func.clear_interrupt(padapter);
746 #endif
747 }
748 #endif
749
750 #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
rtw_hal_inirp_init(_adapter * padapter)751 u32 rtw_hal_inirp_init(_adapter *padapter)
752 {
753 if (is_primary_adapter(padapter))
754 return padapter->hal_func.inirp_init(padapter);
755 return _SUCCESS;
756 }
rtw_hal_inirp_deinit(_adapter * padapter)757 u32 rtw_hal_inirp_deinit(_adapter *padapter)
758 {
759
760 if (is_primary_adapter(padapter))
761 return padapter->hal_func.inirp_deinit(padapter);
762
763 return _SUCCESS;
764 }
765 #endif /* #if defined(CONFIG_USB_HCI) || defined (CONFIG_PCI_HCI) */
766
767 #if defined(CONFIG_PCI_HCI)
rtw_hal_irp_reset(_adapter * padapter)768 void rtw_hal_irp_reset(_adapter *padapter)
769 {
770 padapter->hal_func.irp_reset(GET_PRIMARY_ADAPTER(padapter));
771 }
772
rtw_hal_pci_dbi_write(_adapter * padapter,u16 addr,u8 data)773 void rtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data)
774 {
775 u16 cmd[2];
776
777 cmd[0] = addr;
778 cmd[1] = data;
779
780 padapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_DBI, (u8 *) cmd);
781 }
782
rtw_hal_pci_dbi_read(_adapter * padapter,u16 addr)783 u8 rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr)
784 {
785 padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_DBI, (u8 *)(&addr));
786
787 return (u8)addr;
788 }
789
rtw_hal_pci_mdio_write(_adapter * padapter,u8 addr,u16 data)790 void rtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data)
791 {
792 u16 cmd[2];
793
794 cmd[0] = (u16)addr;
795 cmd[1] = data;
796
797 padapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_MDIO, (u8 *) cmd);
798 }
799
rtw_hal_pci_mdio_read(_adapter * padapter,u8 addr)800 u16 rtw_hal_pci_mdio_read(_adapter *padapter, u8 addr)
801 {
802 padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_MDIO, &addr);
803
804 return (u8)addr;
805 }
806
rtw_hal_pci_l1off_nic_support(_adapter * padapter)807 u8 rtw_hal_pci_l1off_nic_support(_adapter *padapter)
808 {
809 u8 l1off;
810
811 padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_NIC_SUPPORT, &l1off);
812 return l1off;
813 }
814
rtw_hal_pci_l1off_capability(_adapter * padapter)815 u8 rtw_hal_pci_l1off_capability(_adapter *padapter)
816 {
817 u8 l1off;
818
819 padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_CAPABILITY, &l1off);
820 return l1off;
821 }
822
823
824 #endif /* #if defined(CONFIG_PCI_HCI) */
825
826 /* for USB Auto-suspend */
rtw_hal_intf_ps_func(_adapter * padapter,HAL_INTF_PS_FUNC efunc_id,u8 * val)827 u8 rtw_hal_intf_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val)
828 {
829 if (padapter->hal_func.interface_ps_func)
830 return padapter->hal_func.interface_ps_func(padapter, efunc_id, val);
831 return _FAIL;
832 }
833
rtw_hal_xmitframe_enqueue(_adapter * padapter,struct xmit_frame * pxmitframe)834 s32 rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
835 {
836 return padapter->hal_func.hal_xmitframe_enqueue(padapter, pxmitframe);
837 }
838
rtw_hal_xmit(_adapter * padapter,struct xmit_frame * pxmitframe)839 s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe)
840 {
841 return padapter->hal_func.hal_xmit(padapter, pxmitframe);
842 }
843
844 /*
845 * [IMPORTANT] This function would be run in interrupt context.
846 */
rtw_hal_mgnt_xmit(_adapter * padapter,struct xmit_frame * pmgntframe)847 s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe)
848 {
849 s32 ret = _FAIL;
850
851 update_mgntframe_attrib_addr(padapter, pmgntframe);
852
853 #if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
854 if ((!MLME_IS_MESH(padapter) && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE)
855 #ifdef CONFIG_RTW_MESH
856 || (MLME_IS_MESH(padapter) && padapter->mesh_info.mesh_auth_id)
857 #endif
858 )
859 rtw_mgmt_xmitframe_coalesce(padapter, pmgntframe->pkt, pmgntframe);
860 #endif
861
862 ret = padapter->hal_func.mgnt_xmit(padapter, pmgntframe);
863 return ret;
864 }
865
rtw_hal_init_xmit_priv(_adapter * padapter)866 s32 rtw_hal_init_xmit_priv(_adapter *padapter)
867 {
868 return padapter->hal_func.init_xmit_priv(padapter);
869 }
rtw_hal_free_xmit_priv(_adapter * padapter)870 void rtw_hal_free_xmit_priv(_adapter *padapter)
871 {
872 padapter->hal_func.free_xmit_priv(padapter);
873 }
874
rtw_hal_init_recv_priv(_adapter * padapter)875 s32 rtw_hal_init_recv_priv(_adapter *padapter)
876 {
877 return padapter->hal_func.init_recv_priv(padapter);
878 }
rtw_hal_free_recv_priv(_adapter * padapter)879 void rtw_hal_free_recv_priv(_adapter *padapter)
880 {
881 padapter->hal_func.free_recv_priv(padapter);
882 }
883
rtw_sta_ra_registed(_adapter * padapter,struct sta_info * psta)884 void rtw_sta_ra_registed(_adapter *padapter, struct sta_info *psta)
885 {
886 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
887
888 if (psta == NULL) {
889 RTW_ERR(FUNC_ADPT_FMT" sta is NULL\n", FUNC_ADPT_ARG(padapter));
890 rtw_warn_on(1);
891 return;
892 }
893
894 #ifdef CONFIG_AP_MODE
895 if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
896 if (psta->cmn.aid > padapter->stapriv.max_aid) {
897 RTW_ERR("station aid %d exceed the max number\n", psta->cmn.aid);
898 rtw_warn_on(1);
899 return;
900 }
901 rtw_ap_update_sta_ra_info(padapter, psta);
902 }
903 #endif
904
905 psta->cmn.ra_info.ra_bw_mode = rtw_get_tx_bw_mode(padapter, psta);
906 /*set correct initial date rate for each mac_id */
907 hal_data->INIDATA_RATE[psta->cmn.mac_id] = psta->init_rate;
908
909 rtw_phydm_ra_registed(padapter, psta);
910 }
911
rtw_hal_update_ra_mask(struct sta_info * psta)912 void rtw_hal_update_ra_mask(struct sta_info *psta)
913 {
914 _adapter *padapter;
915
916 if (!psta)
917 return;
918
919 padapter = psta->padapter;
920 rtw_sta_ra_registed(padapter, psta);
921 }
922
923 /* Start specifical interface thread */
rtw_hal_start_thread(_adapter * padapter)924 void rtw_hal_start_thread(_adapter *padapter)
925 {
926 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
927 #ifndef CONFIG_SDIO_TX_TASKLET
928 padapter->hal_func.run_thread(padapter);
929 #endif
930 #endif
931 }
932 /* Start specifical interface thread */
rtw_hal_stop_thread(_adapter * padapter)933 void rtw_hal_stop_thread(_adapter *padapter)
934 {
935 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
936 #ifndef CONFIG_SDIO_TX_TASKLET
937
938 padapter->hal_func.cancel_thread(padapter);
939
940 #endif
941 #endif
942 }
943
rtw_hal_read_bbreg(_adapter * padapter,u32 RegAddr,u32 BitMask)944 u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask)
945 {
946 u32 data = 0;
947 if (padapter->hal_func.read_bbreg)
948 data = padapter->hal_func.read_bbreg(padapter, RegAddr, BitMask);
949 return data;
950 }
rtw_hal_write_bbreg(_adapter * padapter,u32 RegAddr,u32 BitMask,u32 Data)951 void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
952 {
953 if (padapter->hal_func.write_bbreg)
954 padapter->hal_func.write_bbreg(padapter, RegAddr, BitMask, Data);
955 }
956
rtw_hal_read_rfreg(_adapter * padapter,enum rf_path eRFPath,u32 RegAddr,u32 BitMask)957 u32 rtw_hal_read_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask)
958 {
959 u32 data = 0;
960
961 if (padapter->hal_func.read_rfreg) {
962 data = padapter->hal_func.read_rfreg(padapter, eRFPath, RegAddr, BitMask);
963
964 #ifdef DBG_IO
965 if (match_rf_read_sniff_ranges(padapter, eRFPath, RegAddr, BitMask)) {
966 RTW_INFO("DBG_IO rtw_hal_read_rfreg(%u, 0x%04x, 0x%08x) read:0x%08x(0x%08x)\n"
967 , eRFPath, RegAddr, BitMask, (data << PHY_CalculateBitShift(BitMask)), data);
968 }
969 #endif
970 }
971
972 return data;
973 }
974
rtw_hal_write_rfreg(_adapter * padapter,enum rf_path eRFPath,u32 RegAddr,u32 BitMask,u32 Data)975 void rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
976 {
977 if (padapter->hal_func.write_rfreg) {
978
979 #ifdef DBG_IO
980 if (match_rf_write_sniff_ranges(padapter, eRFPath, RegAddr, BitMask)) {
981 RTW_INFO("DBG_IO rtw_hal_write_rfreg(%u, 0x%04x, 0x%08x) write:0x%08x(0x%08x)\n"
982 , eRFPath, RegAddr, BitMask, (Data << PHY_CalculateBitShift(BitMask)), Data);
983 }
984 #endif
985
986 padapter->hal_func.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data);
987
988 #ifdef CONFIG_PCI_HCI
989 if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(padapter)) /*For N-Series IC, suggest by Jenyu*/
990 rtw_udelay_os(2);
991 #endif
992 }
993 }
994
995 #ifdef CONFIG_SYSON_INDIRECT_ACCESS
rtw_hal_read_syson_reg(PADAPTER padapter,u32 RegAddr,u32 BitMask)996 u32 rtw_hal_read_syson_reg(PADAPTER padapter, u32 RegAddr, u32 BitMask)
997 {
998 u32 data = 0;
999 if (padapter->hal_func.read_syson_reg)
1000 data = padapter->hal_func.read_syson_reg(padapter, RegAddr, BitMask);
1001
1002 return data;
1003 }
1004
rtw_hal_write_syson_reg(_adapter * padapter,u32 RegAddr,u32 BitMask,u32 Data)1005 void rtw_hal_write_syson_reg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
1006 {
1007 if (padapter->hal_func.write_syson_reg)
1008 padapter->hal_func.write_syson_reg(padapter, RegAddr, BitMask, Data);
1009 }
1010 #endif
1011
1012 #if defined(CONFIG_PCI_HCI)
rtw_hal_interrupt_handler(_adapter * padapter)1013 s32 rtw_hal_interrupt_handler(_adapter *padapter)
1014 {
1015 s32 ret = _FAIL;
1016 ret = padapter->hal_func.interrupt_handler(padapter);
1017 return ret;
1018 }
1019
rtw_hal_unmap_beacon_icf(_adapter * padapter)1020 void rtw_hal_unmap_beacon_icf(_adapter *padapter)
1021 {
1022 padapter->hal_func.unmap_beacon_icf(padapter);
1023 }
1024 #endif
1025 #if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
rtw_hal_interrupt_handler(_adapter * padapter,u16 pkt_len,u8 * pbuf)1026 void rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf)
1027 {
1028 padapter->hal_func.interrupt_handler(padapter, pkt_len, pbuf);
1029 }
1030 #endif
1031
rtw_hal_set_chnl_bw(_adapter * padapter,u8 channel,enum channel_width Bandwidth,u8 Offset40,u8 Offset80)1032 void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80)
1033 {
1034 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1035 /*u8 cch_160 = Bandwidth == CHANNEL_WIDTH_160 ? channel : 0;*/
1036 u8 cch_80 = Bandwidth == CHANNEL_WIDTH_80 ? channel : 0;
1037 u8 cch_40 = Bandwidth == CHANNEL_WIDTH_40 ? channel : 0;
1038 u8 cch_20 = Bandwidth == CHANNEL_WIDTH_20 ? channel : 0;
1039
1040 if (rtw_phydm_is_iqk_in_progress(padapter))
1041 RTW_ERR("%s, %d, IQK may race condition\n", __func__, __LINE__);
1042
1043 #ifdef CONFIG_MP_INCLUDED
1044 /* MP mode channel don't use secondary channel */
1045 if (rtw_mp_mode_check(padapter) == _FALSE)
1046 #endif
1047 {
1048 #if 0
1049 if (cch_160 != 0)
1050 cch_80 = rtw_get_scch_by_cch_offset(cch_160, CHANNEL_WIDTH_160, Offset80);
1051 #endif
1052 if (cch_80 != 0)
1053 cch_40 = rtw_get_scch_by_cch_offset(cch_80, CHANNEL_WIDTH_80, Offset80);
1054 if (cch_40 != 0)
1055 cch_20 = rtw_get_scch_by_cch_offset(cch_40, CHANNEL_WIDTH_40, Offset40);
1056 }
1057
1058 pHalData->cch_80 = cch_80;
1059 pHalData->cch_40 = cch_40;
1060 pHalData->cch_20 = cch_20;
1061
1062 if (0)
1063 RTW_INFO("%s cch:%u, %s, offset40:%u, offset80:%u (%u, %u, %u)\n", __func__
1064 , channel, ch_width_str(Bandwidth), Offset40, Offset80
1065 , pHalData->cch_80, pHalData->cch_40, pHalData->cch_20);
1066
1067 padapter->hal_func.set_chnl_bw_handler(padapter, channel, Bandwidth, Offset40, Offset80);
1068 }
1069
rtw_hal_dm_watchdog(_adapter * padapter)1070 void rtw_hal_dm_watchdog(_adapter *padapter)
1071 {
1072
1073 rtw_hal_turbo_edca(padapter);
1074 padapter->hal_func.hal_dm_watchdog(padapter);
1075 }
1076
1077 #ifdef CONFIG_LPS_LCLK_WD_TIMER
rtw_hal_dm_watchdog_in_lps(_adapter * padapter)1078 void rtw_hal_dm_watchdog_in_lps(_adapter *padapter)
1079 {
1080 #if defined(CONFIG_CONCURRENT_MODE)
1081 #ifndef CONFIG_FW_MULTI_PORT_SUPPORT
1082 if (padapter->hw_port != HW_PORT0)
1083 return;
1084 #endif
1085 #endif
1086
1087 if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE)
1088 rtw_phydm_watchdog_in_lps_lclk(padapter);/* this function caller is in interrupt context */
1089 }
1090 #endif /*CONFIG_LPS_LCLK_WD_TIMER*/
1091
rtw_hal_bcn_related_reg_setting(_adapter * padapter)1092 void rtw_hal_bcn_related_reg_setting(_adapter *padapter)
1093 {
1094 padapter->hal_func.SetBeaconRelatedRegistersHandler(padapter);
1095 }
1096
1097 #ifdef CONFIG_HOSTAPD_MLME
rtw_hal_hostap_mgnt_xmit_entry(_adapter * padapter,_pkt * pkt)1098 s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
1099 {
1100 if (padapter->hal_func.hostap_mgnt_xmit_entry)
1101 return padapter->hal_func.hostap_mgnt_xmit_entry(padapter, pkt);
1102 return _FAIL;
1103 }
1104 #endif /* CONFIG_HOSTAPD_MLME */
1105
1106 #ifdef DBG_CONFIG_ERROR_DETECT
rtw_hal_sreset_init(_adapter * padapter)1107 void rtw_hal_sreset_init(_adapter *padapter)
1108 {
1109 padapter->hal_func.sreset_init_value(padapter);
1110 }
rtw_hal_sreset_reset(_adapter * padapter)1111 void rtw_hal_sreset_reset(_adapter *padapter)
1112 {
1113 padapter = GET_PRIMARY_ADAPTER(padapter);
1114 padapter->hal_func.silentreset(padapter);
1115 }
1116
rtw_hal_sreset_reset_value(_adapter * padapter)1117 void rtw_hal_sreset_reset_value(_adapter *padapter)
1118 {
1119 padapter->hal_func.sreset_reset_value(padapter);
1120 }
1121
rtw_hal_sreset_xmit_status_check(_adapter * padapter)1122 void rtw_hal_sreset_xmit_status_check(_adapter *padapter)
1123 {
1124 padapter->hal_func.sreset_xmit_status_check(padapter);
1125 }
rtw_hal_sreset_linked_status_check(_adapter * padapter)1126 void rtw_hal_sreset_linked_status_check(_adapter *padapter)
1127 {
1128 padapter->hal_func.sreset_linked_status_check(padapter);
1129 }
rtw_hal_sreset_get_wifi_status(_adapter * padapter)1130 u8 rtw_hal_sreset_get_wifi_status(_adapter *padapter)
1131 {
1132 return padapter->hal_func.sreset_get_wifi_status(padapter);
1133 }
1134
rtw_hal_sreset_inprogress(_adapter * padapter)1135 bool rtw_hal_sreset_inprogress(_adapter *padapter)
1136 {
1137 padapter = GET_PRIMARY_ADAPTER(padapter);
1138 return padapter->hal_func.sreset_inprogress(padapter);
1139 }
1140 #endif /* DBG_CONFIG_ERROR_DETECT */
1141
1142 #ifdef CONFIG_IOL
rtw_hal_iol_cmd(ADAPTER * adapter,struct xmit_frame * xmit_frame,u32 max_waiting_ms,u32 bndy_cnt)1143 int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_waiting_ms, u32 bndy_cnt)
1144 {
1145 if (adapter->hal_func.IOL_exec_cmds_sync)
1146 return adapter->hal_func.IOL_exec_cmds_sync(adapter, xmit_frame, max_waiting_ms, bndy_cnt);
1147 return _FAIL;
1148 }
1149 #endif
1150
1151 #ifdef CONFIG_XMIT_THREAD_MODE
rtw_hal_xmit_thread_handler(_adapter * padapter)1152 s32 rtw_hal_xmit_thread_handler(_adapter *padapter)
1153 {
1154 return padapter->hal_func.xmit_thread_handler(padapter);
1155 }
1156 #endif
1157
1158 #ifdef CONFIG_RECV_THREAD_MODE
rtw_hal_recv_hdl(_adapter * adapter)1159 s32 rtw_hal_recv_hdl(_adapter *adapter)
1160 {
1161 return adapter->hal_func.recv_hdl(adapter);
1162 }
1163 #endif
1164
rtw_hal_notch_filter(_adapter * adapter,bool enable)1165 void rtw_hal_notch_filter(_adapter *adapter, bool enable)
1166 {
1167 if (adapter->hal_func.hal_notch_filter)
1168 adapter->hal_func.hal_notch_filter(adapter, enable);
1169 }
1170
1171 #ifdef CONFIG_FW_C2H_REG
rtw_hal_c2h_valid(_adapter * adapter,u8 * buf)1172 inline bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf)
1173 {
1174 HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
1175 bool ret = _FAIL;
1176
1177 ret = C2H_ID_88XX(buf) || C2H_PLEN_88XX(buf);
1178
1179 return ret;
1180 }
1181
rtw_hal_c2h_evt_read(_adapter * adapter,u8 * buf)1182 inline s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf)
1183 {
1184 HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
1185 s32 ret = _FAIL;
1186
1187 ret = c2h_evt_read_88xx(adapter, buf);
1188
1189 return ret;
1190 }
1191
rtw_hal_c2h_reg_hdr_parse(_adapter * adapter,u8 * buf,u8 * id,u8 * seq,u8 * plen,u8 ** payload)1192 bool rtw_hal_c2h_reg_hdr_parse(_adapter *adapter, u8 *buf, u8 *id, u8 *seq, u8 *plen, u8 **payload)
1193 {
1194 HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
1195 bool ret = _FAIL;
1196
1197 *id = C2H_ID_88XX(buf);
1198 *seq = C2H_SEQ_88XX(buf);
1199 *plen = C2H_PLEN_88XX(buf);
1200 *payload = C2H_PAYLOAD_88XX(buf);
1201 ret = _SUCCESS;
1202
1203 return ret;
1204 }
1205 #endif /* CONFIG_FW_C2H_REG */
1206
1207 #ifdef CONFIG_FW_C2H_PKT
rtw_hal_c2h_pkt_hdr_parse(_adapter * adapter,u8 * buf,u16 len,u8 * id,u8 * seq,u8 * plen,u8 ** payload)1208 bool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 *seq, u8 *plen, u8 **payload)
1209 {
1210 HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
1211 bool ret = _FAIL;
1212
1213 if (!buf || len > 256 || len < 3)
1214 goto exit;
1215
1216 *id = C2H_ID_88XX(buf);
1217 *seq = C2H_SEQ_88XX(buf);
1218 *plen = len - 2;
1219 *payload = C2H_PAYLOAD_88XX(buf);
1220 ret = _SUCCESS;
1221
1222 exit:
1223 return ret;
1224 }
1225 #endif /* CONFIG_FW_C2H_PKT */
1226
1227 #if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723B)
1228 #include <rtw_bt_mp.h> /* for MPTBT_FwC2hBtMpCtrl */
1229 #endif
c2h_handler(_adapter * adapter,u8 id,u8 seq,u8 plen,u8 * payload)1230 s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
1231 {
1232 u8 sub_id = 0;
1233 s32 ret = _SUCCESS;
1234
1235 switch (id) {
1236 case C2H_FW_SCAN_COMPLETE:
1237 RTW_INFO("[C2H], FW Scan Complete\n");
1238 break;
1239
1240 #ifdef CONFIG_BT_COEXIST
1241 case C2H_BT_INFO:
1242 rtw_btcoex_BtInfoNotify(adapter, plen, payload);
1243 break;
1244 case C2H_BT_MP_INFO:
1245 #if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723B)
1246 MPTBT_FwC2hBtMpCtrl(adapter, payload, plen);
1247 #endif
1248 rtw_btcoex_BtMpRptNotify(adapter, plen, payload);
1249 break;
1250 case C2H_MAILBOX_STATUS:
1251 RTW_DBG_DUMP("C2H_MAILBOX_STATUS: ", payload, plen);
1252 break;
1253 case C2H_WLAN_INFO:
1254 rtw_btcoex_WlFwDbgInfoNotify(adapter, payload, plen);
1255 break;
1256 #endif /* CONFIG_BT_COEXIST */
1257
1258 case C2H_IQK_FINISH:
1259 c2h_iqk_offload(adapter, payload, plen);
1260 break;
1261
1262 #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
1263 case C2H_FW_CHNL_SWITCH_COMPLETE:
1264 rtw_tdls_chsw_oper_done(adapter);
1265 break;
1266 case C2H_BCN_EARLY_RPT:
1267 rtw_tdls_ch_sw_back_to_base_chnl(adapter);
1268 break;
1269 #endif
1270
1271 #ifdef CONFIG_MCC_MODE
1272 case C2H_MCC:
1273 rtw_hal_mcc_c2h_handler(adapter, plen, payload);
1274 break;
1275 #endif
1276
1277 #ifdef CONFIG_RTW_MAC_HIDDEN_RPT
1278 case C2H_MAC_HIDDEN_RPT:
1279 c2h_mac_hidden_rpt_hdl(adapter, payload, plen);
1280 break;
1281 case C2H_MAC_HIDDEN_RPT_2:
1282 c2h_mac_hidden_rpt_2_hdl(adapter, payload, plen);
1283 break;
1284 #endif
1285
1286 case C2H_DEFEATURE_DBG:
1287 c2h_defeature_dbg_hdl(adapter, payload, plen);
1288 break;
1289
1290 #ifdef CONFIG_RTW_CUSTOMER_STR
1291 case C2H_CUSTOMER_STR_RPT:
1292 c2h_customer_str_rpt_hdl(adapter, payload, plen);
1293 break;
1294 case C2H_CUSTOMER_STR_RPT_2:
1295 c2h_customer_str_rpt_2_hdl(adapter, payload, plen);
1296 break;
1297 #endif
1298 #ifdef RTW_PER_CMD_SUPPORT_FW
1299 case C2H_PER_RATE_RPT:
1300 c2h_per_rate_rpt_hdl(adapter, payload, plen);
1301 break;
1302 #endif
1303 #ifdef CONFIG_LPS_ACK
1304 case C2H_LPS_STATUS_RPT:
1305 c2h_lps_status_rpt(adapter, payload, plen);
1306 break;
1307 #endif
1308 #ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
1309 case C2H_SET_TXPWR_FINISH:
1310 c2h_txpwr_idx_offload_done(adapter, payload, plen);
1311 break;
1312 #endif
1313 case C2H_EXTEND:
1314 sub_id = payload[0];
1315 /* no handle, goto default */
1316 /* fall through */
1317
1318 default:
1319 if (phydm_c2H_content_parsing(adapter_to_phydm(adapter), id, plen, payload) != TRUE)
1320 ret = _FAIL;
1321 break;
1322 }
1323
1324 if (ret != _SUCCESS) {
1325 if (id == C2H_EXTEND)
1326 RTW_WARN("%s: unknown C2H(0x%02x, 0x%02x)\n", __func__, id, sub_id);
1327 else
1328 RTW_WARN("%s: unknown C2H(0x%02x)\n", __func__, id);
1329 }
1330
1331 return ret;
1332 }
1333
1334 #ifndef RTW_HALMAC
rtw_hal_c2h_handler(_adapter * adapter,u8 id,u8 seq,u8 plen,u8 * payload)1335 s32 rtw_hal_c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
1336 {
1337 s32 ret = _FAIL;
1338
1339 ret = adapter->hal_func.c2h_handler(adapter, id, seq, plen, payload);
1340 if (ret != _SUCCESS)
1341 ret = c2h_handler(adapter, id, seq, plen, payload);
1342
1343 return ret;
1344 }
1345
rtw_hal_c2h_id_handle_directly(_adapter * adapter,u8 id,u8 seq,u8 plen,u8 * payload)1346 s32 rtw_hal_c2h_id_handle_directly(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
1347 {
1348 switch (id) {
1349 case C2H_CCX_TX_RPT:
1350 case C2H_BT_MP_INFO:
1351 case C2H_FW_CHNL_SWITCH_COMPLETE:
1352 case C2H_IQK_FINISH:
1353 case C2H_MCC:
1354 case C2H_BCN_EARLY_RPT:
1355 case C2H_AP_REQ_TXRPT:
1356 case C2H_SPC_STAT:
1357 case C2H_SET_TXPWR_FINISH:
1358 return _TRUE;
1359 default:
1360 return _FALSE;
1361 }
1362 }
1363 #endif /* !RTW_HALMAC */
1364
rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter)1365 s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter)
1366 {
1367 return GET_HAL_DATA(padapter)->bDisableSWChannelPlan;
1368 }
1369
1370 #ifdef CONFIG_PROTSEL_MACSLEEP
_rtw_hal_macid_sleep(_adapter * adapter,u8 macid,u8 sleep)1371 static s32 _rtw_hal_macid_sleep(_adapter *adapter, u8 macid, u8 sleep)
1372 {
1373 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1374 u16 reg_sleep_info = macid_ctl->reg_sleep_info;
1375 u16 reg_sleep_ctrl = macid_ctl->reg_sleep_ctrl;
1376 const u32 sel_mask_sel = BIT(0) | BIT(1) | BIT(2);
1377 u8 bit_shift;
1378 u32 val32;
1379 s32 ret = _FAIL;
1380
1381 if (macid >= macid_ctl->num) {
1382 RTW_ERR(ADPT_FMT" %s invalid macid(%u)\n"
1383 , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup" , macid);
1384 goto exit;
1385 }
1386
1387 if (macid < 32) {
1388 bit_shift = macid;
1389 #if (MACID_NUM_SW_LIMIT > 32)
1390 } else if (macid < 64) {
1391 bit_shift = macid - 32;
1392 #endif
1393 #if (MACID_NUM_SW_LIMIT > 64)
1394 } else if (macid < 96) {
1395 bit_shift = macid - 64;
1396 #endif
1397 #if (MACID_NUM_SW_LIMIT > 96)
1398 } else if (macid < 128) {
1399 bit_shift = macid - 96;
1400 #endif
1401 } else {
1402 rtw_warn_on(1);
1403 goto exit;
1404 }
1405
1406 if (!reg_sleep_ctrl || !reg_sleep_info) {
1407 rtw_warn_on(1);
1408 goto exit;
1409 }
1410
1411 val32 = rtw_read32(adapter, reg_sleep_ctrl);
1412 val32 = (val32 &~sel_mask_sel) | ((macid / 32) & sel_mask_sel);
1413 rtw_write32(adapter, reg_sleep_ctrl, val32);
1414
1415 val32 = rtw_read32(adapter, reg_sleep_info);
1416 RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x\n"
1417 , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
1418 , macid, reg_sleep_info, val32);
1419
1420 ret = _SUCCESS;
1421
1422 if (sleep) {
1423 if (val32 & BIT(bit_shift))
1424 goto exit;
1425 val32 |= BIT(bit_shift);
1426 } else {
1427 if (!(val32 & BIT(bit_shift)))
1428 goto exit;
1429 val32 &= ~BIT(bit_shift);
1430 }
1431
1432 rtw_write32(adapter, reg_sleep_info, val32);
1433
1434 exit:
1435 return ret;
1436 }
1437 #else
_rtw_hal_macid_sleep(_adapter * adapter,u8 macid,u8 sleep)1438 static s32 _rtw_hal_macid_sleep(_adapter *adapter, u8 macid, u8 sleep)
1439 {
1440 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1441 u16 reg_sleep;
1442 u8 bit_shift;
1443 u32 val32;
1444 s32 ret = _FAIL;
1445
1446 if (macid >= macid_ctl->num) {
1447 RTW_ERR(ADPT_FMT" %s invalid macid(%u)\n"
1448 , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup" , macid);
1449 goto exit;
1450 }
1451
1452 if (macid < 32) {
1453 reg_sleep = macid_ctl->reg_sleep_m0;
1454 bit_shift = macid;
1455 #if (MACID_NUM_SW_LIMIT > 32)
1456 } else if (macid < 64) {
1457 reg_sleep = macid_ctl->reg_sleep_m1;
1458 bit_shift = macid - 32;
1459 #endif
1460 #if (MACID_NUM_SW_LIMIT > 64)
1461 } else if (macid < 96) {
1462 reg_sleep = macid_ctl->reg_sleep_m2;
1463 bit_shift = macid - 64;
1464 #endif
1465 #if (MACID_NUM_SW_LIMIT > 96)
1466 } else if (macid < 128) {
1467 reg_sleep = macid_ctl->reg_sleep_m3;
1468 bit_shift = macid - 96;
1469 #endif
1470 } else {
1471 rtw_warn_on(1);
1472 goto exit;
1473 }
1474
1475 if (!reg_sleep) {
1476 rtw_warn_on(1);
1477 goto exit;
1478 }
1479
1480 val32 = rtw_read32(adapter, reg_sleep);
1481 RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x\n"
1482 , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
1483 , macid, reg_sleep, val32);
1484
1485 ret = _SUCCESS;
1486
1487 if (sleep) {
1488 if (val32 & BIT(bit_shift))
1489 goto exit;
1490 val32 |= BIT(bit_shift);
1491 } else {
1492 if (!(val32 & BIT(bit_shift)))
1493 goto exit;
1494 val32 &= ~BIT(bit_shift);
1495 }
1496
1497 rtw_write32(adapter, reg_sleep, val32);
1498
1499 exit:
1500 return ret;
1501 }
1502 #endif
1503
rtw_hal_macid_sleep(_adapter * adapter,u8 macid)1504 inline s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid)
1505 {
1506 return _rtw_hal_macid_sleep(adapter, macid, 1);
1507 }
1508
rtw_hal_macid_wakeup(_adapter * adapter,u8 macid)1509 inline s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid)
1510 {
1511 return _rtw_hal_macid_sleep(adapter, macid, 0);
1512 }
1513
1514 #ifdef CONFIG_PROTSEL_MACSLEEP
_rtw_hal_macid_bmp_sleep(_adapter * adapter,struct macid_bmp * bmp,u8 sleep)1515 static s32 _rtw_hal_macid_bmp_sleep(_adapter *adapter, struct macid_bmp *bmp, u8 sleep)
1516 {
1517 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1518 u16 reg_sleep_info = macid_ctl->reg_sleep_info;
1519 u16 reg_sleep_ctrl = macid_ctl->reg_sleep_ctrl;
1520 const u32 sel_mask_sel = BIT(0) | BIT(1) | BIT(2);
1521 u32 m;
1522 u8 mid = 0;
1523 u32 val32;
1524
1525 do {
1526 if (mid == 0) {
1527 m = bmp->m0;
1528 #if (MACID_NUM_SW_LIMIT > 32)
1529 } else if (mid == 1) {
1530 m = bmp->m1;
1531 #endif
1532 #if (MACID_NUM_SW_LIMIT > 64)
1533 } else if (mid == 2) {
1534 m = bmp->m2;
1535 #endif
1536 #if (MACID_NUM_SW_LIMIT > 96)
1537 } else if (mid == 3) {
1538 m = bmp->m3;
1539 #endif
1540 } else {
1541 rtw_warn_on(1);
1542 break;
1543 }
1544
1545 if (m == 0)
1546 goto move_next;
1547
1548 if (!reg_sleep_ctrl || !reg_sleep_info) {
1549 rtw_warn_on(1);
1550 break;
1551 }
1552
1553 val32 = rtw_read32(adapter, reg_sleep_ctrl);
1554 val32 = (val32 &~sel_mask_sel) | (mid & sel_mask_sel);
1555 rtw_write32(adapter, reg_sleep_ctrl, val32);
1556
1557 val32 = rtw_read32(adapter, reg_sleep_info);
1558 RTW_INFO(ADPT_FMT" %s m%u=0x%08x, ori reg_0x%03x=0x%08x\n"
1559 , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
1560 , mid, m, reg_sleep_info, val32);
1561
1562 if (sleep) {
1563 if ((val32 & m) == m)
1564 goto move_next;
1565 val32 |= m;
1566 } else {
1567 if ((val32 & m) == 0)
1568 goto move_next;
1569 val32 &= ~m;
1570 }
1571
1572 rtw_write32(adapter, reg_sleep_info, val32);
1573
1574 move_next:
1575 mid++;
1576 } while (mid * 32 < MACID_NUM_SW_LIMIT);
1577
1578 return _SUCCESS;
1579 }
1580 #else
_rtw_hal_macid_bmp_sleep(_adapter * adapter,struct macid_bmp * bmp,u8 sleep)1581 static s32 _rtw_hal_macid_bmp_sleep(_adapter *adapter, struct macid_bmp *bmp, u8 sleep)
1582 {
1583 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1584 u16 reg_sleep;
1585 u32 m;
1586 u8 mid = 0;
1587 u32 val32;
1588
1589 do {
1590 if (mid == 0) {
1591 m = bmp->m0;
1592 reg_sleep = macid_ctl->reg_sleep_m0;
1593 #if (MACID_NUM_SW_LIMIT > 32)
1594 } else if (mid == 1) {
1595 m = bmp->m1;
1596 reg_sleep = macid_ctl->reg_sleep_m1;
1597 #endif
1598 #if (MACID_NUM_SW_LIMIT > 64)
1599 } else if (mid == 2) {
1600 m = bmp->m2;
1601 reg_sleep = macid_ctl->reg_sleep_m2;
1602 #endif
1603 #if (MACID_NUM_SW_LIMIT > 96)
1604 } else if (mid == 3) {
1605 m = bmp->m3;
1606 reg_sleep = macid_ctl->reg_sleep_m3;
1607 #endif
1608 } else {
1609 rtw_warn_on(1);
1610 break;
1611 }
1612
1613 if (m == 0)
1614 goto move_next;
1615
1616 if (!reg_sleep) {
1617 rtw_warn_on(1);
1618 break;
1619 }
1620
1621 val32 = rtw_read32(adapter, reg_sleep);
1622 RTW_INFO(ADPT_FMT" %s m%u=0x%08x, ori reg_0x%03x=0x%08x\n"
1623 , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
1624 , mid, m, reg_sleep, val32);
1625
1626 if (sleep) {
1627 if ((val32 & m) == m)
1628 goto move_next;
1629 val32 |= m;
1630 } else {
1631 if ((val32 & m) == 0)
1632 goto move_next;
1633 val32 &= ~m;
1634 }
1635
1636 rtw_write32(adapter, reg_sleep, val32);
1637
1638 move_next:
1639 mid++;
1640 } while (mid * 32 < MACID_NUM_SW_LIMIT);
1641
1642 return _SUCCESS;
1643 }
1644 #endif
1645
rtw_hal_macid_sleep_all_used(_adapter * adapter)1646 inline s32 rtw_hal_macid_sleep_all_used(_adapter *adapter)
1647 {
1648 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1649
1650 return _rtw_hal_macid_bmp_sleep(adapter, &macid_ctl->used, 1);
1651 }
1652
rtw_hal_macid_wakeup_all_used(_adapter * adapter)1653 inline s32 rtw_hal_macid_wakeup_all_used(_adapter *adapter)
1654 {
1655 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1656
1657 return _rtw_hal_macid_bmp_sleep(adapter, &macid_ctl->used, 0);
1658 }
1659
_rtw_hal_macid_drop(_adapter * adapter,u8 macid,u8 drop)1660 static s32 _rtw_hal_macid_drop(_adapter *adapter, u8 macid, u8 drop)
1661 {
1662 struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
1663 #ifndef CONFIG_PROTSEL_MACSLEEP
1664 u16 reg_drop = 0;
1665 #else
1666 u16 reg_drop_info = macid_ctl->reg_drop_info;
1667 u16 reg_drop_ctrl = macid_ctl->reg_drop_ctrl;
1668 const u32 sel_mask_sel = BIT(0) | BIT(1) | BIT(2);
1669 #endif /* CONFIG_PROTSEL_MACSLEEP */
1670 u8 bit_shift;
1671 u32 val32;
1672 s32 ret = _FAIL;
1673 /* some IC doesn't have this register */
1674 #ifndef REG_PKT_BUFF_ACCESS_CTRL
1675 #define REG_PKT_BUFF_ACCESS_CTRL 0
1676 #endif
1677
1678 if (macid >= macid_ctl->num) {
1679 RTW_ERR(ADPT_FMT" %s invalid macid(%u)\n"
1680 , ADPT_ARG(adapter), drop ? "drop" : "undrop" , macid);
1681 goto exit;
1682 }
1683
1684 if(_rtw_macid_ctl_chk_cap(adapter, MACID_DROP)) {
1685 if (macid < 32) {
1686 #ifndef CONFIG_PROTSEL_MACSLEEP
1687 reg_drop = macid_ctl->reg_drop_m0;
1688 #endif /* CONFIG_PROTSEL_MACSLEEP */
1689 bit_shift = macid;
1690 #if (MACID_NUM_SW_LIMIT > 32)
1691 } else if (macid < 64) {
1692 #ifndef CONFIG_PROTSEL_MACSLEEP
1693 reg_drop = macid_ctl->reg_drop_m1;
1694 #endif /* CONFIG_PROTSEL_MACSLEEP */
1695 bit_shift = macid - 32;
1696 #endif
1697 #if (MACID_NUM_SW_LIMIT > 64)
1698 } else if (macid < 96) {
1699 #ifndef CONFIG_PROTSEL_MACSLEEP
1700 reg_drop = macid_ctl->reg_drop_m2;
1701 #endif /* CONFIG_PROTSEL_MACSLEEP */
1702 bit_shift = macid - 64;
1703 #endif
1704 #if (MACID_NUM_SW_LIMIT > 96)
1705 } else if (macid < 128) {
1706 #ifndef CONFIG_PROTSEL_MACSLEEP
1707 reg_drop = macid_ctl->reg_drop_m3;
1708 #endif /* CONFIG_PROTSEL_MACSLEEP */
1709 bit_shift = macid - 96;
1710 #endif
1711 } else {
1712 rtw_warn_on(1);
1713 goto exit;
1714 }
1715
1716 #ifndef CONFIG_PROTSEL_MACSLEEP
1717 if (!reg_drop) {
1718 rtw_warn_on(1);
1719 goto exit;
1720 }
1721 val32 = rtw_read32(adapter, reg_drop);
1722 /*RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x \n"
1723 , ADPT_ARG(adapter), drop ? "drop" : "undrop"
1724 , macid, reg_drop, val32);*/
1725 #else
1726 if (!reg_drop_ctrl || !reg_drop_info) {
1727 rtw_warn_on(1);
1728 goto exit;
1729 }
1730
1731 val32 = rtw_read32(adapter, reg_drop_ctrl);
1732 val32 = (val32 &~sel_mask_sel) | ((macid / 32) & sel_mask_sel);
1733 rtw_write32(adapter, reg_drop_ctrl, val32);
1734
1735 val32 = rtw_read32(adapter, reg_drop_info);
1736 /*RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x\n"
1737 , ADPT_ARG(adapter), drop ? "drop" : "undrop"
1738 , macid, reg_drop_info, val32);*/
1739 #endif /* CONFIG_PROTSEL_MACSLEEP */
1740 ret = _SUCCESS;
1741
1742 if (drop) {
1743 if (val32 & BIT(bit_shift))
1744 goto exit;
1745 val32 |= BIT(bit_shift);
1746 } else {
1747 if (!(val32 & BIT(bit_shift)))
1748 goto exit;
1749 val32 &= ~BIT(bit_shift);
1750 }
1751
1752 #ifndef CONFIG_PROTSEL_MACSLEEP
1753 rtw_write32(adapter, reg_drop, val32);
1754 RTW_INFO(ADPT_FMT" %s macid=%d, done reg_0x%03x=0x%08x\n"
1755 , ADPT_ARG(adapter), drop ? "drop" : "undrop"
1756 , macid, reg_drop, val32);
1757 #else
1758 rtw_write32(adapter, reg_drop_info, val32);
1759 RTW_INFO(ADPT_FMT" %s macid=%d, done reg_0x%03x=0x%08x\n"
1760 , ADPT_ARG(adapter), drop ? "drop" : "undrop"
1761 , macid, reg_drop_info, val32);
1762 #endif /* CONFIG_PROTSEL_MACSLEEP */
1763
1764
1765 } else if(_rtw_macid_ctl_chk_cap(adapter, MACID_DROP_INDIRECT)) {
1766 u16 start_addr = macid_ctl->macid_txrpt/8;
1767 u32 txrpt_h4b = 0;
1768 u8 i;
1769
1770 /* each address means 1 byte */
1771 start_addr += macid*(macid_ctl->macid_txrpt_pgsz/8);
1772 /* select tx report buffer */
1773 rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, TXREPORT_BUF_SELECT);
1774 /* set tx report buffer start address for reading */
1775 rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, start_addr);
1776 txrpt_h4b = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
1777 /* OFFSET5 BIT2 is BIT10 of high 4 bytes */
1778 if (drop) {
1779 if (txrpt_h4b & BIT(10))
1780 goto exit;
1781 txrpt_h4b |= BIT(10);
1782 } else {
1783 if (!(txrpt_h4b & BIT(10)))
1784 goto exit;
1785 txrpt_h4b &= ~BIT(10);
1786 }
1787 /* set to macid drop field */
1788 rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, txrpt_h4b);
1789 /* 0x20800000 only write BIT10 of tx report buf */
1790 rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, 0x20800000 | start_addr);
1791 #if 0 /* some ICs doesn't clear the write done bit */
1792 /* checking TX queue status */
1793 for (i = 0 ; i < 50 ; i++) {
1794 txrpt_h4b = rtw_read32(adapter, REG_PKTBUF_DBG_CTRL);
1795 if (txrpt_h4b & BIT(23)) {
1796 RTW_INFO("%s: wait to write TX RTP buf (%d)!\n", __func__, i);
1797 rtw_mdelay_os(10);
1798 } else {
1799 RTW_INFO("%s: wait to write TX RTP buf done (%d)!\n", __func__, i);
1800 break;
1801 }
1802 }
1803 #endif
1804 rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, start_addr);
1805 RTW_INFO("start_addr=%x, data_H:%08x, data_L:%08x, macid=%d, txrpt_h4b=%x\n", start_addr
1806 ,rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H), rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L), macid, txrpt_h4b);
1807 } else {
1808 RTW_INFO("There is no definition for camctl cap , please correct it\n");
1809 }
1810 exit:
1811 return ret;
1812 }
1813
rtw_hal_macid_drop(_adapter * adapter,u8 macid)1814 inline s32 rtw_hal_macid_drop(_adapter *adapter, u8 macid)
1815 {
1816 return _rtw_hal_macid_drop(adapter, macid, 1);
1817 }
1818
rtw_hal_macid_undrop(_adapter * adapter,u8 macid)1819 inline s32 rtw_hal_macid_undrop(_adapter *adapter, u8 macid)
1820 {
1821 return _rtw_hal_macid_drop(adapter, macid, 0);
1822 }
1823
rtw_hal_fill_h2c_cmd(PADAPTER padapter,u8 ElementID,u32 CmdLen,u8 * pCmdBuffer)1824 s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer)
1825 {
1826 _adapter *pri_adapter = GET_PRIMARY_ADAPTER(padapter);
1827
1828 if (GET_HAL_DATA(pri_adapter)->bFWReady == _TRUE)
1829 return padapter->hal_func.fill_h2c_cmd(padapter, ElementID, CmdLen, pCmdBuffer);
1830 else if (padapter->registrypriv.mp_mode == 0)
1831 RTW_PRINT(FUNC_ADPT_FMT" FW doesn't exit when no MP mode, by pass H2C id:0x%02x\n"
1832 , FUNC_ADPT_ARG(padapter), ElementID);
1833 return _FAIL;
1834 }
1835
rtw_hal_fill_fake_txdesc(_adapter * padapter,u8 * pDesc,u32 BufferLen,u8 IsPsPoll,u8 IsBTQosNull,u8 bDataFrame)1836 void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen,
1837 u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame)
1838 {
1839 padapter->hal_func.fill_fake_txdesc(padapter, pDesc, BufferLen, IsPsPoll, IsBTQosNull, bDataFrame);
1840
1841 }
1842
rtw_hal_get_txbuff_rsvd_page_num(_adapter * adapter,bool wowlan)1843 u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan)
1844 {
1845 u8 num = 0;
1846
1847
1848 if (adapter->hal_func.hal_get_tx_buff_rsvd_page_num) {
1849 num = adapter->hal_func.hal_get_tx_buff_rsvd_page_num(adapter, wowlan);
1850 } else {
1851 #ifdef RTW_HALMAC
1852 num = GET_HAL_DATA(adapter)->drv_rsvd_page_number;
1853 #endif /* RTW_HALMAC */
1854 }
1855
1856 return num;
1857 }
1858
1859 #ifdef CONFIG_GPIO_API
rtw_hal_update_hisr_hsisr_ind(_adapter * padapter,u32 flag)1860 void rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag)
1861 {
1862 if (padapter->hal_func.update_hisr_hsisr_ind)
1863 padapter->hal_func.update_hisr_hsisr_ind(padapter, flag);
1864 }
1865
rtw_hal_gpio_func_check(_adapter * padapter,u8 gpio_num)1866 int rtw_hal_gpio_func_check(_adapter *padapter, u8 gpio_num)
1867 {
1868 int ret = _SUCCESS;
1869
1870 if (padapter->hal_func.hal_gpio_func_check)
1871 ret = padapter->hal_func.hal_gpio_func_check(padapter, gpio_num);
1872
1873 return ret;
1874 }
1875
rtw_hal_gpio_multi_func_reset(_adapter * padapter,u8 gpio_num)1876 void rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num)
1877 {
1878 if (padapter->hal_func.hal_gpio_multi_func_reset)
1879 padapter->hal_func.hal_gpio_multi_func_reset(padapter, gpio_num);
1880 }
1881 #endif
1882
1883 #ifdef CONFIG_FW_CORRECT_BCN
rtw_hal_fw_correct_bcn(_adapter * padapter)1884 void rtw_hal_fw_correct_bcn(_adapter *padapter)
1885 {
1886 if (padapter->hal_func.fw_correct_bcn)
1887 padapter->hal_func.fw_correct_bcn(padapter);
1888 }
1889 #endif
1890
rtw_hal_set_tx_power_level(_adapter * adapter,u8 channel)1891 void rtw_hal_set_tx_power_level(_adapter *adapter, u8 channel)
1892 {
1893 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1894
1895 if (phy_chk_ch_setting_consistency(adapter, channel) != _SUCCESS)
1896 return;
1897
1898 hal_data->set_entire_txpwr = 1;
1899
1900 adapter->hal_func.set_tx_power_level_handler(adapter, channel);
1901 rtw_hal_set_txpwr_done(adapter);
1902
1903 hal_data->set_entire_txpwr = 0;
1904 }
1905
rtw_hal_update_txpwr_level(_adapter * adapter)1906 void rtw_hal_update_txpwr_level(_adapter *adapter)
1907 {
1908 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1909
1910 rtw_hal_set_tx_power_level(adapter, hal_data->current_channel);
1911 }
1912
rtw_hal_set_txpwr_done(_adapter * adapter)1913 void rtw_hal_set_txpwr_done(_adapter *adapter)
1914 {
1915 if (adapter->hal_func.set_txpwr_done)
1916 adapter->hal_func.set_txpwr_done(adapter);
1917 }
1918
rtw_hal_set_tx_power_index(_adapter * adapter,u32 powerindex,enum rf_path rfpath,u8 rate)1919 void rtw_hal_set_tx_power_index(_adapter *adapter, u32 powerindex
1920 , enum rf_path rfpath, u8 rate)
1921 {
1922 adapter->hal_func.set_tx_power_index_handler(adapter, powerindex, rfpath, rate);
1923 }
1924
rtw_hal_get_tx_power_index(_adapter * adapter,enum rf_path rfpath,RATE_SECTION rs,enum MGN_RATE rate,enum channel_width bw,BAND_TYPE band,u8 cch,u8 opch,struct txpwr_idx_comp * tic)1925 u8 rtw_hal_get_tx_power_index(_adapter *adapter, enum rf_path rfpath
1926 , RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch
1927 , struct txpwr_idx_comp *tic)
1928 {
1929 return adapter->hal_func.get_tx_power_index_handler(adapter, rfpath
1930 , rs, rate, bw, band, cch, opch, tic);
1931 }
1932
rtw_hal_get_txpwr_target_extra_bias(_adapter * adapter,enum rf_path rfpath,RATE_SECTION rs,enum MGN_RATE rate,enum channel_width bw,BAND_TYPE band,u8 cch)1933 s8 rtw_hal_get_txpwr_target_extra_bias(_adapter *adapter, enum rf_path rfpath
1934 , RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch)
1935 {
1936 s8 val = 0;
1937
1938 if (adapter->hal_func.get_txpwr_target_extra_bias) {
1939 val = adapter->hal_func.get_txpwr_target_extra_bias(adapter
1940 , rfpath, rs, rate, bw, band, cch);
1941 }
1942
1943 return val;
1944 }
1945
1946 #ifdef RTW_HALMAC
1947 /*
1948 * Description:
1949 * Initialize MAC registers
1950 *
1951 * Return:
1952 * _TRUE success
1953 * _FALSE fail
1954 */
rtw_hal_init_mac_register(PADAPTER adapter)1955 u8 rtw_hal_init_mac_register(PADAPTER adapter)
1956 {
1957 return adapter->hal_func.init_mac_register(adapter);
1958 }
1959
1960 /*
1961 * Description:
1962 * Initialize PHY(BB/RF) related functions
1963 *
1964 * Return:
1965 * _TRUE success
1966 * _FALSE fail
1967 */
rtw_hal_init_phy(PADAPTER adapter)1968 u8 rtw_hal_init_phy(PADAPTER adapter)
1969 {
1970 return adapter->hal_func.init_phy(adapter);
1971 }
1972 #endif /* RTW_HALMAC */
1973
1974 #ifdef CONFIG_RFKILL_POLL
rtw_hal_rfkill_poll(_adapter * adapter,u8 * valid)1975 bool rtw_hal_rfkill_poll(_adapter *adapter, u8 *valid)
1976 {
1977 bool ret;
1978
1979 if (adapter->hal_func.hal_radio_onoff_check)
1980 ret = adapter->hal_func.hal_radio_onoff_check(adapter, valid);
1981 else {
1982 *valid = 0;
1983 ret = _FALSE;
1984 }
1985 return ret;
1986 }
1987 #endif
1988
1989 #define rtw_hal_error_msg(ops_fun) \
1990 RTW_PRINT("### %s - Error : Please hook hal_func.%s ###\n", __FUNCTION__, ops_fun)
1991
rtw_hal_ops_check(_adapter * padapter)1992 u8 rtw_hal_ops_check(_adapter *padapter)
1993 {
1994 u8 ret = _SUCCESS;
1995 #if 1
1996 /*** initialize section ***/
1997 if (NULL == padapter->hal_func.read_chip_version) {
1998 rtw_hal_error_msg("read_chip_version");
1999 ret = _FAIL;
2000 }
2001 if (NULL == padapter->hal_func.init_default_value) {
2002 rtw_hal_error_msg("init_default_value");
2003 ret = _FAIL;
2004 }
2005 if (NULL == padapter->hal_func.intf_chip_configure) {
2006 rtw_hal_error_msg("intf_chip_configure");
2007 ret = _FAIL;
2008 }
2009 if (NULL == padapter->hal_func.read_adapter_info) {
2010 rtw_hal_error_msg("read_adapter_info");
2011 ret = _FAIL;
2012 }
2013
2014 if (NULL == padapter->hal_func.hal_power_on) {
2015 rtw_hal_error_msg("hal_power_on");
2016 ret = _FAIL;
2017 }
2018 if (NULL == padapter->hal_func.hal_power_off) {
2019 rtw_hal_error_msg("hal_power_off");
2020 ret = _FAIL;
2021 }
2022
2023 if (NULL == padapter->hal_func.hal_init) {
2024 rtw_hal_error_msg("hal_init");
2025 ret = _FAIL;
2026 }
2027 if (NULL == padapter->hal_func.hal_deinit) {
2028 rtw_hal_error_msg("hal_deinit");
2029 ret = _FAIL;
2030 }
2031
2032 /*** xmit section ***/
2033 if (NULL == padapter->hal_func.init_xmit_priv) {
2034 rtw_hal_error_msg("init_xmit_priv");
2035 ret = _FAIL;
2036 }
2037 if (NULL == padapter->hal_func.free_xmit_priv) {
2038 rtw_hal_error_msg("free_xmit_priv");
2039 ret = _FAIL;
2040 }
2041 if (NULL == padapter->hal_func.hal_xmit) {
2042 rtw_hal_error_msg("hal_xmit");
2043 ret = _FAIL;
2044 }
2045 if (NULL == padapter->hal_func.mgnt_xmit) {
2046 rtw_hal_error_msg("mgnt_xmit");
2047 ret = _FAIL;
2048 }
2049 #ifdef CONFIG_XMIT_THREAD_MODE
2050 if (NULL == padapter->hal_func.xmit_thread_handler) {
2051 rtw_hal_error_msg("xmit_thread_handler");
2052 ret = _FAIL;
2053 }
2054 #endif
2055 if (NULL == padapter->hal_func.hal_xmitframe_enqueue) {
2056 rtw_hal_error_msg("hal_xmitframe_enqueue");
2057 ret = _FAIL;
2058 }
2059 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
2060 #ifndef CONFIG_SDIO_TX_TASKLET
2061 if (NULL == padapter->hal_func.run_thread) {
2062 rtw_hal_error_msg("run_thread");
2063 ret = _FAIL;
2064 }
2065 if (NULL == padapter->hal_func.cancel_thread) {
2066 rtw_hal_error_msg("cancel_thread");
2067 ret = _FAIL;
2068 }
2069 #endif
2070 #endif
2071
2072 /*** recv section ***/
2073 if (NULL == padapter->hal_func.init_recv_priv) {
2074 rtw_hal_error_msg("init_recv_priv");
2075 ret = _FAIL;
2076 }
2077 if (NULL == padapter->hal_func.free_recv_priv) {
2078 rtw_hal_error_msg("free_recv_priv");
2079 ret = _FAIL;
2080 }
2081 #ifdef CONFIG_RECV_THREAD_MODE
2082 if (NULL == padapter->hal_func.recv_hdl) {
2083 rtw_hal_error_msg("recv_hdl");
2084 ret = _FAIL;
2085 }
2086 #endif
2087 #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
2088 if (NULL == padapter->hal_func.inirp_init) {
2089 rtw_hal_error_msg("inirp_init");
2090 ret = _FAIL;
2091 }
2092 if (NULL == padapter->hal_func.inirp_deinit) {
2093 rtw_hal_error_msg("inirp_deinit");
2094 ret = _FAIL;
2095 }
2096 #endif /* #if defined(CONFIG_USB_HCI) || defined (CONFIG_PCI_HCI) */
2097
2098
2099 /*** interrupt hdl section ***/
2100 #if defined(CONFIG_PCI_HCI)
2101 if (NULL == padapter->hal_func.irp_reset) {
2102 rtw_hal_error_msg("irp_reset");
2103 ret = _FAIL;
2104 }
2105 #endif/*#if defined(CONFIG_PCI_HCI)*/
2106 #if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT))
2107 if (NULL == padapter->hal_func.interrupt_handler) {
2108 rtw_hal_error_msg("interrupt_handler");
2109 ret = _FAIL;
2110 }
2111 #endif /*#if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT))*/
2112
2113 #if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
2114 if (NULL == padapter->hal_func.enable_interrupt) {
2115 rtw_hal_error_msg("enable_interrupt");
2116 ret = _FAIL;
2117 }
2118 if (NULL == padapter->hal_func.disable_interrupt) {
2119 rtw_hal_error_msg("disable_interrupt");
2120 ret = _FAIL;
2121 }
2122 #endif /* defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
2123
2124
2125 /*** DM section ***/
2126 if (NULL == padapter->hal_func.dm_init) {
2127 rtw_hal_error_msg("dm_init");
2128 ret = _FAIL;
2129 }
2130 if (NULL == padapter->hal_func.dm_deinit) {
2131 rtw_hal_error_msg("dm_deinit");
2132 ret = _FAIL;
2133 }
2134 if (NULL == padapter->hal_func.hal_dm_watchdog) {
2135 rtw_hal_error_msg("hal_dm_watchdog");
2136 ret = _FAIL;
2137 }
2138
2139 /*** xxx section ***/
2140 if (NULL == padapter->hal_func.set_chnl_bw_handler) {
2141 rtw_hal_error_msg("set_chnl_bw_handler");
2142 ret = _FAIL;
2143 }
2144
2145 if (NULL == padapter->hal_func.set_hw_reg_handler) {
2146 rtw_hal_error_msg("set_hw_reg_handler");
2147 ret = _FAIL;
2148 }
2149 if (NULL == padapter->hal_func.GetHwRegHandler) {
2150 rtw_hal_error_msg("GetHwRegHandler");
2151 ret = _FAIL;
2152 }
2153 if (NULL == padapter->hal_func.get_hal_def_var_handler) {
2154 rtw_hal_error_msg("get_hal_def_var_handler");
2155 ret = _FAIL;
2156 }
2157 if (NULL == padapter->hal_func.SetHalDefVarHandler) {
2158 rtw_hal_error_msg("SetHalDefVarHandler");
2159 ret = _FAIL;
2160 }
2161 if (NULL == padapter->hal_func.GetHalODMVarHandler) {
2162 rtw_hal_error_msg("GetHalODMVarHandler");
2163 ret = _FAIL;
2164 }
2165 if (NULL == padapter->hal_func.SetHalODMVarHandler) {
2166 rtw_hal_error_msg("SetHalODMVarHandler");
2167 ret = _FAIL;
2168 }
2169
2170 if (NULL == padapter->hal_func.SetBeaconRelatedRegistersHandler) {
2171 rtw_hal_error_msg("SetBeaconRelatedRegistersHandler");
2172 ret = _FAIL;
2173 }
2174
2175 if (NULL == padapter->hal_func.fill_h2c_cmd) {
2176 rtw_hal_error_msg("fill_h2c_cmd");
2177 ret = _FAIL;
2178 }
2179
2180 #ifdef RTW_HALMAC
2181 if (NULL == padapter->hal_func.hal_mac_c2h_handler) {
2182 rtw_hal_error_msg("hal_mac_c2h_handler");
2183 ret = _FAIL;
2184 }
2185 #elif !defined(CONFIG_RTL8188E)
2186 if (NULL == padapter->hal_func.c2h_handler) {
2187 rtw_hal_error_msg("c2h_handler");
2188 ret = _FAIL;
2189 }
2190 #endif
2191
2192 #if defined(CONFIG_LPS) || defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
2193 if (NULL == padapter->hal_func.fill_fake_txdesc) {
2194 rtw_hal_error_msg("fill_fake_txdesc");
2195 ret = _FAIL;
2196 }
2197 #endif
2198
2199 #ifndef RTW_HALMAC
2200 if (NULL == padapter->hal_func.hal_get_tx_buff_rsvd_page_num) {
2201 rtw_hal_error_msg("hal_get_tx_buff_rsvd_page_num");
2202 ret = _FAIL;
2203 }
2204 #endif /* !RTW_HALMAC */
2205
2206 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
2207 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
2208 if (NULL == padapter->hal_func.clear_interrupt) {
2209 rtw_hal_error_msg("clear_interrupt");
2210 ret = _FAIL;
2211 }
2212 #endif
2213 #endif /* CONFIG_WOWLAN */
2214
2215 if (NULL == padapter->hal_func.fw_dl) {
2216 rtw_hal_error_msg("fw_dl");
2217 ret = _FAIL;
2218 }
2219
2220 #ifdef CONFIG_FW_CORRECT_BCN
2221 if (IS_HARDWARE_TYPE_8814A(padapter)
2222 && NULL == padapter->hal_func.fw_correct_bcn) {
2223 rtw_hal_error_msg("fw_correct_bcn");
2224 ret = _FAIL;
2225 }
2226 #endif
2227
2228 if (!padapter->hal_func.set_tx_power_level_handler) {
2229 rtw_hal_error_msg("set_tx_power_level_handler");
2230 ret = _FAIL;
2231 }
2232 if (!padapter->hal_func.set_tx_power_index_handler) {
2233 rtw_hal_error_msg("set_tx_power_index_handler");
2234 ret = _FAIL;
2235 }
2236 if (!padapter->hal_func.get_tx_power_index_handler) {
2237 rtw_hal_error_msg("get_tx_power_index_handler");
2238 ret = _FAIL;
2239 }
2240
2241 /*** SReset section ***/
2242 #ifdef DBG_CONFIG_ERROR_DETECT
2243 if (NULL == padapter->hal_func.sreset_init_value) {
2244 rtw_hal_error_msg("sreset_init_value");
2245 ret = _FAIL;
2246 }
2247 if (NULL == padapter->hal_func.sreset_reset_value) {
2248 rtw_hal_error_msg("sreset_reset_value");
2249 ret = _FAIL;
2250 }
2251 if (NULL == padapter->hal_func.silentreset) {
2252 rtw_hal_error_msg("silentreset");
2253 ret = _FAIL;
2254 }
2255 if (NULL == padapter->hal_func.sreset_xmit_status_check) {
2256 rtw_hal_error_msg("sreset_xmit_status_check");
2257 ret = _FAIL;
2258 }
2259 if (NULL == padapter->hal_func.sreset_linked_status_check) {
2260 rtw_hal_error_msg("sreset_linked_status_check");
2261 ret = _FAIL;
2262 }
2263 if (NULL == padapter->hal_func.sreset_get_wifi_status) {
2264 rtw_hal_error_msg("sreset_get_wifi_status");
2265 ret = _FAIL;
2266 }
2267 if (NULL == padapter->hal_func.sreset_inprogress) {
2268 rtw_hal_error_msg("sreset_inprogress");
2269 ret = _FAIL;
2270 }
2271 #endif /* #ifdef DBG_CONFIG_ERROR_DETECT */
2272
2273 #ifdef RTW_HALMAC
2274 if (NULL == padapter->hal_func.init_mac_register) {
2275 rtw_hal_error_msg("init_mac_register");
2276 ret = _FAIL;
2277 }
2278 if (NULL == padapter->hal_func.init_phy) {
2279 rtw_hal_error_msg("init_phy");
2280 ret = _FAIL;
2281 }
2282 #endif /* RTW_HALMAC */
2283
2284 #ifdef CONFIG_RFKILL_POLL
2285 if (padapter->hal_func.hal_radio_onoff_check == NULL) {
2286 rtw_hal_error_msg("hal_radio_onoff_check");
2287 ret = _FAIL;
2288 }
2289 #endif
2290 #endif
2291 return ret;
2292 }
2293