1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _RTW_RF_C_
16
17 #include <drv_types.h>
18 #include <hal_data.h>
19
20 u8 center_ch_2g[CENTER_CH_2G_NUM] = {
21 /* G00 */1, 2,
22 /* G01 */3, 4, 5,
23 /* G02 */6, 7, 8,
24 /* G03 */9, 10, 11,
25 /* G04 */12, 13,
26 /* G05 */14
27 };
28
29 #define ch_to_cch_2g_idx(ch) ((ch) - 1)
30
31 u8 center_ch_2g_40m[CENTER_CH_2G_40M_NUM] = {
32 3,
33 4,
34 5,
35 6,
36 7,
37 8,
38 9,
39 10,
40 11,
41 };
42
43 u8 op_chs_of_cch_2g_40m[CENTER_CH_2G_40M_NUM][2] = {
44 {1, 5}, /* 3 */
45 {2, 6}, /* 4 */
46 {3, 7}, /* 5 */
47 {4, 8}, /* 6 */
48 {5, 9}, /* 7 */
49 {6, 10}, /* 8 */
50 {7, 11}, /* 9 */
51 {8, 12}, /* 10 */
52 {9, 13}, /* 11 */
53 };
54
55 u8 center_ch_5g_all[CENTER_CH_5G_ALL_NUM] = {
56 /* G00 */36, 38, 40,
57 42,
58 /* G01 */44, 46, 48,
59 /* 50, */
60 /* G02 */52, 54, 56,
61 58,
62 /* G03 */60, 62, 64,
63 /* G04 */100, 102, 104,
64 106,
65 /* G05 */108, 110, 112,
66 /* 114, */
67 /* G06 */116, 118, 120,
68 122,
69 /* G07 */124, 126, 128,
70 /* G08 */132, 134, 136,
71 138,
72 /* G09 */140, 142, 144,
73 /* G10 */149, 151, 153,
74 155,
75 /* G11 */157, 159, 161,
76 /* 163, */
77 /* G12 */165, 167, 169,
78 171,
79 /* G13 */173, 175, 177
80 };
81
82 u8 center_ch_5g_20m[CENTER_CH_5G_20M_NUM] = {
83 /* G00 */36, 40,
84 /* G01 */44, 48,
85 /* G02 */52, 56,
86 /* G03 */60, 64,
87 /* G04 */100, 104,
88 /* G05 */108, 112,
89 /* G06 */116, 120,
90 /* G07 */124, 128,
91 /* G08 */132, 136,
92 /* G09 */140, 144,
93 /* G10 */149, 153,
94 /* G11 */157, 161,
95 /* G12 */165, 169,
96 /* G13 */173, 177
97 };
98
99 #define ch_to_cch_5g_20m_idx(ch) \
100 ( \
101 ((ch) >= 36 && (ch) <= 64) ? (((ch) - 36) >> 2) : \
102 ((ch) >= 100 && (ch) <= 144) ? 8 + (((ch) - 100) >> 2) : \
103 ((ch) >= 149 && (ch) <= 177) ? 20 + (((ch) - 149) >> 2) : 255 \
104 )
105
106 u8 center_ch_5g_40m[CENTER_CH_5G_40M_NUM] = {
107 /* G00 */38,
108 /* G01 */46,
109 /* G02 */54,
110 /* G03 */62,
111 /* G04 */102,
112 /* G05 */110,
113 /* G06 */118,
114 /* G07 */126,
115 /* G08 */134,
116 /* G09 */142,
117 /* G10 */151,
118 /* G11 */159,
119 /* G12 */167,
120 /* G13 */175
121 };
122
123 u8 center_ch_5g_20m_40m[CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM] = {
124 /* G00 */36, 38, 40,
125 /* G01 */44, 46, 48,
126 /* G02 */52, 54, 56,
127 /* G03 */60, 62, 64,
128 /* G04 */100, 102, 104,
129 /* G05 */108, 110, 112,
130 /* G06 */116, 118, 120,
131 /* G07 */124, 126, 128,
132 /* G08 */132, 134, 136,
133 /* G09 */140, 142, 144,
134 /* G10 */149, 151, 153,
135 /* G11 */157, 159, 161,
136 /* G12 */165, 167, 169,
137 /* G13 */173, 175, 177
138 };
139
140 u8 op_chs_of_cch_5g_40m[CENTER_CH_5G_40M_NUM][2] = {
141 {36, 40}, /* 38 */
142 {44, 48}, /* 46 */
143 {52, 56}, /* 54 */
144 {60, 64}, /* 62 */
145 {100, 104}, /* 102 */
146 {108, 112}, /* 110 */
147 {116, 120}, /* 118 */
148 {124, 128}, /* 126 */
149 {132, 136}, /* 134 */
150 {140, 144}, /* 142 */
151 {149, 153}, /* 151 */
152 {157, 161}, /* 159 */
153 {165, 169}, /* 167 */
154 {173, 177}, /* 175 */
155 };
156
157 u8 center_ch_5g_80m[CENTER_CH_5G_80M_NUM] = {
158 /* G00 ~ G01*/42,
159 /* G02 ~ G03*/58,
160 /* G04 ~ G05*/106,
161 /* G06 ~ G07*/122,
162 /* G08 ~ G09*/138,
163 /* G10 ~ G11*/155,
164 /* G12 ~ G13*/171
165 };
166
167 u8 op_chs_of_cch_5g_80m[CENTER_CH_5G_80M_NUM][4] = {
168 {36, 40, 44, 48}, /* 42 */
169 {52, 56, 60, 64}, /* 58 */
170 {100, 104, 108, 112}, /* 106 */
171 {116, 120, 124, 128}, /* 122 */
172 {132, 136, 140, 144}, /* 138 */
173 {149, 153, 157, 161}, /* 155 */
174 {165, 169, 173, 177}, /* 171 */
175 };
176
177 u8 center_ch_5g_160m[CENTER_CH_5G_160M_NUM] = {
178 /* G00 ~ G03*/50,
179 /* G04 ~ G07*/114,
180 /* G10 ~ G13*/163
181 };
182
183 u8 op_chs_of_cch_5g_160m[CENTER_CH_5G_160M_NUM][8] = {
184 {36, 40, 44, 48, 52, 56, 60, 64}, /* 50 */
185 {100, 104, 108, 112, 116, 120, 124, 128}, /* 114 */
186 {149, 153, 157, 161, 165, 169, 173, 177}, /* 163 */
187 };
188
189 struct center_chs_ent_t {
190 u8 ch_num;
191 u8 *chs;
192 };
193
194 struct center_chs_ent_t center_chs_2g_by_bw[] = {
195 {CENTER_CH_2G_NUM, center_ch_2g},
196 {CENTER_CH_2G_40M_NUM, center_ch_2g_40m},
197 };
198
199 struct center_chs_ent_t center_chs_5g_by_bw[] = {
200 {CENTER_CH_5G_20M_NUM, center_ch_5g_20m},
201 {CENTER_CH_5G_40M_NUM, center_ch_5g_40m},
202 {CENTER_CH_5G_80M_NUM, center_ch_5g_80m},
203 {CENTER_CH_5G_160M_NUM, center_ch_5g_160m},
204 };
205
206 /*
207 * Get center channel of smaller bandwidth by @param cch, @param bw, @param offset
208 * @cch: the given center channel
209 * @bw: the given bandwidth
210 * @offset: the given primary SC offset of the given bandwidth
211 *
212 * return center channel of smaller bandiwdth if valid, or 0
213 */
rtw_get_scch_by_cch_offset(u8 cch,u8 bw,u8 offset)214 u8 rtw_get_scch_by_cch_offset(u8 cch, u8 bw, u8 offset)
215 {
216 u8 t_cch = 0;
217
218 if (bw == CHANNEL_WIDTH_20) {
219 t_cch = cch;
220 goto exit;
221 }
222
223 if (offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) {
224 rtw_warn_on(1);
225 goto exit;
226 }
227
228 /* 2.4G, 40MHz */
229 if (cch >= 3 && cch <= 11 && bw == CHANNEL_WIDTH_40) {
230 t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2;
231 goto exit;
232 }
233
234 /* 5G, 160MHz */
235 if (cch >= 50 && cch <= 163 && bw == CHANNEL_WIDTH_160) {
236 t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 8 : cch - 8;
237 goto exit;
238
239 /* 5G, 80MHz */
240 } else if (cch >= 42 && cch <= 171 && bw == CHANNEL_WIDTH_80) {
241 t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 4 : cch - 4;
242 goto exit;
243
244 /* 5G, 40MHz */
245 } else if (cch >= 38 && cch <= 175 && bw == CHANNEL_WIDTH_40) {
246 t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2;
247 goto exit;
248
249 } else {
250 rtw_warn_on(1);
251 goto exit;
252 }
253
254 exit:
255 return t_cch;
256 }
257
258 /*
259 * Get center channel of smaller bandwidth by @param cch, @param bw, @param opch
260 * @cch: the given center channel
261 * @bw: the given bandwidth
262 * @opch: the given operating channel
263 *
264 * return center channel of smaller bandiwdth if valid, or 0
265 */
rtw_get_scch_by_cch_opch(u8 cch,u8 bw,u8 opch)266 u8 rtw_get_scch_by_cch_opch(u8 cch, u8 bw, u8 opch)
267 {
268 u8 offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
269
270 if (opch > cch)
271 offset = HAL_PRIME_CHNL_OFFSET_UPPER;
272 else if (opch < cch)
273 offset = HAL_PRIME_CHNL_OFFSET_LOWER;
274
275 return rtw_get_scch_by_cch_offset(cch, bw, offset);
276 }
277
278 struct op_chs_ent_t {
279 u8 ch_num;
280 u8 *chs;
281 };
282
283 struct op_chs_ent_t op_chs_of_cch_2g_by_bw[] = {
284 {1, center_ch_2g},
285 {2, (u8 *)op_chs_of_cch_2g_40m},
286 };
287
288 struct op_chs_ent_t op_chs_of_cch_5g_by_bw[] = {
289 {1, center_ch_5g_20m},
290 {2, (u8 *)op_chs_of_cch_5g_40m},
291 {4, (u8 *)op_chs_of_cch_5g_80m},
292 {8, (u8 *)op_chs_of_cch_5g_160m},
293 };
294
center_chs_2g_num(u8 bw)295 inline u8 center_chs_2g_num(u8 bw)
296 {
297 if (bw > CHANNEL_WIDTH_40)
298 return 0;
299
300 return center_chs_2g_by_bw[bw].ch_num;
301 }
302
center_chs_2g(u8 bw,u8 id)303 inline u8 center_chs_2g(u8 bw, u8 id)
304 {
305 if (bw > CHANNEL_WIDTH_40)
306 return 0;
307
308 if (id >= center_chs_2g_num(bw))
309 return 0;
310
311 return center_chs_2g_by_bw[bw].chs[id];
312 }
313
center_chs_5g_num(u8 bw)314 inline u8 center_chs_5g_num(u8 bw)
315 {
316 if (bw > CHANNEL_WIDTH_160)
317 return 0;
318
319 return center_chs_5g_by_bw[bw].ch_num;
320 }
321
center_chs_5g(u8 bw,u8 id)322 inline u8 center_chs_5g(u8 bw, u8 id)
323 {
324 if (bw > CHANNEL_WIDTH_160)
325 return 0;
326
327 if (id >= center_chs_5g_num(bw))
328 return 0;
329
330 return center_chs_5g_by_bw[bw].chs[id];
331 }
332
333 /*
334 * Get available op channels by @param cch, @param bw
335 * @cch: the given center channel
336 * @bw: the given bandwidth
337 * @op_chs: the pointer to return pointer of op channel array
338 * @op_ch_num: the pointer to return pointer of op channel number
339 *
340 * return valid (1) or not (0)
341 */
rtw_get_op_chs_by_cch_bw(u8 cch,u8 bw,u8 ** op_chs,u8 * op_ch_num)342 u8 rtw_get_op_chs_by_cch_bw(u8 cch, u8 bw, u8 **op_chs, u8 *op_ch_num)
343 {
344 int i;
345 struct center_chs_ent_t *c_chs_ent = NULL;
346 struct op_chs_ent_t *op_chs_ent = NULL;
347 u8 valid = 1;
348
349 if (cch <= 14
350 && bw <= CHANNEL_WIDTH_40
351 ) {
352 c_chs_ent = ¢er_chs_2g_by_bw[bw];
353 op_chs_ent = &op_chs_of_cch_2g_by_bw[bw];
354 } else if (cch >= 36 && cch <= 177
355 && bw <= CHANNEL_WIDTH_160
356 ) {
357 c_chs_ent = ¢er_chs_5g_by_bw[bw];
358 op_chs_ent = &op_chs_of_cch_5g_by_bw[bw];
359 } else {
360 valid = 0;
361 goto exit;
362 }
363
364 for (i = 0; i < c_chs_ent->ch_num; i++)
365 if (cch == *(c_chs_ent->chs + i))
366 break;
367
368 if (i == c_chs_ent->ch_num) {
369 valid = 0;
370 goto exit;
371 }
372
373 *op_chs = op_chs_ent->chs + op_chs_ent->ch_num * i;
374 *op_ch_num = op_chs_ent->ch_num;
375
376 exit:
377 return valid;
378 }
379
rtw_get_offset_by_chbw(u8 ch,u8 bw,u8 * r_offset)380 u8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset)
381 {
382 u8 valid = 1;
383 u8 offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
384
385 if (bw == CHANNEL_WIDTH_20)
386 goto exit;
387
388 if (bw >= CHANNEL_WIDTH_80 && ch <= 14) {
389 valid = 0;
390 goto exit;
391 }
392
393 if (ch >= 1 && ch <= 4)
394 offset = HAL_PRIME_CHNL_OFFSET_LOWER;
395 else if (ch >= 5 && ch <= 9) {
396 if (*r_offset == HAL_PRIME_CHNL_OFFSET_LOWER || *r_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
397 offset = *r_offset; /* both lower and upper is valid, obey input value */
398 else
399 offset = HAL_PRIME_CHNL_OFFSET_UPPER; /* default use upper */
400 } else if (ch >= 10 && ch <= 13)
401 offset = HAL_PRIME_CHNL_OFFSET_UPPER;
402 else if (ch == 14) {
403 valid = 0; /* ch14 doesn't support 40MHz bandwidth */
404 goto exit;
405 } else if (ch >= 36 && ch <= 177) {
406 switch (ch) {
407 case 36:
408 case 44:
409 case 52:
410 case 60:
411 case 100:
412 case 108:
413 case 116:
414 case 124:
415 case 132:
416 case 140:
417 case 149:
418 case 157:
419 case 165:
420 case 173:
421 offset = HAL_PRIME_CHNL_OFFSET_LOWER;
422 break;
423 case 40:
424 case 48:
425 case 56:
426 case 64:
427 case 104:
428 case 112:
429 case 120:
430 case 128:
431 case 136:
432 case 144:
433 case 153:
434 case 161:
435 case 169:
436 case 177:
437 offset = HAL_PRIME_CHNL_OFFSET_UPPER;
438 break;
439 default:
440 valid = 0;
441 break;
442 }
443 } else
444 valid = 0;
445
446 exit:
447 if (valid && r_offset)
448 *r_offset = offset;
449 return valid;
450 }
451
rtw_get_center_ch(u8 ch,u8 bw,u8 offset)452 u8 rtw_get_center_ch(u8 ch, u8 bw, u8 offset)
453 {
454 u8 cch = ch;
455
456 if (bw == CHANNEL_WIDTH_160) {
457 if (ch % 4 == 0) {
458 if (ch >= 36 && ch <= 64)
459 cch = 50;
460 else if (ch >= 100 && ch <= 128)
461 cch = 114;
462 } else if (ch % 4 == 1) {
463 if (ch >= 149 && ch <= 177)
464 cch = 163;
465 }
466
467 } else if (bw == CHANNEL_WIDTH_80) {
468 if (ch <= 14)
469 cch = 7; /* special case for 2.4G */
470 else if (ch % 4 == 0) {
471 if (ch >= 36 && ch <= 48)
472 cch = 42;
473 else if (ch >= 52 && ch <= 64)
474 cch = 58;
475 else if (ch >= 100 && ch <= 112)
476 cch = 106;
477 else if (ch >= 116 && ch <= 128)
478 cch = 122;
479 else if (ch >= 132 && ch <= 144)
480 cch = 138;
481 } else if (ch % 4 == 1) {
482 if (ch >= 149 && ch <= 161)
483 cch = 155;
484 else if (ch >= 165 && ch <= 177)
485 cch = 171;
486 }
487
488 } else if (bw == CHANNEL_WIDTH_40) {
489 if (offset == HAL_PRIME_CHNL_OFFSET_LOWER)
490 cch = ch + 2;
491 else if (offset == HAL_PRIME_CHNL_OFFSET_UPPER)
492 cch = ch - 2;
493
494 } else if (bw == CHANNEL_WIDTH_20
495 || bw == CHANNEL_WIDTH_10
496 || bw == CHANNEL_WIDTH_5
497 )
498 ; /* same as ch */
499 else
500 rtw_warn_on(1);
501
502 return cch;
503 }
504
rtw_get_ch_group(u8 ch,u8 * group,u8 * cck_group)505 u8 rtw_get_ch_group(u8 ch, u8 *group, u8 *cck_group)
506 {
507 BAND_TYPE band = BAND_MAX;
508 s8 gp = -1, cck_gp = -1;
509
510 if (ch <= 14) {
511 band = BAND_ON_2_4G;
512
513 if (1 <= ch && ch <= 2)
514 gp = 0;
515 else if (3 <= ch && ch <= 5)
516 gp = 1;
517 else if (6 <= ch && ch <= 8)
518 gp = 2;
519 else if (9 <= ch && ch <= 11)
520 gp = 3;
521 else if (12 <= ch && ch <= 14)
522 gp = 4;
523 else
524 band = BAND_MAX;
525
526 if (ch == 14)
527 cck_gp = 5;
528 else
529 cck_gp = gp;
530 } else {
531 band = BAND_ON_5G;
532
533 if (36 <= ch && ch <= 42)
534 gp = 0;
535 else if (44 <= ch && ch <= 48)
536 gp = 1;
537 else if (50 <= ch && ch <= 58)
538 gp = 2;
539 else if (60 <= ch && ch <= 64)
540 gp = 3;
541 else if (100 <= ch && ch <= 106)
542 gp = 4;
543 else if (108 <= ch && ch <= 114)
544 gp = 5;
545 else if (116 <= ch && ch <= 122)
546 gp = 6;
547 else if (124 <= ch && ch <= 130)
548 gp = 7;
549 else if (132 <= ch && ch <= 138)
550 gp = 8;
551 else if (140 <= ch && ch <= 144)
552 gp = 9;
553 else if (149 <= ch && ch <= 155)
554 gp = 10;
555 else if (157 <= ch && ch <= 161)
556 gp = 11;
557 else if (165 <= ch && ch <= 171)
558 gp = 12;
559 else if (173 <= ch && ch <= 177)
560 gp = 13;
561 else
562 band = BAND_MAX;
563 }
564
565 if (band == BAND_MAX
566 || (band == BAND_ON_2_4G && cck_gp == -1)
567 || gp == -1
568 ) {
569 RTW_WARN("%s invalid channel:%u", __func__, ch);
570 rtw_warn_on(1);
571 goto exit;
572 }
573
574 if (group)
575 *group = gp;
576 if (cck_group && band == BAND_ON_2_4G)
577 *cck_group = cck_gp;
578
579 exit:
580 return band;
581 }
582
rtw_ch2freq(int chan)583 int rtw_ch2freq(int chan)
584 {
585 /* see 802.11 17.3.8.3.2 and Annex J
586 * there are overlapping channel numbers in 5GHz and 2GHz bands */
587
588 /*
589 * RTK: don't consider the overlapping channel numbers: 5G channel <= 14,
590 * because we don't support it. simply judge from channel number
591 */
592
593 if (chan >= 1 && chan <= 14) {
594 if (chan == 14)
595 return 2484;
596 else if (chan < 14)
597 return 2407 + chan * 5;
598 } else if (chan >= 36 && chan <= 177)
599 return 5000 + chan * 5;
600
601 return 0; /* not supported */
602 }
603
rtw_freq2ch(int freq)604 int rtw_freq2ch(int freq)
605 {
606 /* see 802.11 17.3.8.3.2 and Annex J */
607 if (freq == 2484)
608 return 14;
609 else if (freq < 2484)
610 return (freq - 2407) / 5;
611 else if (freq >= 4910 && freq <= 4980)
612 return (freq - 4000) / 5;
613 else if (freq <= 45000) /* DMG band lower limit */
614 return (freq - 5000) / 5;
615 else if (freq >= 58320 && freq <= 64800)
616 return (freq - 56160) / 2160;
617 else
618 return 0;
619 }
620
rtw_chbw_to_freq_range(u8 ch,u8 bw,u8 offset,u32 * hi,u32 * lo)621 bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo)
622 {
623 u8 c_ch;
624 u32 freq;
625 u32 hi_ret = 0, lo_ret = 0;
626 bool valid = _FALSE;
627
628 if (hi)
629 *hi = 0;
630 if (lo)
631 *lo = 0;
632
633 c_ch = rtw_get_center_ch(ch, bw, offset);
634 freq = rtw_ch2freq(c_ch);
635
636 if (!freq) {
637 rtw_warn_on(1);
638 goto exit;
639 }
640
641 if (bw == CHANNEL_WIDTH_160) {
642 hi_ret = freq + 80;
643 lo_ret = freq - 80;
644 } else if (bw == CHANNEL_WIDTH_80) {
645 hi_ret = freq + 40;
646 lo_ret = freq - 40;
647 } else if (bw == CHANNEL_WIDTH_40) {
648 hi_ret = freq + 20;
649 lo_ret = freq - 20;
650 } else if (bw == CHANNEL_WIDTH_20) {
651 hi_ret = freq + 10;
652 lo_ret = freq - 10;
653 } else
654 rtw_warn_on(1);
655
656 if (hi)
657 *hi = hi_ret;
658 if (lo)
659 *lo = lo_ret;
660
661 valid = _TRUE;
662
663 exit:
664 return valid;
665 }
666
667 const char *const _ch_width_str[CHANNEL_WIDTH_MAX] = {
668 "20MHz",
669 "40MHz",
670 "80MHz",
671 "160MHz",
672 "80_80MHz",
673 "5MHz",
674 "10MHz",
675 };
676
677 const u8 _ch_width_to_bw_cap[CHANNEL_WIDTH_MAX] = {
678 BW_CAP_20M,
679 BW_CAP_40M,
680 BW_CAP_80M,
681 BW_CAP_160M,
682 BW_CAP_80_80M,
683 BW_CAP_5M,
684 BW_CAP_10M,
685 };
686
687 const char *const _band_str[] = {
688 "2.4G",
689 "5G",
690 "BAND_MAX",
691 };
692
693 const u8 _band_to_band_cap[] = {
694 BAND_CAP_2G,
695 BAND_CAP_5G,
696 0,
697 };
698
699 const char *const _opc_bw_str[OPC_BW_NUM] = {
700 "20M ", /* OPC_BW20 */
701 "40M+", /* OPC_BW40PLUS */
702 "40M-", /* OPC_BW40MINUS */
703 "80M ", /* OPC_BW80 */
704 "160M ", /* OPC_BW160 */
705 "80+80M ", /* OPC_BW80P80 */
706 };
707
708 const u8 _opc_bw_to_ch_width[OPC_BW_NUM] = {
709 CHANNEL_WIDTH_20, /* OPC_BW20 */
710 CHANNEL_WIDTH_40, /* OPC_BW40PLUS */
711 CHANNEL_WIDTH_40, /* OPC_BW40MINUS */
712 CHANNEL_WIDTH_80, /* OPC_BW80 */
713 CHANNEL_WIDTH_160, /* OPC_BW160 */
714 CHANNEL_WIDTH_80_80, /* OPC_BW80P80 */
715 };
716
717 /* 802.11-2016 Table E-4, partial */
718 static const struct op_class_map global_op_class[RTW_GLOBAL_OP_CLASS_NUM] = {
719 /* 2G ch1~13, 20M */
720 {81, BAND_ON_2_4G, OPC_BW20, 0x00001FFF},
721 /* 2G ch14, 20M */
722 {82, BAND_ON_2_4G, OPC_BW20, 0x00002000},
723 /* 2G, 40M */
724 {83, BAND_ON_2_4G, OPC_BW40PLUS, 0x000001FF},
725 {84, BAND_ON_2_4G, OPC_BW40MINUS, 0x00001FF0},
726 /* 5G band 1, 20M & 40M */
727 {115, BAND_ON_5G, OPC_BW20, 0x0000000F},
728 {116, BAND_ON_5G, OPC_BW40PLUS, 0x00000005},
729 {117, BAND_ON_5G, OPC_BW40MINUS, 0x0000000A},
730 /* 5G band 2, 20M & 40M */
731 {118, BAND_ON_5G, OPC_BW20, 0x000000F0},
732 {119, BAND_ON_5G, OPC_BW40PLUS, 0x00000050},
733 {120, BAND_ON_5G, OPC_BW40MINUS, 0x000000A0},
734 /* 5G band 3, 20M & 40M */
735 {121, BAND_ON_5G, OPC_BW20, 0x000FFF00},
736 {122, BAND_ON_5G, OPC_BW40PLUS, 0x00055500},
737 {123, BAND_ON_5G, OPC_BW40MINUS, 0x000AAA00},
738 /* 5G band 4, 20M & 40M */
739 {124, BAND_ON_5G, OPC_BW20, 0x00F00000},
740 {125, BAND_ON_5G, OPC_BW20, 0x03F00000},
741 {126, BAND_ON_5G, OPC_BW40PLUS, 0x00500000},
742 {127, BAND_ON_5G, OPC_BW40MINUS, 0x00A00000},
743 /* 5G, 80M & 160M */
744 {128, BAND_ON_5G, OPC_BW80, 0x00FFFFFF},
745 {129, BAND_ON_5G, OPC_BW160, 0x0000FFFF},
746 #if 0 /* TODO */
747 /* 5G, 80+80M */
748 {130, BAND_ON_5G, OPC_BW80P80, 0x0FFFFFF},
749 #endif
750 };
751
global_op_class_get_ch(u8 gid,u8 cid)752 static u8 global_op_class_get_ch(u8 gid, u8 cid)
753 {
754 if (global_op_class[gid].band == BAND_ON_2_4G)
755 return center_ch_2g[cid];
756 if (global_op_class[gid].band == BAND_ON_5G)
757 return center_ch_5g_20m[cid];
758
759 return 0;
760 }
761
global_op_class_get_cid(u8 gid,u8 ch)762 static u8 global_op_class_get_cid(u8 gid, u8 ch)
763 {
764 if (global_op_class[gid].band == BAND_ON_2_4G)
765 return ch_to_cch_2g_idx(ch);
766 else if (global_op_class[gid].band == BAND_ON_5G)
767 return ch_to_cch_5g_20m_idx(ch);
768
769 return 255;
770 }
771
dump_op_class_ch_title(void * sel)772 static void dump_op_class_ch_title(void *sel)
773 {
774 RTW_PRINT_SEL(sel, "%-5s %-4s %-7s ch_list\n"
775 , "class", "band", "bw");
776 }
777
dump_op_class_ch_single(void * sel,u8 gid,u32 ch_bmp,bool negtive)778 static void dump_op_class_ch_single(void *sel, u8 gid, u32 ch_bmp, bool negtive)
779 {
780 u8 i;
781 u8 ch;
782
783 RTW_PRINT_SEL(sel, "%5u %4s %7s"
784 , global_op_class[gid].op_class
785 , band_str(global_op_class[gid].band)
786 , opc_bw_str(global_op_class[gid].bw)
787 );
788
789 if ((ch_bmp | global_op_class[gid].ch_bmp) != global_op_class[gid].ch_bmp) {
790 RTW_WARN("invalid ch_map:0x%x of global op_class:%u", ch_bmp, global_op_class[gid].op_class);
791 rtw_warn_on(1);
792 }
793
794 ch_bmp &= global_op_class[gid].ch_bmp;
795 if (negtive)
796 ch_bmp = (~ch_bmp) & global_op_class[gid].ch_bmp;
797
798 for (i = 0; i < 32; i++) {
799 if (!(ch_bmp & BIT(i)))
800 continue;
801
802 ch = global_op_class_get_ch(gid, i);
803 if (!ch) {
804 rtw_warn_on(1);
805 continue;
806 }
807
808 _RTW_PRINT_SEL(sel, " %u", ch);
809 }
810
811 _RTW_PRINT_SEL(sel, "\n");
812 }
813
dump_global_op_class(void * sel)814 void dump_global_op_class(void *sel)
815 {
816 u8 i;
817
818 dump_op_class_ch_title(sel);
819
820 for (i = 0; i < RTW_GLOBAL_OP_CLASS_NUM; i++)
821 dump_op_class_ch_single(sel, i, global_op_class[i].ch_bmp, 0);
822 }
823
rtw_get_op_class_by_chbw(u8 ch,u8 bw,u8 offset)824 u8 rtw_get_op_class_by_chbw(u8 ch, u8 bw, u8 offset)
825 {
826 BAND_TYPE band = BAND_MAX;
827 int i, j;
828 u8 op_class = 0; /* invalid */
829
830 if (rtw_is_2g_ch(ch))
831 band = BAND_ON_2_4G;
832 else if (rtw_is_5g_ch(ch))
833 band = BAND_ON_5G;
834 else
835 goto exit;
836
837 switch (bw) {
838 case CHANNEL_WIDTH_20:
839 case CHANNEL_WIDTH_40:
840 case CHANNEL_WIDTH_80:
841 case CHANNEL_WIDTH_160:
842 #if 0 /* TODO */
843 case CHANNEL_WIDTH_80_80:
844 #endif
845 break;
846 default:
847 goto exit;
848 }
849
850 for (i = 0; i < RTW_GLOBAL_OP_CLASS_NUM; i++) {
851 if (band != global_op_class[i].band)
852 continue;
853
854 if (opc_bw_to_ch_width(global_op_class[i].bw) != bw)
855 continue;
856
857 if ((global_op_class[i].bw == OPC_BW40PLUS
858 && offset != HAL_PRIME_CHNL_OFFSET_LOWER)
859 || (global_op_class[i].bw == OPC_BW40MINUS
860 && offset != HAL_PRIME_CHNL_OFFSET_UPPER)
861 )
862 continue;
863
864 for (j = 0; j < 32; j++) {
865 if (!(global_op_class[i].ch_bmp & BIT(j)))
866 continue;
867 if (ch == global_op_class_get_ch(i, j))
868 goto get;
869 }
870 }
871
872 get:
873 if (i < RTW_GLOBAL_OP_CLASS_NUM) {
874 #if 0 /* TODO */
875 if (bw == CHANNEL_WIDTH_80_80) {
876 /* search another ch */
877 u8 k;
878
879 for (k = 0; k < 32; k++) {
880 if (k == j || !(global_op_class[i].ch_bmp & BIT(k)))
881 continue;
882 if (ch2 == global_op_class_get_ch(i, k))
883 break;
884 }
885
886 if (k >= 32)
887 goto exit;
888 }
889 #endif
890
891 op_class = global_op_class[i].op_class;
892 }
893
894 exit:
895 return op_class;
896 }
897
rtw_get_bw_offset_by_op_class_ch(u8 op_class,u8 ch,u8 * bw,u8 * offset)898 u8 rtw_get_bw_offset_by_op_class_ch(u8 op_class, u8 ch, u8 *bw, u8 *offset)
899 {
900 u8 valid = 0;
901 int i;
902
903 for (i = 0; i < RTW_GLOBAL_OP_CLASS_NUM; i++) {
904 if (global_op_class[i].op_class != op_class)
905 continue;
906 }
907
908 if (i >= RTW_GLOBAL_OP_CLASS_NUM)
909 goto exit;
910
911 *bw = opc_bw_to_ch_width(global_op_class[i].bw);
912
913 if (global_op_class[i].bw == OPC_BW40PLUS)
914 *offset = HAL_PRIME_CHNL_OFFSET_LOWER;
915 else if (global_op_class[i].bw == OPC_BW40MINUS)
916 *offset = HAL_PRIME_CHNL_OFFSET_UPPER;
917
918 if (rtw_get_offset_by_chbw(ch, *bw, offset))
919 valid = 1;
920
921 exit:
922 return valid;
923 }
924
925 /*
926 * @chset: if specified, init op_class_ch_bmp to fit in current channel plan
927 * if not, init, only according to capability setting
928 */
init_op_class_ch_bmp(_adapter * adapter,RT_CHANNEL_INFO * chset,u32 op_class_ch_bmp[])929 u8 init_op_class_ch_bmp(_adapter *adapter, RT_CHANNEL_INFO *chset, u32 op_class_ch_bmp[])
930 {
931 struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
932 struct registry_priv *regsty = adapter_to_regsty(adapter);
933 u8 ch, bw, offset, pre_cch, cch;
934 int i, j;
935 u8 op_class_num = 0;
936 u8 band_bmp = 0;
937 u8 bw_bmp[BAND_MAX] = {0};
938 u32 tmp_ch_bmp;
939
940 if (IsSupported24G(regsty->wireless_mode) && hal_chk_band_cap(adapter, BAND_CAP_2G))
941 band_bmp |= BAND_CAP_2G;
942 if (is_supported_5g(regsty->wireless_mode) && hal_chk_band_cap(adapter, BAND_CAP_5G))
943 band_bmp |= BAND_CAP_5G;
944
945 bw_bmp[BAND_ON_2_4G] = (ch_width_to_bw_cap(REGSTY_BW_2G(regsty) + 1) - 1) & (GET_HAL_SPEC(adapter)->bw_cap);
946 bw_bmp[BAND_ON_5G] = (ch_width_to_bw_cap(REGSTY_BW_5G(regsty) + 1) - 1) & (GET_HAL_SPEC(adapter)->bw_cap);
947 if (!REGSTY_IS_11AC_ENABLE(regsty)
948 || !is_supported_vht(regsty->wireless_mode)
949 || (chset && rfctl->country_ent && !COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
950 )
951 bw_bmp[BAND_ON_5G] &= ~(BW_CAP_80M | BW_CAP_160M);
952
953 if (0) {
954 RTW_INFO("REGSTY_BW_2G(regsty):%u\n", REGSTY_BW_2G(regsty));
955 RTW_INFO("REGSTY_BW_5G(regsty):%u\n", REGSTY_BW_5G(regsty));
956 RTW_INFO("GET_HAL_SPEC(adapter)->bw_cap:0x%x\n", GET_HAL_SPEC(adapter)->bw_cap);
957 RTW_INFO("band_bmp:0x%x\n", band_bmp);
958 RTW_INFO("bw_bmp[2G]:0x%x\n", bw_bmp[BAND_ON_2_4G]);
959 RTW_INFO("bw_bmp[5G]:0x%x\n", bw_bmp[BAND_ON_5G]);
960 }
961
962 for (i = 0; i < RTW_GLOBAL_OP_CLASS_NUM; i++) {
963 tmp_ch_bmp = 0;
964
965 if (!(band_bmp & band_to_band_cap(global_op_class[i].band)))
966 goto assign_ch_bmp;
967
968 switch (global_op_class[i].bw) {
969 case OPC_BW20:
970 bw = CHANNEL_WIDTH_20;
971 offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
972 break;
973 case OPC_BW40PLUS:
974 bw = CHANNEL_WIDTH_40;
975 offset = HAL_PRIME_CHNL_OFFSET_LOWER;
976 break;
977 case OPC_BW40MINUS:
978 bw = CHANNEL_WIDTH_40;
979 offset = HAL_PRIME_CHNL_OFFSET_UPPER;
980 break;
981 case OPC_BW80:
982 bw = CHANNEL_WIDTH_80;
983 offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
984 break;
985 case OPC_BW160:
986 bw = CHANNEL_WIDTH_160;
987 offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
988 break;
989 case OPC_BW80P80: /* TODO */
990 default:
991 goto assign_ch_bmp;
992 }
993
994 if (!(bw_bmp[global_op_class[i].band] & ch_width_to_bw_cap(bw)))
995 goto assign_ch_bmp;
996
997 pre_cch = 0;
998 for (j = 0; j < 32; j++) {
999 u8 *op_chs;
1000 u8 op_ch_num;
1001 u8 k;
1002 int chset_idx;
1003
1004 if (!(global_op_class[i].ch_bmp & BIT(j)))
1005 continue;
1006
1007 ch = global_op_class_get_ch(i, j);
1008 cch = rtw_get_center_ch(ch ,bw, offset);
1009 /* bypass invalid or the same with previous one(already cheked) */
1010 if (!cch || cch == pre_cch)
1011 continue;
1012 pre_cch = cch;
1013
1014 if (!rtw_get_op_chs_by_cch_bw(cch, bw, &op_chs, &op_ch_num))
1015 continue;
1016
1017 for (k = 0; k < op_ch_num; k++) {
1018 if ((offset == HAL_PRIME_CHNL_OFFSET_LOWER
1019 && *(op_chs + k) > cch)
1020 || (offset == HAL_PRIME_CHNL_OFFSET_UPPER
1021 && *(op_chs + k) < cch))
1022 continue;
1023 if (chset) {
1024 chset_idx = rtw_chset_search_ch(chset, *(op_chs + k));
1025 if (chset_idx == -1)
1026 break;
1027 }
1028
1029 if (chset) {
1030 if (chset[chset_idx].dfs && rtw_rfctl_dfs_domain_unknown(rfctl))
1031 break;
1032 if (chset[chset_idx].ScanType == SCAN_PASSIVE)
1033 break;
1034 }
1035 }
1036 if (k < op_ch_num) /* not all op_chs are usable */
1037 continue;
1038
1039 for (k = 0; k < op_ch_num; k++) {
1040 if ((offset == HAL_PRIME_CHNL_OFFSET_LOWER
1041 && *(op_chs + k) > cch)
1042 || (offset == HAL_PRIME_CHNL_OFFSET_UPPER
1043 && *(op_chs + k) < cch))
1044 continue;
1045 tmp_ch_bmp |= BIT(global_op_class_get_cid(i, *(op_chs + k)));
1046 }
1047 }
1048
1049 assign_ch_bmp:
1050 op_class_ch_bmp[i] = tmp_ch_bmp;
1051
1052 if (op_class_ch_bmp[i])
1053 op_class_num++;
1054 }
1055
1056 return op_class_num;
1057 }
1058
dump_cap_spt_op_class_ch(void * sel,struct rf_ctl_t * rfctl,bool negtive)1059 void dump_cap_spt_op_class_ch(void *sel, struct rf_ctl_t *rfctl, bool negtive)
1060 {
1061 u8 i;
1062
1063 dump_op_class_ch_title(sel);
1064
1065 for (i = 0; i < RTW_GLOBAL_OP_CLASS_NUM; i++) {
1066 if (!rfctl->cap_spt_op_class_ch_bmp[i])
1067 continue;
1068 dump_op_class_ch_single(sel, i, rfctl->cap_spt_op_class_ch_bmp[i], negtive);
1069 }
1070
1071 RTW_PRINT_SEL(sel, "supported op_class number:%d\n", rfctl->cap_spt_op_class_num);
1072 }
1073
dump_cur_spt_op_class_ch(void * sel,struct rf_ctl_t * rfctl,bool negtive)1074 void dump_cur_spt_op_class_ch(void *sel, struct rf_ctl_t *rfctl, bool negtive)
1075 {
1076 u8 i;
1077
1078 dump_op_class_ch_title(sel);
1079
1080 for (i = 0; i < RTW_GLOBAL_OP_CLASS_NUM; i++) {
1081 if (!rfctl->cur_spt_op_class_ch_bmp[i])
1082 continue;
1083 dump_op_class_ch_single(sel, i, rfctl->cur_spt_op_class_ch_bmp[i], negtive);
1084 }
1085
1086 RTW_PRINT_SEL(sel, "supported op_class number:%d\n", rfctl->cur_spt_op_class_num);
1087 }
1088
1089 const u8 _rf_type_to_rf_tx_cnt[RF_TYPE_MAX] = {
1090 1, /* RF_1T1R */
1091 1, /* RF_1T2R */
1092 2, /* RF_2T1R */
1093 2, /* RF_2T2R */
1094 1, /* RF_1T3R */
1095 2, /* RF_2T3R */
1096 3, /* RF_3T1R */
1097 3, /* RF_3T2R */
1098 3, /* RF_3T3R */
1099 1, /* RF_1T4R */
1100 2, /* RF_2T4R */
1101 3, /* RF_3T4R */
1102 4, /* RF_4T1R */
1103 4, /* RF_4T2R */
1104 4, /* RF_4T3R */
1105 4, /* RF_4T4R */
1106 };
1107
1108 const u8 _rf_type_to_rf_rx_cnt[RF_TYPE_MAX] = {
1109 1, /* RF_1T1R */
1110 2, /* RF_1T2R */
1111 1, /* RF_2T1R */
1112 2, /* RF_2T2R */
1113 3, /* RF_1T3R */
1114 3, /* RF_2T3R */
1115 1, /* RF_3T1R */
1116 2, /* RF_3T2R */
1117 3, /* RF_3T3R */
1118 4, /* RF_1T4R */
1119 4, /* RF_2T4R */
1120 4, /* RF_3T4R */
1121 1, /* RF_4T1R */
1122 2, /* RF_4T2R */
1123 3, /* RF_4T3R */
1124 4, /* RF_4T4R */
1125 };
1126
1127 const char *const _rf_type_to_rfpath_str[RF_TYPE_MAX] = {
1128 "RF_1T1R", /* RF_1T1R */
1129 "RF_1T2R", /* RF_1T2R */
1130 "RF_2T1R", /* RF_2T1R */
1131 "RF_2T2R", /* RF_2T2R */
1132 "RF_1T3R", /* RF_1T3R */
1133 "RF_2T3R", /* RF_2T3R */
1134 "RF_3T1R", /* RF_3T1R */
1135 "RF_3T2R", /* RF_3T2R */
1136 "RF_3T3R", /* RF_3T3R */
1137 "RF_1T4R", /* RF_1T4R */
1138 "RF_2T4R", /* RF_2T4R */
1139 "RF_3T4R", /* RF_3T4R */
1140 "RF_4T1R", /* RF_4T1R */
1141 "RF_4T2R", /* RF_4T2R */
1142 "RF_4T3R", /* RF_4T3R */
1143 "RF_4T4R", /* RF_4T4R */
1144 };
1145
rf_type_to_default_trx_bmp(enum rf_type rf,enum bb_path * tx,enum bb_path * rx)1146 void rf_type_to_default_trx_bmp(enum rf_type rf, enum bb_path *tx, enum bb_path *rx)
1147 {
1148 u8 tx_num = rf_type_to_rf_tx_cnt(rf);
1149 u8 rx_num = rf_type_to_rf_rx_cnt(rf);
1150 int i;
1151
1152 *tx = *rx = 0;
1153
1154 for (i = 0; i < tx_num; i++)
1155 *tx |= BIT(i);
1156 for (i = 0; i < rx_num; i++)
1157 *rx |= BIT(i);
1158 }
1159
1160 static const u8 _trx_num_to_rf_type[RF_PATH_MAX][RF_PATH_MAX] = {
1161 {RF_1T1R, RF_1T2R, RF_1T3R, RF_1T4R},
1162 {RF_2T1R, RF_2T2R, RF_2T3R, RF_2T4R},
1163 {RF_3T1R, RF_3T2R, RF_3T3R, RF_3T4R},
1164 {RF_4T1R, RF_4T2R, RF_4T3R, RF_4T4R},
1165 };
1166
trx_num_to_rf_type(u8 tx_num,u8 rx_num)1167 enum rf_type trx_num_to_rf_type(u8 tx_num, u8 rx_num)
1168 {
1169 if (tx_num > 0 && tx_num <= RF_PATH_MAX && rx_num > 0 && rx_num <= RF_PATH_MAX)
1170 return _trx_num_to_rf_type[tx_num - 1][rx_num - 1];
1171 return RF_TYPE_MAX;
1172 }
1173
trx_bmp_to_rf_type(u8 tx_bmp,u8 rx_bmp)1174 enum rf_type trx_bmp_to_rf_type(u8 tx_bmp, u8 rx_bmp)
1175 {
1176 u8 tx_num = 0;
1177 u8 rx_num = 0;
1178 int i;
1179
1180 for (i = 0; i < RF_PATH_MAX; i++) {
1181 if (tx_bmp >> i & BIT0)
1182 tx_num++;
1183 if (rx_bmp >> i & BIT0)
1184 rx_num++;
1185 }
1186
1187 return trx_num_to_rf_type(tx_num, rx_num);
1188 }
1189
rf_type_is_a_in_b(enum rf_type a,enum rf_type b)1190 bool rf_type_is_a_in_b(enum rf_type a, enum rf_type b)
1191 {
1192 return rf_type_to_rf_tx_cnt(a) <= rf_type_to_rf_tx_cnt(b)
1193 && rf_type_to_rf_rx_cnt(a) <= rf_type_to_rf_rx_cnt(b);
1194 }
1195
rtw_path_bmp_limit_from_higher(u8 * bmp,u8 * bmp_bit_cnt,u8 bit_cnt_lmt)1196 static void rtw_path_bmp_limit_from_higher(u8 *bmp, u8 *bmp_bit_cnt, u8 bit_cnt_lmt)
1197 {
1198 int i;
1199
1200 for (i = RF_PATH_MAX - 1; *bmp_bit_cnt > bit_cnt_lmt && i >= 0; i--) {
1201 if (*bmp & BIT(i)) {
1202 *bmp &= ~BIT(i);
1203 (*bmp_bit_cnt)--;
1204 }
1205 }
1206 }
1207
rtw_restrict_trx_path_bmp_by_trx_num_lmt(u8 trx_path_bmp,u8 tx_num_lmt,u8 rx_num_lmt,u8 * tx_num,u8 * rx_num)1208 u8 rtw_restrict_trx_path_bmp_by_trx_num_lmt(u8 trx_path_bmp, u8 tx_num_lmt, u8 rx_num_lmt, u8 *tx_num, u8 *rx_num)
1209 {
1210 u8 bmp_tx = (trx_path_bmp & 0xF0) >> 4;
1211 u8 bmp_rx = trx_path_bmp & 0x0F;
1212 u8 bmp_tx_num = 0, bmp_rx_num = 0;
1213 enum rf_type ret_type = RF_TYPE_MAX;
1214 int i, j;
1215
1216 for (i = 0; i < RF_PATH_MAX; i++) {
1217 if (bmp_tx & BIT(i))
1218 bmp_tx_num++;
1219 if (bmp_rx & BIT(i))
1220 bmp_rx_num++;
1221 }
1222
1223 /* limit higher bit first according to input type */
1224 if (tx_num_lmt)
1225 rtw_path_bmp_limit_from_higher(&bmp_tx, &bmp_tx_num, tx_num_lmt);
1226 if (rx_num_lmt)
1227 rtw_path_bmp_limit_from_higher(&bmp_rx, &bmp_rx_num, rx_num_lmt);
1228
1229 /* search for valid rf_type (larger RX prefer) */
1230 for (j = bmp_rx_num; j > 0; j--) {
1231 for (i = bmp_tx_num; i > 0; i--) {
1232 ret_type = trx_num_to_rf_type(i, j);
1233 if (RF_TYPE_VALID(ret_type)) {
1234 rtw_path_bmp_limit_from_higher(&bmp_tx, &bmp_tx_num, i);
1235 rtw_path_bmp_limit_from_higher(&bmp_rx, &bmp_rx_num, j);
1236 if (tx_num)
1237 *tx_num = bmp_tx_num;
1238 if (rx_num)
1239 *rx_num = bmp_rx_num;
1240 goto exit;
1241 }
1242 }
1243 }
1244
1245 exit:
1246 return RF_TYPE_VALID(ret_type) ? ((bmp_tx << 4) | bmp_rx) : 0x00;
1247 }
1248
rtw_restrict_trx_path_bmp_by_rftype(u8 trx_path_bmp,enum rf_type type,u8 * tx_num,u8 * rx_num)1249 u8 rtw_restrict_trx_path_bmp_by_rftype(u8 trx_path_bmp, enum rf_type type, u8 *tx_num, u8 *rx_num)
1250 {
1251 return rtw_restrict_trx_path_bmp_by_trx_num_lmt(trx_path_bmp
1252 , rf_type_to_rf_tx_cnt(type), rf_type_to_rf_rx_cnt(type), tx_num, rx_num);
1253 }
1254
1255 /* config to non N-TX value, path with lower index prefer */
tx_path_nss_set_default(enum bb_path txpath_nss[],u8 txpath_num_nss[],u8 txpath)1256 void tx_path_nss_set_default(enum bb_path txpath_nss[], u8 txpath_num_nss[], u8 txpath)
1257 {
1258 int i, j;
1259 u8 cnt;
1260
1261 for (i = 4; i > 0; i--) {
1262 cnt = 0;
1263 txpath_nss[i - 1] = 0;
1264 for (j = 0; j < RF_PATH_MAX; j++) {
1265 if (txpath & BIT(j)) {
1266 txpath_nss[i - 1] |= BIT(j);
1267 if (++cnt == i)
1268 break;
1269 }
1270 }
1271 txpath_num_nss[i - 1] = i;
1272 }
1273 }
1274
1275 /* config to full N-TX value */
tx_path_nss_set_full_tx(enum bb_path txpath_nss[],u8 txpath_num_nss[],u8 txpath)1276 void tx_path_nss_set_full_tx(enum bb_path txpath_nss[], u8 txpath_num_nss[], u8 txpath)
1277 {
1278 u8 tx_num = 0;
1279 int i;
1280
1281 for (i = 0; i < RF_PATH_MAX; i++)
1282 if (txpath & BIT(i))
1283 tx_num++;
1284
1285 for (i = 4; i > 0; i--) {
1286 txpath_nss[i - 1] = txpath;
1287 txpath_num_nss[i - 1] = tx_num;
1288 }
1289 }
1290
1291 const char *const _regd_str[] = {
1292 "NONE",
1293 "FCC",
1294 "MKK",
1295 "ETSI",
1296 "IC",
1297 "KCC",
1298 "ACMA",
1299 "CHILE",
1300 "UKRAINE",
1301 "MEXICO",
1302 "CN",
1303 "WW",
1304 };
1305
1306 /*
1307 * input with txpwr value in unit of txpwr index
1308 * return string in length 6 at least (for -xx.xx)
1309 */
txpwr_idx_get_dbm_str(s8 idx,u8 txgi_max,u8 txgi_pdbm,SIZE_T cwidth,char dbm_str[],u8 dbm_str_len)1310 void txpwr_idx_get_dbm_str(s8 idx, u8 txgi_max, u8 txgi_pdbm, SIZE_T cwidth, char dbm_str[], u8 dbm_str_len)
1311 {
1312 char fmt[16];
1313
1314 if (idx == txgi_max) {
1315 snprintf(fmt, 16, "%%%zus", cwidth >= 6 ? cwidth + 1 : 6);
1316 snprintf(dbm_str, dbm_str_len, fmt, "NA");
1317 } else if (idx > -txgi_pdbm && idx < 0) { /* -0.xx */
1318 snprintf(fmt, 16, "%%%zus-0.%%02d", cwidth >= 6 ? cwidth - 4 : 1);
1319 snprintf(dbm_str, dbm_str_len, fmt, "", (rtw_abs(idx) % txgi_pdbm) * 100 / txgi_pdbm);
1320 } else if (idx % txgi_pdbm) { /* d.xx */
1321 snprintf(fmt, 16, "%%%zud.%%02d", cwidth >= 6 ? cwidth - 2 : 3);
1322 snprintf(dbm_str, dbm_str_len, fmt, idx / txgi_pdbm, (rtw_abs(idx) % txgi_pdbm) * 100 / txgi_pdbm);
1323 } else { /* d */
1324 snprintf(fmt, 16, "%%%zud", cwidth >= 6 ? cwidth + 1 : 6);
1325 snprintf(dbm_str, dbm_str_len, fmt, idx / txgi_pdbm);
1326 }
1327 }
1328
1329 /*
1330 * input with txpwr value in unit of mbm
1331 * return string in length 6 at least (for -xx.xx)
1332 */
txpwr_mbm_get_dbm_str(s16 mbm,SIZE_T cwidth,char dbm_str[],u8 dbm_str_len)1333 void txpwr_mbm_get_dbm_str(s16 mbm, SIZE_T cwidth, char dbm_str[], u8 dbm_str_len)
1334 {
1335 char fmt[16];
1336
1337 if (mbm == UNSPECIFIED_MBM) {
1338 snprintf(fmt, 16, "%%%zus", cwidth >= 6 ? cwidth + 1 : 6);
1339 snprintf(dbm_str, dbm_str_len, fmt, "NA");
1340 } else if (mbm > -MBM_PDBM && mbm < 0) { /* -0.xx */
1341 snprintf(fmt, 16, "%%%zus-0.%%02d", cwidth >= 6 ? cwidth - 4 : 1);
1342 snprintf(dbm_str, dbm_str_len, fmt, "", (rtw_abs(mbm) % MBM_PDBM) * 100 / MBM_PDBM);
1343 } else if (mbm % MBM_PDBM) { /* d.xx */
1344 snprintf(fmt, 16, "%%%zud.%%02d", cwidth >= 6 ? cwidth - 2 : 3);
1345 snprintf(dbm_str, dbm_str_len, fmt, mbm / MBM_PDBM, (rtw_abs(mbm) % MBM_PDBM) * 100 / MBM_PDBM);
1346 } else { /* d */
1347 snprintf(fmt, 16, "%%%zud", cwidth >= 6 ? cwidth + 1 : 6);
1348 snprintf(dbm_str, dbm_str_len, fmt, mbm / MBM_PDBM);
1349 }
1350 }
1351
1352 static const s16 _mb_of_ntx[] = {
1353 0, /* 1TX */
1354 301, /* 2TX */
1355 477, /* 3TX */
1356 602, /* 4TX */
1357 699, /* 5TX */
1358 778, /* 6TX */
1359 845, /* 7TX */
1360 903, /* 8TX */
1361 };
1362
1363 /* get mB(100 *dB) for specifc TX count relative to 1TX */
mb_of_ntx(u8 ntx)1364 s16 mb_of_ntx(u8 ntx)
1365 {
1366 if (ntx == 0 || ntx > 8) {
1367 RTW_ERR("ntx=%u, out of range\n", ntx);
1368 rtw_warn_on(1);
1369 }
1370
1371 return _mb_of_ntx[ntx - 1];
1372 }
1373
1374 #if CONFIG_TXPWR_LIMIT
_dump_regd_exc_list(void * sel,struct rf_ctl_t * rfctl)1375 void _dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl)
1376 {
1377 struct regd_exc_ent *ent;
1378 _list *cur, *head;
1379
1380 RTW_PRINT_SEL(sel, "regd_exc_num:%u\n", rfctl->regd_exc_num);
1381
1382 if (!rfctl->regd_exc_num)
1383 goto exit;
1384
1385 RTW_PRINT_SEL(sel, "%-7s %-6s %-9s\n", "country", "domain", "regd_name");
1386
1387 head = &rfctl->reg_exc_list;
1388 cur = get_next(head);
1389
1390 while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
1391 u8 has_country;
1392
1393 ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list);
1394 cur = get_next(cur);
1395 has_country = (ent->country[0] == '\0' && ent->country[1] == '\0') ? 0 : 1;
1396
1397 RTW_PRINT_SEL(sel, " %c%c 0x%02x %s\n"
1398 , has_country ? ent->country[0] : '0'
1399 , has_country ? ent->country[1] : '0'
1400 , ent->domain
1401 , ent->regd_name
1402 );
1403 }
1404
1405 exit:
1406 return;
1407 }
1408
dump_regd_exc_list(void * sel,struct rf_ctl_t * rfctl)1409 inline void dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl)
1410 {
1411 _irqL irqL;
1412
1413 _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
1414 _dump_regd_exc_list(sel, rfctl);
1415 _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
1416 }
1417
rtw_regd_exc_add_with_nlen(struct rf_ctl_t * rfctl,const char * country,u8 domain,const char * regd_name,u32 nlen)1418 void rtw_regd_exc_add_with_nlen(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name, u32 nlen)
1419 {
1420 struct regd_exc_ent *ent;
1421 _irqL irqL;
1422
1423 if (!regd_name || !nlen) {
1424 rtw_warn_on(1);
1425 goto exit;
1426 }
1427
1428 ent = (struct regd_exc_ent *)rtw_zmalloc(sizeof(struct regd_exc_ent) + nlen + 1);
1429 if (!ent)
1430 goto exit;
1431
1432 _rtw_init_listhead(&ent->list);
1433 if (country)
1434 _rtw_memcpy(ent->country, country, 2);
1435 ent->domain = domain;
1436 _rtw_memcpy(ent->regd_name, regd_name, nlen);
1437
1438 _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
1439
1440 rtw_list_insert_tail(&ent->list, &rfctl->reg_exc_list);
1441 rfctl->regd_exc_num++;
1442
1443 _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
1444
1445 exit:
1446 return;
1447 }
1448
rtw_regd_exc_add(struct rf_ctl_t * rfctl,const char * country,u8 domain,const char * regd_name)1449 inline void rtw_regd_exc_add(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name)
1450 {
1451 rtw_regd_exc_add_with_nlen(rfctl, country, domain, regd_name, strlen(regd_name));
1452 }
1453
_rtw_regd_exc_search(struct rf_ctl_t * rfctl,const char * country,u8 domain)1454 struct regd_exc_ent *_rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain)
1455 {
1456 struct regd_exc_ent *ent;
1457 _list *cur, *head;
1458 u8 match = 0;
1459
1460 head = &rfctl->reg_exc_list;
1461 cur = get_next(head);
1462
1463 while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
1464 u8 has_country;
1465
1466 ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list);
1467 cur = get_next(cur);
1468 has_country = (ent->country[0] == '\0' && ent->country[1] == '\0') ? 0 : 1;
1469
1470 /* entry has country condition to match */
1471 if (has_country) {
1472 if (!country)
1473 continue;
1474 if (ent->country[0] != country[0]
1475 || ent->country[1] != country[1])
1476 continue;
1477 }
1478
1479 /* entry has domain condition to match */
1480 if (ent->domain != 0xFF) {
1481 if (domain == 0xFF)
1482 continue;
1483 if (ent->domain != domain)
1484 continue;
1485 }
1486
1487 match = 1;
1488 break;
1489 }
1490
1491 if (match)
1492 return ent;
1493 else
1494 return NULL;
1495 }
1496
rtw_regd_exc_search(struct rf_ctl_t * rfctl,const char * country,u8 domain)1497 inline struct regd_exc_ent *rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain)
1498 {
1499 struct regd_exc_ent *ent;
1500 _irqL irqL;
1501
1502 _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
1503 ent = _rtw_regd_exc_search(rfctl, country, domain);
1504 _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
1505
1506 return ent;
1507 }
1508
rtw_regd_exc_list_free(struct rf_ctl_t * rfctl)1509 void rtw_regd_exc_list_free(struct rf_ctl_t *rfctl)
1510 {
1511 struct regd_exc_ent *ent;
1512 _irqL irqL;
1513 _list *cur, *head;
1514
1515 _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
1516
1517 head = &rfctl->reg_exc_list;
1518 cur = get_next(head);
1519
1520 while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
1521 ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list);
1522 cur = get_next(cur);
1523 rtw_list_delete(&ent->list);
1524 rtw_mfree((u8 *)ent, sizeof(struct regd_exc_ent) + strlen(ent->regd_name) + 1);
1525 }
1526 rfctl->regd_exc_num = 0;
1527
1528 _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
1529 }
1530
dump_txpwr_lmt(void * sel,_adapter * adapter)1531 void dump_txpwr_lmt(void *sel, _adapter *adapter)
1532 {
1533 #define TMP_STR_LEN 16
1534 struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
1535 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1536 struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
1537 _irqL irqL;
1538 char fmt[16];
1539 char tmp_str[TMP_STR_LEN];
1540 s8 *lmt_idx = NULL;
1541 int bw, band, ch_num, tlrs, ntx_idx, rs, i, path;
1542 u8 ch, n, rfpath_num;
1543
1544 _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
1545
1546 _dump_regd_exc_list(sel, rfctl);
1547 RTW_PRINT_SEL(sel, "\n");
1548
1549 if (!rfctl->txpwr_regd_num)
1550 goto release_lock;
1551
1552 lmt_idx = rtw_malloc(sizeof(s8) * RF_PATH_MAX * rfctl->txpwr_regd_num);
1553 if (!lmt_idx) {
1554 RTW_ERR("%s alloc fail\n", __func__);
1555 goto release_lock;
1556 }
1557
1558 RTW_PRINT_SEL(sel, "txpwr_lmt_2g_cck_ofdm_state:0x%02x\n", rfctl->txpwr_lmt_2g_cck_ofdm_state);
1559 #if CONFIG_IEEE80211_BAND_5GHZ
1560 if (IS_HARDWARE_TYPE_JAGUAR_ALL(adapter)) {
1561 RTW_PRINT_SEL(sel, "txpwr_lmt_5g_cck_ofdm_state:0x%02x\n", rfctl->txpwr_lmt_5g_cck_ofdm_state);
1562 RTW_PRINT_SEL(sel, "txpwr_lmt_5g_20_40_ref:0x%02x\n", rfctl->txpwr_lmt_5g_20_40_ref);
1563 }
1564 #endif
1565 RTW_PRINT_SEL(sel, "\n");
1566
1567 for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
1568 if (!hal_is_band_support(adapter, band))
1569 continue;
1570
1571 rfpath_num = (band == BAND_ON_2_4G ? hal_spec->rfpath_num_2g : hal_spec->rfpath_num_5g);
1572
1573 for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; bw++) {
1574
1575 if (bw >= CHANNEL_WIDTH_160)
1576 break;
1577 if (band == BAND_ON_2_4G && bw >= CHANNEL_WIDTH_80)
1578 break;
1579
1580 if (band == BAND_ON_2_4G)
1581 ch_num = CENTER_CH_2G_NUM;
1582 else
1583 ch_num = center_chs_5g_num(bw);
1584
1585 if (ch_num == 0) {
1586 rtw_warn_on(1);
1587 break;
1588 }
1589
1590 for (tlrs = TXPWR_LMT_RS_CCK; tlrs < TXPWR_LMT_RS_NUM; tlrs++) {
1591
1592 if (band == BAND_ON_2_4G && tlrs == TXPWR_LMT_RS_VHT)
1593 continue;
1594 if (band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK)
1595 continue;
1596 if (bw > CHANNEL_WIDTH_20 && (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM))
1597 continue;
1598 if (bw > CHANNEL_WIDTH_40 && tlrs == TXPWR_LMT_RS_HT)
1599 continue;
1600 if (tlrs == TXPWR_LMT_RS_VHT && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
1601 continue;
1602
1603 for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
1604 struct txpwr_lmt_ent *ent;
1605 _list *cur, *head;
1606
1607 if (ntx_idx + 1 > hal_data->max_tx_cnt)
1608 continue;
1609
1610 /* bypass CCK multi-TX is not defined */
1611 if (tlrs == TXPWR_LMT_RS_CCK && ntx_idx > RF_1TX) {
1612 if (band == BAND_ON_2_4G
1613 && !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_CCK_1T << ntx_idx)))
1614 continue;
1615 }
1616
1617 /* bypass OFDM multi-TX is not defined */
1618 if (tlrs == TXPWR_LMT_RS_OFDM && ntx_idx > RF_1TX) {
1619 if (band == BAND_ON_2_4G
1620 && !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))
1621 continue;
1622 #if CONFIG_IEEE80211_BAND_5GHZ
1623 if (band == BAND_ON_5G
1624 && !(rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))
1625 continue;
1626 #endif
1627 }
1628
1629 /* bypass 5G 20M, 40M pure reference */
1630 #if CONFIG_IEEE80211_BAND_5GHZ
1631 if (band == BAND_ON_5G && (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)) {
1632 if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_HT_FROM_VHT) {
1633 if (tlrs == TXPWR_LMT_RS_HT)
1634 continue;
1635 } else if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_VHT_FROM_HT) {
1636 if (tlrs == TXPWR_LMT_RS_VHT && bw <= CHANNEL_WIDTH_40)
1637 continue;
1638 }
1639 }
1640 #endif
1641
1642 /* choose n-SS mapping rate section to get lmt diff value */
1643 if (tlrs == TXPWR_LMT_RS_CCK)
1644 rs = CCK;
1645 else if (tlrs == TXPWR_LMT_RS_OFDM)
1646 rs = OFDM;
1647 else if (tlrs == TXPWR_LMT_RS_HT)
1648 rs = HT_1SS + ntx_idx;
1649 else if (tlrs == TXPWR_LMT_RS_VHT)
1650 rs = VHT_1SS + ntx_idx;
1651 else {
1652 RTW_ERR("%s invalid tlrs %u\n", __func__, tlrs);
1653 continue;
1654 }
1655
1656 RTW_PRINT_SEL(sel, "[%s][%s][%s][%uT]\n"
1657 , band_str(band)
1658 , ch_width_str(bw)
1659 , txpwr_lmt_rs_str(tlrs)
1660 , ntx_idx + 1
1661 );
1662
1663 /* header for limit in db */
1664 RTW_PRINT_SEL(sel, "%3s ", "ch");
1665
1666 head = &rfctl->txpwr_lmt_list;
1667 cur = get_next(head);
1668 while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
1669 ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
1670 cur = get_next(cur);
1671
1672 sprintf(fmt, "%%%zus%%s ", strlen(ent->regd_name) >= 6 ? 1 : 6 - strlen(ent->regd_name));
1673 snprintf(tmp_str, TMP_STR_LEN, fmt
1674 , strcmp(ent->regd_name, rfctl->regd_name) == 0 ? "*" : ""
1675 , ent->regd_name);
1676 _RTW_PRINT_SEL(sel, "%s", tmp_str);
1677 }
1678 sprintf(fmt, "%%%zus%%s ", strlen(regd_str(TXPWR_LMT_WW)) >= 6 ? 1 : 6 - strlen(regd_str(TXPWR_LMT_WW)));
1679 snprintf(tmp_str, TMP_STR_LEN, fmt
1680 , strcmp(rfctl->regd_name, regd_str(TXPWR_LMT_WW)) == 0 ? "*" : ""
1681 , regd_str(TXPWR_LMT_WW));
1682 _RTW_PRINT_SEL(sel, "%s", tmp_str);
1683
1684 /* header for limit offset */
1685 for (path = 0; path < RF_PATH_MAX; path++) {
1686 if (path >= rfpath_num)
1687 break;
1688 _RTW_PRINT_SEL(sel, "|");
1689 head = &rfctl->txpwr_lmt_list;
1690 cur = get_next(head);
1691 while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
1692 ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
1693 cur = get_next(cur);
1694 _RTW_PRINT_SEL(sel, "%3c "
1695 , strcmp(ent->regd_name, rfctl->regd_name) == 0 ? rf_path_char(path) : ' ');
1696 }
1697 _RTW_PRINT_SEL(sel, "%3c "
1698 , strcmp(rfctl->regd_name, regd_str(TXPWR_LMT_WW)) == 0 ? rf_path_char(path) : ' ');
1699 }
1700 _RTW_PRINT_SEL(sel, "\n");
1701
1702 for (n = 0; n < ch_num; n++) {
1703 s8 lmt;
1704 s8 lmt_offset;
1705 u8 base;
1706
1707 if (band == BAND_ON_2_4G)
1708 ch = n + 1;
1709 else
1710 ch = center_chs_5g(bw, n);
1711
1712 if (ch == 0) {
1713 rtw_warn_on(1);
1714 break;
1715 }
1716
1717 /* dump limit in dBm */
1718 RTW_PRINT_SEL(sel, "%3u ", ch);
1719 head = &rfctl->txpwr_lmt_list;
1720 cur = get_next(head);
1721 while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
1722 ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
1723 cur = get_next(cur);
1724 lmt = phy_get_txpwr_lmt(adapter, ent->regd_name, band, bw, tlrs, ntx_idx, ch, 0);
1725 txpwr_idx_get_dbm_str(lmt, hal_spec->txgi_max, hal_spec->txgi_pdbm, strlen(ent->regd_name), tmp_str, TMP_STR_LEN);
1726 _RTW_PRINT_SEL(sel, "%s ", tmp_str);
1727 }
1728 lmt = phy_get_txpwr_lmt(adapter, regd_str(TXPWR_LMT_WW), band, bw, tlrs, ntx_idx, ch, 0);
1729 txpwr_idx_get_dbm_str(lmt, hal_spec->txgi_max, hal_spec->txgi_pdbm, strlen(regd_str(TXPWR_LMT_WW)), tmp_str, TMP_STR_LEN);
1730 _RTW_PRINT_SEL(sel, "%s ", tmp_str);
1731
1732 /* dump limit offset of each path */
1733 for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
1734 if (path >= rfpath_num)
1735 break;
1736
1737 base = phy_get_target_txpwr(adapter, band, path, rs);
1738
1739 _RTW_PRINT_SEL(sel, "|");
1740 head = &rfctl->txpwr_lmt_list;
1741 cur = get_next(head);
1742 i = 0;
1743 while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
1744 ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
1745 cur = get_next(cur);
1746 lmt_offset = phy_get_txpwr_lmt_diff(adapter, ent->regd_name, band, bw, path, rs, tlrs, ntx_idx, ch, 0);
1747 if (lmt_offset == hal_spec->txgi_max) {
1748 *(lmt_idx + i * RF_PATH_MAX + path) = hal_spec->txgi_max;
1749 _RTW_PRINT_SEL(sel, "%3s ", "NA");
1750 } else {
1751 *(lmt_idx + i * RF_PATH_MAX + path) = lmt_offset + base;
1752 _RTW_PRINT_SEL(sel, "%3d ", lmt_offset);
1753 }
1754 i++;
1755 }
1756 lmt_offset = phy_get_txpwr_lmt_diff(adapter, regd_str(TXPWR_LMT_WW), band, bw, path, rs, tlrs, ntx_idx, ch, 0);
1757 if (lmt_offset == hal_spec->txgi_max)
1758 _RTW_PRINT_SEL(sel, "%3s ", "NA");
1759 else
1760 _RTW_PRINT_SEL(sel, "%3d ", lmt_offset);
1761
1762 }
1763
1764 /* compare limit_idx of each path, print 'x' when mismatch */
1765 if (rfpath_num > 1) {
1766 for (i = 0; i < rfctl->txpwr_regd_num; i++) {
1767 for (path = 0; path < RF_PATH_MAX; path++) {
1768 if (path >= rfpath_num)
1769 break;
1770 if (*(lmt_idx + i * RF_PATH_MAX + path) != *(lmt_idx + i * RF_PATH_MAX + ((path + 1) % rfpath_num)))
1771 break;
1772 }
1773 if (path >= rfpath_num)
1774 _RTW_PRINT_SEL(sel, " ");
1775 else
1776 _RTW_PRINT_SEL(sel, "x");
1777 }
1778 }
1779 _RTW_PRINT_SEL(sel, "\n");
1780
1781 }
1782 RTW_PRINT_SEL(sel, "\n");
1783 }
1784 } /* loop for rate sections */
1785 } /* loop for bandwidths */
1786 } /* loop for bands */
1787
1788 if (lmt_idx)
1789 rtw_mfree(lmt_idx, sizeof(s8) * RF_PATH_MAX * rfctl->txpwr_regd_num);
1790
1791 release_lock:
1792 _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
1793 }
1794
1795 /* search matcing first, if not found, alloc one */
rtw_txpwr_lmt_add_with_nlen(struct rf_ctl_t * rfctl,const char * regd_name,u32 nlen,u8 band,u8 bw,u8 tlrs,u8 ntx_idx,u8 ch_idx,s8 lmt)1796 void rtw_txpwr_lmt_add_with_nlen(struct rf_ctl_t *rfctl, const char *regd_name, u32 nlen
1797 , u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt)
1798 {
1799 struct hal_spec_t *hal_spec = GET_HAL_SPEC(dvobj_get_primary_adapter(rfctl_to_dvobj(rfctl)));
1800 struct txpwr_lmt_ent *ent;
1801 _irqL irqL;
1802 _list *cur, *head;
1803 s8 pre_lmt;
1804
1805 if (!regd_name || !nlen) {
1806 rtw_warn_on(1);
1807 goto exit;
1808 }
1809
1810 _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
1811
1812 /* search for existed entry */
1813 head = &rfctl->txpwr_lmt_list;
1814 cur = get_next(head);
1815 while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
1816 ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
1817 cur = get_next(cur);
1818
1819 if (strlen(ent->regd_name) == nlen
1820 && _rtw_memcmp(ent->regd_name, regd_name, nlen) == _TRUE)
1821 goto chk_lmt_val;
1822 }
1823
1824 /* alloc new one */
1825 ent = (struct txpwr_lmt_ent *)rtw_zvmalloc(sizeof(struct txpwr_lmt_ent) + nlen + 1);
1826 if (!ent)
1827 goto release_lock;
1828
1829 _rtw_init_listhead(&ent->list);
1830 _rtw_memcpy(ent->regd_name, regd_name, nlen);
1831 {
1832 u8 j, k, l, m;
1833
1834 for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j)
1835 for (k = 0; k < TXPWR_LMT_RS_NUM_2G; ++k)
1836 for (m = 0; m < CENTER_CH_2G_NUM; ++m)
1837 for (l = 0; l < MAX_TX_COUNT; ++l)
1838 ent->lmt_2g[j][k][m][l] = hal_spec->txgi_max;
1839 #if CONFIG_IEEE80211_BAND_5GHZ
1840 for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j)
1841 for (k = 0; k < TXPWR_LMT_RS_NUM_5G; ++k)
1842 for (m = 0; m < CENTER_CH_5G_ALL_NUM; ++m)
1843 for (l = 0; l < MAX_TX_COUNT; ++l)
1844 ent->lmt_5g[j][k][m][l] = hal_spec->txgi_max;
1845 #endif
1846 }
1847
1848 rtw_list_insert_tail(&ent->list, &rfctl->txpwr_lmt_list);
1849 rfctl->txpwr_regd_num++;
1850
1851 chk_lmt_val:
1852 if (band == BAND_ON_2_4G)
1853 pre_lmt = ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx];
1854 #if CONFIG_IEEE80211_BAND_5GHZ
1855 else if (band == BAND_ON_5G)
1856 pre_lmt = ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx];
1857 #endif
1858 else
1859 goto release_lock;
1860
1861 if (pre_lmt != hal_spec->txgi_max)
1862 RTW_PRINT("duplicate txpwr_lmt for [%s][%s][%s][%s][%uT][%d]\n"
1863 , regd_name, band_str(band), ch_width_str(bw), txpwr_lmt_rs_str(tlrs), ntx_idx + 1
1864 , band == BAND_ON_2_4G ? ch_idx + 1 : center_ch_5g_all[ch_idx]);
1865
1866 lmt = rtw_min(pre_lmt, lmt);
1867 if (band == BAND_ON_2_4G)
1868 ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx] = lmt;
1869 #if CONFIG_IEEE80211_BAND_5GHZ
1870 else if (band == BAND_ON_5G)
1871 ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx] = lmt;
1872 #endif
1873
1874 if (0)
1875 RTW_PRINT("%s, %4s, %6s, %7s, %uT, ch%3d = %d\n"
1876 , regd_name, band_str(band), ch_width_str(bw), txpwr_lmt_rs_str(tlrs), ntx_idx + 1
1877 , band == BAND_ON_2_4G ? ch_idx + 1 : center_ch_5g_all[ch_idx]
1878 , lmt);
1879
1880 release_lock:
1881 _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
1882
1883 exit:
1884 return;
1885 }
1886
rtw_txpwr_lmt_add(struct rf_ctl_t * rfctl,const char * regd_name,u8 band,u8 bw,u8 tlrs,u8 ntx_idx,u8 ch_idx,s8 lmt)1887 inline void rtw_txpwr_lmt_add(struct rf_ctl_t *rfctl, const char *regd_name
1888 , u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt)
1889 {
1890 rtw_txpwr_lmt_add_with_nlen(rfctl, regd_name, strlen(regd_name)
1891 , band, bw, tlrs, ntx_idx, ch_idx, lmt);
1892 }
1893
_rtw_txpwr_lmt_get_by_name(struct rf_ctl_t * rfctl,const char * regd_name)1894 struct txpwr_lmt_ent *_rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name)
1895 {
1896 struct txpwr_lmt_ent *ent;
1897 _list *cur, *head;
1898 u8 found = 0;
1899
1900 head = &rfctl->txpwr_lmt_list;
1901 cur = get_next(head);
1902
1903 while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
1904 ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
1905 cur = get_next(cur);
1906
1907 if (strcmp(ent->regd_name, regd_name) == 0) {
1908 found = 1;
1909 break;
1910 }
1911 }
1912
1913 if (found)
1914 return ent;
1915 return NULL;
1916 }
1917
rtw_txpwr_lmt_get_by_name(struct rf_ctl_t * rfctl,const char * regd_name)1918 inline struct txpwr_lmt_ent *rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name)
1919 {
1920 struct txpwr_lmt_ent *ent;
1921 _irqL irqL;
1922
1923 _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
1924 ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_name);
1925 _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
1926
1927 return ent;
1928 }
1929
rtw_txpwr_lmt_list_free(struct rf_ctl_t * rfctl)1930 void rtw_txpwr_lmt_list_free(struct rf_ctl_t *rfctl)
1931 {
1932 struct txpwr_lmt_ent *ent;
1933 _irqL irqL;
1934 _list *cur, *head;
1935
1936 _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
1937
1938 head = &rfctl->txpwr_lmt_list;
1939 cur = get_next(head);
1940
1941 while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
1942 ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
1943 cur = get_next(cur);
1944 if (ent->regd_name == rfctl->regd_name)
1945 rfctl->regd_name = regd_str(TXPWR_LMT_NONE);
1946 rtw_list_delete(&ent->list);
1947 rtw_vmfree((u8 *)ent, sizeof(struct txpwr_lmt_ent) + strlen(ent->regd_name) + 1);
1948 }
1949 rfctl->txpwr_regd_num = 0;
1950
1951 _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
1952 }
1953 #endif /* CONFIG_TXPWR_LIMIT */
1954
rtw_ch_to_bb_gain_sel(int ch)1955 int rtw_ch_to_bb_gain_sel(int ch)
1956 {
1957 int sel = -1;
1958
1959 if (ch >= 1 && ch <= 14)
1960 sel = BB_GAIN_2G;
1961 #if CONFIG_IEEE80211_BAND_5GHZ
1962 else if (ch >= 36 && ch < 48)
1963 sel = BB_GAIN_5GLB1;
1964 else if (ch >= 52 && ch <= 64)
1965 sel = BB_GAIN_5GLB2;
1966 else if (ch >= 100 && ch <= 120)
1967 sel = BB_GAIN_5GMB1;
1968 else if (ch >= 124 && ch <= 144)
1969 sel = BB_GAIN_5GMB2;
1970 else if (ch >= 149 && ch <= 177)
1971 sel = BB_GAIN_5GHB;
1972 #endif
1973
1974 return sel;
1975 }
1976
rtw_rf_get_kfree_tx_gain_offset(_adapter * padapter,u8 path,u8 ch)1977 s8 rtw_rf_get_kfree_tx_gain_offset(_adapter *padapter, u8 path, u8 ch)
1978 {
1979 s8 kfree_offset = 0;
1980
1981 #ifdef CONFIG_RF_POWER_TRIM
1982 struct kfree_data_t *kfree_data = GET_KFREE_DATA(padapter);
1983 s8 bb_gain_sel = rtw_ch_to_bb_gain_sel(ch);
1984
1985 if (bb_gain_sel < BB_GAIN_2G || bb_gain_sel >= BB_GAIN_NUM) {
1986 rtw_warn_on(1);
1987 goto exit;
1988 }
1989
1990 if (kfree_data->flag & KFREE_FLAG_ON) {
1991 kfree_offset = kfree_data->bb_gain[bb_gain_sel][path];
1992 if (IS_HARDWARE_TYPE_8723D(padapter))
1993 RTW_INFO("%s path:%s, ch:%u, bb_gain_sel:%d, kfree_offset:%d\n"
1994 , __func__, (path == 0)?"S1":"S0",
1995 ch, bb_gain_sel, kfree_offset);
1996 else
1997 RTW_INFO("%s path:%u, ch:%u, bb_gain_sel:%d, kfree_offset:%d\n"
1998 , __func__, path, ch, bb_gain_sel, kfree_offset);
1999 }
2000 exit:
2001 #endif /* CONFIG_RF_POWER_TRIM */
2002 return kfree_offset;
2003 }
2004
rtw_rf_set_tx_gain_offset(_adapter * adapter,u8 path,s8 offset)2005 void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset)
2006 {
2007 #if !defined(CONFIG_RTL8814A) && !defined(CONFIG_RTL8822B) && !defined(CONFIG_RTL8821C) && !defined(CONFIG_RTL8822C)
2008 u8 write_value;
2009 #endif
2010 u8 target_path = 0;
2011 u32 val32 = 0;
2012
2013 if (IS_HARDWARE_TYPE_8723D(adapter)) {
2014 target_path = RF_PATH_A; /*in 8723D case path means S0/S1*/
2015 if (path == PPG_8723D_S1)
2016 RTW_INFO("kfree gain_offset 0x55:0x%x ",
2017 rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff));
2018 else if (path == PPG_8723D_S0)
2019 RTW_INFO("kfree gain_offset 0x65:0x%x ",
2020 rtw_hal_read_rfreg(adapter, target_path, 0x65, 0xffffffff));
2021 } else {
2022 target_path = path;
2023 RTW_INFO("kfree gain_offset 0x55:0x%x ", rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff));
2024 }
2025
2026 switch (rtw_get_chip_type(adapter)) {
2027 #ifdef CONFIG_RTL8723D
2028 case RTL8723D:
2029 write_value = RF_TX_GAIN_OFFSET_8723D(offset);
2030 if (path == PPG_8723D_S1)
2031 rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value);
2032 else if (path == PPG_8723D_S0)
2033 rtw_hal_write_rfreg(adapter, target_path, 0x65, 0x0f8000, write_value);
2034 break;
2035 #endif /* CONFIG_RTL8723D */
2036 #ifdef CONFIG_RTL8703B
2037 case RTL8703B:
2038 write_value = RF_TX_GAIN_OFFSET_8703B(offset);
2039 rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value);
2040 break;
2041 #endif /* CONFIG_RTL8703B */
2042 #ifdef CONFIG_RTL8188F
2043 case RTL8188F:
2044 write_value = RF_TX_GAIN_OFFSET_8188F(offset);
2045 rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value);
2046 break;
2047 #endif /* CONFIG_RTL8188F */
2048 #ifdef CONFIG_RTL8188GTV
2049 case RTL8188GTV:
2050 write_value = RF_TX_GAIN_OFFSET_8188GTV(offset);
2051 rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value);
2052 break;
2053 #endif /* CONFIG_RTL8188GTV */
2054 #ifdef CONFIG_RTL8192E
2055 case RTL8192E:
2056 write_value = RF_TX_GAIN_OFFSET_8192E(offset);
2057 rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value);
2058 break;
2059 #endif /* CONFIG_RTL8188F */
2060
2061 #ifdef CONFIG_RTL8821A
2062 case RTL8821:
2063 write_value = RF_TX_GAIN_OFFSET_8821A(offset);
2064 rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value);
2065 break;
2066 #endif /* CONFIG_RTL8821A */
2067 #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822C)
2068 case RTL8814A:
2069 case RTL8822B:
2070 case RTL8822C:
2071 case RTL8821C:
2072 case RTL8192F:
2073 RTW_INFO("\nkfree by PhyDM on the sw CH. path %d\n", path);
2074 break;
2075 #endif /* CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
2076
2077 default:
2078 rtw_warn_on(1);
2079 break;
2080 }
2081
2082 if (IS_HARDWARE_TYPE_8723D(adapter)) {
2083 if (path == PPG_8723D_S1)
2084 val32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff);
2085 else if (path == PPG_8723D_S0)
2086 val32 = rtw_hal_read_rfreg(adapter, target_path, 0x65, 0xffffffff);
2087 } else {
2088 val32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff);
2089 }
2090 RTW_INFO(" after :0x%x\n", val32);
2091 }
2092
rtw_rf_apply_tx_gain_offset(_adapter * adapter,u8 ch)2093 void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch)
2094 {
2095 struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
2096 s8 kfree_offset = 0;
2097 s8 tx_pwr_track_offset = 0; /* TODO: 8814A should consider tx pwr track when setting tx gain offset */
2098 s8 total_offset;
2099 int i, total = 0;
2100
2101 if (IS_HARDWARE_TYPE_8723D(adapter))
2102 total = 2; /* S1 and S0 */
2103 else
2104 total = hal_spec->rf_reg_path_num;
2105
2106 for (i = 0; i < total; i++) {
2107 kfree_offset = rtw_rf_get_kfree_tx_gain_offset(adapter, i, ch);
2108 total_offset = kfree_offset + tx_pwr_track_offset;
2109 rtw_rf_set_tx_gain_offset(adapter, i, total_offset);
2110 }
2111 }
2112
rtw_is_long_cac_range(u32 hi,u32 lo,u8 dfs_region)2113 bool rtw_is_long_cac_range(u32 hi, u32 lo, u8 dfs_region)
2114 {
2115 return (dfs_region == PHYDM_DFS_DOMAIN_ETSI && rtw_is_range_overlap(hi, lo, 5650, 5600)) ? _TRUE : _FALSE;
2116 }
2117
rtw_is_long_cac_ch(u8 ch,u8 bw,u8 offset,u8 dfs_region)2118 bool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset, u8 dfs_region)
2119 {
2120 u32 hi, lo;
2121
2122 if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)
2123 return _FALSE;
2124
2125 return rtw_is_long_cac_range(hi, lo, dfs_region) ? _TRUE : _FALSE;
2126 }
2127