1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _RTW_MP_C_
16 #include <drv_types.h>
17 #ifdef PLATFORM_FREEBSD
18 #include <sys/unistd.h> /* for RFHIGHPID */
19 #endif
20
21 #include "../hal/phydm/phydm_precomp.h"
22 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8821A)
23 #include <rtw_bt_mp.h>
24 #endif
25
26 #ifdef CONFIG_MP_VHT_HW_TX_MODE
27 #define CEILING_POS(X) ((X - (int)(X)) > 0 ? (int)(X + 1) : (int)(X))
28 #define CEILING_NEG(X) ((X - (int)(X)) < 0 ? (int)(X - 1) : (int)(X))
29 #define ceil(X) (((X) > 0) ? CEILING_POS(X) : CEILING_NEG(X))
30
rtfloor(float x)31 int rtfloor(float x)
32 {
33 int i = x - 2;
34 while
35 (++i <= x - 1)
36 ;
37 return i;
38 }
39 #endif
40
41 #ifdef CONFIG_MP_INCLUDED
read_macreg(_adapter * padapter,u32 addr,u32 sz)42 u32 read_macreg(_adapter *padapter, u32 addr, u32 sz)
43 {
44 u32 val = 0;
45
46 switch (sz) {
47 case 1:
48 val = rtw_read8(padapter, addr);
49 break;
50 case 2:
51 val = rtw_read16(padapter, addr);
52 break;
53 case 4:
54 val = rtw_read32(padapter, addr);
55 break;
56 default:
57 val = 0xffffffff;
58 break;
59 }
60
61 return val;
62
63 }
64
write_macreg(_adapter * padapter,u32 addr,u32 val,u32 sz)65 void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz)
66 {
67 switch (sz) {
68 case 1:
69 rtw_write8(padapter, addr, (u8)val);
70 break;
71 case 2:
72 rtw_write16(padapter, addr, (u16)val);
73 break;
74 case 4:
75 rtw_write32(padapter, addr, val);
76 break;
77 default:
78 break;
79 }
80
81 }
82
read_bbreg(_adapter * padapter,u32 addr,u32 bitmask)83 u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask)
84 {
85 return rtw_hal_read_bbreg(padapter, addr, bitmask);
86 }
87
write_bbreg(_adapter * padapter,u32 addr,u32 bitmask,u32 val)88 void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val)
89 {
90 rtw_hal_write_bbreg(padapter, addr, bitmask, val);
91 }
92
_read_rfreg(PADAPTER padapter,u8 rfpath,u32 addr,u32 bitmask)93 u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask)
94 {
95 return rtw_hal_read_rfreg(padapter, rfpath, addr, bitmask);
96 }
97
_write_rfreg(PADAPTER padapter,u8 rfpath,u32 addr,u32 bitmask,u32 val)98 void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val)
99 {
100 rtw_hal_write_rfreg(padapter, rfpath, addr, bitmask, val);
101 }
102
read_rfreg(PADAPTER padapter,u8 rfpath,u32 addr)103 u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr)
104 {
105 return _read_rfreg(padapter, rfpath, addr, bRFRegOffsetMask);
106 }
107
write_rfreg(PADAPTER padapter,u8 rfpath,u32 addr,u32 val)108 void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val)
109 {
110 _write_rfreg(padapter, rfpath, addr, bRFRegOffsetMask, val);
111 }
112
_init_mp_priv_(struct mp_priv * pmp_priv)113 static void _init_mp_priv_(struct mp_priv *pmp_priv)
114 {
115 WLAN_BSSID_EX *pnetwork;
116
117 _rtw_memset(pmp_priv, 0, sizeof(struct mp_priv));
118
119 pmp_priv->mode = MP_OFF;
120
121 pmp_priv->channel = 1;
122 pmp_priv->bandwidth = CHANNEL_WIDTH_20;
123 pmp_priv->prime_channel_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
124 pmp_priv->rateidx = RATE_1M;
125 pmp_priv->txpoweridx = 0x2A;
126
127 pmp_priv->antenna_tx = ANTENNA_A;
128 pmp_priv->antenna_rx = ANTENNA_AB;
129
130 pmp_priv->check_mp_pkt = 0;
131
132 pmp_priv->tx_pktcount = 0;
133
134 pmp_priv->rx_bssidpktcount = 0;
135 pmp_priv->rx_pktcount = 0;
136 pmp_priv->rx_crcerrpktcount = 0;
137
138 pmp_priv->network_macaddr[0] = 0x00;
139 pmp_priv->network_macaddr[1] = 0xE0;
140 pmp_priv->network_macaddr[2] = 0x4C;
141 pmp_priv->network_macaddr[3] = 0x87;
142 pmp_priv->network_macaddr[4] = 0x66;
143 pmp_priv->network_macaddr[5] = 0x55;
144
145 pmp_priv->bSetRxBssid = _FALSE;
146 pmp_priv->bRTWSmbCfg = _FALSE;
147 pmp_priv->bloopback = _FALSE;
148
149 pmp_priv->bloadefusemap = _FALSE;
150 pmp_priv->brx_filter_beacon = _FALSE;
151 pmp_priv->mplink_brx = _FALSE;
152
153 pnetwork = &pmp_priv->mp_network.network;
154 _rtw_memcpy(pnetwork->MacAddress, pmp_priv->network_macaddr, ETH_ALEN);
155
156 pnetwork->Ssid.SsidLength = 8;
157 _rtw_memcpy(pnetwork->Ssid.Ssid, "mp_871x", pnetwork->Ssid.SsidLength);
158
159 pmp_priv->tx.payload = MP_TX_Payload_default_random;
160 #ifdef CONFIG_80211N_HT
161 pmp_priv->tx.attrib.ht_en = 1;
162 #endif
163
164 pmp_priv->mpt_ctx.mpt_rate_index = 1;
165
166 }
167
168
mp_init_xmit_attrib(struct mp_tx * pmptx,PADAPTER padapter)169 static void mp_init_xmit_attrib(struct mp_tx *pmptx, PADAPTER padapter)
170 {
171 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
172
173 struct pkt_attrib *pattrib;
174
175 /* init xmitframe attribute */
176 pattrib = &pmptx->attrib;
177 _rtw_memset(pattrib, 0, sizeof(struct pkt_attrib));
178 _rtw_memset(pmptx->desc, 0, TXDESC_SIZE);
179
180 pattrib->ether_type = 0x8712;
181 #if 0
182 _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
183 _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
184 #endif
185 _rtw_memset(pattrib->dst, 0xFF, ETH_ALEN);
186
187 /* pattrib->dhcp_pkt = 0;
188 * pattrib->pktlen = 0; */
189 pattrib->ack_policy = 0;
190 /* pattrib->pkt_hdrlen = ETH_HLEN; */
191 pattrib->hdrlen = WLAN_HDR_A3_LEN;
192 pattrib->subtype = WIFI_DATA;
193 pattrib->priority = 0;
194 pattrib->qsel = pattrib->priority;
195 /* do_queue_select(padapter, pattrib); */
196 pattrib->nr_frags = 1;
197 pattrib->encrypt = 0;
198 pattrib->bswenc = _FALSE;
199 pattrib->qos_en = _FALSE;
200
201 pattrib->pktlen = 1500;
202
203 if (pHalData->rf_type == RF_2T2R)
204 pattrib->raid = RATEID_IDX_BGN_40M_2SS;
205 else
206 pattrib->raid = RATEID_IDX_BGN_40M_1SS;
207
208 #ifdef CONFIG_80211AC_VHT
209 if (pHalData->rf_type == RF_1T1R)
210 pattrib->raid = RATEID_IDX_VHT_1SS;
211 else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
212 pattrib->raid = RATEID_IDX_VHT_2SS;
213 else if (pHalData->rf_type == RF_3T3R)
214 pattrib->raid = RATEID_IDX_VHT_3SS;
215 else
216 pattrib->raid = RATEID_IDX_BGN_40M_1SS;
217 #endif
218 }
219
init_mp_priv(PADAPTER padapter)220 s32 init_mp_priv(PADAPTER padapter)
221 {
222 struct mp_priv *pmppriv = &padapter->mppriv;
223 PHAL_DATA_TYPE pHalData;
224
225 pHalData = GET_HAL_DATA(padapter);
226
227 _init_mp_priv_(pmppriv);
228 pmppriv->papdater = padapter;
229 if (IS_HARDWARE_TYPE_8822C(padapter))
230 pmppriv->mp_dm = 1;/* default enable dpk tracking */
231 else
232 pmppriv->mp_dm = 0;
233
234 pmppriv->tx.stop = 1;
235 pmppriv->bSetTxPower = 0; /*for manually set tx power*/
236 pmppriv->bTxBufCkFail = _FALSE;
237 pmppriv->pktInterval = 0;
238 pmppriv->pktLength = 1000;
239 pmppriv->bprocess_mp_mode = _FALSE;
240
241 mp_init_xmit_attrib(&pmppriv->tx, padapter);
242
243 switch (GET_HAL_RFPATH(padapter)) {
244 case RF_1T1R:
245 pmppriv->antenna_tx = ANTENNA_A;
246 pmppriv->antenna_rx = ANTENNA_A;
247 break;
248 case RF_1T2R:
249 default:
250 pmppriv->antenna_tx = ANTENNA_A;
251 pmppriv->antenna_rx = ANTENNA_AB;
252 break;
253 case RF_2T2R:
254 pmppriv->antenna_tx = ANTENNA_AB;
255 pmppriv->antenna_rx = ANTENNA_AB;
256 break;
257 case RF_2T4R:
258 pmppriv->antenna_tx = ANTENNA_BC;
259 pmppriv->antenna_rx = ANTENNA_ABCD;
260 break;
261 }
262
263 pHalData->AntennaRxPath = pmppriv->antenna_rx;
264 pHalData->antenna_tx_path = pmppriv->antenna_tx;
265
266 return _SUCCESS;
267 }
268
free_mp_priv(struct mp_priv * pmp_priv)269 void free_mp_priv(struct mp_priv *pmp_priv)
270 {
271 if (pmp_priv->pallocated_mp_xmitframe_buf) {
272 rtw_mfree(pmp_priv->pallocated_mp_xmitframe_buf, 0);
273 pmp_priv->pallocated_mp_xmitframe_buf = NULL;
274 }
275 pmp_priv->pmp_xmtframe_buf = NULL;
276 }
277
278 #if 0
279 static void PHY_IQCalibrate_default(
280 PADAPTER pAdapter,
281 BOOLEAN bReCovery
282 )
283 {
284 RTW_INFO("%s\n", __func__);
285 }
286
287 static void PHY_LCCalibrate_default(
288 PADAPTER pAdapter
289 )
290 {
291 RTW_INFO("%s\n", __func__);
292 }
293
294 static void PHY_SetRFPathSwitch_default(
295 PADAPTER pAdapter,
296 BOOLEAN bMain
297 )
298 {
299 RTW_INFO("%s\n", __func__);
300 }
301 #endif
302
mpt_InitHWConfig(PADAPTER Adapter)303 void mpt_InitHWConfig(PADAPTER Adapter)
304 {
305 PHAL_DATA_TYPE hal;
306
307 hal = GET_HAL_DATA(Adapter);
308
309 if (IS_HARDWARE_TYPE_8723B(Adapter)) {
310 /* TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type. */
311 /* TODO: A better solution is configure it according EFUSE during the run-time. */
312
313 phy_set_mac_reg(Adapter, 0x64, BIT20, 0x0); /* 0x66[4]=0 */
314 phy_set_mac_reg(Adapter, 0x64, BIT24, 0x0); /* 0x66[8]=0 */
315 phy_set_mac_reg(Adapter, 0x40, BIT4, 0x0); /* 0x40[4]=0 */
316 phy_set_mac_reg(Adapter, 0x40, BIT3, 0x1); /* 0x40[3]=1 */
317 phy_set_mac_reg(Adapter, 0x4C, BIT24, 0x1); /* 0x4C[24:23]=10 */
318 phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0); /* 0x4C[24:23]=10 */
319 phy_set_bb_reg(Adapter, 0x944, BIT1 | BIT0, 0x3); /* 0x944[1:0]=11 */
320 phy_set_bb_reg(Adapter, 0x930, bMaskByte0, 0x77);/* 0x930[7:0]=77 */
321 phy_set_mac_reg(Adapter, 0x38, BIT11, 0x1);/* 0x38[11]=1 */
322
323 /* TODO: <20130206, Kordan> The default setting is wrong, hard-coded here. */
324 phy_set_mac_reg(Adapter, 0x778, 0x3, 0x3); /* Turn off hardware PTA control (Asked by Scott) */
325 phy_set_mac_reg(Adapter, 0x64, bMaskDWord, 0x36000000);/* Fix BT S0/S1 */
326 phy_set_mac_reg(Adapter, 0x948, bMaskDWord, 0x0); /* Fix BT can't Tx */
327
328 /* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou) */
329 phy_set_bb_reg(Adapter, 0xA00, BIT8, 0x0); /*0xA01[0] = 0*/
330 } else if (IS_HARDWARE_TYPE_8821(Adapter)) {
331 /* <20131121, VincentL> Add for 8821AU DPDT setting and fix switching antenna issue (Asked by Rock)
332 <20131122, VincentL> Enable for all 8821A/8811AU (Asked by Alex)*/
333 phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0); /*0x4C[23:22]=01*/
334 phy_set_mac_reg(Adapter, 0x4C, BIT22, 0x1); /*0x4C[23:22]=01*/
335 } else if (IS_HARDWARE_TYPE_8188ES(Adapter))
336 phy_set_mac_reg(Adapter, 0x4C , BIT23, 0); /*select DPDT_P and DPDT_N as output pin*/
337 #ifdef CONFIG_RTL8814A
338 else if (IS_HARDWARE_TYPE_8814A(Adapter))
339 PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814A, 0x2000);
340 #endif
341
342 #ifdef CONFIG_RTL8812A
343 else if (IS_HARDWARE_TYPE_8812(Adapter)) {
344 rtw_write32(Adapter, 0x520, rtw_read32(Adapter, 0x520) | 0x8000);
345 rtw_write32(Adapter, 0x524, rtw_read32(Adapter, 0x524) & (~0x800));
346 }
347 #endif
348
349
350 #ifdef CONFIG_RTL8822B
351 else if (IS_HARDWARE_TYPE_8822B(Adapter)) {
352 u32 tmp_reg = 0;
353
354 PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8822B, 0x2000);
355 /* fixed wifi can't 2.4g tx suggest by Szuyitasi 20160504 */
356 phy_set_bb_reg(Adapter, 0x70, bMaskByte3, 0x0e);
357 RTW_INFO(" 0x73 = 0x%x\n", phy_query_bb_reg(Adapter, 0x70, bMaskByte3));
358 phy_set_bb_reg(Adapter, 0x1704, bMaskDWord, 0x0000ff00);
359 RTW_INFO(" 0x1704 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1704, bMaskDWord));
360 phy_set_bb_reg(Adapter, 0x1700, bMaskDWord, 0xc00f0038);
361 RTW_INFO(" 0x1700 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1700, bMaskDWord));
362 }
363 #endif /* CONFIG_RTL8822B */
364 #ifdef CONFIG_RTL8821C
365 else if (IS_HARDWARE_TYPE_8821C(Adapter))
366 PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8821C, 0x2000);
367 #endif /* CONFIG_RTL8821C */
368 #if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV)
369 else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) {
370 if (IS_A_CUT(hal->version_id) || IS_B_CUT(hal->version_id)) {
371 RTW_INFO("%s() Active large power detection\n", __func__);
372 phy_active_large_power_detection_8188f(&(GET_HAL_DATA(Adapter)->odmpriv));
373 }
374 }
375 #endif
376 #if defined(CONFIG_RTL8822C)
377 else if( IS_HARDWARE_TYPE_8822C(Adapter)) {
378 rtw_write16(Adapter, REG_RXFLTMAP1_8822C, 0x2000);
379 /* 0x7D8[31] : time out enable when cca is not assert
380 0x60D[7:0] : time out value (Unit : us)*/
381 rtw_write8(Adapter, 0x7db, 0xc0);
382 RTW_INFO(" 0x7d8 = 0x%x\n", rtw_read8(Adapter, 0x7d8));
383 rtw_write8(Adapter, 0x60d, 0x0c);
384 RTW_INFO(" 0x60d = 0x%x\n", rtw_read8(Adapter, 0x60d));
385 phy_set_bb_reg(Adapter, 0x1c44, BIT10, 0x1);
386 RTW_INFO(" 0x1c44 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1c44, bMaskDWord));
387 }
388 #endif
389 #if defined(CONFIG_RTL8814B)
390 else if(IS_HARDWARE_TYPE_8814B(Adapter))
391 {
392 PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814B, 0x2000);
393 }
394 #endif
395
396 }
397
PHY_IQCalibrate(PADAPTER padapter,u8 bReCovery)398 static void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery)
399 {
400 halrf_iqk_trigger(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery);
401 }
402
PHY_LCCalibrate(PADAPTER padapter)403 static void PHY_LCCalibrate(PADAPTER padapter)
404 {
405 halrf_lck_trigger(&(GET_HAL_DATA(padapter)->odmpriv));
406 }
407
PHY_QueryRFPathSwitch(PADAPTER padapter)408 static u8 PHY_QueryRFPathSwitch(PADAPTER padapter)
409 {
410 u8 bmain = 0;
411 /*
412 if (IS_HARDWARE_TYPE_8723B(padapter)) {
413 #ifdef CONFIG_RTL8723B
414 bmain = PHY_QueryRFPathSwitch_8723B(padapter);
415 #endif
416 } else if (IS_HARDWARE_TYPE_8188E(padapter)) {
417 #ifdef CONFIG_RTL8188E
418 bmain = PHY_QueryRFPathSwitch_8188E(padapter);
419 #endif
420 } else if (IS_HARDWARE_TYPE_8814A(padapter)) {
421 #ifdef CONFIG_RTL8814A
422 bmain = PHY_QueryRFPathSwitch_8814A(padapter);
423 #endif
424 } else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) {
425 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
426 bmain = PHY_QueryRFPathSwitch_8812A(padapter);
427 #endif
428 } else if (IS_HARDWARE_TYPE_8192E(padapter)) {
429 #ifdef CONFIG_RTL8192E
430 bmain = PHY_QueryRFPathSwitch_8192E(padapter);
431 #endif
432 } else if (IS_HARDWARE_TYPE_8703B(padapter)) {
433 #ifdef CONFIG_RTL8703B
434 bmain = PHY_QueryRFPathSwitch_8703B(padapter);
435 #endif
436 } else if (IS_HARDWARE_TYPE_8188F(padapter)) {
437 #ifdef CONFIG_RTL8188F
438 bmain = PHY_QueryRFPathSwitch_8188F(padapter);
439 #endif
440 } else if (IS_HARDWARE_TYPE_8188GTV(padapter)) {
441 #ifdef CONFIG_RTL8188GTV
442 bmain = PHY_QueryRFPathSwitch_8188GTV(padapter);
443 #endif
444 } else if (IS_HARDWARE_TYPE_8822B(padapter)) {
445 #ifdef CONFIG_RTL8822B
446 bmain = PHY_QueryRFPathSwitch_8822B(padapter);
447 #endif
448 } else if (IS_HARDWARE_TYPE_8723D(padapter)) {
449 #ifdef CONFIG_RTL8723D
450 bmain = PHY_QueryRFPathSwitch_8723D(padapter);
451 #endif
452 } else
453 */
454
455 if (IS_HARDWARE_TYPE_8821C(padapter)) {
456 #ifdef CONFIG_RTL8821C
457 bmain = phy_query_rf_path_switch_8821c(padapter);
458 #endif
459 }
460
461 return bmain;
462 }
463
PHY_SetRFPathSwitch(PADAPTER padapter,BOOLEAN bMain)464 static void PHY_SetRFPathSwitch(PADAPTER padapter , BOOLEAN bMain) {
465
466 PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
467 struct dm_struct *phydm = &hal->odmpriv;
468
469 if (IS_HARDWARE_TYPE_8723B(padapter)) {
470 #ifdef CONFIG_RTL8723B
471 phy_set_rf_path_switch_8723b(phydm, bMain);
472 #endif
473 } else if (IS_HARDWARE_TYPE_8188E(padapter)) {
474 #ifdef CONFIG_RTL8188E
475 phy_set_rf_path_switch_8188e(phydm, bMain);
476 #endif
477 } else if (IS_HARDWARE_TYPE_8814A(padapter)) {
478 #ifdef CONFIG_RTL8814A
479 phy_set_rf_path_switch_8814a(phydm, bMain);
480 #endif
481 } else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) {
482 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
483 phy_set_rf_path_switch_8812a(phydm, bMain);
484 #endif
485 } else if (IS_HARDWARE_TYPE_8192E(padapter)) {
486 #ifdef CONFIG_RTL8192E
487 phy_set_rf_path_switch_8192e(phydm, bMain);
488 #endif
489 } else if (IS_HARDWARE_TYPE_8703B(padapter)) {
490 #ifdef CONFIG_RTL8703B
491 phy_set_rf_path_switch_8703b(phydm, bMain);
492 #endif
493 } else if (IS_HARDWARE_TYPE_8188F(padapter) || IS_HARDWARE_TYPE_8188GTV(padapter)) {
494 #if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV)
495 phy_set_rf_path_switch_8188f(phydm, bMain);
496 #endif
497 } else if (IS_HARDWARE_TYPE_8192F(padapter)) {
498 #ifdef CONFIG_RTL8192F
499 phy_set_rf_path_switch_8192f(padapter, bMain);
500 #endif
501 } else if (IS_HARDWARE_TYPE_8822B(padapter)) {
502 #ifdef CONFIG_RTL8822B
503 phy_set_rf_path_switch_8822b(phydm, bMain);
504 #endif
505 } else if (IS_HARDWARE_TYPE_8723D(padapter)) {
506 #ifdef CONFIG_RTL8723D
507 phy_set_rf_path_switch_8723d(phydm, bMain);
508 #endif
509 } else if (IS_HARDWARE_TYPE_8821C(padapter)) {
510 #ifdef CONFIG_RTL8821C
511 phy_set_rf_path_switch_8821c(phydm, bMain);
512 #endif
513 } else if (IS_HARDWARE_TYPE_8822C(padapter)) {
514 #ifdef CONFIG_RTL8822C
515 phy_set_rf_path_switch_8822c(phydm, bMain);
516 #endif
517 } else if (IS_HARDWARE_TYPE_8814B(padapter)) {
518 #ifdef CONFIG_RTL8814B
519 /* phy_set_rf_path_switch_8814b(phydm, bMain); */
520 #endif
521 }
522 }
523
524
phy_switch_rf_path_set(PADAPTER padapter,u8 * prf_set_State)525 static void phy_switch_rf_path_set(PADAPTER padapter , u8 *prf_set_State) {
526 #ifdef CONFIG_RTL8821C
527 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
528 struct dm_struct *p_dm = &pHalData->odmpriv;
529
530 if (IS_HARDWARE_TYPE_8821C(padapter)) {
531 config_phydm_set_ant_path(p_dm, *prf_set_State, p_dm->current_ant_num_8821c);
532 /* Do IQK when switching to BTG/WLG, requested by RF Binson */
533 if (*prf_set_State == SWITCH_TO_BTG || *prf_set_State == SWITCH_TO_WLG)
534 PHY_IQCalibrate(padapter, FALSE);
535 }
536 #endif
537
538 }
539
540
541 #ifdef CONFIG_ANTENNA_DIVERSITY
rtw_mp_set_antdiv(PADAPTER padapter,BOOLEAN bMain)542 u8 rtw_mp_set_antdiv(PADAPTER padapter, BOOLEAN bMain)
543 {
544 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
545 u8 cur_ant, change_ant;
546
547 if (!pHalData->AntDivCfg)
548 return _FALSE;
549 /*rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &cur_ant, NULL);*/
550 change_ant = (bMain == MAIN_ANT) ? MAIN_ANT : AUX_ANT;
551
552 RTW_INFO("%s: config %s\n", __func__, (bMain == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
553 rtw_antenna_select_cmd(padapter, change_ant, _FALSE);
554
555 return _TRUE;
556 }
557 #endif
558
559 s32
MPT_InitializeAdapter(PADAPTER pAdapter,u8 Channel)560 MPT_InitializeAdapter(
561 PADAPTER pAdapter,
562 u8 Channel
563 )
564 {
565 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
566 s32 rtStatus = _SUCCESS;
567 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
568 u32 ledsetting;
569
570 pMptCtx->bMptDrvUnload = _FALSE;
571 pMptCtx->bMassProdTest = _FALSE;
572 pMptCtx->bMptIndexEven = _TRUE; /* default gain index is -6.0db */
573 pMptCtx->h2cReqNum = 0x0;
574 /* init for BT MP */
575 #if defined(CONFIG_RTL8723B)
576 pMptCtx->bMPh2c_timeout = _FALSE;
577 pMptCtx->MptH2cRspEvent = _FALSE;
578 pMptCtx->MptBtC2hEvent = _FALSE;
579 _rtw_init_sema(&pMptCtx->MPh2c_Sema, 0);
580 rtw_init_timer(&pMptCtx->MPh2c_timeout_timer, pAdapter, MPh2c_timeout_handle, pAdapter);
581 #endif
582
583 mpt_InitHWConfig(pAdapter);
584
585 #ifdef CONFIG_RTL8723B
586 rtl8723b_InitAntenna_Selection(pAdapter);
587 if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
588
589 /* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou)*/
590 phy_set_bb_reg(pAdapter, 0xA00, BIT8, 0x0);
591 PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /*default use Main*/
592
593 if (pHalData->PackageType == PACKAGE_DEFAULT)
594 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
595 else
596 phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6F10E);
597
598 }
599 /*set ant to wifi side in mp mode*/
600 rtw_write16(pAdapter, 0x870, 0x300);
601 rtw_write16(pAdapter, 0x860, 0x110);
602 #endif
603
604 pMptCtx->bMptWorkItemInProgress = _FALSE;
605 pMptCtx->CurrMptAct = NULL;
606 pMptCtx->mpt_rf_path = RF_PATH_A;
607 /* ------------------------------------------------------------------------- */
608 /* Don't accept any packets */
609 rtw_write32(pAdapter, REG_RCR, 0);
610
611 /* ledsetting = rtw_read32(pAdapter, REG_LEDCFG0); */
612 /* rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS); */
613
614 /* rtw_write32(pAdapter, REG_LEDCFG0, 0x08080); */
615 ledsetting = rtw_read32(pAdapter, REG_LEDCFG0);
616
617
618 PHY_LCCalibrate(pAdapter);
619 PHY_IQCalibrate(pAdapter, _FALSE);
620 /* dm_check_txpowertracking(&pHalData->odmpriv); */ /* trigger thermal meter */
621
622 PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /* default use Main */
623
624 pMptCtx->backup0xc50 = (u8)phy_query_bb_reg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0);
625 pMptCtx->backup0xc58 = (u8)phy_query_bb_reg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0);
626 pMptCtx->backup0xc30 = (u8)phy_query_bb_reg(pAdapter, rOFDM0_RxDetector1, bMaskByte0);
627 pMptCtx->backup0x52_RF_A = (u8)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
628 pMptCtx->backup0x52_RF_B = (u8)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
629 #ifdef CONFIG_RTL8188E
630 rtw_write32(pAdapter, REG_MACID_NO_LINK_0, 0x0);
631 rtw_write32(pAdapter, REG_MACID_NO_LINK_1, 0x0);
632 #endif
633 #ifdef CONFIG_RTL8814A
634 if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
635 pHalData->BackUp_IG_REG_4_Chnl_Section[0] = (u8)phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
636 pHalData->BackUp_IG_REG_4_Chnl_Section[1] = (u8)phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
637 pHalData->BackUp_IG_REG_4_Chnl_Section[2] = (u8)phy_query_bb_reg(pAdapter, rC_IGI_Jaguar2, bMaskByte0);
638 pHalData->BackUp_IG_REG_4_Chnl_Section[3] = (u8)phy_query_bb_reg(pAdapter, rD_IGI_Jaguar2, bMaskByte0);
639 }
640 #endif
641 return rtStatus;
642 }
643
644 /*-----------------------------------------------------------------------------
645 * Function: MPT_DeInitAdapter()
646 *
647 * Overview: Extra DeInitialization for Mass Production Test.
648 *
649 * Input: PADAPTER pAdapter
650 *
651 * Output: NONE
652 *
653 * Return: NONE
654 *
655 * Revised History:
656 * When Who Remark
657 * 05/08/2007 MHC Create Version 0.
658 * 05/18/2007 MHC Add normal driver MPHalt code.
659 *
660 *---------------------------------------------------------------------------*/
661 void
MPT_DeInitAdapter(PADAPTER pAdapter)662 MPT_DeInitAdapter(
663 PADAPTER pAdapter
664 )
665 {
666 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
667
668 pMptCtx->bMptDrvUnload = _TRUE;
669 #if defined(CONFIG_RTL8723B)
670 _rtw_free_sema(&(pMptCtx->MPh2c_Sema));
671 _cancel_timer_ex(&pMptCtx->MPh2c_timeout_timer);
672 #endif
673 #if defined(CONFIG_RTL8723B)
674 phy_set_bb_reg(pAdapter, 0xA01, BIT0, 1); /* /suggestion by jerry for MP Rx. */
675 #endif
676 #if 0 /* for Windows */
677 PlatformFreeWorkItem(&(pMptCtx->MptWorkItem));
678
679 while (pMptCtx->bMptWorkItemInProgress) {
680 if (NdisWaitEvent(&(pMptCtx->MptWorkItemEvent), 50))
681 break;
682 }
683 NdisFreeSpinLock(&(pMptCtx->MptWorkItemSpinLock));
684 #endif
685 }
686
mpt_ProStartTest(PADAPTER padapter)687 static u8 mpt_ProStartTest(PADAPTER padapter)
688 {
689 PMPT_CONTEXT pMptCtx = &padapter->mppriv.mpt_ctx;
690
691 pMptCtx->bMassProdTest = _TRUE;
692 pMptCtx->is_start_cont_tx = _FALSE;
693 pMptCtx->bCckContTx = _FALSE;
694 pMptCtx->bOfdmContTx = _FALSE;
695 pMptCtx->bSingleCarrier = _FALSE;
696 pMptCtx->is_carrier_suppression = _FALSE;
697 pMptCtx->is_single_tone = _FALSE;
698 pMptCtx->HWTxmode = PACKETS_TX;
699
700 return _SUCCESS;
701 }
702
703 /*
704 * General use
705 */
SetPowerTracking(PADAPTER padapter,u8 enable)706 s32 SetPowerTracking(PADAPTER padapter, u8 enable)
707 {
708
709 hal_mpt_SetPowerTracking(padapter, enable);
710 return 0;
711 }
712
GetPowerTracking(PADAPTER padapter,u8 * enable)713 void GetPowerTracking(PADAPTER padapter, u8 *enable)
714 {
715 hal_mpt_GetPowerTracking(padapter, enable);
716 }
717
rtw_mp_trigger_iqk(PADAPTER padapter)718 void rtw_mp_trigger_iqk(PADAPTER padapter)
719 {
720 PHY_IQCalibrate(padapter, _FALSE);
721 }
722
rtw_mp_trigger_lck(PADAPTER padapter)723 void rtw_mp_trigger_lck(PADAPTER padapter)
724 {
725 PHY_LCCalibrate(padapter);
726 }
727
rtw_mp_trigger_dpk(PADAPTER padapter)728 void rtw_mp_trigger_dpk(PADAPTER padapter)
729 {
730 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
731 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
732
733 halrf_dpk_trigger(pDM_Odm);
734 }
735
init_mp_data(PADAPTER padapter)736 static void init_mp_data(PADAPTER padapter)
737 {
738 u8 v8;
739 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
740 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
741
742 /*disable BCN*/
743 #ifdef CONFIG_PROTSEL_PORT
744 rtw_hal_hw_port_disable(padapter);
745 #else
746 v8 = rtw_read8(padapter, REG_BCN_CTRL);
747 v8 &= ~EN_BCN_FUNCTION;
748 rtw_write8(padapter, REG_BCN_CTRL, v8);
749 #endif
750
751 pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
752 }
753
754
MPT_PwrCtlDM(PADAPTER padapter,u32 trk_type)755 void MPT_PwrCtlDM(PADAPTER padapter, u32 trk_type)
756 {
757 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
758 struct dm_struct *pDM_Odm = &pHalData->odmpriv;
759 u32 rf_ability;
760
761 padapter->mppriv.tssitrk_on = trk_type == 3;
762
763 if (trk_type == 0) { /* thermal PwrTrk off*/
764 struct txpwrtrack_cfg c;
765 u8 chnl = 0 ;
766
767 RTW_INFO("in Thermal tracking off\n");
768 rf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) & ~HAL_RF_TX_PWR_TRACK;
769 halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability);
770 halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_POWER_TRACK_CONTROL, trk_type);
771 halrf_set_pwr_track(pDM_Odm, FALSE);
772 pDM_Odm->rf_calibrate_info.txpowertrack_control = trk_type;
773 if (IS_HARDWARE_TYPE_8822C(padapter))
774 padapter->mppriv.mp_dm = 1; /* default enable dpk tracking */
775 else
776 padapter->mppriv.mp_dm = 0;
777
778 _rtw_memset(&c, 0, sizeof(struct txpwrtrack_cfg));
779 configure_txpower_track(pDM_Odm, &c);
780 odm_clear_txpowertracking_state(pDM_Odm);
781 if (*c.odm_tx_pwr_track_set_pwr) {
782 if (pDM_Odm->support_ic_type == ODM_RTL8188F)
783 (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_A, chnl);
784 else if (pDM_Odm->support_ic_type == ODM_RTL8723D) {
785 (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl);
786 SetTxPower(padapter);
787 } else if (pDM_Odm->support_ic_type == ODM_RTL8192F) {
788 (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_A, chnl);
789 (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_B, chnl);
790 } else {
791 (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl);
792 (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_B, chnl);
793 }
794 }
795 return ;
796 }
797
798 rf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) | HAL_RF_TX_PWR_TRACK;
799 halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability);
800 halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_POWER_TRACK_CONTROL, trk_type);
801 if (trk_type == 1 || trk_type == 3) /* Thermal PwrTrk ON , TSSI PwrTrk ON */
802 halrf_set_pwr_track(pDM_Odm, TRUE);
803 else
804 halrf_set_pwr_track(pDM_Odm, false);/* TSSI K */
805 pDM_Odm->rf_calibrate_info.txpowertrack_control = trk_type;
806 padapter->mppriv.mp_dm = 1;
807
808 }
809
810
mp_join(PADAPTER padapter,u8 mode)811 u32 mp_join(PADAPTER padapter, u8 mode)
812 {
813 WLAN_BSSID_EX bssid;
814 struct sta_info *psta;
815 u32 length;
816 _irqL irqL;
817 s32 res = _SUCCESS;
818
819 struct mp_priv *pmppriv = &padapter->mppriv;
820 struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
821 struct wlan_network *tgt_network = &pmlmepriv->cur_network;
822 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
823 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
824 WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
825
826 /* 1. initialize a new WLAN_BSSID_EX */
827 _rtw_memset(&bssid, 0, sizeof(WLAN_BSSID_EX));
828 RTW_INFO("%s ,pmppriv->network_macaddr=%x %x %x %x %x %x\n", __func__,
829 pmppriv->network_macaddr[0], pmppriv->network_macaddr[1], pmppriv->network_macaddr[2], pmppriv->network_macaddr[3], pmppriv->network_macaddr[4],
830 pmppriv->network_macaddr[5]);
831 _rtw_memcpy(bssid.MacAddress, pmppriv->network_macaddr, ETH_ALEN);
832
833 if (mode == WIFI_FW_ADHOC_STATE) {
834 bssid.Ssid.SsidLength = strlen("mp_pseudo_adhoc");
835 _rtw_memcpy(bssid.Ssid.Ssid, (u8 *)"mp_pseudo_adhoc", bssid.Ssid.SsidLength);
836 bssid.InfrastructureMode = Ndis802_11IBSS;
837 bssid.IELength = 0;
838 bssid.Configuration.DSConfig = pmppriv->channel;
839
840 } else if (mode == WIFI_FW_STATION_STATE) {
841 bssid.Ssid.SsidLength = strlen("mp_pseudo_STATION");
842 _rtw_memcpy(bssid.Ssid.Ssid, (u8 *)"mp_pseudo_STATION", bssid.Ssid.SsidLength);
843 bssid.InfrastructureMode = Ndis802_11Infrastructure;
844 bssid.IELength = 0;
845 }
846
847 length = get_WLAN_BSSID_EX_sz(&bssid);
848 if (length % 4)
849 bssid.Length = ((length >> 2) + 1) << 2; /* round up to multiple of 4 bytes. */
850 else
851 bssid.Length = length;
852
853 _enter_critical_bh(&pmlmepriv->lock, &irqL);
854
855 if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
856 goto end_of_mp_start_test;
857
858 /* init mp_start_test status */
859 if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
860 rtw_disassoc_cmd(padapter, 500, 0);
861 rtw_indicate_disconnect(padapter, 0, _FALSE);
862 rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);
863 }
864 pmppriv->prev_fw_state = get_fwstate(pmlmepriv);
865 /*pmlmepriv->fw_state = WIFI_MP_STATE;*/
866 init_fwstate(pmlmepriv, WIFI_MP_STATE);
867
868 set_fwstate(pmlmepriv, WIFI_UNDER_LINKING);
869
870 /* 3 2. create a new psta for mp driver */
871 /* clear psta in the cur_network, if any */
872 psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress);
873 if (psta)
874 rtw_free_stainfo(padapter, psta);
875
876 psta = rtw_alloc_stainfo(&padapter->stapriv, bssid.MacAddress);
877 if (psta == NULL) {
878 /*pmlmepriv->fw_state = pmppriv->prev_fw_state;*/
879 init_fwstate(pmlmepriv, pmppriv->prev_fw_state);
880 res = _FAIL;
881 goto end_of_mp_start_test;
882 }
883 if (mode == WIFI_FW_ADHOC_STATE)
884 set_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
885 else
886 set_fwstate(pmlmepriv, WIFI_STATION_STATE);
887 /* 3 3. join psudo AdHoc */
888 tgt_network->join_res = 1;
889 tgt_network->aid = psta->cmn.aid = 1;
890
891 _rtw_memcpy(&padapter->registrypriv.dev_network, &bssid, length);
892 rtw_update_registrypriv_dev_network(padapter);
893 _rtw_memcpy(&tgt_network->network, &padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length);
894 _rtw_memcpy(pnetwork, &padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length);
895
896 rtw_indicate_connect(padapter);
897 _clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
898 set_fwstate(pmlmepriv, WIFI_ASOC_STATE);
899
900 end_of_mp_start_test:
901
902 _exit_critical_bh(&pmlmepriv->lock, &irqL);
903
904 if (1) { /* (res == _SUCCESS) */
905 /* set MSR to WIFI_FW_ADHOC_STATE */
906 if (mode == WIFI_FW_ADHOC_STATE) {
907 /* set msr to WIFI_FW_ADHOC_STATE */
908 pmlmeinfo->state = WIFI_FW_ADHOC_STATE;
909 Set_MSR(padapter, (pmlmeinfo->state & 0x3));
910 rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress);
911 rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED);
912 pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;
913 } else {
914 Set_MSR(padapter, WIFI_FW_STATION_STATE);
915
916 RTW_INFO("%s , pmppriv->network_macaddr =%x %x %x %x %x %x\n", __func__,
917 pmppriv->network_macaddr[0], pmppriv->network_macaddr[1], pmppriv->network_macaddr[2], pmppriv->network_macaddr[3], pmppriv->network_macaddr[4],
918 pmppriv->network_macaddr[5]);
919
920 rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmppriv->network_macaddr);
921 }
922 }
923
924 return res;
925 }
926 /* This function initializes the DUT to the MP test mode */
mp_start_test(PADAPTER padapter)927 s32 mp_start_test(PADAPTER padapter)
928 {
929 struct mp_priv *pmppriv = &padapter->mppriv;
930 #ifdef CONFIG_PCI_HCI
931 PHAL_DATA_TYPE hal;
932 #endif
933 s32 res = _SUCCESS;
934
935 padapter->registrypriv.mp_mode = 1;
936
937 init_mp_data(padapter);
938 #ifdef CONFIG_RTL8814A
939 rtl8814_InitHalDm(padapter);
940 #endif /* CONFIG_RTL8814A */
941 #ifdef CONFIG_RTL8812A
942 rtl8812_InitHalDm(padapter);
943 #endif /* CONFIG_RTL8812A */
944 #ifdef CONFIG_RTL8723B
945 rtl8723b_InitHalDm(padapter);
946 #endif /* CONFIG_RTL8723B */
947 #ifdef CONFIG_RTL8703B
948 rtl8703b_InitHalDm(padapter);
949 #endif /* CONFIG_RTL8703B */
950 #ifdef CONFIG_RTL8192E
951 rtl8192e_InitHalDm(padapter);
952 #endif
953 #ifdef CONFIG_RTL8188F
954 rtl8188f_InitHalDm(padapter);
955 #endif
956 #ifdef CONFIG_RTL8188GTV
957 rtl8188gtv_InitHalDm(padapter);
958 #endif
959 #ifdef CONFIG_RTL8188E
960 rtl8188e_InitHalDm(padapter);
961 #endif
962 #ifdef CONFIG_RTL8723D
963 rtl8723d_InitHalDm(padapter);
964 #endif /* CONFIG_RTL8723D */
965
966 #ifdef CONFIG_PCI_HCI
967 hal = GET_HAL_DATA(padapter);
968 hal->pci_backdoor_ctrl = 0;
969 rtw_pci_aspm_config(padapter);
970 #endif
971
972
973 /* 3 0. update mp_priv */
974 switch (GET_HAL_RFPATH(padapter)) {
975 case RF_1T1R:
976 pmppriv->antenna_tx = ANTENNA_A;
977 pmppriv->antenna_rx = ANTENNA_A;
978 break;
979 case RF_1T2R:
980 default:
981 pmppriv->antenna_tx = ANTENNA_A;
982 pmppriv->antenna_rx = ANTENNA_AB;
983 break;
984 case RF_2T2R:
985 pmppriv->antenna_tx = ANTENNA_AB;
986 pmppriv->antenna_rx = ANTENNA_AB;
987 break;
988 case RF_2T4R:
989 pmppriv->antenna_tx = ANTENNA_AB;
990 pmppriv->antenna_rx = ANTENNA_ABCD;
991 break;
992 }
993
994 mpt_ProStartTest(padapter);
995
996 mp_join(padapter, WIFI_FW_ADHOC_STATE);
997
998 return res;
999 }
1000 /* ------------------------------------------------------------------------------
1001 * This function change the DUT from the MP test mode into normal mode */
mp_stop_test(PADAPTER padapter)1002 void mp_stop_test(PADAPTER padapter)
1003 {
1004 struct mp_priv *pmppriv = &padapter->mppriv;
1005 struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
1006 struct wlan_network *tgt_network = &pmlmepriv->cur_network;
1007 struct sta_info *psta;
1008 #ifdef CONFIG_PCI_HCI
1009 struct registry_priv *registry_par = &padapter->registrypriv;
1010 PHAL_DATA_TYPE hal;
1011 #endif
1012
1013 _irqL irqL;
1014
1015 if (pmppriv->mode == MP_ON) {
1016 pmppriv->bSetTxPower = 0;
1017 _enter_critical_bh(&pmlmepriv->lock, &irqL);
1018 if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE)
1019 goto end_of_mp_stop_test;
1020
1021 /* 3 1. disconnect psudo AdHoc */
1022 rtw_indicate_disconnect(padapter, 0, _FALSE);
1023
1024 /* 3 2. clear psta used in mp test mode.
1025 * rtw_free_assoc_resources(padapter, _TRUE); */
1026 psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress);
1027 if (psta)
1028 rtw_free_stainfo(padapter, psta);
1029
1030 /* 3 3. return to normal state (default:station mode) */
1031 /*pmlmepriv->fw_state = pmppriv->prev_fw_state; */ /* WIFI_STATION_STATE;*/
1032 init_fwstate(pmlmepriv, pmppriv->prev_fw_state);
1033
1034 /* flush the cur_network */
1035 _rtw_memset(tgt_network, 0, sizeof(struct wlan_network));
1036
1037 _clr_fwstate_(pmlmepriv, WIFI_MP_STATE);
1038
1039 end_of_mp_stop_test:
1040
1041 _exit_critical_bh(&pmlmepriv->lock, &irqL);
1042
1043 #ifdef CONFIG_PCI_HCI
1044 hal = GET_HAL_DATA(padapter);
1045 hal->pci_backdoor_ctrl = registry_par->pci_aspm_config;
1046 rtw_pci_aspm_config(padapter);
1047 #endif
1048
1049 #ifdef CONFIG_RTL8812A
1050 rtl8812_InitHalDm(padapter);
1051 #endif
1052 #ifdef CONFIG_RTL8723B
1053 rtl8723b_InitHalDm(padapter);
1054 #endif
1055 #ifdef CONFIG_RTL8703B
1056 rtl8703b_InitHalDm(padapter);
1057 #endif
1058 #ifdef CONFIG_RTL8192E
1059 rtl8192e_InitHalDm(padapter);
1060 #endif
1061 #ifdef CONFIG_RTL8188F
1062 rtl8188f_InitHalDm(padapter);
1063 #endif
1064 #ifdef CONFIG_RTL8188GTV
1065 rtl8188gtv_InitHalDm(padapter);
1066 #endif
1067 #ifdef CONFIG_RTL8723D
1068 rtl8723d_InitHalDm(padapter);
1069 #endif
1070 }
1071 }
1072 /*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
1073 #if 0
1074 /* #ifdef CONFIG_USB_HCI */
1075 static void mpt_AdjustRFRegByRateByChan92CU(PADAPTER pAdapter, u8 RateIdx, u8 Channel, u8 BandWidthID)
1076 {
1077 u8 eRFPath;
1078 u32 rfReg0x26;
1079 struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter);
1080
1081
1082 if (RateIdx < MPT_RATE_6M) /* CCK rate,for 88cu */
1083 rfReg0x26 = 0xf400;
1084 else if ((RateIdx >= MPT_RATE_6M) && (RateIdx <= MPT_RATE_54M)) {/* OFDM rate,for 88cu */
1085 if ((4 == Channel) || (8 == Channel) || (12 == Channel))
1086 rfReg0x26 = 0xf000;
1087 else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))
1088 rfReg0x26 = 0xf400;
1089 else
1090 rfReg0x26 = 0x4f200;
1091 } else if ((RateIdx >= MPT_RATE_MCS0) && (RateIdx <= MPT_RATE_MCS15)) {
1092 /* MCS 20M ,for 88cu */ /* MCS40M rate,for 88cu */
1093
1094 if (CHANNEL_WIDTH_20 == BandWidthID) {
1095 if ((4 == Channel) || (8 == Channel))
1096 rfReg0x26 = 0xf000;
1097 else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))
1098 rfReg0x26 = 0xf400;
1099 else
1100 rfReg0x26 = 0x4f200;
1101 } else {
1102 if ((4 == Channel) || (8 == Channel))
1103 rfReg0x26 = 0xf000;
1104 else if ((5 == Channel) || (7 == Channel))
1105 rfReg0x26 = 0xf400;
1106 else
1107 rfReg0x26 = 0x4f200;
1108 }
1109 }
1110
1111 for (eRFPath = 0; eRFPath < hal_spec->rf_reg_path_num; eRFPath++)
1112 write_rfreg(pAdapter, eRFPath, RF_SYN_G2, rfReg0x26);
1113 }
1114 #endif
1115 /*-----------------------------------------------------------------------------
1116 * Function: mpt_SwitchRfSetting
1117 *
1118 * Overview: Change RF Setting when we siwthc channel/rate/BW for MP.
1119 *
1120 * Input: PADAPTER pAdapter
1121 *
1122 * Output: NONE
1123 *
1124 * Return: NONE
1125 *
1126 * Revised History:
1127 * When Who Remark
1128 * 01/08/2009 MHC Suggestion from SD3 Willis for 92S series.
1129 * 01/09/2009 MHC Add CCK modification for 40MHZ. Suggestion from SD3.
1130 *
1131 *---------------------------------------------------------------------------*/
1132 #if 0
1133 static void mpt_SwitchRfSetting(PADAPTER pAdapter)
1134 {
1135 hal_mpt_SwitchRfSetting(pAdapter);
1136 }
1137
1138 /*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
1139 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
1140 static void MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
1141 {
1142 hal_mpt_CCKTxPowerAdjust(Adapter, bInCH14);
1143 }
1144 #endif
1145
1146 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
1147
1148 /*
1149 * SetChannel
1150 * Description
1151 * Use H2C command to change channel,
1152 * not only modify rf register, but also other setting need to be done.
1153 */
SetChannel(PADAPTER pAdapter)1154 void SetChannel(PADAPTER pAdapter)
1155 {
1156 hal_mpt_SetChannel(pAdapter);
1157 }
1158
1159 /*
1160 * Notice
1161 * Switch bandwitdth may change center frequency(channel)
1162 */
SetBandwidth(PADAPTER pAdapter)1163 void SetBandwidth(PADAPTER pAdapter)
1164 {
1165 hal_mpt_SetBandwidth(pAdapter);
1166
1167 }
1168
SetAntenna(PADAPTER pAdapter)1169 void SetAntenna(PADAPTER pAdapter)
1170 {
1171 hal_mpt_SetAntenna(pAdapter);
1172 }
1173
SetTxPower(PADAPTER pAdapter)1174 int SetTxPower(PADAPTER pAdapter)
1175 {
1176
1177 hal_mpt_SetTxPower(pAdapter);
1178 return _TRUE;
1179 }
1180
SetTxAGCOffset(PADAPTER pAdapter,u32 ulTxAGCOffset)1181 void SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset)
1182 {
1183 u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC;
1184
1185 TxAGCOffset_B = (ulTxAGCOffset & 0x000000ff);
1186 TxAGCOffset_C = ((ulTxAGCOffset & 0x0000ff00) >> 8);
1187 TxAGCOffset_D = ((ulTxAGCOffset & 0x00ff0000) >> 16);
1188
1189 tmpAGC = (TxAGCOffset_D << 8 | TxAGCOffset_C << 4 | TxAGCOffset_B);
1190 write_bbreg(pAdapter, rFPGA0_TxGainStage,
1191 (bXBTxAGC | bXCTxAGC | bXDTxAGC), tmpAGC);
1192 }
1193
SetDataRate(PADAPTER pAdapter)1194 void SetDataRate(PADAPTER pAdapter)
1195 {
1196 hal_mpt_SetDataRate(pAdapter);
1197 }
1198
MP_PHY_SetRFPathSwitch(PADAPTER pAdapter,BOOLEAN bMain)1199 void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain)
1200 {
1201
1202 PHY_SetRFPathSwitch(pAdapter, bMain);
1203
1204 }
1205
mp_phy_switch_rf_path_set(PADAPTER pAdapter,u8 * pstate)1206 void mp_phy_switch_rf_path_set(PADAPTER pAdapter , u8 *pstate)
1207 {
1208
1209 phy_switch_rf_path_set(pAdapter, pstate);
1210
1211 }
1212
MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter)1213 u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter)
1214 {
1215 return PHY_QueryRFPathSwitch(pAdapter);
1216 }
1217
SetThermalMeter(PADAPTER pAdapter,u8 target_ther)1218 s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
1219 {
1220 return hal_mpt_SetThermalMeter(pAdapter, target_ther);
1221 }
1222
1223 #if 0
1224 static void TriggerRFThermalMeter(PADAPTER pAdapter)
1225 {
1226 hal_mpt_TriggerRFThermalMeter(pAdapter);
1227 }
1228
1229 static u8 ReadRFThermalMeter(PADAPTER pAdapter)
1230 {
1231 return hal_mpt_ReadRFThermalMeter(pAdapter);
1232 }
1233 #endif
1234
GetThermalMeter(PADAPTER pAdapter,u8 rfpath,u8 * value)1235 void GetThermalMeter(PADAPTER pAdapter, u8 rfpath ,u8 *value)
1236 {
1237 hal_mpt_GetThermalMeter(pAdapter, rfpath, value);
1238 }
1239
SetSingleCarrierTx(PADAPTER pAdapter,u8 bStart)1240 void SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
1241 {
1242 PhySetTxPowerLevel(pAdapter);
1243 hal_mpt_SetSingleCarrierTx(pAdapter, bStart);
1244 }
1245
SetSingleToneTx(PADAPTER pAdapter,u8 bStart)1246 void SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
1247 {
1248 PhySetTxPowerLevel(pAdapter);
1249 hal_mpt_SetSingleToneTx(pAdapter, bStart);
1250 }
1251
SetCarrierSuppressionTx(PADAPTER pAdapter,u8 bStart)1252 void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
1253 {
1254 PhySetTxPowerLevel(pAdapter);
1255 hal_mpt_SetCarrierSuppressionTx(pAdapter, bStart);
1256 }
1257
SetContinuousTx(PADAPTER pAdapter,u8 bStart)1258 void SetContinuousTx(PADAPTER pAdapter, u8 bStart)
1259 {
1260 PhySetTxPowerLevel(pAdapter);
1261 hal_mpt_SetContinuousTx(pAdapter, bStart);
1262 }
1263
1264
PhySetTxPowerLevel(PADAPTER pAdapter)1265 void PhySetTxPowerLevel(PADAPTER pAdapter)
1266 {
1267 struct mp_priv *pmp_priv = &pAdapter->mppriv;
1268
1269
1270 if (pmp_priv->bSetTxPower == 0) /* for NO manually set power index */
1271 rtw_hal_set_tx_power_level(pAdapter, pmp_priv->channel);
1272 }
1273
1274 /* ------------------------------------------------------------------------------ */
dump_mpframe(PADAPTER padapter,struct xmit_frame * pmpframe)1275 static void dump_mpframe(PADAPTER padapter, struct xmit_frame *pmpframe)
1276 {
1277 rtw_hal_mgnt_xmit(padapter, pmpframe);
1278 }
1279
alloc_mp_xmitframe(struct xmit_priv * pxmitpriv)1280 static struct xmit_frame *alloc_mp_xmitframe(struct xmit_priv *pxmitpriv)
1281 {
1282 struct xmit_frame *pmpframe;
1283 struct xmit_buf *pxmitbuf;
1284
1285 pmpframe = rtw_alloc_xmitframe(pxmitpriv, 0);
1286 if (pmpframe == NULL)
1287 return NULL;
1288
1289 pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
1290 if (pxmitbuf == NULL) {
1291 rtw_free_xmitframe(pxmitpriv, pmpframe);
1292 return NULL;
1293 }
1294
1295 pmpframe->frame_tag = MP_FRAMETAG;
1296
1297 pmpframe->pxmitbuf = pxmitbuf;
1298
1299 pmpframe->buf_addr = pxmitbuf->pbuf;
1300
1301 pxmitbuf->priv_data = pmpframe;
1302
1303 return pmpframe;
1304
1305 }
1306
1307 #ifdef CONFIG_PCI_HCI
check_nic_enough_desc(_adapter * padapter,struct pkt_attrib * pattrib)1308 static u8 check_nic_enough_desc(_adapter *padapter, struct pkt_attrib *pattrib)
1309 {
1310 u32 prio;
1311 struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
1312 struct rtw_tx_ring *ring;
1313
1314 switch (pattrib->qsel) {
1315 case 0:
1316 case 3:
1317 prio = BE_QUEUE_INX;
1318 break;
1319 case 1:
1320 case 2:
1321 prio = BK_QUEUE_INX;
1322 break;
1323 case 4:
1324 case 5:
1325 prio = VI_QUEUE_INX;
1326 break;
1327 case 6:
1328 case 7:
1329 prio = VO_QUEUE_INX;
1330 break;
1331 default:
1332 prio = BE_QUEUE_INX;
1333 break;
1334 }
1335
1336 ring = &pxmitpriv->tx_ring[prio];
1337
1338 /*
1339 * for now we reserve two free descriptor as a safety boundary
1340 * between the tail and the head
1341 */
1342 if ((ring->entries - ring->qlen) >= 2)
1343 return _TRUE;
1344 else
1345 return _FALSE;
1346 }
1347 #endif
1348
mp_xmit_packet_thread(thread_context context)1349 static thread_return mp_xmit_packet_thread(thread_context context)
1350 {
1351 struct xmit_frame *pxmitframe;
1352 struct mp_tx *pmptx;
1353 struct mp_priv *pmp_priv;
1354 struct xmit_priv *pxmitpriv;
1355 PADAPTER padapter;
1356
1357 pmp_priv = (struct mp_priv *)context;
1358 pmptx = &pmp_priv->tx;
1359 padapter = pmp_priv->papdater;
1360 pxmitpriv = &(padapter->xmitpriv);
1361
1362 thread_enter("RTW_MP_THREAD");
1363
1364 RTW_INFO("%s:pkTx Start\n", __func__);
1365 while (1) {
1366 pxmitframe = alloc_mp_xmitframe(pxmitpriv);
1367 #ifdef CONFIG_PCI_HCI
1368 if(check_nic_enough_desc(padapter, &pmptx->attrib) == _FALSE) {
1369 rtw_usleep_os(1000);
1370 continue;
1371 }
1372 #endif
1373 if (pxmitframe == NULL) {
1374 if (pmptx->stop ||
1375 RTW_CANNOT_RUN(padapter))
1376 goto exit;
1377 else {
1378 rtw_usleep_os(10);
1379 continue;
1380 }
1381 }
1382 _rtw_memcpy((u8 *)(pxmitframe->buf_addr + TXDESC_OFFSET), pmptx->buf, pmptx->write_size);
1383 _rtw_memcpy(&(pxmitframe->attrib), &(pmptx->attrib), sizeof(struct pkt_attrib));
1384
1385
1386 rtw_usleep_os(padapter->mppriv.pktInterval);
1387 dump_mpframe(padapter, pxmitframe);
1388
1389 pmptx->sended++;
1390 pmp_priv->tx_pktcount++;
1391
1392 if (pmptx->stop ||
1393 RTW_CANNOT_RUN(padapter))
1394 goto exit;
1395 if ((pmptx->count != 0) &&
1396 (pmptx->count == pmptx->sended))
1397 goto exit;
1398
1399 flush_signals_thread();
1400 }
1401
1402 exit:
1403 /* RTW_INFO("%s:pkTx Exit\n", __func__); */
1404 rtw_mfree(pmptx->pallocated_buf, pmptx->buf_size);
1405 pmptx->pallocated_buf = NULL;
1406 pmptx->stop = 1;
1407
1408 thread_exit(NULL);
1409 return 0;
1410 }
1411
fill_txdesc_for_mp(PADAPTER padapter,u8 * ptxdesc)1412 void fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc)
1413 {
1414 struct mp_priv *pmp_priv = &padapter->mppriv;
1415 _rtw_memcpy(ptxdesc, pmp_priv->tx.desc, TXDESC_SIZE);
1416 }
1417
1418 #if defined(CONFIG_RTL8188E)
fill_tx_desc_8188e(PADAPTER padapter)1419 void fill_tx_desc_8188e(PADAPTER padapter)
1420 {
1421 struct mp_priv *pmp_priv = &padapter->mppriv;
1422 struct tx_desc *desc = (struct tx_desc *)&(pmp_priv->tx.desc);
1423 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1424 u32 pkt_size = pattrib->last_txcmdsz;
1425 s32 bmcast = IS_MCAST(pattrib->ra);
1426 /* offset 0 */
1427 #if !defined(CONFIG_RTL8188E_SDIO) && !defined(CONFIG_PCI_HCI)
1428 desc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
1429 desc->txdw0 |= cpu_to_le32(pkt_size & 0x0000FFFF); /* packet size */
1430 desc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00FF0000); /* 32 bytes for TX Desc */
1431 if (bmcast)
1432 desc->txdw0 |= cpu_to_le32(BMC); /* broadcast packet */
1433
1434 desc->txdw1 |= cpu_to_le32((0x01 << 26) & 0xff000000);
1435 #endif
1436
1437 desc->txdw1 |= cpu_to_le32((pattrib->mac_id) & 0x3F); /* CAM_ID(MAC_ID) */
1438 desc->txdw1 |= cpu_to_le32((pattrib->qsel << QSEL_SHT) & 0x00001F00); /* Queue Select, TID */
1439 desc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000F0000); /* Rate Adaptive ID */
1440 /* offset 8 */
1441 /* desc->txdw2 |= cpu_to_le32(AGG_BK); */ /* AGG BK */
1442
1443 desc->txdw3 |= cpu_to_le32((pattrib->seqnum << 16) & 0x0fff0000);
1444 desc->txdw4 |= cpu_to_le32(HW_SSN);
1445
1446 desc->txdw4 |= cpu_to_le32(USERATE);
1447 desc->txdw4 |= cpu_to_le32(DISDATAFB);
1448
1449 if (pmp_priv->preamble) {
1450 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1451 desc->txdw4 |= cpu_to_le32(DATA_SHORT); /* CCK Short Preamble */
1452 }
1453
1454 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1455 desc->txdw4 |= cpu_to_le32(DATA_BW);
1456
1457 /* offset 20 */
1458 desc->txdw5 |= cpu_to_le32(pmp_priv->rateidx & 0x0000001F);
1459
1460 if (pmp_priv->preamble) {
1461 if (HwRateToMPTRate(pmp_priv->rateidx) > MPT_RATE_54M)
1462 desc->txdw5 |= cpu_to_le32(SGI); /* MCS Short Guard Interval */
1463 }
1464
1465 desc->txdw5 |= cpu_to_le32(RTY_LMT_EN); /* retry limit enable */
1466 desc->txdw5 |= cpu_to_le32(0x00180000); /* DATA/RTS Rate Fallback Limit */
1467
1468
1469 }
1470 #endif
1471
1472 #if defined(CONFIG_RTL8814A)
fill_tx_desc_8814a(PADAPTER padapter)1473 void fill_tx_desc_8814a(PADAPTER padapter)
1474 {
1475 struct mp_priv *pmp_priv = &padapter->mppriv;
1476 u8 *pDesc = (u8 *)&(pmp_priv->tx.desc);
1477 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1478
1479 u32 pkt_size = pattrib->last_txcmdsz;
1480 s32 bmcast = IS_MCAST(pattrib->ra);
1481 u8 offset;
1482
1483 /* SET_TX_DESC_FIRST_SEG_8814A(pDesc, 1); */
1484 SET_TX_DESC_LAST_SEG_8814A(pDesc, 1);
1485 /* SET_TX_DESC_OWN_(pDesc, 1); */
1486
1487 SET_TX_DESC_PKT_SIZE_8814A(pDesc, pkt_size);
1488
1489 offset = TXDESC_SIZE + OFFSET_SZ;
1490
1491 SET_TX_DESC_OFFSET_8814A(pDesc, offset);
1492 #if defined(CONFIG_PCI_HCI)
1493 SET_TX_DESC_PKT_OFFSET_8814A(pDesc, 0); /* 8814AE pkt_offset is 0 */
1494 #else
1495 SET_TX_DESC_PKT_OFFSET_8814A(pDesc, 1);
1496 #endif
1497
1498 if (bmcast)
1499 SET_TX_DESC_BMC_8814A(pDesc, 1);
1500
1501 SET_TX_DESC_MACID_8814A(pDesc, pattrib->mac_id);
1502 SET_TX_DESC_RATE_ID_8814A(pDesc, pattrib->raid);
1503
1504 /* SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G); */
1505 SET_TX_DESC_QUEUE_SEL_8814A(pDesc, pattrib->qsel);
1506 /* SET_TX_DESC_QUEUE_SEL_8812(pDesc, QSLT_MGNT); */
1507
1508 if (pmp_priv->preamble)
1509 SET_TX_DESC_DATA_SHORT_8814A(pDesc, 1);
1510
1511 if (!pattrib->qos_en) {
1512 SET_TX_DESC_HWSEQ_EN_8814A(pDesc, 1); /* Hw set sequence number */
1513 } else
1514 SET_TX_DESC_SEQ_8814A(pDesc, pattrib->seqnum);
1515
1516 if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160)
1517 SET_TX_DESC_DATA_BW_8814A(pDesc, pmp_priv->bandwidth);
1518 else {
1519 RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
1520 SET_TX_DESC_DATA_BW_8814A(pDesc, CHANNEL_WIDTH_20);
1521 }
1522
1523 SET_TX_DESC_DISABLE_FB_8814A(pDesc, 1);
1524 SET_TX_DESC_USE_RATE_8814A(pDesc, 1);
1525 SET_TX_DESC_TX_RATE_8814A(pDesc, pmp_priv->rateidx);
1526
1527 }
1528 #endif
1529
1530 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
fill_tx_desc_8812a(PADAPTER padapter)1531 void fill_tx_desc_8812a(PADAPTER padapter)
1532 {
1533 struct mp_priv *pmp_priv = &padapter->mppriv;
1534 u8 *pDesc = (u8 *)&(pmp_priv->tx.desc);
1535 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1536
1537 u32 pkt_size = pattrib->last_txcmdsz;
1538 s32 bmcast = IS_MCAST(pattrib->ra);
1539 u8 data_rate, pwr_status, offset;
1540
1541 SET_TX_DESC_FIRST_SEG_8812(pDesc, 1);
1542 SET_TX_DESC_LAST_SEG_8812(pDesc, 1);
1543 SET_TX_DESC_OWN_8812(pDesc, 1);
1544
1545 SET_TX_DESC_PKT_SIZE_8812(pDesc, pkt_size);
1546
1547 offset = TXDESC_SIZE + OFFSET_SZ;
1548
1549 SET_TX_DESC_OFFSET_8812(pDesc, offset);
1550
1551 #if defined(CONFIG_PCI_HCI)
1552 SET_TX_DESC_PKT_OFFSET_8812(pDesc, 0);
1553 #else
1554 SET_TX_DESC_PKT_OFFSET_8812(pDesc, 1);
1555 #endif
1556 if (bmcast)
1557 SET_TX_DESC_BMC_8812(pDesc, 1);
1558
1559 SET_TX_DESC_MACID_8812(pDesc, pattrib->mac_id);
1560 SET_TX_DESC_RATE_ID_8812(pDesc, pattrib->raid);
1561
1562 /* SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G); */
1563 SET_TX_DESC_QUEUE_SEL_8812(pDesc, pattrib->qsel);
1564 /* SET_TX_DESC_QUEUE_SEL_8812(pDesc, QSLT_MGNT); */
1565
1566 if (!pattrib->qos_en) {
1567 SET_TX_DESC_HWSEQ_EN_8812(pDesc, 1); /* Hw set sequence number */
1568 } else
1569 SET_TX_DESC_SEQ_8812(pDesc, pattrib->seqnum);
1570
1571 if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160)
1572 SET_TX_DESC_DATA_BW_8812(pDesc, pmp_priv->bandwidth);
1573 else {
1574 RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
1575 SET_TX_DESC_DATA_BW_8812(pDesc, CHANNEL_WIDTH_20);
1576 }
1577
1578 SET_TX_DESC_DISABLE_FB_8812(pDesc, 1);
1579 SET_TX_DESC_USE_RATE_8812(pDesc, 1);
1580 SET_TX_DESC_TX_RATE_8812(pDesc, pmp_priv->rateidx);
1581
1582 }
1583 #endif
1584 #if defined(CONFIG_RTL8192E)
fill_tx_desc_8192e(PADAPTER padapter)1585 void fill_tx_desc_8192e(PADAPTER padapter)
1586 {
1587 struct mp_priv *pmp_priv = &padapter->mppriv;
1588 u8 *pDesc = (u8 *)&(pmp_priv->tx.desc);
1589 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1590
1591 u32 pkt_size = pattrib->last_txcmdsz;
1592 s32 bmcast = IS_MCAST(pattrib->ra);
1593 u8 data_rate, pwr_status, offset;
1594
1595
1596 SET_TX_DESC_PKT_SIZE_92E(pDesc, pkt_size);
1597
1598 offset = TXDESC_SIZE + OFFSET_SZ;
1599
1600 SET_TX_DESC_OFFSET_92E(pDesc, offset);
1601 #if defined(CONFIG_PCI_HCI) /* 8192EE */
1602
1603 SET_TX_DESC_PKT_OFFSET_92E(pDesc, 0); /* 8192EE pkt_offset is 0 */
1604 #else /* 8192EU 8192ES */
1605 SET_TX_DESC_PKT_OFFSET_92E(pDesc, 1);
1606 #endif
1607
1608 if (bmcast)
1609 SET_TX_DESC_BMC_92E(pDesc, 1);
1610
1611 SET_TX_DESC_MACID_92E(pDesc, pattrib->mac_id);
1612 SET_TX_DESC_RATE_ID_92E(pDesc, pattrib->raid);
1613
1614
1615 SET_TX_DESC_QUEUE_SEL_92E(pDesc, pattrib->qsel);
1616 /* SET_TX_DESC_QUEUE_SEL_8812(pDesc, QSLT_MGNT); */
1617
1618 if (!pattrib->qos_en) {
1619 SET_TX_DESC_EN_HWSEQ_92E(pDesc, 1);/* Hw set sequence number */
1620 SET_TX_DESC_HWSEQ_SEL_92E(pDesc, pattrib->hw_ssn_sel);
1621 } else
1622 SET_TX_DESC_SEQ_92E(pDesc, pattrib->seqnum);
1623
1624 if ((pmp_priv->bandwidth == CHANNEL_WIDTH_20) || (pmp_priv->bandwidth == CHANNEL_WIDTH_40))
1625 SET_TX_DESC_DATA_BW_92E(pDesc, pmp_priv->bandwidth);
1626 else {
1627 RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
1628 SET_TX_DESC_DATA_BW_92E(pDesc, CHANNEL_WIDTH_20);
1629 }
1630
1631 /* SET_TX_DESC_DATA_SC_92E(pDesc, SCMapping_92E(padapter,pattrib)); */
1632
1633 SET_TX_DESC_DISABLE_FB_92E(pDesc, 1);
1634 SET_TX_DESC_USE_RATE_92E(pDesc, 1);
1635 SET_TX_DESC_TX_RATE_92E(pDesc, pmp_priv->rateidx);
1636
1637 }
1638 #endif
1639
1640 #if defined(CONFIG_RTL8723B)
fill_tx_desc_8723b(PADAPTER padapter)1641 void fill_tx_desc_8723b(PADAPTER padapter)
1642 {
1643 struct mp_priv *pmp_priv = &padapter->mppriv;
1644 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1645 u8 *ptxdesc = pmp_priv->tx.desc;
1646
1647 SET_TX_DESC_AGG_BREAK_8723B(ptxdesc, 1);
1648 SET_TX_DESC_MACID_8723B(ptxdesc, pattrib->mac_id);
1649 SET_TX_DESC_QUEUE_SEL_8723B(ptxdesc, pattrib->qsel);
1650
1651 SET_TX_DESC_RATE_ID_8723B(ptxdesc, pattrib->raid);
1652 SET_TX_DESC_SEQ_8723B(ptxdesc, pattrib->seqnum);
1653 SET_TX_DESC_HWSEQ_EN_8723B(ptxdesc, 1);
1654 SET_TX_DESC_USE_RATE_8723B(ptxdesc, 1);
1655 SET_TX_DESC_DISABLE_FB_8723B(ptxdesc, 1);
1656
1657 if (pmp_priv->preamble) {
1658 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1659 SET_TX_DESC_DATA_SHORT_8723B(ptxdesc, 1);
1660 }
1661
1662 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1663 SET_TX_DESC_DATA_BW_8723B(ptxdesc, 1);
1664
1665 SET_TX_DESC_TX_RATE_8723B(ptxdesc, pmp_priv->rateidx);
1666
1667 SET_TX_DESC_DATA_RATE_FB_LIMIT_8723B(ptxdesc, 0x1F);
1668 SET_TX_DESC_RTS_RATE_FB_LIMIT_8723B(ptxdesc, 0xF);
1669 }
1670 #endif
1671
1672 #if defined(CONFIG_RTL8703B)
fill_tx_desc_8703b(PADAPTER padapter)1673 void fill_tx_desc_8703b(PADAPTER padapter)
1674 {
1675 struct mp_priv *pmp_priv = &padapter->mppriv;
1676 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1677 u8 *ptxdesc = pmp_priv->tx.desc;
1678
1679 SET_TX_DESC_AGG_BREAK_8703B(ptxdesc, 1);
1680 SET_TX_DESC_MACID_8703B(ptxdesc, pattrib->mac_id);
1681 SET_TX_DESC_QUEUE_SEL_8703B(ptxdesc, pattrib->qsel);
1682
1683 SET_TX_DESC_RATE_ID_8703B(ptxdesc, pattrib->raid);
1684 SET_TX_DESC_SEQ_8703B(ptxdesc, pattrib->seqnum);
1685 SET_TX_DESC_HWSEQ_EN_8703B(ptxdesc, 1);
1686 SET_TX_DESC_USE_RATE_8703B(ptxdesc, 1);
1687 SET_TX_DESC_DISABLE_FB_8703B(ptxdesc, 1);
1688
1689 if (pmp_priv->preamble) {
1690 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1691 SET_TX_DESC_DATA_SHORT_8703B(ptxdesc, 1);
1692 }
1693
1694 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1695 SET_TX_DESC_DATA_BW_8703B(ptxdesc, 1);
1696
1697 SET_TX_DESC_TX_RATE_8703B(ptxdesc, pmp_priv->rateidx);
1698
1699 SET_TX_DESC_DATA_RATE_FB_LIMIT_8703B(ptxdesc, 0x1F);
1700 SET_TX_DESC_RTS_RATE_FB_LIMIT_8703B(ptxdesc, 0xF);
1701 }
1702 #endif
1703
1704 #if defined(CONFIG_RTL8188F)
fill_tx_desc_8188f(PADAPTER padapter)1705 void fill_tx_desc_8188f(PADAPTER padapter)
1706 {
1707 struct mp_priv *pmp_priv = &padapter->mppriv;
1708 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1709 u8 *ptxdesc = pmp_priv->tx.desc;
1710
1711 SET_TX_DESC_AGG_BREAK_8188F(ptxdesc, 1);
1712 SET_TX_DESC_MACID_8188F(ptxdesc, pattrib->mac_id);
1713 SET_TX_DESC_QUEUE_SEL_8188F(ptxdesc, pattrib->qsel);
1714
1715 SET_TX_DESC_RATE_ID_8188F(ptxdesc, pattrib->raid);
1716 SET_TX_DESC_SEQ_8188F(ptxdesc, pattrib->seqnum);
1717 SET_TX_DESC_HWSEQ_EN_8188F(ptxdesc, 1);
1718 SET_TX_DESC_USE_RATE_8188F(ptxdesc, 1);
1719 SET_TX_DESC_DISABLE_FB_8188F(ptxdesc, 1);
1720
1721 if (pmp_priv->preamble)
1722 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1723 SET_TX_DESC_DATA_SHORT_8188F(ptxdesc, 1);
1724
1725 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1726 SET_TX_DESC_DATA_BW_8188F(ptxdesc, 1);
1727
1728 SET_TX_DESC_TX_RATE_8188F(ptxdesc, pmp_priv->rateidx);
1729
1730 SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(ptxdesc, 0x1F);
1731 SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(ptxdesc, 0xF);
1732 }
1733 #endif
1734
1735 #if defined(CONFIG_RTL8188GTV)
fill_tx_desc_8188gtv(PADAPTER padapter)1736 void fill_tx_desc_8188gtv(PADAPTER padapter)
1737 {
1738 struct mp_priv *pmp_priv = &padapter->mppriv;
1739 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1740 u8 *ptxdesc = pmp_priv->tx.desc;
1741
1742 SET_TX_DESC_AGG_BREAK_8188GTV(ptxdesc, 1);
1743 SET_TX_DESC_MACID_8188GTV(ptxdesc, pattrib->mac_id);
1744 SET_TX_DESC_QUEUE_SEL_8188GTV(ptxdesc, pattrib->qsel);
1745
1746 SET_TX_DESC_RATE_ID_8188GTV(ptxdesc, pattrib->raid);
1747 SET_TX_DESC_SEQ_8188GTV(ptxdesc, pattrib->seqnum);
1748 SET_TX_DESC_HWSEQ_EN_8188GTV(ptxdesc, 1);
1749 SET_TX_DESC_USE_RATE_8188GTV(ptxdesc, 1);
1750 SET_TX_DESC_DISABLE_FB_8188GTV(ptxdesc, 1);
1751
1752 if (pmp_priv->preamble)
1753 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1754 SET_TX_DESC_DATA_SHORT_8188GTV(ptxdesc, 1);
1755
1756 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1757 SET_TX_DESC_DATA_BW_8188GTV(ptxdesc, 1);
1758
1759 SET_TX_DESC_TX_RATE_8188GTV(ptxdesc, pmp_priv->rateidx);
1760
1761 SET_TX_DESC_DATA_RATE_FB_LIMIT_8188GTV(ptxdesc, 0x1F);
1762 SET_TX_DESC_RTS_RATE_FB_LIMIT_8188GTV(ptxdesc, 0xF);
1763 }
1764 #endif
1765
1766 #if defined(CONFIG_RTL8723D)
fill_tx_desc_8723d(PADAPTER padapter)1767 void fill_tx_desc_8723d(PADAPTER padapter)
1768 {
1769 struct mp_priv *pmp_priv = &padapter->mppriv;
1770 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1771 u8 *ptxdesc = pmp_priv->tx.desc;
1772
1773 SET_TX_DESC_BK_8723D(ptxdesc, 1);
1774 SET_TX_DESC_MACID_8723D(ptxdesc, pattrib->mac_id);
1775 SET_TX_DESC_QUEUE_SEL_8723D(ptxdesc, pattrib->qsel);
1776
1777 SET_TX_DESC_RATE_ID_8723D(ptxdesc, pattrib->raid);
1778 SET_TX_DESC_SEQ_8723D(ptxdesc, pattrib->seqnum);
1779 SET_TX_DESC_HWSEQ_EN_8723D(ptxdesc, 1);
1780 SET_TX_DESC_USE_RATE_8723D(ptxdesc, 1);
1781 SET_TX_DESC_DISABLE_FB_8723D(ptxdesc, 1);
1782
1783 if (pmp_priv->preamble) {
1784 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1785 SET_TX_DESC_DATA_SHORT_8723D(ptxdesc, 1);
1786 }
1787
1788 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1789 SET_TX_DESC_DATA_BW_8723D(ptxdesc, 1);
1790
1791 SET_TX_DESC_TX_RATE_8723D(ptxdesc, pmp_priv->rateidx);
1792
1793 SET_TX_DESC_DATA_RATE_FB_LIMIT_8723D(ptxdesc, 0x1F);
1794 SET_TX_DESC_RTS_RATE_FB_LIMIT_8723D(ptxdesc, 0xF);
1795 }
1796 #endif
1797
1798 #if defined(CONFIG_RTL8710B)
fill_tx_desc_8710b(PADAPTER padapter)1799 void fill_tx_desc_8710b(PADAPTER padapter)
1800 {
1801 struct mp_priv *pmp_priv = &padapter->mppriv;
1802 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1803 u8 *ptxdesc = pmp_priv->tx.desc;
1804
1805 SET_TX_DESC_BK_8710B(ptxdesc, 1);
1806 SET_TX_DESC_MACID_8710B(ptxdesc, pattrib->mac_id);
1807 SET_TX_DESC_QUEUE_SEL_8710B(ptxdesc, pattrib->qsel);
1808
1809 SET_TX_DESC_RATE_ID_8710B(ptxdesc, pattrib->raid);
1810 SET_TX_DESC_SEQ_8710B(ptxdesc, pattrib->seqnum);
1811 SET_TX_DESC_HWSEQ_EN_8710B(ptxdesc, 1);
1812 SET_TX_DESC_USE_RATE_8710B(ptxdesc, 1);
1813 SET_TX_DESC_DISABLE_FB_8710B(ptxdesc, 1);
1814
1815 if (pmp_priv->preamble) {
1816 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1817 SET_TX_DESC_DATA_SHORT_8710B(ptxdesc, 1);
1818 }
1819
1820 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1821 SET_TX_DESC_DATA_BW_8710B(ptxdesc, 1);
1822
1823 SET_TX_DESC_TX_RATE_8710B(ptxdesc, pmp_priv->rateidx);
1824
1825 SET_TX_DESC_DATA_RATE_FB_LIMIT_8710B(ptxdesc, 0x1F);
1826 SET_TX_DESC_RTS_RATE_FB_LIMIT_8710B(ptxdesc, 0xF);
1827 }
1828 #endif
1829
1830 #if defined(CONFIG_RTL8192F)
fill_tx_desc_8192f(PADAPTER padapter)1831 void fill_tx_desc_8192f(PADAPTER padapter)
1832 {
1833 struct mp_priv *pmp_priv = &padapter->mppriv;
1834 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1835 u8 *ptxdesc = pmp_priv->tx.desc;
1836
1837 SET_TX_DESC_BK_8192F(ptxdesc, 1);
1838 SET_TX_DESC_MACID_8192F(ptxdesc, pattrib->mac_id);
1839 SET_TX_DESC_QUEUE_SEL_8192F(ptxdesc, pattrib->qsel);
1840
1841 SET_TX_DESC_RATE_ID_8192F(ptxdesc, pattrib->raid);
1842 SET_TX_DESC_SEQ_8192F(ptxdesc, pattrib->seqnum);
1843 SET_TX_DESC_HWSEQ_EN_8192F(ptxdesc, 1);
1844 SET_TX_DESC_USE_RATE_8192F(ptxdesc, 1);
1845 SET_TX_DESC_DISABLE_FB_8192F(ptxdesc, 1);
1846
1847 if (pmp_priv->preamble) {
1848 if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M)
1849 SET_TX_DESC_DATA_SHORT_8192F(ptxdesc, 1);
1850 }
1851
1852 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1853 SET_TX_DESC_DATA_BW_8192F(ptxdesc, 1);
1854
1855 SET_TX_DESC_TX_RATE_8192F(ptxdesc, pmp_priv->rateidx);
1856
1857 SET_TX_DESC_DATA_RATE_FB_LIMIT_8192F(ptxdesc, 0x1F);
1858 SET_TX_DESC_RTS_RATE_FB_LIMIT_8192F(ptxdesc, 0xF);
1859 }
1860
1861 #endif
Rtw_MPSetMacTxEDCA(PADAPTER padapter)1862 static void Rtw_MPSetMacTxEDCA(PADAPTER padapter)
1863 {
1864
1865 rtw_write32(padapter, 0x508 , 0x00a422); /* Disable EDCA BE Txop for MP pkt tx adjust Packet interval */
1866 /* RTW_INFO("%s:write 0x508~~~~~~ 0x%x\n", __func__,rtw_read32(padapter, 0x508)); */
1867 phy_set_mac_reg(padapter, 0x458 , bMaskDWord , 0x0);
1868 /*RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" ,__func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));*/
1869 phy_set_mac_reg(padapter, 0x460 , bMaskLWord , 0x0); /* fast EDCA queue packet interval & time out value*/
1870 /*phy_set_mac_reg(padapter, ODM_EDCA_VO_PARAM ,bMaskLWord , 0x431C);*/
1871 /*phy_set_mac_reg(padapter, ODM_EDCA_BE_PARAM ,bMaskLWord , 0x431C);*/
1872 /*phy_set_mac_reg(padapter, ODM_EDCA_BK_PARAM ,bMaskLWord , 0x431C);*/
1873 RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" , __func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));
1874
1875 }
1876
SetPacketTx(PADAPTER padapter)1877 void SetPacketTx(PADAPTER padapter)
1878 {
1879 u8 *ptr, *pkt_start, *pkt_end;
1880 u32 pkt_size = 0, i = 0, idx = 0, tmp_idx = 0;
1881 struct rtw_ieee80211_hdr *hdr;
1882 u8 payload;
1883 s32 bmcast;
1884 struct pkt_attrib *pattrib;
1885 struct mp_priv *pmp_priv;
1886
1887 pmp_priv = &padapter->mppriv;
1888
1889 if (pmp_priv->tx.stop)
1890 return;
1891 pmp_priv->tx.sended = 0;
1892 pmp_priv->tx.stop = 0;
1893 pmp_priv->tx_pktcount = 0;
1894
1895 /* 3 1. update_attrib() */
1896 pattrib = &pmp_priv->tx.attrib;
1897 _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
1898 _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
1899 _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
1900 bmcast = IS_MCAST(pattrib->ra);
1901 if (bmcast)
1902 pattrib->psta = rtw_get_bcmc_stainfo(padapter);
1903 else
1904 pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));
1905
1906 if (pattrib->psta == NULL) {
1907 RTW_INFO("%s:psta = NULL !!\n", __func__);
1908 return;
1909 }
1910
1911 pattrib->mac_id = pattrib->psta->cmn.mac_id;
1912 pattrib->mbssid = 0;
1913
1914 pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen;
1915
1916 /* 3 2. allocate xmit buffer */
1917 pkt_size = pattrib->last_txcmdsz;
1918
1919 if (pmp_priv->tx.pallocated_buf)
1920 rtw_mfree(pmp_priv->tx.pallocated_buf, pmp_priv->tx.buf_size);
1921 pmp_priv->tx.write_size = pkt_size;
1922 pmp_priv->tx.buf_size = pkt_size + XMITBUF_ALIGN_SZ;
1923 pmp_priv->tx.pallocated_buf = rtw_zmalloc(pmp_priv->tx.buf_size);
1924 if (pmp_priv->tx.pallocated_buf == NULL) {
1925 RTW_INFO("%s: malloc(%d) fail!!\n", __func__, pmp_priv->tx.buf_size);
1926 return;
1927 }
1928 pmp_priv->tx.buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pmp_priv->tx.pallocated_buf), XMITBUF_ALIGN_SZ);
1929 ptr = pmp_priv->tx.buf;
1930
1931 _rtw_memset(pmp_priv->tx.desc, 0, TXDESC_SIZE);
1932 pkt_start = ptr;
1933 pkt_end = pkt_start + pkt_size;
1934
1935 /* 3 3. init TX descriptor */
1936 #if defined(CONFIG_RTL8188E)
1937 if (IS_HARDWARE_TYPE_8188E(padapter))
1938 fill_tx_desc_8188e(padapter);
1939 #endif
1940
1941 #if defined(CONFIG_RTL8814A)
1942 if (IS_HARDWARE_TYPE_8814A(padapter))
1943 fill_tx_desc_8814a(padapter);
1944 #endif /* defined(CONFIG_RTL8814A) */
1945
1946 #if defined(CONFIG_RTL8822B)
1947 if (IS_HARDWARE_TYPE_8822B(padapter))
1948 rtl8822b_prepare_mp_txdesc(padapter, pmp_priv);
1949 #endif /* CONFIG_RTL8822B */
1950
1951 #if defined(CONFIG_RTL8822C)
1952 if (IS_HARDWARE_TYPE_8822C(padapter))
1953 rtl8822c_prepare_mp_txdesc(padapter, pmp_priv);
1954 #endif /* CONFIG_RTL8822C */
1955
1956 #if defined(CONFIG_RTL8821C)
1957 if (IS_HARDWARE_TYPE_8821C(padapter))
1958 rtl8821c_prepare_mp_txdesc(padapter, pmp_priv);
1959 #endif /* CONFIG_RTL8821C */
1960
1961 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1962 if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter))
1963 fill_tx_desc_8812a(padapter);
1964 #endif
1965
1966 #if defined(CONFIG_RTL8192E)
1967 if (IS_HARDWARE_TYPE_8192E(padapter))
1968 fill_tx_desc_8192e(padapter);
1969 #endif
1970 #if defined(CONFIG_RTL8723B)
1971 if (IS_HARDWARE_TYPE_8723B(padapter))
1972 fill_tx_desc_8723b(padapter);
1973 #endif
1974 #if defined(CONFIG_RTL8703B)
1975 if (IS_HARDWARE_TYPE_8703B(padapter))
1976 fill_tx_desc_8703b(padapter);
1977 #endif
1978
1979 #if defined(CONFIG_RTL8188F)
1980 if (IS_HARDWARE_TYPE_8188F(padapter))
1981 fill_tx_desc_8188f(padapter);
1982 #endif
1983
1984 #if defined(CONFIG_RTL8188GTV)
1985 if (IS_HARDWARE_TYPE_8188GTV(padapter))
1986 fill_tx_desc_8188gtv(padapter);
1987 #endif
1988
1989 #if defined(CONFIG_RTL8723D)
1990 if (IS_HARDWARE_TYPE_8723D(padapter))
1991 fill_tx_desc_8723d(padapter);
1992 #endif
1993 #if defined(CONFIG_RTL8192F)
1994 if (IS_HARDWARE_TYPE_8192F(padapter))
1995 fill_tx_desc_8192f(padapter);
1996 #endif
1997
1998 #if defined(CONFIG_RTL8710B)
1999 if (IS_HARDWARE_TYPE_8710B(padapter))
2000 fill_tx_desc_8710b(padapter);
2001 #endif
2002
2003 #if defined(CONFIG_RTL8814B)
2004 if (IS_HARDWARE_TYPE_8814B(padapter))
2005 rtl8814b_prepare_mp_txdesc(padapter, pmp_priv);
2006 #endif /* CONFIG_RTL8814B */
2007
2008 /* 3 4. make wlan header, make_wlanhdr() */
2009 hdr = (struct rtw_ieee80211_hdr *)pkt_start;
2010 set_frame_sub_type(&hdr->frame_ctl, pattrib->subtype);
2011
2012 _rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); /* DA */
2013 _rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); /* SA */
2014 _rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); /* RA, BSSID */
2015
2016 /* 3 5. make payload */
2017 ptr = pkt_start + pattrib->hdrlen;
2018
2019 if (pmp_priv->mplink_btx == _TRUE) {
2020 _rtw_memcpy(ptr, pmp_priv->mplink_buf, pkt_end - ptr);
2021 } else {
2022 switch (pmp_priv->tx.payload) {
2023 case MP_TX_Payload_00:
2024 RTW_INFO("MP packet tx 0x00 payload!\n");
2025 payload = 0x00;
2026 _rtw_memset(ptr, 0x00, pkt_end - ptr);
2027 break;
2028 case MP_TX_Payload_5a:
2029 RTW_INFO("MP packet tx 0x5a payload!\n");
2030 payload = 0x5a;
2031 _rtw_memset(ptr, 0x5a, pkt_end - ptr);
2032 break;
2033 case MP_TX_Payload_a5:
2034 RTW_INFO("MP packet tx 0xa5 payload!\n");
2035 payload = 0xa5;
2036 _rtw_memset(ptr, 0xa5, pkt_end - ptr);
2037 break;
2038 case MP_TX_Payload_ff:
2039 RTW_INFO("MP packet tx 0xff payload!\n");
2040 payload = 0xff;
2041 _rtw_memset(ptr, 0xff, pkt_end - ptr);
2042 break;
2043 case MP_TX_Payload_prbs9:
2044 RTW_INFO("MP packet tx PRBS9 payload!\n");
2045 while (idx <= pkt_end - ptr) {
2046 int start = 0x02;
2047 int a = start;
2048
2049 for (i = 0;; i++) {
2050 int newbit = (((a >> 8) ^ (a >> 4)) & 1);
2051 a = ((a << 1) | newbit) & 0x1ff;
2052 RTW_DBG("%x ", a);
2053 ptr[idx + i] = a;
2054
2055 if (a == start) {
2056 RTW_INFO("payload repetition period is %d , end %d\n", i , idx);
2057 tmp_idx += i;
2058 break;
2059 }
2060 if (idx + i >= (pkt_end - ptr)) {
2061 tmp_idx += (idx + i);
2062 RTW_INFO(" repetition period payload end curr ptr %d\n", idx + i);
2063 break;
2064 }
2065 }
2066 idx = tmp_idx;
2067 }
2068 break;
2069 case MP_TX_Payload_default_random:
2070 RTW_INFO("MP packet tx default random payload!\n");
2071 for (i = 0; i < pkt_end - ptr; i++)
2072 ptr[i] = rtw_random32() % 0xFF;
2073 break;
2074 default:
2075 RTW_INFO("Config payload type default use 0x%x\n!", pmp_priv->tx.payload);
2076 _rtw_memset(ptr, pmp_priv->tx.payload, pkt_end - ptr);
2077 break;
2078 }
2079 }
2080 /* 3 6. start thread */
2081 #ifdef PLATFORM_LINUX
2082 pmp_priv->tx.PktTxThread = kthread_run(mp_xmit_packet_thread, pmp_priv, "RTW_MP_THREAD");
2083 if (IS_ERR(pmp_priv->tx.PktTxThread)) {
2084 RTW_ERR("Create PktTx Thread Fail !!!!!\n");
2085 pmp_priv->tx.PktTxThread = NULL;
2086 }
2087 #endif
2088 #ifdef PLATFORM_FREEBSD
2089 {
2090 struct proc *p;
2091 struct thread *td;
2092 pmp_priv->tx.PktTxThread = kproc_kthread_add(mp_xmit_packet_thread, pmp_priv,
2093 &p, &td, RFHIGHPID, 0, "MPXmitThread", "MPXmitThread");
2094
2095 if (pmp_priv->tx.PktTxThread < 0)
2096 RTW_INFO("Create PktTx Thread Fail !!!!!\n");
2097 }
2098 #endif
2099
2100 Rtw_MPSetMacTxEDCA(padapter);
2101 return;
2102 }
2103
SetPacketRx(PADAPTER pAdapter,u8 bStartRx,u8 bAB)2104 void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB)
2105 {
2106 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
2107 struct mp_priv *pmppriv = &pAdapter->mppriv;
2108
2109
2110 if (bStartRx) {
2111 #ifdef CONFIG_RTL8723B
2112 phy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x3); /* Power on adc (in RX_WAIT_CCA state) */
2113 write_bbreg(pAdapter, 0xa01, BIT0, bDisable);/* improve Rx performance by jerry */
2114 #endif
2115 pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AMF | RCR_HTC_LOC_CTRL;
2116 pHalData->ReceiveConfig |= RCR_ACRC32;
2117 pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC;
2118
2119 if (pmppriv->bSetRxBssid == _TRUE) {
2120 RTW_INFO("%s: pmppriv->network_macaddr=" MAC_FMT "\n", __func__,
2121 MAC_ARG(pmppriv->network_macaddr));
2122 pHalData->ReceiveConfig = 0;
2123 pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN |RCR_APM | RCR_AM | RCR_AB |RCR_AMF;
2124 pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF;
2125
2126 #if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
2127 write_bbreg(pAdapter, 0x550, BIT3, bEnable);
2128 #endif
2129 rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFEF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */
2130 pmppriv->brx_filter_beacon = _TRUE;
2131
2132 } else {
2133 pHalData->ReceiveConfig |= RCR_ADF;
2134 /* Accept all data frames */
2135 rtw_write16(pAdapter, REG_RXFLTMAP2, 0xFFFF);
2136 }
2137
2138 if (bAB)
2139 pHalData->ReceiveConfig |= RCR_AB;
2140 } else {
2141 #ifdef CONFIG_RTL8723B
2142 phy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x00); /* Power off adc (in RX_WAIT_CCA state)*/
2143 write_bbreg(pAdapter, 0xa01, BIT0, bEnable);/* improve Rx performance by jerry */
2144 #endif
2145 pHalData->ReceiveConfig = 0;
2146 rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFFF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */
2147 }
2148
2149 rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig);
2150 }
2151
ResetPhyRxPktCount(PADAPTER pAdapter)2152 void ResetPhyRxPktCount(PADAPTER pAdapter)
2153 {
2154 u32 i, phyrx_set = 0;
2155
2156 for (i = 0; i <= 0xF; i++) {
2157 phyrx_set = 0;
2158 phyrx_set |= _RXERR_RPT_SEL(i); /* select */
2159 phyrx_set |= RXERR_RPT_RST; /* set counter to zero */
2160 rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set);
2161 }
2162 }
2163
GetPhyRxPktCounts(PADAPTER pAdapter,u32 selbit)2164 static u32 GetPhyRxPktCounts(PADAPTER pAdapter, u32 selbit)
2165 {
2166 /* selection */
2167 u32 phyrx_set = 0, count = 0;
2168
2169 phyrx_set = _RXERR_RPT_SEL(selbit & 0xF);
2170 rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set);
2171
2172 /* Read packet count */
2173 count = rtw_read32(pAdapter, REG_RXERR_RPT) & RXERR_COUNTER_MASK;
2174
2175 return count;
2176 }
2177
GetPhyRxPktReceived(PADAPTER pAdapter)2178 u32 GetPhyRxPktReceived(PADAPTER pAdapter)
2179 {
2180 u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
2181
2182 OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_OK);
2183 CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_OK);
2184 HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_OK);
2185
2186 return OFDM_cnt + CCK_cnt + HT_cnt;
2187 }
2188
GetPhyRxPktCRC32Error(PADAPTER pAdapter)2189 u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter)
2190 {
2191 u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
2192
2193 OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_FAIL);
2194 CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_FAIL);
2195 HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_FAIL);
2196
2197 return OFDM_cnt + CCK_cnt + HT_cnt;
2198 }
2199
2200 struct psd_init_regs {
2201 /* 3 wire */
2202 int reg_88c;
2203 int reg_c00;
2204 int reg_e00;
2205 int reg_1800;
2206 int reg_1a00;
2207 /* cck */
2208 int reg_800;
2209 int reg_808;
2210 };
2211
rtw_mp_psd_init(PADAPTER padapter,struct psd_init_regs * regs)2212 static int rtw_mp_psd_init(PADAPTER padapter, struct psd_init_regs *regs)
2213 {
2214 HAL_DATA_TYPE *phal_data = GET_HAL_DATA(padapter);
2215
2216 switch (phal_data->rf_type) {
2217 /* 1R */
2218 case RF_1T1R:
2219 if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
2220 /* 11AC 1R PSD Setting 3wire & cck off */
2221 regs->reg_c00 = rtw_read32(padapter, 0xC00);
2222 phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
2223 regs->reg_808 = rtw_read32(padapter, 0x808);
2224 phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
2225 } else {
2226 /* 11N 3-wire off 1 */
2227 regs->reg_88c = rtw_read32(padapter, 0x88C);
2228 phy_set_bb_reg(padapter, 0x88C, 0x300000, 0x3);
2229 /* 11N CCK off */
2230 regs->reg_800 = rtw_read32(padapter, 0x800);
2231 phy_set_bb_reg(padapter, 0x800, 0x1000000, 0x0);
2232 }
2233 break;
2234
2235 /* 2R */
2236 case RF_1T2R:
2237 case RF_2T2R:
2238 if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
2239 /* 11AC 2R PSD Setting 3wire & cck off */
2240 regs->reg_c00 = rtw_read32(padapter, 0xC00);
2241 regs->reg_e00 = rtw_read32(padapter, 0xE00);
2242 phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
2243 phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);
2244 regs->reg_808 = rtw_read32(padapter, 0x808);
2245 phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
2246 } else {
2247 /* 11N 3-wire off 2 */
2248 regs->reg_88c = rtw_read32(padapter, 0x88C);
2249 phy_set_bb_reg(padapter, 0x88C, 0xF00000, 0xF);
2250 /* 11N CCK off */
2251 regs->reg_800 = rtw_read32(padapter, 0x800);
2252 phy_set_bb_reg(padapter, 0x800, 0x1000000, 0x0);
2253 }
2254 break;
2255
2256 /* 3R */
2257 case RF_2T3R:
2258 case RF_3T3R:
2259 if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
2260 /* 11AC 3R PSD Setting 3wire & cck off */
2261 regs->reg_c00 = rtw_read32(padapter, 0xC00);
2262 regs->reg_e00 = rtw_read32(padapter, 0xE00);
2263 regs->reg_1800 = rtw_read32(padapter, 0x1800);
2264 phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
2265 phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);
2266 phy_set_bb_reg(padapter, 0x1800, 0x3, 0x00);
2267 regs->reg_808 = rtw_read32(padapter, 0x808);
2268 phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
2269 } else {
2270 RTW_ERR("%s: 11n don't support 3R\n", __func__);
2271 return -1;
2272 }
2273 break;
2274
2275 /* 4R */
2276 case RF_2T4R:
2277 case RF_3T4R:
2278 case RF_4T4R:
2279 if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
2280 /* 11AC 4R PSD Setting 3wire & cck off */
2281 regs->reg_c00 = rtw_read32(padapter, 0xC00);
2282 regs->reg_e00 = rtw_read32(padapter, 0xE00);
2283 regs->reg_1800 = rtw_read32(padapter, 0x1800);
2284 regs->reg_1a00 = rtw_read32(padapter, 0x1A00);
2285 phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
2286 phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);
2287 phy_set_bb_reg(padapter, 0x1800, 0x3, 0x00);
2288 phy_set_bb_reg(padapter, 0x1A00, 0x3, 0x00);
2289 regs->reg_808 = rtw_read32(padapter, 0x808);
2290 phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
2291 } else {
2292 RTW_ERR("%s: 11n don't support 4R\n", __func__);
2293 return -1;
2294 }
2295 break;
2296
2297 default:
2298 RTW_ERR("%s: unknown %d rf type\n", __func__, phal_data->rf_type);
2299 return -1;
2300 }
2301
2302 /* Set PSD points, 0=128, 1=256, 2=512, 3=1024 */
2303 if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC))
2304 phy_set_bb_reg(padapter, 0x910, 0xC000, 3);
2305 else
2306 phy_set_bb_reg(padapter, 0x808, 0xC000, 3);
2307
2308 RTW_INFO("%s: set %d rf type done\n", __func__, phal_data->rf_type);
2309 return 0;
2310 }
2311
rtw_mp_psd_close(PADAPTER padapter,struct psd_init_regs * regs)2312 static int rtw_mp_psd_close(PADAPTER padapter, struct psd_init_regs *regs)
2313 {
2314 HAL_DATA_TYPE *phal_data = GET_HAL_DATA(padapter);
2315
2316
2317 if (!hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
2318 /* 11n 3wire restore */
2319 rtw_write32(padapter, 0x88C, regs->reg_88c);
2320 /* 11n cck restore */
2321 rtw_write32(padapter, 0x800, regs->reg_800);
2322 RTW_INFO("%s: restore %d rf type\n", __func__, phal_data->rf_type);
2323 return 0;
2324 }
2325
2326 /* 11ac 3wire restore */
2327 switch (phal_data->rf_type) {
2328 case RF_1T1R:
2329 rtw_write32(padapter, 0xC00, regs->reg_c00);
2330 break;
2331 case RF_1T2R:
2332 case RF_2T2R:
2333 rtw_write32(padapter, 0xC00, regs->reg_c00);
2334 rtw_write32(padapter, 0xE00, regs->reg_e00);
2335 break;
2336 case RF_2T3R:
2337 case RF_3T3R:
2338 rtw_write32(padapter, 0xC00, regs->reg_c00);
2339 rtw_write32(padapter, 0xE00, regs->reg_e00);
2340 rtw_write32(padapter, 0x1800, regs->reg_1800);
2341 break;
2342 case RF_2T4R:
2343 case RF_3T4R:
2344 case RF_4T4R:
2345 rtw_write32(padapter, 0xC00, regs->reg_c00);
2346 rtw_write32(padapter, 0xE00, regs->reg_e00);
2347 rtw_write32(padapter, 0x1800, regs->reg_1800);
2348 rtw_write32(padapter, 0x1A00, regs->reg_1a00);
2349 break;
2350 default:
2351 RTW_WARN("%s: unknown %d rf type\n", __func__, phal_data->rf_type);
2352 break;
2353 }
2354
2355 /* 11ac cck restore */
2356 rtw_write32(padapter, 0x808, regs->reg_808);
2357 RTW_INFO("%s: restore %d rf type done\n", __func__, phal_data->rf_type);
2358 return 0;
2359 }
2360
2361 /* reg 0x808[9:0]: FFT data x
2362 * reg 0x808[22]: 0 --> 1 to get 1 FFT data y
2363 * reg 0x8B4[15:0]: FFT data y report */
rtw_GetPSDData(PADAPTER pAdapter,u32 point)2364 static u32 rtw_GetPSDData(PADAPTER pAdapter, u32 point)
2365 {
2366 u32 psd_val = 0;
2367
2368 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
2369 u16 psd_reg = 0x910;
2370 u16 psd_regL = 0xF44;
2371 #else
2372 u16 psd_reg = 0x808;
2373 u16 psd_regL = 0x8B4;
2374 #endif
2375
2376 psd_val = rtw_read32(pAdapter, psd_reg);
2377
2378 psd_val &= 0xFFBFFC00;
2379 psd_val |= point;
2380
2381 rtw_write32(pAdapter, psd_reg, psd_val);
2382 rtw_mdelay_os(1);
2383 psd_val |= 0x00400000;
2384
2385 rtw_write32(pAdapter, psd_reg, psd_val);
2386 rtw_mdelay_os(1);
2387
2388 psd_val = rtw_read32(pAdapter, psd_regL);
2389 #if defined(CONFIG_RTL8821C)
2390 psd_val = (psd_val & 0x00FFFFFF) / 32;
2391 #else
2392 psd_val &= 0x0000FFFF;
2393 #endif
2394
2395 return psd_val;
2396 }
2397
2398 /*
2399 * pts start_point_min stop_point_max
2400 * 128 64 64 + 128 = 192
2401 * 256 128 128 + 256 = 384
2402 * 512 256 256 + 512 = 768
2403 * 1024 512 512 + 1024 = 1536
2404 *
2405 */
mp_query_psd(PADAPTER pAdapter,u8 * data)2406 u32 mp_query_psd(PADAPTER pAdapter, u8 *data)
2407 {
2408 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2409 struct dm_struct *p_dm = adapter_to_phydm(pAdapter);
2410
2411 u32 i, psd_pts = 0, psd_start = 0, psd_stop = 0;
2412 u32 psd_data = 0;
2413 struct psd_init_regs regs = {};
2414 int psd_analysis = 0;
2415 char *pdata = NULL;
2416
2417
2418 #ifdef PLATFORM_LINUX
2419 if (!netif_running(pAdapter->pnetdev)) {
2420 return 0;
2421 }
2422 #endif
2423
2424 if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
2425 return 0;
2426 }
2427
2428 if (strlen(data) == 0) { /* default value */
2429 psd_pts = 128;
2430 psd_start = 64;
2431 psd_stop = 128;
2432 } else if (strncmp(data, "analysis,", 9) == 0) {
2433 if (rtw_mp_psd_init(pAdapter, ®s) != 0)
2434 return 0;
2435 psd_analysis = 1;
2436 sscanf(data + 9, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop);
2437 } else
2438 sscanf(data, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop);
2439
2440 data[0] = '\0';
2441 pdata = data;
2442
2443 if (psd_stop > 1536 || psd_stop < 1) {
2444 rtw_warn_on(1);
2445 psd_stop = 1536;
2446 }
2447
2448 if (IS_HARDWARE_TYPE_8822C(pAdapter)) {
2449 u32 *psdbuf = rtw_zmalloc(sizeof(u32)*256);
2450
2451 if (psdbuf == NULL) {
2452 RTW_INFO("%s: psd buf malloc fail!!\n", __func__);
2453 return 0;
2454 }
2455
2456 halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_POINT, psd_pts);
2457 halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_START_POINT, psd_start);
2458 halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_STOP_POINT, psd_stop);
2459 halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_AVERAGE, 0x20000);
2460
2461 halrf_psd_init(p_dm);
2462 #ifdef CONFIG_LONG_DELAY_ISSUE
2463 rtw_msleep_os(100);
2464 #else
2465 rtw_mdelay_os(10);
2466 #endif
2467 halrf_psd_query(p_dm, psdbuf, 256);
2468
2469 i = 0;
2470 while (i < 256) {
2471 pdata += sprintf(pdata, "%x ", (psdbuf[i]));
2472 i++;
2473 }
2474
2475 if (psdbuf)
2476 rtw_mfree(psdbuf, sizeof(u32)*256);
2477
2478 } else {
2479 i = psd_start;
2480
2481 while (i < psd_stop) {
2482 if (i >= psd_pts)
2483 psd_data = rtw_GetPSDData(pAdapter, i - psd_pts);
2484 else
2485 psd_data = rtw_GetPSDData(pAdapter, i);
2486
2487 pdata += sprintf(pdata, "%x ", psd_data);
2488 i++;
2489 }
2490
2491 }
2492
2493 #ifdef CONFIG_LONG_DELAY_ISSUE
2494 rtw_msleep_os(100);
2495 #else
2496 rtw_mdelay_os(100);
2497 #endif
2498
2499 if (psd_analysis)
2500 rtw_mp_psd_close(pAdapter, ®s);
2501
2502 return strlen(data) + 1;
2503 }
2504
2505
2506 #if 0
2507 void _rtw_mp_xmit_priv(struct xmit_priv *pxmitpriv)
2508 {
2509 int i, res;
2510 _adapter *padapter = pxmitpriv->adapter;
2511 struct xmit_frame *pxmitframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf;
2512 struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf;
2513
2514 u32 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
2515 u32 num_xmit_extbuf = NR_XMIT_EXTBUFF;
2516 if (padapter->registrypriv.mp_mode == 0) {
2517 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
2518 num_xmit_extbuf = NR_XMIT_EXTBUFF;
2519 } else {
2520 max_xmit_extbuf_size = 6000;
2521 num_xmit_extbuf = 8;
2522 }
2523
2524 pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
2525 for (i = 0; i < num_xmit_extbuf; i++) {
2526 rtw_os_xmit_resource_free(padapter, pxmitbuf, (max_xmit_extbuf_size + XMITBUF_ALIGN_SZ), _FALSE);
2527
2528 pxmitbuf++;
2529 }
2530
2531 if (pxmitpriv->pallocated_xmit_extbuf)
2532 rtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, num_xmit_extbuf * sizeof(struct xmit_buf) + 4);
2533
2534 if (padapter->registrypriv.mp_mode == 0) {
2535 max_xmit_extbuf_size = 6000;
2536 num_xmit_extbuf = 8;
2537 } else {
2538 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
2539 num_xmit_extbuf = NR_XMIT_EXTBUFF;
2540 }
2541
2542 /* Init xmit extension buff */
2543 _rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue);
2544
2545 pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(num_xmit_extbuf * sizeof(struct xmit_buf) + 4);
2546
2547 if (pxmitpriv->pallocated_xmit_extbuf == NULL) {
2548 res = _FAIL;
2549 goto exit;
2550 }
2551
2552 pxmitpriv->pxmit_extbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmit_extbuf), 4);
2553
2554 pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
2555
2556 for (i = 0; i < num_xmit_extbuf; i++) {
2557 _rtw_init_listhead(&pxmitbuf->list);
2558
2559 pxmitbuf->priv_data = NULL;
2560 pxmitbuf->padapter = padapter;
2561 pxmitbuf->buf_tag = XMITBUF_MGNT;
2562
2563 res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, max_xmit_extbuf_size + XMITBUF_ALIGN_SZ, _TRUE);
2564 if (res == _FAIL) {
2565 res = _FAIL;
2566 goto exit;
2567 }
2568
2569 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
2570 pxmitbuf->phead = pxmitbuf->pbuf;
2571 pxmitbuf->pend = pxmitbuf->pbuf + max_xmit_extbuf_size;
2572 pxmitbuf->len = 0;
2573 pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
2574 #endif
2575
2576 rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue));
2577 #ifdef DBG_XMIT_BUF_EXT
2578 pxmitbuf->no = i;
2579 #endif
2580 pxmitbuf++;
2581
2582 }
2583
2584 pxmitpriv->free_xmit_extbuf_cnt = num_xmit_extbuf;
2585
2586 exit:
2587 ;
2588 }
2589 #endif
2590
2591 u8
mpt_to_mgnt_rate(u32 MptRateIdx)2592 mpt_to_mgnt_rate(
2593 u32 MptRateIdx
2594 )
2595 {
2596 /* Mapped to MGN_XXX defined in MgntGen.h */
2597 switch (MptRateIdx) {
2598 /* CCK rate. */
2599 case MPT_RATE_1M:
2600 return MGN_1M;
2601 case MPT_RATE_2M:
2602 return MGN_2M;
2603 case MPT_RATE_55M:
2604 return MGN_5_5M;
2605 case MPT_RATE_11M:
2606 return MGN_11M;
2607
2608 /* OFDM rate. */
2609 case MPT_RATE_6M:
2610 return MGN_6M;
2611 case MPT_RATE_9M:
2612 return MGN_9M;
2613 case MPT_RATE_12M:
2614 return MGN_12M;
2615 case MPT_RATE_18M:
2616 return MGN_18M;
2617 case MPT_RATE_24M:
2618 return MGN_24M;
2619 case MPT_RATE_36M:
2620 return MGN_36M;
2621 case MPT_RATE_48M:
2622 return MGN_48M;
2623 case MPT_RATE_54M:
2624 return MGN_54M;
2625
2626 /* HT rate. */
2627 case MPT_RATE_MCS0:
2628 return MGN_MCS0;
2629 case MPT_RATE_MCS1:
2630 return MGN_MCS1;
2631 case MPT_RATE_MCS2:
2632 return MGN_MCS2;
2633 case MPT_RATE_MCS3:
2634 return MGN_MCS3;
2635 case MPT_RATE_MCS4:
2636 return MGN_MCS4;
2637 case MPT_RATE_MCS5:
2638 return MGN_MCS5;
2639 case MPT_RATE_MCS6:
2640 return MGN_MCS6;
2641 case MPT_RATE_MCS7:
2642 return MGN_MCS7;
2643 case MPT_RATE_MCS8:
2644 return MGN_MCS8;
2645 case MPT_RATE_MCS9:
2646 return MGN_MCS9;
2647 case MPT_RATE_MCS10:
2648 return MGN_MCS10;
2649 case MPT_RATE_MCS11:
2650 return MGN_MCS11;
2651 case MPT_RATE_MCS12:
2652 return MGN_MCS12;
2653 case MPT_RATE_MCS13:
2654 return MGN_MCS13;
2655 case MPT_RATE_MCS14:
2656 return MGN_MCS14;
2657 case MPT_RATE_MCS15:
2658 return MGN_MCS15;
2659 case MPT_RATE_MCS16:
2660 return MGN_MCS16;
2661 case MPT_RATE_MCS17:
2662 return MGN_MCS17;
2663 case MPT_RATE_MCS18:
2664 return MGN_MCS18;
2665 case MPT_RATE_MCS19:
2666 return MGN_MCS19;
2667 case MPT_RATE_MCS20:
2668 return MGN_MCS20;
2669 case MPT_RATE_MCS21:
2670 return MGN_MCS21;
2671 case MPT_RATE_MCS22:
2672 return MGN_MCS22;
2673 case MPT_RATE_MCS23:
2674 return MGN_MCS23;
2675 case MPT_RATE_MCS24:
2676 return MGN_MCS24;
2677 case MPT_RATE_MCS25:
2678 return MGN_MCS25;
2679 case MPT_RATE_MCS26:
2680 return MGN_MCS26;
2681 case MPT_RATE_MCS27:
2682 return MGN_MCS27;
2683 case MPT_RATE_MCS28:
2684 return MGN_MCS28;
2685 case MPT_RATE_MCS29:
2686 return MGN_MCS29;
2687 case MPT_RATE_MCS30:
2688 return MGN_MCS30;
2689 case MPT_RATE_MCS31:
2690 return MGN_MCS31;
2691
2692 /* VHT rate. */
2693 case MPT_RATE_VHT1SS_MCS0:
2694 return MGN_VHT1SS_MCS0;
2695 case MPT_RATE_VHT1SS_MCS1:
2696 return MGN_VHT1SS_MCS1;
2697 case MPT_RATE_VHT1SS_MCS2:
2698 return MGN_VHT1SS_MCS2;
2699 case MPT_RATE_VHT1SS_MCS3:
2700 return MGN_VHT1SS_MCS3;
2701 case MPT_RATE_VHT1SS_MCS4:
2702 return MGN_VHT1SS_MCS4;
2703 case MPT_RATE_VHT1SS_MCS5:
2704 return MGN_VHT1SS_MCS5;
2705 case MPT_RATE_VHT1SS_MCS6:
2706 return MGN_VHT1SS_MCS6;
2707 case MPT_RATE_VHT1SS_MCS7:
2708 return MGN_VHT1SS_MCS7;
2709 case MPT_RATE_VHT1SS_MCS8:
2710 return MGN_VHT1SS_MCS8;
2711 case MPT_RATE_VHT1SS_MCS9:
2712 return MGN_VHT1SS_MCS9;
2713 case MPT_RATE_VHT2SS_MCS0:
2714 return MGN_VHT2SS_MCS0;
2715 case MPT_RATE_VHT2SS_MCS1:
2716 return MGN_VHT2SS_MCS1;
2717 case MPT_RATE_VHT2SS_MCS2:
2718 return MGN_VHT2SS_MCS2;
2719 case MPT_RATE_VHT2SS_MCS3:
2720 return MGN_VHT2SS_MCS3;
2721 case MPT_RATE_VHT2SS_MCS4:
2722 return MGN_VHT2SS_MCS4;
2723 case MPT_RATE_VHT2SS_MCS5:
2724 return MGN_VHT2SS_MCS5;
2725 case MPT_RATE_VHT2SS_MCS6:
2726 return MGN_VHT2SS_MCS6;
2727 case MPT_RATE_VHT2SS_MCS7:
2728 return MGN_VHT2SS_MCS7;
2729 case MPT_RATE_VHT2SS_MCS8:
2730 return MGN_VHT2SS_MCS8;
2731 case MPT_RATE_VHT2SS_MCS9:
2732 return MGN_VHT2SS_MCS9;
2733 case MPT_RATE_VHT3SS_MCS0:
2734 return MGN_VHT3SS_MCS0;
2735 case MPT_RATE_VHT3SS_MCS1:
2736 return MGN_VHT3SS_MCS1;
2737 case MPT_RATE_VHT3SS_MCS2:
2738 return MGN_VHT3SS_MCS2;
2739 case MPT_RATE_VHT3SS_MCS3:
2740 return MGN_VHT3SS_MCS3;
2741 case MPT_RATE_VHT3SS_MCS4:
2742 return MGN_VHT3SS_MCS4;
2743 case MPT_RATE_VHT3SS_MCS5:
2744 return MGN_VHT3SS_MCS5;
2745 case MPT_RATE_VHT3SS_MCS6:
2746 return MGN_VHT3SS_MCS6;
2747 case MPT_RATE_VHT3SS_MCS7:
2748 return MGN_VHT3SS_MCS7;
2749 case MPT_RATE_VHT3SS_MCS8:
2750 return MGN_VHT3SS_MCS8;
2751 case MPT_RATE_VHT3SS_MCS9:
2752 return MGN_VHT3SS_MCS9;
2753 case MPT_RATE_VHT4SS_MCS0:
2754 return MGN_VHT4SS_MCS0;
2755 case MPT_RATE_VHT4SS_MCS1:
2756 return MGN_VHT4SS_MCS1;
2757 case MPT_RATE_VHT4SS_MCS2:
2758 return MGN_VHT4SS_MCS2;
2759 case MPT_RATE_VHT4SS_MCS3:
2760 return MGN_VHT4SS_MCS3;
2761 case MPT_RATE_VHT4SS_MCS4:
2762 return MGN_VHT4SS_MCS4;
2763 case MPT_RATE_VHT4SS_MCS5:
2764 return MGN_VHT4SS_MCS5;
2765 case MPT_RATE_VHT4SS_MCS6:
2766 return MGN_VHT4SS_MCS6;
2767 case MPT_RATE_VHT4SS_MCS7:
2768 return MGN_VHT4SS_MCS7;
2769 case MPT_RATE_VHT4SS_MCS8:
2770 return MGN_VHT4SS_MCS8;
2771 case MPT_RATE_VHT4SS_MCS9:
2772 return MGN_VHT4SS_MCS9;
2773
2774 case MPT_RATE_LAST: /* fully automatiMGN_VHT2SS_MCS1; */
2775 default:
2776 RTW_INFO("<===mpt_to_mgnt_rate(), Invalid Rate: %d!!\n", MptRateIdx);
2777 return 0x0;
2778 }
2779 }
2780
2781
HwRateToMPTRate(u8 rate)2782 u8 HwRateToMPTRate(u8 rate)
2783 {
2784 u8 ret_rate = MGN_1M;
2785
2786 switch (rate) {
2787 case DESC_RATE1M:
2788 ret_rate = MPT_RATE_1M;
2789 break;
2790 case DESC_RATE2M:
2791 ret_rate = MPT_RATE_2M;
2792 break;
2793 case DESC_RATE5_5M:
2794 ret_rate = MPT_RATE_55M;
2795 break;
2796 case DESC_RATE11M:
2797 ret_rate = MPT_RATE_11M;
2798 break;
2799 case DESC_RATE6M:
2800 ret_rate = MPT_RATE_6M;
2801 break;
2802 case DESC_RATE9M:
2803 ret_rate = MPT_RATE_9M;
2804 break;
2805 case DESC_RATE12M:
2806 ret_rate = MPT_RATE_12M;
2807 break;
2808 case DESC_RATE18M:
2809 ret_rate = MPT_RATE_18M;
2810 break;
2811 case DESC_RATE24M:
2812 ret_rate = MPT_RATE_24M;
2813 break;
2814 case DESC_RATE36M:
2815 ret_rate = MPT_RATE_36M;
2816 break;
2817 case DESC_RATE48M:
2818 ret_rate = MPT_RATE_48M;
2819 break;
2820 case DESC_RATE54M:
2821 ret_rate = MPT_RATE_54M;
2822 break;
2823 case DESC_RATEMCS0:
2824 ret_rate = MPT_RATE_MCS0;
2825 break;
2826 case DESC_RATEMCS1:
2827 ret_rate = MPT_RATE_MCS1;
2828 break;
2829 case DESC_RATEMCS2:
2830 ret_rate = MPT_RATE_MCS2;
2831 break;
2832 case DESC_RATEMCS3:
2833 ret_rate = MPT_RATE_MCS3;
2834 break;
2835 case DESC_RATEMCS4:
2836 ret_rate = MPT_RATE_MCS4;
2837 break;
2838 case DESC_RATEMCS5:
2839 ret_rate = MPT_RATE_MCS5;
2840 break;
2841 case DESC_RATEMCS6:
2842 ret_rate = MPT_RATE_MCS6;
2843 break;
2844 case DESC_RATEMCS7:
2845 ret_rate = MPT_RATE_MCS7;
2846 break;
2847 case DESC_RATEMCS8:
2848 ret_rate = MPT_RATE_MCS8;
2849 break;
2850 case DESC_RATEMCS9:
2851 ret_rate = MPT_RATE_MCS9;
2852 break;
2853 case DESC_RATEMCS10:
2854 ret_rate = MPT_RATE_MCS10;
2855 break;
2856 case DESC_RATEMCS11:
2857 ret_rate = MPT_RATE_MCS11;
2858 break;
2859 case DESC_RATEMCS12:
2860 ret_rate = MPT_RATE_MCS12;
2861 break;
2862 case DESC_RATEMCS13:
2863 ret_rate = MPT_RATE_MCS13;
2864 break;
2865 case DESC_RATEMCS14:
2866 ret_rate = MPT_RATE_MCS14;
2867 break;
2868 case DESC_RATEMCS15:
2869 ret_rate = MPT_RATE_MCS15;
2870 break;
2871 case DESC_RATEMCS16:
2872 ret_rate = MPT_RATE_MCS16;
2873 break;
2874 case DESC_RATEMCS17:
2875 ret_rate = MPT_RATE_MCS17;
2876 break;
2877 case DESC_RATEMCS18:
2878 ret_rate = MPT_RATE_MCS18;
2879 break;
2880 case DESC_RATEMCS19:
2881 ret_rate = MPT_RATE_MCS19;
2882 break;
2883 case DESC_RATEMCS20:
2884 ret_rate = MPT_RATE_MCS20;
2885 break;
2886 case DESC_RATEMCS21:
2887 ret_rate = MPT_RATE_MCS21;
2888 break;
2889 case DESC_RATEMCS22:
2890 ret_rate = MPT_RATE_MCS22;
2891 break;
2892 case DESC_RATEMCS23:
2893 ret_rate = MPT_RATE_MCS23;
2894 break;
2895 case DESC_RATEMCS24:
2896 ret_rate = MPT_RATE_MCS24;
2897 break;
2898 case DESC_RATEMCS25:
2899 ret_rate = MPT_RATE_MCS25;
2900 break;
2901 case DESC_RATEMCS26:
2902 ret_rate = MPT_RATE_MCS26;
2903 break;
2904 case DESC_RATEMCS27:
2905 ret_rate = MPT_RATE_MCS27;
2906 break;
2907 case DESC_RATEMCS28:
2908 ret_rate = MPT_RATE_MCS28;
2909 break;
2910 case DESC_RATEMCS29:
2911 ret_rate = MPT_RATE_MCS29;
2912 break;
2913 case DESC_RATEMCS30:
2914 ret_rate = MPT_RATE_MCS30;
2915 break;
2916 case DESC_RATEMCS31:
2917 ret_rate = MPT_RATE_MCS31;
2918 break;
2919 case DESC_RATEVHTSS1MCS0:
2920 ret_rate = MPT_RATE_VHT1SS_MCS0;
2921 break;
2922 case DESC_RATEVHTSS1MCS1:
2923 ret_rate = MPT_RATE_VHT1SS_MCS1;
2924 break;
2925 case DESC_RATEVHTSS1MCS2:
2926 ret_rate = MPT_RATE_VHT1SS_MCS2;
2927 break;
2928 case DESC_RATEVHTSS1MCS3:
2929 ret_rate = MPT_RATE_VHT1SS_MCS3;
2930 break;
2931 case DESC_RATEVHTSS1MCS4:
2932 ret_rate = MPT_RATE_VHT1SS_MCS4;
2933 break;
2934 case DESC_RATEVHTSS1MCS5:
2935 ret_rate = MPT_RATE_VHT1SS_MCS5;
2936 break;
2937 case DESC_RATEVHTSS1MCS6:
2938 ret_rate = MPT_RATE_VHT1SS_MCS6;
2939 break;
2940 case DESC_RATEVHTSS1MCS7:
2941 ret_rate = MPT_RATE_VHT1SS_MCS7;
2942 break;
2943 case DESC_RATEVHTSS1MCS8:
2944 ret_rate = MPT_RATE_VHT1SS_MCS8;
2945 break;
2946 case DESC_RATEVHTSS1MCS9:
2947 ret_rate = MPT_RATE_VHT1SS_MCS9;
2948 break;
2949 case DESC_RATEVHTSS2MCS0:
2950 ret_rate = MPT_RATE_VHT2SS_MCS0;
2951 break;
2952 case DESC_RATEVHTSS2MCS1:
2953 ret_rate = MPT_RATE_VHT2SS_MCS1;
2954 break;
2955 case DESC_RATEVHTSS2MCS2:
2956 ret_rate = MPT_RATE_VHT2SS_MCS2;
2957 break;
2958 case DESC_RATEVHTSS2MCS3:
2959 ret_rate = MPT_RATE_VHT2SS_MCS3;
2960 break;
2961 case DESC_RATEVHTSS2MCS4:
2962 ret_rate = MPT_RATE_VHT2SS_MCS4;
2963 break;
2964 case DESC_RATEVHTSS2MCS5:
2965 ret_rate = MPT_RATE_VHT2SS_MCS5;
2966 break;
2967 case DESC_RATEVHTSS2MCS6:
2968 ret_rate = MPT_RATE_VHT2SS_MCS6;
2969 break;
2970 case DESC_RATEVHTSS2MCS7:
2971 ret_rate = MPT_RATE_VHT2SS_MCS7;
2972 break;
2973 case DESC_RATEVHTSS2MCS8:
2974 ret_rate = MPT_RATE_VHT2SS_MCS8;
2975 break;
2976 case DESC_RATEVHTSS2MCS9:
2977 ret_rate = MPT_RATE_VHT2SS_MCS9;
2978 break;
2979 case DESC_RATEVHTSS3MCS0:
2980 ret_rate = MPT_RATE_VHT3SS_MCS0;
2981 break;
2982 case DESC_RATEVHTSS3MCS1:
2983 ret_rate = MPT_RATE_VHT3SS_MCS1;
2984 break;
2985 case DESC_RATEVHTSS3MCS2:
2986 ret_rate = MPT_RATE_VHT3SS_MCS2;
2987 break;
2988 case DESC_RATEVHTSS3MCS3:
2989 ret_rate = MPT_RATE_VHT3SS_MCS3;
2990 break;
2991 case DESC_RATEVHTSS3MCS4:
2992 ret_rate = MPT_RATE_VHT3SS_MCS4;
2993 break;
2994 case DESC_RATEVHTSS3MCS5:
2995 ret_rate = MPT_RATE_VHT3SS_MCS5;
2996 break;
2997 case DESC_RATEVHTSS3MCS6:
2998 ret_rate = MPT_RATE_VHT3SS_MCS6;
2999 break;
3000 case DESC_RATEVHTSS3MCS7:
3001 ret_rate = MPT_RATE_VHT3SS_MCS7;
3002 break;
3003 case DESC_RATEVHTSS3MCS8:
3004 ret_rate = MPT_RATE_VHT3SS_MCS8;
3005 break;
3006 case DESC_RATEVHTSS3MCS9:
3007 ret_rate = MPT_RATE_VHT3SS_MCS9;
3008 break;
3009 case DESC_RATEVHTSS4MCS0:
3010 ret_rate = MPT_RATE_VHT4SS_MCS0;
3011 break;
3012 case DESC_RATEVHTSS4MCS1:
3013 ret_rate = MPT_RATE_VHT4SS_MCS1;
3014 break;
3015 case DESC_RATEVHTSS4MCS2:
3016 ret_rate = MPT_RATE_VHT4SS_MCS2;
3017 break;
3018 case DESC_RATEVHTSS4MCS3:
3019 ret_rate = MPT_RATE_VHT4SS_MCS3;
3020 break;
3021 case DESC_RATEVHTSS4MCS4:
3022 ret_rate = MPT_RATE_VHT4SS_MCS4;
3023 break;
3024 case DESC_RATEVHTSS4MCS5:
3025 ret_rate = MPT_RATE_VHT4SS_MCS5;
3026 break;
3027 case DESC_RATEVHTSS4MCS6:
3028 ret_rate = MPT_RATE_VHT4SS_MCS6;
3029 break;
3030 case DESC_RATEVHTSS4MCS7:
3031 ret_rate = MPT_RATE_VHT4SS_MCS7;
3032 break;
3033 case DESC_RATEVHTSS4MCS8:
3034 ret_rate = MPT_RATE_VHT4SS_MCS8;
3035 break;
3036 case DESC_RATEVHTSS4MCS9:
3037 ret_rate = MPT_RATE_VHT4SS_MCS9;
3038 break;
3039
3040 default:
3041 RTW_INFO("hw_rate_to_m_rate(): Non supported Rate [%x]!!!\n", rate);
3042 break;
3043 }
3044 return ret_rate;
3045 }
3046
rtw_mpRateParseFunc(PADAPTER pAdapter,u8 * targetStr)3047 u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr)
3048 {
3049 u16 i = 0;
3050 u8 *rateindex_Array[] = { "1M", "2M", "5.5M", "11M", "6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M",
3051 "HTMCS0", "HTMCS1", "HTMCS2", "HTMCS3", "HTMCS4", "HTMCS5", "HTMCS6", "HTMCS7",
3052 "HTMCS8", "HTMCS9", "HTMCS10", "HTMCS11", "HTMCS12", "HTMCS13", "HTMCS14", "HTMCS15",
3053 "HTMCS16", "HTMCS17", "HTMCS18", "HTMCS19", "HTMCS20", "HTMCS21", "HTMCS22", "HTMCS23",
3054 "HTMCS24", "HTMCS25", "HTMCS26", "HTMCS27", "HTMCS28", "HTMCS29", "HTMCS30", "HTMCS31",
3055 "VHT1MCS0", "VHT1MCS1", "VHT1MCS2", "VHT1MCS3", "VHT1MCS4", "VHT1MCS5", "VHT1MCS6", "VHT1MCS7", "VHT1MCS8", "VHT1MCS9",
3056 "VHT2MCS0", "VHT2MCS1", "VHT2MCS2", "VHT2MCS3", "VHT2MCS4", "VHT2MCS5", "VHT2MCS6", "VHT2MCS7", "VHT2MCS8", "VHT2MCS9",
3057 "VHT3MCS0", "VHT3MCS1", "VHT3MCS2", "VHT3MCS3", "VHT3MCS4", "VHT3MCS5", "VHT3MCS6", "VHT3MCS7", "VHT3MCS8", "VHT3MCS9",
3058 "VHT4MCS0", "VHT4MCS1", "VHT4MCS2", "VHT4MCS3", "VHT4MCS4", "VHT4MCS5", "VHT4MCS6", "VHT4MCS7", "VHT4MCS8", "VHT4MCS9"
3059 };
3060
3061 for (i = 0; i <= 83; i++) {
3062 if (strcmp(targetStr, rateindex_Array[i]) == 0) {
3063 RTW_INFO("%s , index = %d\n", __func__ , i);
3064 return i;
3065 }
3066 }
3067
3068 printk("%s ,please input a Data RATE String as:", __func__);
3069 for (i = 0; i <= 83; i++) {
3070 printk("%s ", rateindex_Array[i]);
3071 if (i % 10 == 0)
3072 printk("\n");
3073 }
3074 return _FAIL;
3075 }
3076
rtw_mp_mode_check(PADAPTER pAdapter)3077 u8 rtw_mp_mode_check(PADAPTER pAdapter)
3078 {
3079 PADAPTER primary_adapter = GET_PRIMARY_ADAPTER(pAdapter);
3080
3081 if (primary_adapter->registrypriv.mp_mode == 1 || primary_adapter->mppriv.bprocess_mp_mode == _TRUE)
3082 return _TRUE;
3083 else
3084 return _FALSE;
3085 }
3086
rtw_is_mp_tssitrk_on(_adapter * adapter)3087 bool rtw_is_mp_tssitrk_on(_adapter *adapter)
3088 {
3089 _adapter *primary_adapter = GET_PRIMARY_ADAPTER(adapter);
3090
3091 return primary_adapter->mppriv.tssitrk_on;
3092 }
3093
mpt_ProQueryCalTxPower(PADAPTER pAdapter,u8 RfPath)3094 u32 mpt_ProQueryCalTxPower(
3095 PADAPTER pAdapter,
3096 u8 RfPath
3097 )
3098 {
3099
3100 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
3101 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
3102
3103 u32 TxPower = 1;
3104 struct txpwr_idx_comp tic;
3105 u8 mgn_rate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
3106 RATE_SECTION rs = mgn_rate_to_rs(mgn_rate);
3107
3108 TxPower = rtw_hal_get_tx_power_index(pAdapter, RfPath, rs, mgn_rate
3109 , pHalData->current_channel_bw, pHalData->current_band_type, pHalData->current_channel, 0, &tic);
3110
3111 dump_tx_power_index_inline(RTW_DBGDUMP, pAdapter, RfPath
3112 , pHalData->current_channel_bw, pHalData->current_channel
3113 , mgn_rate, TxPower, &tic);
3114
3115 pAdapter->mppriv.txpoweridx = (u8)TxPower;
3116 if (RfPath == RF_PATH_A)
3117 pMptCtx->TxPwrLevel[RF_PATH_A] = (u8)TxPower;
3118 else if (RfPath == RF_PATH_B)
3119 pMptCtx->TxPwrLevel[RF_PATH_B] = (u8)TxPower;
3120 else if (RfPath == RF_PATH_C)
3121 pMptCtx->TxPwrLevel[RF_PATH_C] = (u8)TxPower;
3122 else if (RfPath == RF_PATH_D)
3123 pMptCtx->TxPwrLevel[RF_PATH_D] = (u8)TxPower;
3124 hal_mpt_SetTxPower(pAdapter);
3125
3126 return TxPower;
3127 }
3128
mpt_get_tx_power_finalabs_val(PADAPTER padapter,u8 rf_path)3129 u32 mpt_get_tx_power_finalabs_val(PADAPTER padapter, u8 rf_path)
3130 {
3131 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3132 PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx);
3133
3134 u8 mgn_rate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
3135 u32 powerdbm = 0;
3136
3137 powerdbm = phy_get_tx_power_final_absolute_value(padapter, rf_path, mgn_rate, pHalData->current_channel_bw, pHalData->current_channel);
3138
3139 RTW_INFO("bw=%d, ch=%d, rateid=%d, TSSI Power(dBm):%d\n",
3140 pHalData->current_channel_bw, pHalData->current_channel, mgn_rate ,powerdbm);
3141
3142 return powerdbm;
3143 }
3144
3145 #ifdef CONFIG_MP_VHT_HW_TX_MODE
dump_buf(u8 * buf,u32 len)3146 static inline void dump_buf(u8 *buf, u32 len)
3147 {
3148 u32 i;
3149
3150 RTW_INFO("-----------------Len %d----------------\n", len);
3151 for (i = 0; i < len; i++)
3152 RTW_INFO("%2.2x-", *(buf + i));
3153 RTW_INFO("\n");
3154 }
3155
ByteToBit(u8 * out,bool * in,u8 in_size)3156 void ByteToBit(
3157 u8 *out,
3158 bool *in,
3159 u8 in_size)
3160 {
3161 u8 i = 0, j = 0;
3162
3163 for (i = 0; i < in_size; i++) {
3164 for (j = 0; j < 8; j++) {
3165 if (in[8 * i + j])
3166 out[i] |= (1 << j);
3167 }
3168 }
3169 }
3170
3171
CRC16_generator(bool * out,bool * in,u8 in_size)3172 void CRC16_generator(
3173 bool *out,
3174 bool *in,
3175 u8 in_size
3176 )
3177 {
3178 u8 i = 0;
3179 bool temp = 0, reg[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
3180
3181 for (i = 0; i < in_size; i++) {/* take one's complement and bit reverse*/
3182 temp = in[i] ^ reg[15];
3183 reg[15] = reg[14];
3184 reg[14] = reg[13];
3185 reg[13] = reg[12];
3186 reg[12] = reg[11];
3187 reg[11] = reg[10];
3188 reg[10] = reg[9];
3189 reg[9] = reg[8];
3190 reg[8] = reg[7];
3191
3192 reg[7] = reg[6];
3193 reg[6] = reg[5];
3194 reg[5] = reg[4];
3195 reg[4] = reg[3];
3196 reg[3] = reg[2];
3197 reg[2] = reg[1];
3198 reg[1] = reg[0];
3199 reg[12] = reg[12] ^ temp;
3200 reg[5] = reg[5] ^ temp;
3201 reg[0] = temp;
3202 }
3203 for (i = 0; i < 16; i++) /* take one's complement and bit reverse*/
3204 out[i] = 1 - reg[15 - i];
3205 }
3206
3207
3208
3209 /*========================================
3210 SFD SIGNAL SERVICE LENGTH CRC
3211 16 bit 8 bit 8 bit 16 bit 16 bit
3212 ========================================*/
CCK_generator(PRT_PMAC_TX_INFO pPMacTxInfo,PRT_PMAC_PKT_INFO pPMacPktInfo)3213 void CCK_generator(
3214 PRT_PMAC_TX_INFO pPMacTxInfo,
3215 PRT_PMAC_PKT_INFO pPMacPktInfo
3216 )
3217 {
3218 double ratio = 0;
3219 bool crc16_in[32] = {0}, crc16_out[16] = {0};
3220 bool LengthExtBit;
3221 double LengthExact;
3222 double LengthPSDU;
3223 u8 i;
3224 u32 PacketLength = pPMacTxInfo->PacketLength;
3225
3226 if (pPMacTxInfo->bSPreamble)
3227 pPMacTxInfo->SFD = 0x05CF;
3228 else
3229 pPMacTxInfo->SFD = 0xF3A0;
3230
3231 switch (pPMacPktInfo->MCS) {
3232 case 0:
3233 pPMacTxInfo->SignalField = 0xA;
3234 ratio = 8;
3235 /*CRC16_in(1,0:7)=[0 1 0 1 0 0 0 0]*/
3236 crc16_in[1] = crc16_in[3] = 1;
3237 break;
3238 case 1:
3239 pPMacTxInfo->SignalField = 0x14;
3240 ratio = 4;
3241 /*CRC16_in(1,0:7)=[0 0 1 0 1 0 0 0];*/
3242 crc16_in[2] = crc16_in[4] = 1;
3243 break;
3244 case 2:
3245 pPMacTxInfo->SignalField = 0x37;
3246 ratio = 8.0 / 5.5;
3247 /*CRC16_in(1,0:7)=[1 1 1 0 1 1 0 0];*/
3248 crc16_in[0] = crc16_in[1] = crc16_in[2] = crc16_in[4] = crc16_in[5] = 1;
3249 break;
3250 case 3:
3251 pPMacTxInfo->SignalField = 0x6E;
3252 ratio = 8.0 / 11.0;
3253 /*CRC16_in(1,0:7)=[0 1 1 1 0 1 1 0];*/
3254 crc16_in[1] = crc16_in[2] = crc16_in[3] = crc16_in[5] = crc16_in[6] = 1;
3255 break;
3256 }
3257
3258 LengthExact = PacketLength * ratio;
3259 LengthPSDU = ceil(LengthExact);
3260
3261 if ((pPMacPktInfo->MCS == 3) &&
3262 ((LengthPSDU - LengthExact) >= 0.727 || (LengthPSDU - LengthExact) <= -0.727))
3263 LengthExtBit = 1;
3264 else
3265 LengthExtBit = 0;
3266
3267
3268 pPMacTxInfo->LENGTH = (u32)LengthPSDU;
3269 /* CRC16_in(1,16:31) = LengthPSDU[0:15]*/
3270 for (i = 0; i < 16; i++)
3271 crc16_in[i + 16] = (pPMacTxInfo->LENGTH >> i) & 0x1;
3272
3273 if (LengthExtBit == 0) {
3274 pPMacTxInfo->ServiceField = 0x0;
3275 /* CRC16_in(1,8:15) = [0 0 0 0 0 0 0 0];*/
3276 } else {
3277 pPMacTxInfo->ServiceField = 0x80;
3278 /*CRC16_in(1,8:15)=[0 0 0 0 0 0 0 1];*/
3279 crc16_in[15] = 1;
3280 }
3281
3282 CRC16_generator(crc16_out, crc16_in, 32);
3283
3284 _rtw_memset(pPMacTxInfo->CRC16, 0, 2);
3285 ByteToBit(pPMacTxInfo->CRC16, crc16_out, 2);
3286
3287 }
3288
3289
PMAC_Get_Pkt_Param(PRT_PMAC_TX_INFO pPMacTxInfo,PRT_PMAC_PKT_INFO pPMacPktInfo)3290 void PMAC_Get_Pkt_Param(
3291 PRT_PMAC_TX_INFO pPMacTxInfo,
3292 PRT_PMAC_PKT_INFO pPMacPktInfo)
3293 {
3294
3295 u8 TX_RATE_HEX = 0, MCS = 0;
3296 u8 TX_RATE = pPMacTxInfo->TX_RATE;
3297
3298 /* TX_RATE & Nss */
3299 if (MPT_IS_2SS_RATE(TX_RATE))
3300 pPMacPktInfo->Nss = 2;
3301 else if (MPT_IS_3SS_RATE(TX_RATE))
3302 pPMacPktInfo->Nss = 3;
3303 else if (MPT_IS_4SS_RATE(TX_RATE))
3304 pPMacPktInfo->Nss = 4;
3305 else
3306 pPMacPktInfo->Nss = 1;
3307
3308 RTW_INFO("PMacTxInfo.Nss =%d\n", pPMacPktInfo->Nss);
3309
3310 /* MCS & TX_RATE_HEX*/
3311 if (MPT_IS_CCK_RATE(TX_RATE)) {
3312 switch (TX_RATE) {
3313 case MPT_RATE_1M:
3314 TX_RATE_HEX = MCS = 0;
3315 break;
3316 case MPT_RATE_2M:
3317 TX_RATE_HEX = MCS = 1;
3318 break;
3319 case MPT_RATE_55M:
3320 TX_RATE_HEX = MCS = 2;
3321 break;
3322 case MPT_RATE_11M:
3323 TX_RATE_HEX = MCS = 3;
3324 break;
3325 }
3326 } else if (MPT_IS_OFDM_RATE(TX_RATE)) {
3327 MCS = TX_RATE - MPT_RATE_6M;
3328 TX_RATE_HEX = MCS + 4;
3329 } else if (MPT_IS_HT_RATE(TX_RATE)) {
3330 MCS = TX_RATE - MPT_RATE_MCS0;
3331 TX_RATE_HEX = MCS + 12;
3332 } else if (MPT_IS_VHT_RATE(TX_RATE)) {
3333 TX_RATE_HEX = TX_RATE - MPT_RATE_VHT1SS_MCS0 + 44;
3334
3335 if (MPT_IS_VHT_2S_RATE(TX_RATE))
3336 MCS = TX_RATE - MPT_RATE_VHT2SS_MCS0;
3337 else if (MPT_IS_VHT_3S_RATE(TX_RATE))
3338 MCS = TX_RATE - MPT_RATE_VHT3SS_MCS0;
3339 else if (MPT_IS_VHT_4S_RATE(TX_RATE))
3340 MCS = TX_RATE - MPT_RATE_VHT4SS_MCS0;
3341 else
3342 MCS = TX_RATE - MPT_RATE_VHT1SS_MCS0;
3343 }
3344
3345 pPMacPktInfo->MCS = MCS;
3346 pPMacTxInfo->TX_RATE_HEX = TX_RATE_HEX;
3347
3348 RTW_INFO(" MCS=%d, TX_RATE_HEX =0x%x\n", MCS, pPMacTxInfo->TX_RATE_HEX);
3349 /* mSTBC & Nsts*/
3350 pPMacPktInfo->Nsts = pPMacPktInfo->Nss;
3351 if (pPMacTxInfo->bSTBC) {
3352 if (pPMacPktInfo->Nss == 1) {
3353 pPMacTxInfo->m_STBC = 2;
3354 pPMacPktInfo->Nsts = pPMacPktInfo->Nss * 2;
3355 } else
3356 pPMacTxInfo->m_STBC = 1;
3357 } else
3358 pPMacTxInfo->m_STBC = 1;
3359 }
3360
3361
LDPC_parameter_generator(u32 N_pld_int,u32 N_CBPSS,u32 N_SS,u32 R,u32 m_STBC,u32 N_TCB_int)3362 u32 LDPC_parameter_generator(
3363 u32 N_pld_int,
3364 u32 N_CBPSS,
3365 u32 N_SS,
3366 u32 R,
3367 u32 m_STBC,
3368 u32 N_TCB_int
3369 )
3370 {
3371 double CR = 0.;
3372 double N_pld = (double)N_pld_int;
3373 double N_TCB = (double)N_TCB_int;
3374 double N_CW = 0., N_shrt = 0., N_spcw = 0., N_fshrt = 0.;
3375 double L_LDPC = 0., K_LDPC = 0., L_LDPC_info = 0.;
3376 double N_punc = 0., N_ppcw = 0., N_fpunc = 0., N_rep = 0., N_rpcw = 0., N_frep = 0.;
3377 double R_eff = 0.;
3378 u32 VHTSIGA2B3 = 0;/* extra symbol from VHT-SIG-A2 Bit 3*/
3379
3380 if (R == 0)
3381 CR = 0.5;
3382 else if (R == 1)
3383 CR = 2. / 3.;
3384 else if (R == 2)
3385 CR = 3. / 4.;
3386 else if (R == 3)
3387 CR = 5. / 6.;
3388
3389 if (N_TCB <= 648.) {
3390 N_CW = 1.;
3391 if (N_TCB >= N_pld + 912.*(1. - CR))
3392 L_LDPC = 1296.;
3393 else
3394 L_LDPC = 648.;
3395 } else if (N_TCB <= 1296.) {
3396 N_CW = 1.;
3397 if (N_TCB >= (double)N_pld + 1464.*(1. - CR))
3398 L_LDPC = 1944.;
3399 else
3400 L_LDPC = 1296.;
3401 } else if (N_TCB <= 1944.) {
3402 N_CW = 1.;
3403 L_LDPC = 1944.;
3404 } else if (N_TCB <= 2592.) {
3405 N_CW = 2.;
3406 if (N_TCB >= N_pld + 2916.*(1. - CR))
3407 L_LDPC = 1944.;
3408 else
3409 L_LDPC = 1296.;
3410 } else {
3411 N_CW = ceil(N_pld / 1944. / CR);
3412 L_LDPC = 1944.;
3413 }
3414 /* Number of information bits per CW*/
3415 K_LDPC = L_LDPC * CR;
3416 /* Number of shortening bits max(0, (N_CW * L_LDPC * R) - N_pld)*/
3417 N_shrt = (N_CW * K_LDPC - N_pld) > 0. ? (N_CW * K_LDPC - N_pld) : 0.;
3418 /* Number of shortening bits per CW N_spcw = rtfloor(N_shrt/N_CW)*/
3419 N_spcw = rtfloor(N_shrt / N_CW);
3420 /* The first N_fshrt CWs shorten 1 bit more*/
3421 N_fshrt = (double)((int)N_shrt % (int)N_CW);
3422 /* Number of data bits for the last N_CW-N_fshrt CWs*/
3423 L_LDPC_info = K_LDPC - N_spcw;
3424 /* Number of puncturing bits*/
3425 N_punc = (N_CW * L_LDPC - N_TCB - N_shrt) > 0. ? (N_CW * L_LDPC - N_TCB - N_shrt) : 0.;
3426 if (((N_punc > .1 * N_CW * L_LDPC * (1. - CR)) && (N_shrt < 1.2 * N_punc * CR / (1. - CR))) ||
3427 (N_punc > 0.3 * N_CW * L_LDPC * (1. - CR))) {
3428 /*cout << "*** N_TCB and N_punc are Recomputed ***" << endl;*/
3429 VHTSIGA2B3 = 1;
3430 N_TCB += (double)N_CBPSS * N_SS * m_STBC;
3431 N_punc = (N_CW * L_LDPC - N_TCB - N_shrt) > 0. ? (N_CW * L_LDPC - N_TCB - N_shrt) : 0.;
3432 } else
3433 VHTSIGA2B3 = 0;
3434
3435 return VHTSIGA2B3;
3436 } /* function end of LDPC_parameter_generator */
3437
3438 /*========================================
3439 Data field of PPDU
3440 Get N_sym and SIGA2BB3
3441 ========================================*/
PMAC_Nsym_generator(PRT_PMAC_TX_INFO pPMacTxInfo,PRT_PMAC_PKT_INFO pPMacPktInfo)3442 void PMAC_Nsym_generator(
3443 PRT_PMAC_TX_INFO pPMacTxInfo,
3444 PRT_PMAC_PKT_INFO pPMacPktInfo)
3445 {
3446 u32 SIGA2B3 = 0;
3447 u8 TX_RATE = pPMacTxInfo->TX_RATE;
3448
3449 u32 R, R_list[10] = {0, 0, 2, 0, 2, 1, 2, 3, 2, 3};
3450 double CR = 0;
3451 u32 N_SD, N_BPSC_list[10] = {1, 2, 2, 4, 4, 6, 6, 6, 8, 8};
3452 u32 N_BPSC = 0, N_CBPS = 0, N_DBPS = 0, N_ES = 0, N_SYM = 0, N_pld = 0, N_TCB = 0;
3453 int D_R = 0;
3454
3455 RTW_INFO("TX_RATE = %d\n", TX_RATE);
3456 /* N_SD*/
3457 if (pPMacTxInfo->BandWidth == 0)
3458 N_SD = 52;
3459 else if (pPMacTxInfo->BandWidth == 1)
3460 N_SD = 108;
3461 else
3462 N_SD = 234;
3463
3464 if (MPT_IS_HT_RATE(TX_RATE)) {
3465 u8 MCS_temp;
3466
3467 if (pPMacPktInfo->MCS > 23)
3468 MCS_temp = pPMacPktInfo->MCS - 24;
3469 else if (pPMacPktInfo->MCS > 15)
3470 MCS_temp = pPMacPktInfo->MCS - 16;
3471 else if (pPMacPktInfo->MCS > 7)
3472 MCS_temp = pPMacPktInfo->MCS - 8;
3473 else
3474 MCS_temp = pPMacPktInfo->MCS;
3475
3476 R = R_list[MCS_temp];
3477
3478 switch (R) {
3479 case 0:
3480 CR = .5;
3481 break;
3482 case 1:
3483 CR = 2. / 3.;
3484 break;
3485 case 2:
3486 CR = 3. / 4.;
3487 break;
3488 case 3:
3489 CR = 5. / 6.;
3490 break;
3491 }
3492
3493 N_BPSC = N_BPSC_list[MCS_temp];
3494 N_CBPS = N_BPSC * N_SD * pPMacPktInfo->Nss;
3495 N_DBPS = (u32)((double)N_CBPS * CR);
3496
3497 if (pPMacTxInfo->bLDPC == FALSE) {
3498 N_ES = (u32)ceil((double)(N_DBPS * pPMacPktInfo->Nss) / 4. / 300.);
3499 RTW_INFO("N_ES = %d\n", N_ES);
3500
3501 /* N_SYM = m_STBC* (8*length+16+6*N_ES) / (m_STBC*N_DBPS)*/
3502 N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16 + N_ES * 6) /
3503 (double)(N_DBPS * pPMacTxInfo->m_STBC));
3504
3505 } else {
3506 N_ES = 1;
3507 /* N_pld = length * 8 + 16*/
3508 N_pld = pPMacTxInfo->PacketLength * 8 + 16;
3509 RTW_INFO("N_pld = %d\n", N_pld);
3510 N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(N_pld) /
3511 (double)(N_DBPS * pPMacTxInfo->m_STBC));
3512 RTW_INFO("N_SYM = %d\n", N_SYM);
3513 /* N_avbits = N_CBPS *m_STBC *(N_pld/N_CBPS*R*m_STBC)*/
3514 N_TCB = N_CBPS * N_SYM;
3515 RTW_INFO("N_TCB = %d\n", N_TCB);
3516 SIGA2B3 = LDPC_parameter_generator(N_pld, N_CBPS, pPMacPktInfo->Nss, R, pPMacTxInfo->m_STBC, N_TCB);
3517 RTW_INFO("SIGA2B3 = %d\n", SIGA2B3);
3518 N_SYM = N_SYM + SIGA2B3 * pPMacTxInfo->m_STBC;
3519 RTW_INFO("N_SYM = %d\n", N_SYM);
3520 }
3521 } else if (MPT_IS_VHT_RATE(TX_RATE)) {
3522 R = R_list[pPMacPktInfo->MCS];
3523
3524 switch (R) {
3525 case 0:
3526 CR = .5;
3527 break;
3528 case 1:
3529 CR = 2. / 3.;
3530 break;
3531 case 2:
3532 CR = 3. / 4.;
3533 break;
3534 case 3:
3535 CR = 5. / 6.;
3536 break;
3537 }
3538 N_BPSC = N_BPSC_list[pPMacPktInfo->MCS];
3539 N_CBPS = N_BPSC * N_SD * pPMacPktInfo->Nss;
3540 N_DBPS = (u32)((double)N_CBPS * CR);
3541 if (pPMacTxInfo->bLDPC == FALSE) {
3542 if (pPMacTxInfo->bSGI)
3543 N_ES = (u32)ceil((double)(N_DBPS) / 3.6 / 600.);
3544 else
3545 N_ES = (u32)ceil((double)(N_DBPS) / 4. / 600.);
3546 /* N_SYM = m_STBC* (8*length+16+6*N_ES) / (m_STBC*N_DBPS)*/
3547 N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16 + N_ES * 6) / (double)(N_DBPS * pPMacTxInfo->m_STBC));
3548 SIGA2B3 = 0;
3549 } else {
3550 N_ES = 1;
3551 /* N_SYM = m_STBC* (8*length+N_service) / (m_STBC*N_DBPS)*/
3552 N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16) / (double)(N_DBPS * pPMacTxInfo->m_STBC));
3553 /* N_avbits = N_sys_init * N_CBPS*/
3554 N_TCB = N_CBPS * N_SYM;
3555 /* N_pld = N_sys_init * N_DBPS*/
3556 N_pld = N_SYM * N_DBPS;
3557 SIGA2B3 = LDPC_parameter_generator(N_pld, N_CBPS, pPMacPktInfo->Nss, R, pPMacTxInfo->m_STBC, N_TCB);
3558 N_SYM = N_SYM + SIGA2B3 * pPMacTxInfo->m_STBC;
3559 }
3560
3561 switch (R) {
3562 case 0:
3563 D_R = 2;
3564 break;
3565 case 1:
3566 D_R = 3;
3567 break;
3568 case 2:
3569 D_R = 4;
3570 break;
3571 case 3:
3572 D_R = 6;
3573 break;
3574 }
3575
3576 if (((N_CBPS / N_ES) % D_R) != 0) {
3577 RTW_INFO("MCS= %d is not supported when Nss=%d and BW= %d !!\n", pPMacPktInfo->MCS, pPMacPktInfo->Nss, pPMacTxInfo->BandWidth);
3578 return;
3579 }
3580
3581 RTW_INFO("MCS= %d Nss=%d and BW= %d !!\n", pPMacPktInfo->MCS, pPMacPktInfo->Nss, pPMacTxInfo->BandWidth);
3582 }
3583
3584 pPMacPktInfo->N_sym = N_SYM;
3585 pPMacPktInfo->SIGA2B3 = SIGA2B3;
3586 }
3587
3588 /*========================================
3589 L-SIG Rate R Length P Tail
3590 4b 1b 12b 1b 6b
3591 ========================================*/
3592
L_SIG_generator(u32 N_SYM,PRT_PMAC_TX_INFO pPMacTxInfo,PRT_PMAC_PKT_INFO pPMacPktInfo)3593 void L_SIG_generator(
3594 u32 N_SYM, /* Max: 750*/
3595 PRT_PMAC_TX_INFO pPMacTxInfo,
3596 PRT_PMAC_PKT_INFO pPMacPktInfo)
3597 {
3598 u8 sig_bi[24] = {0}; /* 24 BIT*/
3599 u32 mode, LENGTH;
3600 int i;
3601
3602 if (MPT_IS_OFDM_RATE(pPMacTxInfo->TX_RATE)) {
3603 mode = pPMacPktInfo->MCS;
3604 LENGTH = pPMacTxInfo->PacketLength;
3605 } else {
3606 u8 N_LTF;
3607 double T_data;
3608 u32 OFDM_symbol;
3609
3610 mode = 0;
3611
3612 /* Table 20-13 Num of HT-DLTFs request*/
3613 if (pPMacPktInfo->Nsts <= 2)
3614 N_LTF = pPMacPktInfo->Nsts;
3615 else
3616 N_LTF = 4;
3617
3618 if (pPMacTxInfo->bSGI)
3619 T_data = 3.6;
3620 else
3621 T_data = 4.0;
3622
3623 /*(L-SIG, HT-SIG, HT-STF, HT-LTF....HT-LTF, Data)*/
3624 if (MPT_IS_VHT_RATE(pPMacTxInfo->TX_RATE))
3625 OFDM_symbol = (u32)ceil((double)(8 + 4 + N_LTF * 4 + N_SYM * T_data + 4) / 4.);
3626 else
3627 OFDM_symbol = (u32)ceil((double)(8 + 4 + N_LTF * 4 + N_SYM * T_data) / 4.);
3628
3629 RTW_INFO("%s , OFDM_symbol =%d\n", __func__, OFDM_symbol);
3630 LENGTH = OFDM_symbol * 3 - 3;
3631 RTW_INFO("%s , LENGTH =%d\n", __func__, LENGTH);
3632
3633 }
3634 /* Rate Field*/
3635 switch (mode) {
3636 case 0:
3637 sig_bi[0] = 1;
3638 sig_bi[1] = 1;
3639 sig_bi[2] = 0;
3640 sig_bi[3] = 1;
3641 break;
3642 case 1:
3643 sig_bi[0] = 1;
3644 sig_bi[1] = 1;
3645 sig_bi[2] = 1;
3646 sig_bi[3] = 1;
3647 break;
3648 case 2:
3649 sig_bi[0] = 0;
3650 sig_bi[1] = 1;
3651 sig_bi[2] = 0;
3652 sig_bi[3] = 1;
3653 break;
3654 case 3:
3655 sig_bi[0] = 0;
3656 sig_bi[1] = 1;
3657 sig_bi[2] = 1;
3658 sig_bi[3] = 1;
3659 break;
3660 case 4:
3661 sig_bi[0] = 1;
3662 sig_bi[1] = 0;
3663 sig_bi[2] = 0;
3664 sig_bi[3] = 1;
3665 break;
3666 case 5:
3667 sig_bi[0] = 1;
3668 sig_bi[1] = 0;
3669 sig_bi[2] = 1;
3670 sig_bi[3] = 1;
3671 break;
3672 case 6:
3673 sig_bi[0] = 0;
3674 sig_bi[1] = 0;
3675 sig_bi[2] = 0;
3676 sig_bi[3] = 1;
3677 break;
3678 case 7:
3679 sig_bi[0] = 0;
3680 sig_bi[1] = 0;
3681 sig_bi[2] = 1;
3682 sig_bi[3] = 1;
3683 break;
3684 }
3685 /*Reserved bit*/
3686 sig_bi[4] = 0;
3687
3688 /* Length Field*/
3689 for (i = 0; i < 12; i++)
3690 sig_bi[i + 5] = (LENGTH >> i) & 1;
3691
3692 /* Parity Bit*/
3693 sig_bi[17] = 0;
3694 for (i = 0; i < 17; i++)
3695 sig_bi[17] = sig_bi[17] + sig_bi[i];
3696
3697 sig_bi[17] %= 2;
3698
3699 /* Tail Field*/
3700 for (i = 18; i < 24; i++)
3701 sig_bi[i] = 0;
3702
3703 /* dump_buf(sig_bi,24);*/
3704 _rtw_memset(pPMacTxInfo->LSIG, 0, 3);
3705 ByteToBit(pPMacTxInfo->LSIG, (bool *)sig_bi, 3);
3706 }
3707
3708
CRC8_generator(bool * out,bool * in,u8 in_size)3709 void CRC8_generator(
3710 bool *out,
3711 bool *in,
3712 u8 in_size
3713 )
3714 {
3715 u8 i = 0;
3716 bool temp = 0, reg[] = {1, 1, 1, 1, 1, 1, 1, 1};
3717
3718 for (i = 0; i < in_size; i++) { /* take one's complement and bit reverse*/
3719 temp = in[i] ^ reg[7];
3720 reg[7] = reg[6];
3721 reg[6] = reg[5];
3722 reg[5] = reg[4];
3723 reg[4] = reg[3];
3724 reg[3] = reg[2];
3725 reg[2] = reg[1] ^ temp;
3726 reg[1] = reg[0] ^ temp;
3727 reg[0] = temp;
3728 }
3729 for (i = 0; i < 8; i++)/* take one's complement and bit reverse*/
3730 out[i] = reg[7 - i] ^ 1;
3731 }
3732
3733 /*/================================================================================
3734 HT-SIG1 MCS CW Length 24BIT + 24BIT
3735 7b 1b 16b
3736 HT-SIG2 Smoothing Not sounding Rsvd AGG STBC FEC SGI N_ELTF CRC Tail
3737 1b 1b 1b 1b 2b 1b 1b 2b 8b 6b
3738 ================================================================================*/
HT_SIG_generator(PRT_PMAC_TX_INFO pPMacTxInfo,PRT_PMAC_PKT_INFO pPMacPktInfo)3739 void HT_SIG_generator(
3740 PRT_PMAC_TX_INFO pPMacTxInfo,
3741 PRT_PMAC_PKT_INFO pPMacPktInfo
3742 )
3743 {
3744 u32 i;
3745 bool sig_bi[48] = {0}, crc8[8] = {0};
3746 /* MCS Field*/
3747 for (i = 0; i < 7; i++)
3748 sig_bi[i] = (pPMacPktInfo->MCS >> i) & 0x1;
3749 /* Packet BW Setting*/
3750 sig_bi[7] = pPMacTxInfo->BandWidth;
3751 /* HT-Length Field*/
3752 for (i = 0; i < 16; i++)
3753 sig_bi[i + 8] = (pPMacTxInfo->PacketLength >> i) & 0x1;
3754 /* Smoothing; 1->allow smoothing*/
3755 sig_bi[24] = 1;
3756 /*Not Sounding*/
3757 sig_bi[25] = 1 - pPMacTxInfo->NDP_sound;
3758 /*Reserved bit*/
3759 sig_bi[26] = 1;
3760 /*/Aggregate*/
3761 sig_bi[27] = 0;
3762 /*STBC Field*/
3763 if (pPMacTxInfo->bSTBC) {
3764 sig_bi[28] = 1;
3765 sig_bi[29] = 0;
3766 } else {
3767 sig_bi[28] = 0;
3768 sig_bi[29] = 0;
3769 }
3770 /*Advance Coding, 0: BCC, 1: LDPC*/
3771 sig_bi[30] = pPMacTxInfo->bLDPC;
3772 /* Short GI*/
3773 sig_bi[31] = pPMacTxInfo->bSGI;
3774 /* N_ELTFs*/
3775 if (pPMacTxInfo->NDP_sound == FALSE) {
3776 sig_bi[32] = 0;
3777 sig_bi[33] = 0;
3778 } else {
3779 int N_ELTF = pPMacTxInfo->Ntx - pPMacPktInfo->Nss;
3780
3781 for (i = 0; i < 2; i++)
3782 sig_bi[32 + i] = (N_ELTF >> i) % 2;
3783 }
3784 /* CRC-8*/
3785 CRC8_generator(crc8, sig_bi, 34);
3786
3787 for (i = 0; i < 8; i++)
3788 sig_bi[34 + i] = crc8[i];
3789
3790 /*Tail*/
3791 for (i = 42; i < 48; i++)
3792 sig_bi[i] = 0;
3793
3794 _rtw_memset(pPMacTxInfo->HT_SIG, 0, 6);
3795 ByteToBit(pPMacTxInfo->HT_SIG, sig_bi, 6);
3796 }
3797
3798
3799 /*======================================================================================
3800 VHT-SIG-A1
3801 BW Reserved STBC G_ID SU_Nsts P_AID TXOP_PS_NOT_ALLOW Reserved
3802 2b 1b 1b 6b 3b 9b 1b 2b 1b
3803 VHT-SIG-A2
3804 SGI SGI_Nsym SU/MU coding LDPC_Extra SU_NCS Beamformed Reserved CRC Tail
3805 1b 1b 1b 1b 4b 1b 1b 8b 6b
3806 ======================================================================================*/
VHT_SIG_A_generator(PRT_PMAC_TX_INFO pPMacTxInfo,PRT_PMAC_PKT_INFO pPMacPktInfo)3807 void VHT_SIG_A_generator(
3808 PRT_PMAC_TX_INFO pPMacTxInfo,
3809 PRT_PMAC_PKT_INFO pPMacPktInfo)
3810 {
3811 u32 i;
3812 bool sig_bi[48], crc8[8];
3813
3814 _rtw_memset(sig_bi, 0, 48);
3815 _rtw_memset(crc8, 0, 8);
3816
3817 /* BW Setting*/
3818 for (i = 0; i < 2; i++)
3819 sig_bi[i] = (pPMacTxInfo->BandWidth >> i) & 0x1;
3820 /* Reserved Bit*/
3821 sig_bi[2] = 1;
3822 /*STBC Field*/
3823 sig_bi[3] = pPMacTxInfo->bSTBC;
3824 /*Group ID: Single User->A value of 0 or 63 indicates an SU PPDU. */
3825 for (i = 0; i < 6; i++)
3826 sig_bi[4 + i] = 0;
3827 /* N_STS/Partial AID*/
3828 for (i = 0; i < 12; i++) {
3829 if (i < 3)
3830 sig_bi[10 + i] = ((pPMacPktInfo->Nsts - 1) >> i) & 0x1;
3831 else
3832 sig_bi[10 + i] = 0;
3833 }
3834 /*TXOP_PS_NOT_ALLPWED*/
3835 sig_bi[22] = 0;
3836 /*Reserved Bits*/
3837 sig_bi[23] = 1;
3838 /*Short GI*/
3839 sig_bi[24] = pPMacTxInfo->bSGI;
3840 if (pPMacTxInfo->bSGI > 0 && (pPMacPktInfo->N_sym % 10) == 9)
3841 sig_bi[25] = 1;
3842 else
3843 sig_bi[25] = 0;
3844 /* SU/MU[0] Coding*/
3845 sig_bi[26] = pPMacTxInfo->bLDPC; /* 0:BCC, 1:LDPC */
3846 sig_bi[27] = pPMacPktInfo->SIGA2B3; /*/ Record Extra OFDM Symols is added or not when LDPC is used*/
3847 /*SU MCS/MU[1-3] Coding*/
3848 for (i = 0; i < 4; i++)
3849 sig_bi[28 + i] = (pPMacPktInfo->MCS >> i) & 0x1;
3850 /*SU Beamform */
3851 sig_bi[32] = 0; /*packet.TXBF_en;*/
3852 /*Reserved Bit*/
3853 sig_bi[33] = 1;
3854 /*CRC-8*/
3855 CRC8_generator(crc8, sig_bi, 34);
3856 for (i = 0; i < 8; i++)
3857 sig_bi[34 + i] = crc8[i];
3858 /*Tail*/
3859 for (i = 42; i < 48; i++)
3860 sig_bi[i] = 0;
3861
3862 _rtw_memset(pPMacTxInfo->VHT_SIG_A, 0, 6);
3863 ByteToBit(pPMacTxInfo->VHT_SIG_A, sig_bi, 6);
3864 }
3865
3866 /*======================================================================================
3867 VHT-SIG-B
3868 Length Resesrved Trail
3869 17/19/21 BIT 3/2/2 BIT 6b
3870 ======================================================================================*/
VHT_SIG_B_generator(PRT_PMAC_TX_INFO pPMacTxInfo)3871 void VHT_SIG_B_generator(
3872 PRT_PMAC_TX_INFO pPMacTxInfo)
3873 {
3874 bool sig_bi[32], crc8_bi[8];
3875 u32 i, len, res, tail = 6, total_len, crc8_in_len;
3876 u32 sigb_len;
3877
3878 _rtw_memset(sig_bi, 0, 32);
3879 _rtw_memset(crc8_bi, 0, 8);
3880
3881 /*Sounding Packet*/
3882 if (pPMacTxInfo->NDP_sound == 1) {
3883 if (pPMacTxInfo->BandWidth == 0) {
3884 bool sigb_temp[26] = {0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0};
3885
3886 _rtw_memcpy(sig_bi, sigb_temp, 26);
3887 } else if (pPMacTxInfo->BandWidth == 1) {
3888 bool sigb_temp[27] = {1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0};
3889
3890 _rtw_memcpy(sig_bi, sigb_temp, 27);
3891 } else if (pPMacTxInfo->BandWidth == 2) {
3892 bool sigb_temp[29] = {0, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0};
3893
3894 _rtw_memcpy(sig_bi, sigb_temp, 29);
3895 }
3896 } else { /* Not NDP Sounding*/
3897 bool *sigb_temp[29] = {0};
3898
3899 if (pPMacTxInfo->BandWidth == 0) {
3900 len = 17;
3901 res = 3;
3902 } else if (pPMacTxInfo->BandWidth == 1) {
3903 len = 19;
3904 res = 2;
3905 } else if (pPMacTxInfo->BandWidth == 2) {
3906 len = 21;
3907 res = 2;
3908 } else {
3909 len = 21;
3910 res = 2;
3911 }
3912 total_len = len + res + tail;
3913 crc8_in_len = len + res;
3914
3915 /*Length Field*/
3916 sigb_len = (pPMacTxInfo->PacketLength + 3) >> 2;
3917
3918 for (i = 0; i < len; i++)
3919 sig_bi[i] = (sigb_len >> i) & 0x1;
3920 /*Reserved Field*/
3921 for (i = 0; i < res; i++)
3922 sig_bi[len + i] = 1;
3923 /* CRC-8*/
3924 CRC8_generator(crc8_bi, sig_bi, crc8_in_len);
3925
3926 /* Tail */
3927 for (i = 0; i < tail; i++)
3928 sig_bi[len + res + i] = 0;
3929 }
3930
3931 _rtw_memset(pPMacTxInfo->VHT_SIG_B, 0, 4);
3932 ByteToBit(pPMacTxInfo->VHT_SIG_B, sig_bi, 4);
3933
3934 pPMacTxInfo->VHT_SIG_B_CRC = 0;
3935 ByteToBit(&(pPMacTxInfo->VHT_SIG_B_CRC), crc8_bi, 1);
3936 }
3937
3938 /*=======================
3939 VHT Delimiter
3940 =======================*/
VHT_Delimiter_generator(PRT_PMAC_TX_INFO pPMacTxInfo)3941 void VHT_Delimiter_generator(
3942 PRT_PMAC_TX_INFO pPMacTxInfo
3943 )
3944 {
3945 bool sig_bi[32] = {0}, crc8[8] = {0};
3946 u32 crc8_in_len = 16;
3947 u32 PacketLength = pPMacTxInfo->PacketLength;
3948 int j;
3949
3950 /* Delimiter[0]: EOF*/
3951 sig_bi[0] = 1;
3952 /* Delimiter[1]: Reserved*/
3953 sig_bi[1] = 0;
3954 /* Delimiter[3:2]: MPDU Length High*/
3955 sig_bi[2] = ((PacketLength - 4) >> 12) % 2;
3956 sig_bi[3] = ((PacketLength - 4) >> 13) % 2;
3957 /* Delimiter[15:4]: MPDU Length Low*/
3958 for (j = 4; j < 16; j++)
3959 sig_bi[j] = ((PacketLength - 4) >> (j - 4)) % 2;
3960 CRC8_generator(crc8, sig_bi, crc8_in_len);
3961 for (j = 16; j < 24; j++) /* Delimiter[23:16]: CRC 8*/
3962 sig_bi[j] = crc8[j - 16];
3963 for (j = 24; j < 32; j++) /* Delimiter[31:24]: Signature ('4E' in Hex, 78 in Dec)*/
3964 sig_bi[j] = (78 >> (j - 24)) % 2;
3965
3966 _rtw_memset(pPMacTxInfo->VHT_Delimiter, 0, 4);
3967 ByteToBit(pPMacTxInfo->VHT_Delimiter, sig_bi, 4);
3968 }
3969
3970 #endif
3971 #endif
3972