1 /* 2 * Include file private to the SOC Interconnect support files. 3 * 4 * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation 5 * 6 * Copyright (C) 1999-2017, Broadcom Corporation 7 * 8 * Unless you and Broadcom execute a separate written software license 9 * agreement governing use of this software, this software is licensed to you 10 * under the terms of the GNU General Public License version 2 (the "GPL"), 11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12 * following added to such license: 13 * 14 * As a special exception, the copyright holders of this software give you 15 * permission to link this software with independent modules, and to copy and 16 * distribute the resulting executable under terms of your choice, provided that 17 * you also meet, for each linked independent module, the terms and conditions of 18 * the license of that module. An independent module is a module which is not 19 * derived from this software. The special exception does not apply to any 20 * modifications of the software. 21 * 22 * Notwithstanding the above, under no circumstances may you combine this 23 * software in any way with any other Broadcom software provided under a license 24 * other than the GPL, without Broadcom's express prior written consent. 25 * 26 * 27 * <<Broadcom-WL-IPTag/Open:>> 28 * 29 * $Id: siutils_priv.h 698933 2017-05-11 06:05:10Z $ 30 */ 31 32 #ifndef _siutils_priv_h_ 33 #define _siutils_priv_h_ 34 35 #if defined(SI_ERROR_ENFORCE) 36 #define SI_ERROR(args) printf args 37 #else 38 #define SI_ERROR(args) 39 #endif // endif 40 41 #if defined(ENABLE_CORECAPTURE) 42 43 #define SI_PRINT(args) osl_wificc_logDebug args 44 45 #else 46 47 #define SI_PRINT(args) printf args 48 49 #endif /* ENABLE_CORECAPTURE */ 50 51 #define SI_MSG(args) 52 53 #ifdef BCMDBG_SI 54 #define SI_VMSG(args) printf args 55 #else 56 #define SI_VMSG(args) 57 #endif // endif 58 59 #define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID)) 60 61 typedef uint32 (*si_intrsoff_t)(void *intr_arg); 62 typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg); 63 typedef bool (*si_intrsenabled_t)(void *intr_arg); 64 65 #define SI_GPIO_MAX 16 66 67 typedef struct gci_gpio_item { 68 void *arg; 69 uint8 gci_gpio; 70 uint8 status; 71 gci_gpio_handler_t handler; 72 struct gci_gpio_item *next; 73 } gci_gpio_item_t; 74 75 #define AI_SLAVE_WRAPPER 0 76 #define AI_MASTER_WRAPPER 1 77 78 typedef struct axi_wrapper { 79 uint32 mfg; 80 uint32 cid; 81 uint32 rev; 82 uint32 wrapper_type; 83 uint32 wrapper_addr; 84 uint32 wrapper_size; 85 } axi_wrapper_t; 86 87 #define SI_MAX_AXI_WRAPPERS 32 88 #define AI_REG_READ_TIMEOUT 300 /* in msec */ 89 90 /* for some combo chips, BT side accesses chipcommon->0x190, as a 16 byte addr */ 91 /* register at 0x19C doesn't exist, so error is logged at the slave wrapper */ 92 #define BT_CC_SPROM_BADREG_LO 0x18000190 93 #define BT_CC_SPROM_BADREG_SIZE 4 94 #define BT_CC_SPROM_BADREG_HI 0 95 #define BCM4350_BT_AXI_ID 6 96 #define BCM4345_BT_AXI_ID 6 97 #define BCM4349_BT_AXI_ID 5 98 #define BCM4364_BT_AXI_ID 5 99 100 /* for BT logging and memory dump, ignore failed access to BT memory */ 101 #define BCM4347_BT_ADDR_HI 0 102 #define BCM4347_BT_ADDR_LO 0x19000000 /* BT address space */ 103 #define BCM4347_BT_SIZE 0x01000000 /* BT address space size */ 104 #define BCM4347_UNUSED_AXI_ID 0xffffffff 105 #define BCM4347_CC_AXI_ID 0 106 #define BCM4347_PCIE_AXI_ID 1 107 108 typedef struct si_cores_info { 109 volatile void *regs[SI_MAXCORES]; /* other regs va */ 110 111 uint coreid[SI_MAXCORES]; /**< id of each core */ 112 uint32 coresba[SI_MAXCORES]; /**< backplane address of each core */ 113 void *regs2[SI_MAXCORES]; /**< va of each core second register set (usbh20) */ 114 uint32 coresba2[SI_MAXCORES]; /**< address of each core second register set (usbh20) */ 115 uint32 coresba_size[SI_MAXCORES]; /**< backplane address space size */ 116 uint32 coresba2_size[SI_MAXCORES]; /**< second address space size */ 117 118 void *wrappers[SI_MAXCORES]; /**< other cores wrapper va */ 119 uint32 wrapba[SI_MAXCORES]; /**< address of controlling wrapper */ 120 121 void *wrappers2[SI_MAXCORES]; /**< other cores wrapper va */ 122 uint32 wrapba2[SI_MAXCORES]; /**< address of controlling wrapper */ 123 124 void *wrappers3[SI_MAXCORES]; /**< other cores wrapper va */ 125 uint32 wrapba3[SI_MAXCORES]; /**< address of controlling wrapper */ 126 127 uint32 cia[SI_MAXCORES]; /**< erom cia entry for each core */ 128 uint32 cib[SI_MAXCORES]; /**< erom cia entry for each core */ 129 130 uint32 csp2ba[SI_MAXCORES]; /**< Second slave port base addr 0 */ 131 uint32 csp2ba_size[SI_MAXCORES]; /**< Second slave port addr space size */ 132 } si_cores_info_t; 133 134 /** misc si info needed by some of the routines */ 135 typedef struct si_info { 136 struct si_pub pub; /**< back plane public state (must be first field) */ 137 138 void *osh; /**< osl os handle */ 139 void *sdh; /**< bcmsdh handle */ 140 141 uint dev_coreid; /**< the core provides driver functions */ 142 void *intr_arg; /**< interrupt callback function arg */ 143 si_intrsoff_t intrsoff_fn; /**< turns chip interrupts off */ 144 si_intrsrestore_t intrsrestore_fn; /**< restore chip interrupts */ 145 si_intrsenabled_t intrsenabled_fn; /**< check if interrupts are enabled */ 146 147 void *pch; /**< PCI/E core handle */ 148 149 bool memseg; /**< flag to toggle MEM_SEG register */ 150 151 char *vars; 152 uint varsz; 153 154 volatile void *curmap; /* current regs va */ 155 156 uint curidx; /**< current core index */ 157 uint numcores; /**< # discovered cores */ 158 159 void *curwrap; /**< current wrapper va */ 160 161 uint32 oob_router; /**< oob router registers for axi */ 162 uint32 oob_router1; /**< oob router registers for axi */ 163 164 si_cores_info_t *cores_info; 165 gci_gpio_item_t *gci_gpio_head; /**< gci gpio interrupts head */ 166 uint chipnew; /**< new chip number */ 167 uint second_bar0win; /**< Backplane region */ 168 uint num_br; /**< # discovered bridges */ 169 uint32 br_wrapba[SI_MAXBR]; /**< address of bridge controlling wrapper */ 170 uint32 xtalfreq; 171 uint32 openloop_dco_code; /**< OPEN loop calibration dco code */ 172 uint8 spurmode; 173 bool device_removed; 174 uint axi_num_wrappers; 175 axi_wrapper_t * axi_wrapper; 176 uint8 device_wake_opt; /* device_wake GPIO number */ 177 uint8 lhl_ps_mode; 178 } si_info_t; 179 180 #define SI_INFO(sih) ((si_info_t *)(uintptr)sih) 181 182 #define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \ 183 ISALIGNED((x), SI_CORE_SIZE)) 184 #define GOODREGS(regs) ((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE)) 185 #define BADCOREADDR 0 186 #define GOODIDX(idx) (((uint)idx) < SI_MAXCORES) 187 #define NOREV -1 /**< Invalid rev */ 188 189 #define PCI(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 190 ((si)->pub.buscoretype == PCI_CORE_ID)) 191 192 #define PCIE_GEN1(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 193 ((si)->pub.buscoretype == PCIE_CORE_ID)) 194 195 #define PCIE_GEN2(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 196 ((si)->pub.buscoretype == PCIE2_CORE_ID)) 197 198 #define PCIE(si) (PCIE_GEN1(si) || PCIE_GEN2(si)) 199 200 #define PCMCIA(si) ((BUSTYPE((si)->pub.bustype) == PCMCIA_BUS) && ((si)->memseg == TRUE)) 201 202 /** Newer chips can access PCI/PCIE and CC core without requiring to change PCI BAR0 WIN */ 203 #define SI_FAST(si) (PCIE(si) || (PCI(si) && ((si)->pub.buscorerev >= 13))) 204 205 #define CCREGS_FAST(si) \ 206 (((si)->curmap == NULL) ? NULL : \ 207 ((volatile char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET)) 208 #define PCIEREGS(si) (((volatile char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET)) 209 210 /* 211 * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/ 212 * after core switching to avoid invalid register accesss inside ISR. 213 */ 214 #define INTR_OFF(si, intr_val) \ 215 if ((si)->intrsoff_fn && (si)->cores_info->coreid[(si)->curidx] == (si)->dev_coreid) { \ 216 intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); } 217 #define INTR_RESTORE(si, intr_val) \ 218 if ((si)->intrsrestore_fn && (si)->cores_info->coreid[(si)->curidx] == (si)->dev_coreid) { \ 219 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); } 220 221 /* dynamic clock control defines */ 222 #define LPOMINFREQ 25000 /**< low power oscillator min */ 223 #define LPOMAXFREQ 43000 /**< low power oscillator max */ 224 #define XTALMINFREQ 19800000 /**< 20 MHz - 1% */ 225 #define XTALMAXFREQ 20200000 /**< 20 MHz + 1% */ 226 #define PCIMINFREQ 25000000 /**< 25 MHz */ 227 #define PCIMAXFREQ 34000000 /**< 33 MHz + fudge */ 228 229 #define ILP_DIV_5MHZ 0 /**< ILP = 5 MHz */ 230 #define ILP_DIV_1MHZ 4 /**< ILP = 1 MHz */ 231 232 /* GPIO Based LED powersave defines */ 233 #define DEFAULT_GPIO_ONTIME 10 /**< Default: 10% on */ 234 #define DEFAULT_GPIO_OFFTIME 90 /**< Default: 10% on */ 235 236 #ifndef DEFAULT_GPIOTIMERVAL 237 #define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME) 238 #endif // endif 239 240 /* Silicon Backplane externs */ 241 extern void sb_scan(si_t *sih, volatile void *regs, uint devid); 242 extern uint sb_coreid(si_t *sih); 243 extern uint sb_intflag(si_t *sih); 244 extern uint sb_flag(si_t *sih); 245 extern void sb_setint(si_t *sih, int siflag); 246 extern uint sb_corevendor(si_t *sih); 247 extern uint sb_corerev(si_t *sih); 248 extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 249 extern volatile uint32 *sb_corereg_addr(si_t *sih, uint coreidx, uint regoff); 250 extern bool sb_iscoreup(si_t *sih); 251 extern volatile void *sb_setcoreidx(si_t *sih, uint coreidx); 252 extern uint32 sb_core_cflags(si_t *sih, uint32 mask, uint32 val); 253 extern void sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); 254 extern uint32 sb_core_sflags(si_t *sih, uint32 mask, uint32 val); 255 extern void sb_commit(si_t *sih); 256 extern uint32 sb_base(uint32 admatch); 257 extern uint32 sb_size(uint32 admatch); 258 extern void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 259 extern void sb_core_disable(si_t *sih, uint32 bits); 260 extern uint32 sb_addrspace(si_t *sih, uint asidx); 261 extern uint32 sb_addrspacesize(si_t *sih, uint asidx); 262 extern int sb_numaddrspaces(si_t *sih); 263 264 extern uint32 sb_set_initiator_to(si_t *sih, uint32 to, uint idx); 265 266 extern bool sb_taclear(si_t *sih, bool details); 267 268 #if defined(BCMDBG_PHYDUMP) 269 extern void sb_dumpregs(si_t *sih, struct bcmstrbuf *b); 270 #endif // endif 271 272 /* Wake-on-wireless-LAN (WOWL) */ 273 extern bool sb_pci_pmecap(si_t *sih); 274 struct osl_info; 275 extern bool sb_pci_fastpmecap(struct osl_info *osh); 276 extern bool sb_pci_pmeclr(si_t *sih); 277 extern void sb_pci_pmeen(si_t *sih); 278 extern uint sb_pcie_readreg(void *sih, uint addrtype, uint offset); 279 280 /* AMBA Interconnect exported externs */ 281 extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype, 282 void *sdh, char **vars, uint *varsz); 283 extern si_t *ai_kattach(osl_t *osh); 284 extern void ai_scan(si_t *sih, void *regs, uint32 erombase, uint devid); 285 286 extern uint ai_flag(si_t *sih); 287 extern uint ai_flag_alt(si_t *sih); 288 extern void ai_setint(si_t *sih, int siflag); 289 extern uint ai_coreidx(si_t *sih); 290 extern uint ai_corevendor(si_t *sih); 291 extern uint ai_corerev(si_t *sih); 292 extern uint ai_corerev_minor(si_t *sih); 293 extern volatile uint32 *ai_corereg_addr(si_t *sih, uint coreidx, uint regoff); 294 extern bool ai_iscoreup(si_t *sih); 295 extern volatile void *ai_setcoreidx(si_t *sih, uint coreidx); 296 extern volatile void *ai_setcoreidx_2ndwrap(si_t *sih, uint coreidx); 297 extern volatile void *ai_setcoreidx_3rdwrap(si_t *sih, uint coreidx); 298 extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val); 299 extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); 300 extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val); 301 extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 302 extern uint ai_corereg_writeonly(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 303 extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 304 extern void ai_d11rsdb_core_reset(si_t *sih, uint32 bits, 305 uint32 resetbits, void *p, volatile void *s); 306 extern void ai_core_disable(si_t *sih, uint32 bits); 307 extern void ai_d11rsdb_core_disable(const si_info_t *sii, uint32 bits, 308 aidmp_t *pmacai, aidmp_t *smacai); 309 extern int ai_numaddrspaces(si_t *sih); 310 extern uint32 ai_addrspace(si_t *sih, uint spidx, uint baidx); 311 extern uint32 ai_addrspacesize(si_t *sih, uint spidx, uint baidx); 312 extern void ai_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size); 313 extern uint ai_wrap_reg(si_t *sih, uint32 offset, uint32 mask, uint32 val); 314 extern void ai_update_backplane_timeouts(si_t *sih, bool enable, uint32 timeout, uint32 cid); 315 extern uint32 ai_clear_backplane_to(si_t *sih); 316 void ai_force_clocks(si_t *sih, uint clock_state); 317 extern uint ai_num_slaveports(si_t *sih, uint coreidx); 318 319 #ifdef BCM_BACKPLANE_TIMEOUT 320 uint32 ai_clear_backplane_to_fast(si_t *sih, void * addr); 321 #endif /* BCM_BACKPLANE_TIMEOUT */ 322 323 #if defined(AXI_TIMEOUTS) || defined(BCM_BACKPLANE_TIMEOUT) 324 extern uint32 ai_clear_backplane_to_per_core(si_t *sih, uint coreid, uint coreunit, void * wrap); 325 #endif /* AXI_TIMEOUTS || BCM_BACKPLANE_TIMEOUT */ 326 327 #if defined(BCMDBG_PHYDUMP) 328 extern void ai_dumpregs(si_t *sih, struct bcmstrbuf *b); 329 #endif // endif 330 331 extern uint32 ai_wrapper_dump_buf_size(si_t *sih); 332 extern uint32 ai_wrapper_dump_binary(si_t *sih, uchar *p); 333 extern bool ai_check_enable_backplane_log(si_t *sih); 334 extern uint32 ai_wrapper_dump_last_timeout(si_t *sih, uint32 *error, uint32 *core, uint32 *ba, 335 uchar *p); 336 337 #define ub_scan(a, b, c) do {} while (0) 338 #define ub_flag(a) (0) 339 #define ub_setint(a, b) do {} while (0) 340 #define ub_coreidx(a) (0) 341 #define ub_corevendor(a) (0) 342 #define ub_corerev(a) (0) 343 #define ub_iscoreup(a) (0) 344 #define ub_setcoreidx(a, b) (0) 345 #define ub_core_cflags(a, b, c) (0) 346 #define ub_core_cflags_wo(a, b, c) do {} while (0) 347 #define ub_core_sflags(a, b, c) (0) 348 #define ub_corereg(a, b, c, d, e) (0) 349 #define ub_core_reset(a, b, c) do {} while (0) 350 #define ub_core_disable(a, b) do {} while (0) 351 #define ub_numaddrspaces(a) (0) 352 #define ub_addrspace(a, b) (0) 353 #define ub_addrspacesize(a, b) (0) 354 #define ub_view(a, b) do {} while (0) 355 #define ub_dumpregs(a, b) do {} while (0) 356 357 #endif /* _siutils_priv_h_ */ 358