1 /* 2 * otpdefs.h SROM/OTP definitions. 3 * 4 * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation 5 * 6 * Copyright 2021 Broadcom 7 * 8 * This program is the proprietary software of Broadcom and/or 9 * its licensors, and may only be used, duplicated, modified or distributed 10 * pursuant to the terms and conditions of a separate, written license 11 * agreement executed between you and Broadcom (an "Authorized License"). 12 * Except as set forth in an Authorized License, Broadcom grants no license 13 * (express or implied), right to use, or waiver of any kind with respect to 14 * the Software, and Broadcom expressly reserves all rights in and to the 15 * Software and all intellectual property rights therein. IF YOU HAVE NO 16 * AUTHORIZED LICENSE, THEN YOU HAVE NO RIGHT TO USE THIS SOFTWARE IN ANY 17 * WAY, AND SHOULD IMMEDIATELY NOTIFY BROADCOM AND DISCONTINUE ALL USE OF 18 * THE SOFTWARE. 19 * 20 * Except as expressly set forth in the Authorized License, 21 * 22 * 1. This program, including its structure, sequence and organization, 23 * constitutes the valuable trade secrets of Broadcom, and you shall use 24 * all reasonable efforts to protect the confidentiality thereof, and to 25 * use this information only in connection with your use of Broadcom 26 * integrated circuit products. 27 * 28 * 2. TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED 29 * "AS IS" AND WITH ALL FAULTS AND BROADCOM MAKES NO PROMISES, 30 * REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR 31 * OTHERWISE, WITH RESPECT TO THE SOFTWARE. BROADCOM SPECIFICALLY 32 * DISCLAIMS ANY AND ALL IMPLIED WARRANTIES OF TITLE, MERCHANTABILITY, 33 * NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, 34 * ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 35 * CORRESPONDENCE TO DESCRIPTION. YOU ASSUME THE ENTIRE RISK ARISING 36 * OUT OF USE OR PERFORMANCE OF THE SOFTWARE. 37 * 38 * 3. TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL 39 * BROADCOM OR ITS LICENSORS BE LIABLE FOR (i) CONSEQUENTIAL, INCIDENTAL, 40 * SPECIAL, INDIRECT, OR EXEMPLARY DAMAGES WHATSOEVER ARISING OUT OF OR 41 * IN ANY WAY RELATING TO YOUR USE OF OR INABILITY TO USE THE SOFTWARE EVEN 42 * IF BROADCOM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES; OR (ii) 43 * ANY AMOUNT IN EXCESS OF THE AMOUNT ACTUALLY PAID FOR THE SOFTWARE ITSELF 44 * OR U.S. $1, WHICHEVER IS GREATER. THESE LIMITATIONS SHALL APPLY 45 * NOTWITHSTANDING ANY FAILURE OF ESSENTIAL PURPOSE OF ANY LIMITED REMEDY. 46 * 47 * <<Broadcom-WL-IPTag/Open:>> 48 * 49 * $Id$ 50 */ 51 52 #ifndef _OTPDEFS_H_ 53 #define _OTPDEFS_H_ 54 55 /* SFLASH */ 56 #define SFLASH_ADDRESS_OFFSET_4368 0x1C000000u 57 #define SFLASH_SKU_OFFSET_4368 0xEu 58 #define SFLASH_MACADDR_OFFSET_4368 0x4u 59 /* 60 * In sflash based chips, first word in sflash says the length. 61 * So only default value is defined here. Actual length is read 62 * from sflash in dhdpcie_srom_sflash_health_chk 63 * 0x0521 * 2 .x2 since length says number of words. 64 */ 65 #define SFLASH_LEN_4368 0xA42u 66 67 #define SROM_ADDRESS_OFFSET_4355 0x0800u 68 #define SROM_ADDRESS_OFFSET_4364 0xA000u 69 #define SROM_ADDRESS_OFFSET_4377 0x0800u 70 #define SROM_ADDRESS(sih, offset) (SI_ENUM_BASE(sih) + (offset)) 71 #define SROM_MACADDR_OFFSET_4355 0x84u 72 #define SROM_MACADDR_OFFSET_4364 0x82u 73 #define SROM_MACADDR_OFFSET_4377 0xE2u 74 #define SROM_SKU_OFFSET_4355 0x8Au 75 #define SROM_SKU_OFFSET_4364 0x8Cu 76 #define SROM_SKU_OFFSET_4377 0xECu 77 #define SROM_CAL_SIG1_OFFSET_4355 0xB8u 78 #define SROM_CAL_SIG2_OFFSET_4355 0xBAu 79 #define SROM_CAL_SIG1_OFFSET_4364 0xA0u 80 #define SROM_CAL_SIG2_OFFSET_4364 0xA2u 81 #define SROM_CAL_SIG1 0x4c42u 82 #define SROM_CAL_SIG2 0x424fu 83 #define SROM_LEN_4355 512u 84 #define SROM_LEN_4364 2048u 85 #define SROM_LEN_4377 2048u 86 87 #define OTP_USER_AREA_OFFSET_4355 0xC0u 88 #define OTP_USER_AREA_OFFSET_4364 0xC0u 89 #define OTP_USER_AREA_OFFSET_4368 0x120u 90 #define OTP_USER_AREA_OFFSET_4377 0x120u 91 #define OTP_OFFSET_4368 0x5000u 92 #define OTP_OFFSET_4377 0x11000u 93 #define OTP_CTRL1_VAL 0xFA0000 94 #define OTP_ADDRESS(sih, offset) (SI_ENUM_BASE(sih) + (offset)) 95 #define OTP_VERSION_TUPLE_ID 0x15 96 #define OTP_VENDOR_TUPLE_ID 0x80 97 #define OTP_CIS_REGION_END_TUPLE_ID 0XFF 98 99 #define PCIE_CTRL_REG_ADDR(sih) (SI_ENUM_BASE(sih) + 0x3000) 100 #define SPROM_CTRL_REG_ADDR(sih) (SI_ENUM_BASE(sih) + CC_SROM_CTRL) 101 #define SPROM_CTRL_OPCODE_READ_MASK 0x9FFFFFFF 102 #define SPROM_CTRL_START_BUSY_MASK 0x80000000 103 #define SPROM_ADDR(sih) (SI_ENUM_BASE(sih) + CC_SROM_ADDRESS) 104 #define SPROM_DATA(sih) (SI_ENUM_BASE(sih) + CC_SROM_DATA) 105 #define OTP_CTRL1_REG_ADDR(sih) (SI_ENUM_BASE(sih) + 0xF4) 106 #define PMU_MINRESMASK_REG_ADDR(sih) (SI_ENUM_BASE(sih) + MINRESMASKREG) 107 #define CHIP_COMMON_STATUS_REG_ADDR(sih) (SI_ENUM_BASE(sih) + CC_CHIPST) 108 #define CHIP_COMMON_CLKDIV2_ADDR(sih) (SI_ENUM_BASE(sih) + CC_CLKDIV2) 109 110 #define CC_CLKDIV2_SPROMDIV_MASK 0x7u 111 #define CC_CLKDIV2_SPROMDIV_VAL 0X4u 112 #define CC_CHIPSTATUS_STRAP_BTUART_MASK 0x40u 113 #define PMU_OTP_PWR_ON_MASK 0xC47 114 #define PMU_PWRUP_DELAY 500 /* in us */ 115 #define DONGLE_TREFUP_PROGRAM_DELAY 5000 /* 5ms in us */ 116 #define SPROM_BUSY_POLL_DELAY 5 /* 5us */ 117 118 typedef enum { 119 BCM4355_IDX = 0, 120 BCM4364_IDX, 121 BCM4368_IDX, 122 BCM4377_IDX, 123 BCMMAX_IDX 124 } chip_idx_t; 125 126 typedef enum { 127 BCM4368_BTOP_IDX, 128 BCM4377_BTOP_IDX, 129 BCMMAX_BTOP_IDX 130 } chip_idx_btop_t; 131 132 typedef enum { 133 BCM4368_SFLASH_IDX, 134 BCMMAX_SFLASH_IDX 135 } chip_idx_sflash_t; 136 137 extern uint32 otp_addr_offsets[]; 138 extern uint32 otp_usrarea_offsets[]; 139 extern uint32 sku_offsets[]; 140 extern uint32 srf_addr_offsets[]; 141 extern uint32 supported_chips[]; 142 143 char *dhd_get_plat_sku(void); 144 #endif /* _OTPDEFS_H */ 145