1 /*
2 * Misc utility routines for accessing the SOC Interconnects
3 * of Broadcom HNBU chips.
4 *
5 * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation
6 *
7 * Copyright (C) 1999-2017, Broadcom Corporation
8 *
9 * Unless you and Broadcom execute a separate written software license
10 * agreement governing use of this software, this software is licensed to you
11 * under the terms of the GNU General Public License version 2 (the "GPL"),
12 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
13 * following added to such license:
14 *
15 * As a special exception, the copyright holders of this software give you
16 * permission to link this software with independent modules, and to copy and
17 * distribute the resulting executable under terms of your choice, provided that
18 * you also meet, for each linked independent module, the terms and conditions of
19 * the license of that module. An independent module is a module which is not
20 * derived from this software. The special exception does not apply to any
21 * modifications of the software.
22 *
23 * Notwithstanding the above, under no circumstances may you combine this
24 * software in any way with any other Broadcom software provided under a license
25 * other than the GPL, without Broadcom's express prior written consent.
26 *
27 *
28 * <<Broadcom-WL-IPTag/Open:>>
29 *
30 * $Id: siutils.h 699906 2017-05-16 22:39:33Z $
31 */
32
33 #ifndef _siutils_h_
34 #define _siutils_h_
35
36 #ifdef SR_DEBUG
37 #include "wlioctl.h"
38 #endif /* SR_DEBUG */
39
40 #define WARM_BOOT 0xA0B0C0D0
41
42 #ifdef BCM_BACKPLANE_TIMEOUT
43
44 #define SI_MAX_ERRLOG_SIZE 4
45 typedef struct si_axi_error
46 {
47 uint32 error;
48 uint32 coreid;
49 uint32 errlog_lo;
50 uint32 errlog_hi;
51 uint32 errlog_id;
52 uint32 errlog_flags;
53 uint32 errlog_status;
54 } si_axi_error_t;
55
56 typedef struct si_axi_error_info
57 {
58 uint32 count;
59 si_axi_error_t axi_error[SI_MAX_ERRLOG_SIZE];
60 } si_axi_error_info_t;
61 #endif /* BCM_BACKPLANE_TIMEOUT */
62
63 /**
64 * Data structure to export all chip specific common variables
65 * public (read-only) portion of siutils handle returned by si_attach()/si_kattach()
66 */
67 struct si_pub {
68 uint socitype; /**< SOCI_SB, SOCI_AI */
69
70 uint bustype; /**< SI_BUS, PCI_BUS */
71 uint buscoretype; /**< PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
72 uint buscorerev; /**< buscore rev */
73 uint buscoreidx; /**< buscore index */
74 int ccrev; /**< chip common core rev */
75 uint32 cccaps; /**< chip common capabilities */
76 uint32 cccaps_ext; /**< chip common capabilities extension */
77 int pmurev; /**< pmu core rev */
78 uint32 pmucaps; /**< pmu capabilities */
79 uint boardtype; /**< board type */
80 uint boardrev; /* board rev */
81 uint boardvendor; /**< board vendor */
82 uint boardflags; /**< board flags */
83 uint boardflags2; /**< board flags2 */
84 uint boardflags4; /**< board flags4 */
85 uint chip; /**< chip number */
86 uint chiprev; /**< chip revision */
87 uint chippkg; /**< chip package option */
88 uint32 chipst; /**< chip status */
89 bool issim; /**< chip is in simulation or emulation */
90 uint socirev; /**< SOC interconnect rev */
91 bool pci_pr32414;
92 int gcirev; /**< gci core rev */
93 int lpflags; /**< low power flags */
94 uint32 enum_base; /**< backplane address where the chipcommon core resides */
95
96 #ifdef BCM_BACKPLANE_TIMEOUT
97 si_axi_error_info_t * err_info;
98 #endif /* BCM_BACKPLANE_TIMEOUT */
99
100 bool _multibp_enable;
101 bool secureboot;
102 bool chipidpresent;
103 };
104
105 /* for HIGH_ONLY driver, the si_t must be writable to allow states sync from BMAC to HIGH driver
106 * for monolithic driver, it is readonly to prevent accident change
107 */
108 typedef struct si_pub si_t;
109
110 /*
111 * Many of the routines below take an 'sih' handle as their first arg.
112 * Allocate this by calling si_attach(). Free it by calling si_detach().
113 * At any one time, the sih is logically focused on one particular si core
114 * (the "current core").
115 * Use si_setcore() or si_setcoreidx() to change the association to another core.
116 */
117 #define SI_OSH NULL /**< Use for si_kattach when no osh is available */
118
119 #define BADIDX (SI_MAXCORES + 1)
120
121 /* clkctl xtal what flags */
122 #define XTAL 0x1 /**< primary crystal oscillator (2050) */
123 #define PLL 0x2 /**< main chip pll */
124
125 /* clkctl clk mode */
126 #define CLK_FAST 0 /**< force fast (pll) clock */
127 #define CLK_DYNAMIC 2 /**< enable dynamic clock control */
128
129 /* GPIO usage priorities */
130 #define GPIO_DRV_PRIORITY 0 /**< Driver */
131 #define GPIO_APP_PRIORITY 1 /**< Application */
132 #define GPIO_HI_PRIORITY 2 /**< Highest priority. Ignore GPIO reservation */
133
134 /* GPIO pull up/down */
135 #define GPIO_PULLUP 0
136 #define GPIO_PULLDN 1
137
138 /* GPIO event regtype */
139 #define GPIO_REGEVT 0 /**< GPIO register event */
140 #define GPIO_REGEVT_INTMSK 1 /**< GPIO register event int mask */
141 #define GPIO_REGEVT_INTPOL 2 /**< GPIO register event int polarity */
142
143 /* device path */
144 #define SI_DEVPATH_BUFSZ 16 /**< min buffer size in bytes */
145
146 /* SI routine enumeration: to be used by update function with multiple hooks */
147 #define SI_DOATTACH 1
148 #define SI_PCIDOWN 2 /**< wireless interface is down */
149 #define SI_PCIUP 3 /**< wireless interface is up */
150
151 #ifdef SR_DEBUG
152 #define PMU_RES 31
153 #endif /* SR_DEBUG */
154
155 /* "access" param defines for si_seci_access() below */
156 #define SECI_ACCESS_STATUSMASK_SET 0
157 #define SECI_ACCESS_INTRS 1
158 #define SECI_ACCESS_UART_CTS 2
159 #define SECI_ACCESS_UART_RTS 3
160 #define SECI_ACCESS_UART_RXEMPTY 4
161 #define SECI_ACCESS_UART_GETC 5
162 #define SECI_ACCESS_UART_TXFULL 6
163 #define SECI_ACCESS_UART_PUTC 7
164 #define SECI_ACCESS_STATUSMASK_GET 8
165
166 #if defined(BCMQT)
167 #define ISSIM_ENAB(sih) TRUE
168 #else
169 #define ISSIM_ENAB(sih) FALSE
170 #endif // endif
171
172 #define INVALID_ADDR (~0)
173
174 /* PMU clock/power control */
175 #if defined(BCMPMUCTL)
176 #define PMUCTL_ENAB(sih) (BCMPMUCTL)
177 #else
178 #define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU)
179 #endif // endif
180
181 #if defined(BCMAOBENAB)
182 #define AOB_ENAB(sih) (BCMAOBENAB)
183 #else
184 #define AOB_ENAB(sih) ((sih)->ccrev >= 35 ? \
185 ((sih)->cccaps_ext & CC_CAP_EXT_AOB_PRESENT) : 0)
186 #endif /* BCMAOBENAB */
187
188 /* chipcommon clock/power control (exclusive with PMU's) */
189 #if defined(BCMPMUCTL) && BCMPMUCTL
190 #define CCCTL_ENAB(sih) (0)
191 #define CCPLL_ENAB(sih) (0)
192 #else
193 #define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL)
194 #define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
195 #endif // endif
196
197 typedef void (*gci_gpio_handler_t)(uint32 stat, void *arg);
198
199 /* External BT Coex enable mask */
200 #define CC_BTCOEX_EN_MASK 0x01
201 /* External PA enable mask */
202 #define GPIO_CTRL_EPA_EN_MASK 0x40
203 /* WL/BT control enable mask */
204 #define GPIO_CTRL_5_6_EN_MASK 0x60
205 #define GPIO_CTRL_7_6_EN_MASK 0xC0
206 #define GPIO_OUT_7_EN_MASK 0x80
207
208 /* CR4 specific defines used by the host driver */
209 #define SI_CR4_CAP (0x04)
210 #define SI_CR4_BANKIDX (0x40)
211 #define SI_CR4_BANKINFO (0x44)
212 #define SI_CR4_BANKPDA (0x4C)
213
214 #define ARMCR4_TCBBNB_MASK 0xf0
215 #define ARMCR4_TCBBNB_SHIFT 4
216 #define ARMCR4_TCBANB_MASK 0xf
217 #define ARMCR4_TCBANB_SHIFT 0
218
219 #define SICF_CPUHALT (0x0020)
220 #define ARMCR4_BSZ_MASK 0x7f
221 #define ARMCR4_BUNITSZ_MASK 0x200
222 #define ARMCR4_BSZ_8K 8192
223 #define ARMCR4_BSZ_1K 1024
224 #define SI_BPIND_1BYTE 0x1
225 #define SI_BPIND_2BYTE 0x3
226 #define SI_BPIND_4BYTE 0xF
227
228 #define GET_GCI_OFFSET(sih, gci_reg) \
229 (AOB_ENAB(sih)? OFFSETOF(gciregs_t, gci_reg) : OFFSETOF(chipcregs_t, gci_reg))
230
231 #define GET_GCI_CORE(sih) \
232 (AOB_ENAB(sih)? si_findcoreidx(sih, GCI_CORE_ID, 0) : SI_CC_IDX)
233
234 #include <osl_decl.h>
235 /* === exported functions === */
236 extern si_t *si_attach(uint pcidev, osl_t *osh, volatile void *regs, uint bustype,
237 void *sdh, char **vars, uint *varsz);
238 extern si_t *si_kattach(osl_t *osh);
239 extern void si_detach(si_t *sih);
240 extern volatile void *
241 si_d11_switch_addrbase(si_t *sih, uint coreunit);
242 extern uint si_corelist(si_t *sih, uint coreid[]);
243 extern uint si_coreid(si_t *sih);
244 extern uint si_flag(si_t *sih);
245 extern uint si_flag_alt(si_t *sih);
246 extern uint si_intflag(si_t *sih);
247 extern uint si_coreidx(si_t *sih);
248 extern uint si_coreunit(si_t *sih);
249 extern uint si_corevendor(si_t *sih);
250 extern uint si_corerev(si_t *sih);
251 extern uint si_corerev_minor(si_t *sih);
252 extern void *si_osh(si_t *sih);
253 extern void si_setosh(si_t *sih, osl_t *osh);
254 extern int si_backplane_access(si_t *sih, uint addr, uint size,
255 uint *val, bool read);
256 extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
257 extern uint si_corereg_writeonly(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
258 extern uint si_pmu_corereg(si_t *sih, uint32 idx, uint regoff, uint mask, uint val);
259 extern volatile uint32 *si_corereg_addr(si_t *sih, uint coreidx, uint regoff);
260 extern volatile void *si_coreregs(si_t *sih);
261 extern uint si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
262 extern uint si_core_wrapperreg(si_t *sih, uint32 coreidx, uint32 offset, uint32 mask, uint32 val);
263 extern void *si_wrapperregs(si_t *sih);
264 extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val);
265 extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
266 extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val);
267 extern void si_commit(si_t *sih);
268 extern bool si_iscoreup(si_t *sih);
269 extern uint si_numcoreunits(si_t *sih, uint coreid);
270 extern uint si_numd11coreunits(si_t *sih);
271 extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
272 extern volatile void *si_setcoreidx(si_t *sih, uint coreidx);
273 extern volatile void *si_setcore(si_t *sih, uint coreid, uint coreunit);
274 extern uint32 si_oobr_baseaddr(si_t *sih, bool second);
275 extern volatile void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val);
276 extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
277 extern int si_numaddrspaces(si_t *sih);
278 extern uint32 si_addrspace(si_t *sih, uint spidx, uint baidx);
279 extern uint32 si_addrspacesize(si_t *sih, uint spidx, uint baidx);
280 extern void si_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size);
281 extern int si_corebist(si_t *sih);
282 extern void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
283 extern void si_core_disable(si_t *sih, uint32 bits);
284 extern uint32 si_clock_rate(uint32 pll_type, uint32 n, uint32 m);
285 extern uint si_chip_hostif(si_t *sih);
286 extern uint32 si_clock(si_t *sih);
287 extern uint32 si_alp_clock(si_t *sih); /* returns [Hz] units */
288 extern uint32 si_ilp_clock(si_t *sih); /* returns [Hz] units */
289 extern void si_pci_setup(si_t *sih, uint coremask);
290 extern void si_pcmcia_init(si_t *sih);
291 extern void si_setint(si_t *sih, int siflag);
292 extern bool si_backplane64(si_t *sih);
293 extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,
294 void *intrsenabled_fn, void *intr_arg);
295 extern void si_deregister_intr_callback(si_t *sih);
296 extern void si_clkctl_init(si_t *sih);
297 extern uint16 si_clkctl_fast_pwrup_delay(si_t *sih);
298 extern bool si_clkctl_cc(si_t *sih, uint mode);
299 extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
300 extern uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 val);
301 extern void si_btcgpiowar(si_t *sih);
302 extern bool si_deviceremoved(si_t *sih);
303 extern void si_set_device_removed(si_t *sih, bool status);
304 extern uint32 si_sysmem_size(si_t *sih);
305 extern uint32 si_socram_size(si_t *sih);
306 extern uint32 si_socdevram_size(si_t *sih);
307 extern uint32 si_socram_srmem_size(si_t *sih);
308 extern void si_socram_set_bankpda(si_t *sih, uint32 bankidx, uint32 bankpda);
309 extern void si_socdevram(si_t *sih, bool set, uint8 *ennable, uint8 *protect, uint8 *remap);
310 extern bool si_socdevram_pkg(si_t *sih);
311 extern bool si_socdevram_remap_isenb(si_t *sih);
312 extern uint32 si_socdevram_remap_size(si_t *sih);
313
314 extern void si_watchdog(si_t *sih, uint ticks);
315 extern void si_watchdog_ms(si_t *sih, uint32 ms);
316 extern uint32 si_watchdog_msticks(void);
317 extern volatile void *si_gpiosetcore(si_t *sih);
318 extern uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority);
319 extern uint32 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority);
320 extern uint32 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority);
321 extern uint32 si_gpioin(si_t *sih);
322 extern uint32 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority);
323 extern uint32 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority);
324 extern uint32 si_gpioeventintmask(si_t *sih, uint32 mask, uint32 val, uint8 priority);
325 extern uint32 si_gpioled(si_t *sih, uint32 mask, uint32 val);
326 extern uint32 si_gpioreserve(si_t *sih, uint32 gpio_num, uint8 priority);
327 extern uint32 si_gpiorelease(si_t *sih, uint32 gpio_num, uint8 priority);
328 extern uint32 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val);
329 extern uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val);
330 extern uint32 si_gpio_int_enable(si_t *sih, bool enable);
331 extern void si_gci_uart_init(si_t *sih, osl_t *osh, uint8 seci_mode);
332 extern void si_gci_enable_gpio(si_t *sih, uint8 gpio, uint32 mask, uint32 value);
333 extern uint8 si_gci_host_wake_gpio_init(si_t *sih);
334 extern uint8 si_gci_time_sync_gpio_init(si_t *sih);
335 extern void si_gci_host_wake_gpio_enable(si_t *sih, uint8 gpio, bool state);
336 extern void si_gci_time_sync_gpio_enable(si_t *sih, uint8 gpio, bool state);
337
338 extern void si_invalidate_second_bar0win(si_t *sih);
339
340 extern void si_gci_shif_config_wake_pin(si_t *sih, uint8 gpio_n,
341 uint8 wake_events, bool gci_gpio);
342 extern void si_shif_int_enable(si_t *sih, uint8 gpio_n, uint8 wake_events, bool enable);
343
344 /* GCI interrupt handlers */
345 extern void si_gci_handler_process(si_t *sih);
346
347 extern void si_enable_gpio_wake(si_t *sih, uint8 *wake_mask, uint8 *cur_status, uint8 gci_gpio,
348 uint32 pmu_cc2_mask, uint32 pmu_cc2_value);
349
350 /* GCI GPIO event handlers */
351 extern void *si_gci_gpioint_handler_register(si_t *sih, uint8 gpio, uint8 sts,
352 gci_gpio_handler_t cb, void *arg);
353 extern void si_gci_gpioint_handler_unregister(si_t *sih, void* gci_i);
354
355 extern uint8 si_gci_gpio_status(si_t *sih, uint8 gci_gpio, uint8 mask, uint8 value);
356 extern void si_gci_config_wake_pin(si_t *sih, uint8 gpio_n, uint8 wake_events,
357 bool gci_gpio);
358 extern void si_gci_free_wake_pin(si_t *sih, uint8 gpio_n);
359
360 /* Wake-on-wireless-LAN (WOWL) */
361 extern bool si_pci_pmecap(si_t *sih);
362 extern bool si_pci_fastpmecap(struct osl_info *osh);
363 extern bool si_pci_pmestat(si_t *sih);
364 extern void si_pci_pmeclr(si_t *sih);
365 extern void si_pci_pmeen(si_t *sih);
366 extern void si_pci_pmestatclr(si_t *sih);
367 extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset);
368 extern uint si_pcie_writereg(void *sih, uint addrtype, uint offset, uint val);
369 extern void si_deepsleep_count(si_t *sih, bool arm_wakeup);
370
371 #ifdef BCMSDIO
372 extern void si_sdio_init(si_t *sih);
373 extern void *si_get_sdio_addrbase(void *sdh);
374 #endif // endif
375
376 extern uint16 si_d11_devid(si_t *sih);
377 extern int si_corepciid(si_t *sih, uint func, uint16 *pcivendor, uint16 *pcidevice,
378 uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif, uint8 *pciheader);
379
380 extern uint32 si_seci_access(si_t *sih, uint32 val, int access);
381 extern volatile void* si_seci_init(si_t *sih, uint8 seci_mode);
382 extern void si_seci_clk_force(si_t *sih, bool val);
383 extern bool si_seci_clk_force_status(si_t *sih);
384
385 #define si_eci(sih) 0
si_eci_init(si_t * sih)386 static INLINE void * si_eci_init(si_t *sih) {return NULL;}
387 #define si_eci_notify_bt(sih, type, val) (0)
388 #define si_seci(sih) 0
389 #define si_seci_upd(sih, a) do {} while (0)
si_gci_init(si_t * sih)390 static INLINE void * si_gci_init(si_t *sih) {return NULL;}
391 #define si_seci_down(sih) do {} while (0)
392 #define si_gci(sih) 0
393
394 /* OTP status */
395 extern bool si_is_otp_disabled(si_t *sih);
396 extern bool si_is_otp_powered(si_t *sih);
397 extern void si_otp_power(si_t *sih, bool on, uint32* min_res_mask);
398
399 /* SPROM availability */
400 extern bool si_is_sprom_available(si_t *sih);
401
402 /* OTP/SROM CIS stuff */
403 extern int si_cis_source(si_t *sih);
404 #define CIS_DEFAULT 0
405 #define CIS_SROM 1
406 #define CIS_OTP 2
407
408 /* Fab-id information */
409 #define DEFAULT_FAB 0x0 /**< Original/first fab used for this chip */
410 #define CSM_FAB7 0x1 /**< CSM Fab7 chip */
411 #define TSMC_FAB12 0x2 /**< TSMC Fab12/Fab14 chip */
412 #define SMIC_FAB4 0x3 /**< SMIC Fab4 chip */
413
414 extern uint16 si_fabid(si_t *sih);
415 extern uint16 si_chipid(si_t *sih);
416
417 /*
418 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
419 * The returned path is NULL terminated and has trailing '/'.
420 * Return 0 on success, nonzero otherwise.
421 */
422 extern int si_devpath(si_t *sih, char *path, int size);
423 extern int si_devpath_pcie(si_t *sih, char *path, int size);
424 /* Read variable with prepending the devpath to the name */
425 extern char *si_getdevpathvar(si_t *sih, const char *name);
426 extern int si_getdevpathintvar(si_t *sih, const char *name);
427 extern char *si_coded_devpathvar(si_t *sih, char *varname, int var_len, const char *name);
428
429 extern uint8 si_pcieclkreq(si_t *sih, uint32 mask, uint32 val);
430 extern uint32 si_pcielcreg(si_t *sih, uint32 mask, uint32 val);
431 extern uint8 si_pcieltrenable(si_t *sih, uint32 mask, uint32 val);
432 extern uint8 si_pcieobffenable(si_t *sih, uint32 mask, uint32 val);
433 extern uint32 si_pcieltr_reg(si_t *sih, uint32 reg, uint32 mask, uint32 val);
434 extern uint32 si_pcieltrspacing_reg(si_t *sih, uint32 mask, uint32 val);
435 extern uint32 si_pcieltrhysteresiscnt_reg(si_t *sih, uint32 mask, uint32 val);
436 extern void si_pcie_set_error_injection(si_t *sih, uint32 mode);
437 extern void si_pcie_set_L1substate(si_t *sih, uint32 substate);
438 extern uint32 si_pcie_get_L1substate(si_t *sih);
439 extern void si_war42780_clkreq(si_t *sih, bool clkreq);
440 extern void si_pci_down(si_t *sih);
441 extern void si_pci_up(si_t *sih);
442 extern void si_pci_sleep(si_t *sih);
443 extern void si_pcie_war_ovr_update(si_t *sih, uint8 aspm);
444 extern void si_pcie_power_save_enable(si_t *sih, bool enable);
445 extern void si_pcie_extendL1timer(si_t *sih, bool extend);
446 extern int si_pci_fixcfg(si_t *sih);
447 extern void si_chippkg_set(si_t *sih, uint);
448 extern bool si_is_warmboot(void);
449
450 extern void si_chipcontrl_restore(si_t *sih, uint32 val);
451 extern uint32 si_chipcontrl_read(si_t *sih);
452 extern void si_chipcontrl_srom4360(si_t *sih, bool on);
453 extern void si_srom_clk_set(si_t *sih); /**< for chips with fast BP clock */
454 extern void si_btc_enable_chipcontrol(si_t *sih);
455 extern void si_pmu_avb_clk_set(si_t *sih, osl_t *osh, bool set_flag);
456 /* === debug routines === */
457
458 extern bool si_taclear(si_t *sih, bool details);
459
460 #if defined(BCMDBG_PHYDUMP)
461 struct bcmstrbuf;
462 extern int si_dump_pcieinfo(si_t *sih, struct bcmstrbuf *b);
463 extern void si_dump_pmuregs(si_t *sih, struct bcmstrbuf *b);
464 extern int si_dump_pcieregs(si_t *sih, struct bcmstrbuf *b);
465 #endif // endif
466
467 #if defined(BCMDBG_PHYDUMP)
468 extern void si_dumpregs(si_t *sih, struct bcmstrbuf *b);
469 #endif // endif
470
471 extern uint32 si_ccreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
472 extern uint32 si_pciereg(si_t *sih, uint32 offset, uint32 mask, uint32 val, uint type);
473 extern int si_bpind_access(si_t *sih, uint32 addr_high, uint32 addr_low,
474 int32* data, bool read);
475 #ifdef SR_DEBUG
476 extern void si_dump_pmu(si_t *sih, void *pmu_var);
477 extern void si_pmu_keep_on(si_t *sih, int32 int_val);
478 extern uint32 si_pmu_keep_on_get(si_t *sih);
479 extern uint32 si_power_island_set(si_t *sih, uint32 int_val);
480 extern uint32 si_power_island_get(si_t *sih);
481 #endif /* SR_DEBUG */
482 extern uint32 si_pcieserdesreg(si_t *sih, uint32 mdioslave, uint32 offset, uint32 mask, uint32 val);
483 extern void si_pcie_set_request_size(si_t *sih, uint16 size);
484 extern uint16 si_pcie_get_request_size(si_t *sih);
485 extern void si_pcie_set_maxpayload_size(si_t *sih, uint16 size);
486 extern uint16 si_pcie_get_maxpayload_size(si_t *sih);
487 extern uint16 si_pcie_get_ssid(si_t *sih);
488 extern uint32 si_pcie_get_bar0(si_t *sih);
489 extern int si_pcie_configspace_cache(si_t *sih);
490 extern int si_pcie_configspace_restore(si_t *sih);
491 extern int si_pcie_configspace_get(si_t *sih, uint8 *buf, uint size);
492
493 #ifdef BCM_BACKPLANE_TIMEOUT
494 extern const si_axi_error_info_t * si_get_axi_errlog_info(si_t *sih);
495 extern void si_reset_axi_errlog_info(si_t * sih);
496 #endif /* BCM_BACKPLANE_TIMEOUT */
497
498 extern void si_update_backplane_timeouts(si_t *sih, bool enable, uint32 timeout, uint32 cid);
499
500 extern uint32 si_tcm_size(si_t *sih);
501 extern bool si_has_flops(si_t *sih);
502
503 extern int si_set_sromctl(si_t *sih, uint32 value);
504 extern uint32 si_get_sromctl(si_t *sih);
505
506 extern uint32 si_gci_direct(si_t *sih, uint offset, uint32 mask, uint32 val);
507 extern uint32 si_gci_indirect(si_t *sih, uint regidx, uint offset, uint32 mask, uint32 val);
508 extern uint32 si_gci_output(si_t *sih, uint reg, uint32 mask, uint32 val);
509 extern uint32 si_gci_input(si_t *sih, uint reg);
510 extern uint32 si_gci_int_enable(si_t *sih, bool enable);
511 extern void si_gci_reset(si_t *sih);
512 #ifdef BCMLTECOEX
513 extern void si_ercx_init(si_t *sih, uint32 ltecx_mux, uint32 ltecx_padnum,
514 uint32 ltecx_fnsel, uint32 ltecx_gcigpio);
515 #endif /* BCMLTECOEX */
516 extern void si_gci_seci_init(si_t *sih);
517 extern void si_wci2_init(si_t *sih, uint8 baudrate, uint32 ltecx_mux, uint32 ltecx_padnum,
518 uint32 ltecx_fnsel, uint32 ltecx_gcigpio, uint32 xtalfreq);
519
520 extern bool si_btcx_wci2_init(si_t *sih);
521
522 extern void si_gci_set_functionsel(si_t *sih, uint32 pin, uint8 fnsel);
523 extern uint32 si_gci_get_functionsel(si_t *sih, uint32 pin);
524 extern void si_gci_clear_functionsel(si_t *sih, uint8 fnsel);
525 extern uint8 si_gci_get_chipctrlreg_idx(uint32 pin, uint32 *regidx, uint32 *pos);
526 extern uint32 si_gci_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val);
527 extern uint32 si_gci_chipstatus(si_t *sih, uint reg);
528 extern uint8 si_enable_device_wake(si_t *sih, uint8 *wake_status, uint8 *cur_status);
529 extern uint8 si_get_device_wake_opt(si_t *sih);
530 extern void si_swdenable(si_t *sih, uint32 swdflag);
531 extern uint8 si_enable_perst_wake(si_t *sih, uint8 *perst_wake_mask, uint8 *perst_cur_status);
532
533 extern uint32 si_get_pmu_reg_addr(si_t *sih, uint32 offset);
534 #define CHIPCTRLREG1 0x1
535 #define CHIPCTRLREG2 0x2
536 #define CHIPCTRLREG3 0x3
537 #define CHIPCTRLREG4 0x4
538 #define CHIPCTRLREG5 0x5
539 #define MINRESMASKREG 0x618
540 #define MAXRESMASKREG 0x61c
541 #define CHIPCTRLADDR 0x650
542 #define CHIPCTRLDATA 0x654
543 #define RSRCTABLEADDR 0x620
544 #define RSRCUPDWNTIME 0x628
545 #define PMUREG_RESREQ_MASK 0x68c
546
547 void si_update_masks(si_t *sih);
548 void si_force_islanding(si_t *sih, bool enable);
549 extern uint32 si_pmu_res_req_timer_clr(si_t *sih);
550 extern void si_pmu_rfldo(si_t *sih, bool on);
551 extern uint32 si_pcie_set_ctrlreg(si_t *sih, uint32 sperst_mask, uint32 spert_val);
552 extern void si_pcie_ltr_war(si_t *sih);
553 extern void si_pcie_hw_LTR_war(si_t *sih);
554 extern void si_pcie_hw_L1SS_war(si_t *sih);
555 extern void si_pciedev_crwlpciegen2(si_t *sih);
556 extern void si_pcie_prep_D3(si_t *sih, bool enter_D3);
557 extern void si_pciedev_reg_pm_clk_period(si_t *sih);
558 extern void si_d11rsdb_core1_alt_reg_clk_dis(si_t *sih);
559 extern void si_d11rsdb_core1_alt_reg_clk_en(si_t *sih);
560 extern void si_pcie_disable_oobselltr(si_t *sih);
561 extern uint32 si_raw_reg(si_t *sih, uint32 reg, uint32 val, uint32 wrire_req);
562
563 #ifdef WLRSDB
564 extern void si_d11rsdb_core_disable(si_t *sih, uint32 bits);
565 extern void si_d11rsdb_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
566 extern void set_secondary_d11_core(si_t *sih, volatile void **secmap, volatile void **secwrap);
567 #endif // endif
568
569 /* Macro to enable clock gating changes in different cores */
570 #define MEM_CLK_GATE_BIT 5
571 #define GCI_CLK_GATE_BIT 18
572
573 #define USBAPP_CLK_BIT 0
574 #define PCIE_CLK_BIT 3
575 #define ARMCR4_DBG_CLK_BIT 4
576 #define SAMPLE_SYNC_CLK_BIT 17
577 #define PCIE_TL_CLK_BIT 18
578 #define HQ_REQ_BIT 24
579 #define PLL_DIV2_BIT_START 9
580 #define PLL_DIV2_MASK (0x37 << PLL_DIV2_BIT_START)
581 #define PLL_DIV2_DIS_OP (0x37 << PLL_DIV2_BIT_START)
582
583 #define pmu_corereg(si, cc_idx, member, mask, val) \
584 (AOB_ENAB(si) ? \
585 si_pmu_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \
586 OFFSETOF(pmuregs_t, member), mask, val): \
587 si_pmu_corereg(si, cc_idx, OFFSETOF(chipcregs_t, member), mask, val))
588
589 /* Used only for the regs present in the pmu core and not present in the old cc core */
590 #define PMU_REG_NEW(si, member, mask, val) \
591 si_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \
592 OFFSETOF(pmuregs_t, member), mask, val)
593
594 #define PMU_REG(si, member, mask, val) \
595 (AOB_ENAB(si) ? \
596 si_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \
597 OFFSETOF(pmuregs_t, member), mask, val): \
598 si_corereg(si, SI_CC_IDX, OFFSETOF(chipcregs_t, member), mask, val))
599
600 /* Used only for the regs present in the pmu core and not present in the old cc core */
601 #define PMU_REG_NEW(si, member, mask, val) \
602 si_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \
603 OFFSETOF(pmuregs_t, member), mask, val)
604
605 #define GCI_REG(si, offset, mask, val) \
606 (AOB_ENAB(si) ? \
607 si_corereg(si, si_findcoreidx(si, GCI_CORE_ID, 0), \
608 offset, mask, val): \
609 si_corereg(si, SI_CC_IDX, offset, mask, val))
610
611 /* Used only for the regs present in the gci core and not present in the old cc core */
612 #define GCI_REG_NEW(si, member, mask, val) \
613 si_corereg(si, si_findcoreidx(si, GCI_CORE_ID, 0), \
614 OFFSETOF(gciregs_t, member), mask, val)
615
616 #define LHL_REG(si, member, mask, val) \
617 si_corereg(si, si_findcoreidx(si, GCI_CORE_ID, 0), \
618 OFFSETOF(gciregs_t, member), mask, val)
619
620 #define CHIPC_REG(si, member, mask, val) \
621 si_corereg(si, SI_CC_IDX, OFFSETOF(chipcregs_t, member), mask, val)
622
623 /* GCI Macros */
624 #define ALLONES_32 0xFFFFFFFF
625 #define GCI_CCTL_SECIRST_OFFSET 0 /**< SeciReset */
626 #define GCI_CCTL_RSTSL_OFFSET 1 /**< ResetSeciLogic */
627 #define GCI_CCTL_SECIEN_OFFSET 2 /**< EnableSeci */
628 #define GCI_CCTL_FSL_OFFSET 3 /**< ForceSeciOutLow */
629 #define GCI_CCTL_SMODE_OFFSET 4 /**< SeciOpMode, 6:4 */
630 #define GCI_CCTL_US_OFFSET 7 /**< UpdateSeci */
631 #define GCI_CCTL_BRKONSLP_OFFSET 8 /**< BreakOnSleep */
632 #define GCI_CCTL_SILOWTOUT_OFFSET 9 /**< SeciInLowTimeout, 10:9 */
633 #define GCI_CCTL_RSTOCC_OFFSET 11 /**< ResetOffChipCoex */
634 #define GCI_CCTL_ARESEND_OFFSET 12 /**< AutoBTSigResend */
635 #define GCI_CCTL_FGCR_OFFSET 16 /**< ForceGciClkReq */
636 #define GCI_CCTL_FHCRO_OFFSET 17 /**< ForceHWClockReqOff */
637 #define GCI_CCTL_FREGCLK_OFFSET 18 /**< ForceRegClk */
638 #define GCI_CCTL_FSECICLK_OFFSET 19 /**< ForceSeciClk */
639 #define GCI_CCTL_FGCA_OFFSET 20 /**< ForceGciClkAvail */
640 #define GCI_CCTL_FGCAV_OFFSET 21 /**< ForceGciClkAvailValue */
641 #define GCI_CCTL_SCS_OFFSET 24 /**< SeciClkStretch, 31:24 */
642 #define GCI_CCTL_SCS 25 /* SeciClkStretch */
643
644 #define GCI_MODE_UART 0x0
645 #define GCI_MODE_SECI 0x1
646 #define GCI_MODE_BTSIG 0x2
647 #define GCI_MODE_GPIO 0x3
648 #define GCI_MODE_MASK 0x7
649
650 #define GCI_CCTL_LOWTOUT_DIS 0x0
651 #define GCI_CCTL_LOWTOUT_10BIT 0x1
652 #define GCI_CCTL_LOWTOUT_20BIT 0x2
653 #define GCI_CCTL_LOWTOUT_30BIT 0x3
654 #define GCI_CCTL_LOWTOUT_MASK 0x3
655
656 #define GCI_CCTL_SCS_DEF 0x19
657 #define GCI_CCTL_SCS_MASK 0xFF
658
659 #define GCI_SECIIN_MODE_OFFSET 0
660 #define GCI_SECIIN_GCIGPIO_OFFSET 4
661 #define GCI_SECIIN_RXID2IP_OFFSET 8
662
663 #define GCI_SECIIN_MODE_MASK 0x7
664 #define GCI_SECIIN_GCIGPIO_MASK 0xF
665
666 #define GCI_SECIOUT_MODE_OFFSET 0
667 #define GCI_SECIOUT_GCIGPIO_OFFSET 4
668 #define GCI_SECIOUT_LOOPBACK_OFFSET 8
669 #define GCI_SECIOUT_SECIINRELATED_OFFSET 16
670
671 #define GCI_SECIOUT_MODE_MASK 0x7
672 #define GCI_SECIOUT_GCIGPIO_MASK 0xF
673 #define GCI_SECIOUT_SECIINRELATED_MASK 0x1
674
675 #define GCI_SECIOUT_SECIINRELATED 0x1
676
677 #define GCI_SECIAUX_RXENABLE_OFFSET 0
678 #define GCI_SECIFIFO_RXENABLE_OFFSET 16
679
680 #define GCI_SECITX_ENABLE_OFFSET 0
681
682 #define GCI_GPIOCTL_INEN_OFFSET 0
683 #define GCI_GPIOCTL_OUTEN_OFFSET 1
684 #define GCI_GPIOCTL_PDN_OFFSET 4
685
686 #define GCI_GPIOIDX_OFFSET 16
687
688 #define GCI_LTECX_SECI_ID 0 /**< SECI port for LTECX */
689 #define GCI_LTECX_TXCONF_EN_OFFSET 2
690 #define GCI_LTECX_PRISEL_EN_OFFSET 3
691
692 /* To access per GCI bit registers */
693 #define GCI_REG_WIDTH 32
694
695 /* number of event summary bits */
696 #define GCI_EVENT_NUM_BITS 32
697
698 /* gci event bits per core */
699 #define GCI_EVENT_BITS_PER_CORE 4
700 #define GCI_EVENT_HWBIT_1 1
701 #define GCI_EVENT_HWBIT_2 2
702 #define GCI_EVENT_SWBIT_1 3
703 #define GCI_EVENT_SWBIT_2 4
704
705 #define GCI_MBDATA_TOWLAN_POS 96
706 #define GCI_MBACK_TOWLAN_POS 104
707 #define GCI_WAKE_TOWLAN_PO 112
708 #define GCI_SWREADY_POS 120
709
710 /* GCI bit positions */
711 /* GCI [127:000] = WLAN [127:0] */
712 #define GCI_WLAN_IP_ID 0
713 #define GCI_WLAN_BEGIN 0
714 #define GCI_WLAN_PRIO_POS (GCI_WLAN_BEGIN + 4)
715 #define GCI_WLAN_PERST_POS (GCI_WLAN_BEGIN + 15)
716
717 /* GCI [255:128] = BT [127:0] */
718 #define GCI_BT_IP_ID 1
719 #define GCI_BT_BEGIN 128
720 #define GCI_BT_MBDATA_TOWLAN_POS (GCI_BT_BEGIN + GCI_MBDATA_TOWLAN_POS)
721 #define GCI_BT_MBACK_TOWLAN_POS (GCI_BT_BEGIN + GCI_MBACK_TOWLAN_POS)
722 #define GCI_BT_WAKE_TOWLAN_POS (GCI_BT_BEGIN + GCI_WAKE_TOWLAN_PO)
723 #define GCI_BT_SWREADY_POS (GCI_BT_BEGIN + GCI_SWREADY_POS)
724
725 /* GCI [639:512] = LTE [127:0] */
726 #define GCI_LTE_IP_ID 4
727 #define GCI_LTE_BEGIN 512
728 #define GCI_LTE_FRAMESYNC_POS (GCI_LTE_BEGIN + 0)
729 #define GCI_LTE_RX_POS (GCI_LTE_BEGIN + 1)
730 #define GCI_LTE_TX_POS (GCI_LTE_BEGIN + 2)
731 #define GCI_LTE_WCI2TYPE_POS (GCI_LTE_BEGIN + 48)
732 #define GCI_LTE_WCI2TYPE_MASK 7
733 #define GCI_LTE_AUXRXDVALID_POS (GCI_LTE_BEGIN + 56)
734
735 /* Reg Index corresponding to ECI bit no x of ECI space */
736 #define GCI_REGIDX(x) ((x)/GCI_REG_WIDTH)
737 /* Bit offset of ECI bit no x in 32-bit words */
738 #define GCI_BITOFFSET(x) ((x)%GCI_REG_WIDTH)
739
740 /* BT SMEM Control Register 0 */
741 #define GCI_BT_SMEM_CTRL0_SUBCORE_ENABLE_PKILL (1 << 28)
742
743 /* End - GCI Macros */
744
745 #define AXI_OOB 0x7
746
747 extern void si_pll_sr_reinit(si_t *sih);
748 extern void si_pll_closeloop(si_t *sih);
749 void si_config_4364_d11_oob(si_t *sih, uint coreid);
750 extern void si_gci_set_femctrl(si_t *sih, osl_t *osh, bool set);
751 extern void si_gci_set_femctrl_mask_ant01(si_t *sih, osl_t *osh, bool set);
752 extern uint si_num_slaveports(si_t *sih, uint coreid);
753 extern uint32 si_get_slaveport_addr(si_t *sih, uint spidx, uint baidx,
754 uint core_id, uint coreunit);
755 extern uint32 si_get_d11_slaveport_addr(si_t *sih, uint spidx,
756 uint baidx, uint coreunit);
757 uint si_introff(si_t *sih);
758 void si_intrrestore(si_t *sih, uint intr_val);
759 void si_nvram_res_masks(si_t *sih, uint32 *min_mask, uint32 *max_mask);
760 extern uint32 si_xtalfreq(si_t *sih);
761 extern uint8 si_getspurmode(si_t *sih);
762 extern uint32 si_get_openloop_dco_code(si_t *sih);
763 extern void si_set_openloop_dco_code(si_t *sih, uint32 openloop_dco_code);
764 extern uint32 si_wrapper_dump_buf_size(si_t *sih);
765 extern uint32 si_wrapper_dump_binary(si_t *sih, uchar *p);
766 extern uint32 si_wrapper_dump_last_timeout(si_t *sih, uint32 *error, uint32 *core, uint32 *ba,
767 uchar *p);
768
769 /* SR Power Control */
770 extern uint32 si_srpwr_request(si_t *sih, uint32 mask, uint32 val);
771 extern uint32 si_srpwr_stat_spinwait(si_t *sih, uint32 mask, uint32 val);
772 extern uint32 si_srpwr_stat(si_t *sih);
773 extern uint32 si_srpwr_domain(si_t *sih);
774 extern uint32 si_srpwr_domain_all_mask(si_t *sih);
775
776 /* SR Power Control */
777 /* No capabilities bit so using chipid for now */
778 #define SRPWR_CAP(sih) (BCM4347_CHIP(sih->chip) || BCM4369_CHIP(sih->chip))
779
780 #ifdef BCMSRPWR
781 extern bool _bcmsrpwr;
782 #if defined(ROM_ENAB_RUNTIME_CHECK) || !defined(DONGLEBUILD)
783 #define SRPWR_ENAB() (_bcmsrpwr)
784 #elif defined(BCMSRPWR_DISABLED)
785 #define SRPWR_ENAB() (0)
786 #else
787 #define SRPWR_ENAB() (1)
788 #endif
789 #else
790 #define SRPWR_ENAB() (0)
791 #endif /* BCMSRPWR */
792
793 /*
794 * Multi-BackPlane architecture. Each can power up/down independently.
795 * Common backplane: shared between BT and WL
796 * ChipC, PCIe, GCI, PMU, SRs
797 * HW powers up as needed
798 * WL BackPlane (WLBP):
799 * ARM, TCM, Main, Aux
800 * Host needs to power up
801 */
802 #ifdef CHIPS_CUSTOMER_HW6
803 #define MULTIBP_CAP(sih) (BCM4368_CHIP(sih->chip) || BCM4378_CHIP(sih->chip) || \
804 BCM4387_CHIP(sih->chip))
805 #else /* !CHIPS_CUSTOMER_HW6 */
806 #define MULTIBP_CAP(sih) (FALSE)
807 #endif /* CHIPS_CUSTOMER_HW6 */
808 #define MULTIBP_ENAB(sih) ((sih) && (sih)->_multibp_enable)
809
810 uint32 si_enum_base(uint devid);
811 uint32 si_pcie_enum_base(uint devid);
812
813 extern uint8 si_lhl_ps_mode(si_t *sih);
814
815 #ifdef UART_TRAP_DBG
816 void ai_dump_APB_Bridge_registers(si_t *sih);
817 #endif /* UART_TRAP_DBG */
818
819 void si_clrirq_idx(si_t *sih, uint core_idx);
820
821 /* return if scan core is present */
822 bool si_scan_core_present(si_t *sih);
823
824 #endif /* _siutils_h_ */
825