1 /* 2 * Structure used by apps whose drivers access SDIO drivers. 3 * Pulled out separately so dhdu and wlu can both use it. 4 * 5 * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation 6 * 7 * Copyright (C) 1999-2017, Broadcom Corporation 8 * 9 * Unless you and Broadcom execute a separate written software license 10 * agreement governing use of this software, this software is licensed to you 11 * under the terms of the GNU General Public License version 2 (the "GPL"), 12 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 13 * following added to such license: 14 * 15 * As a special exception, the copyright holders of this software give you 16 * permission to link this software with independent modules, and to copy and 17 * distribute the resulting executable under terms of your choice, provided that 18 * you also meet, for each linked independent module, the terms and conditions of 19 * the license of that module. An independent module is a module which is not 20 * derived from this software. The special exception does not apply to any 21 * modifications of the software. 22 * 23 * Notwithstanding the above, under no circumstances may you combine this 24 * software in any way with any other Broadcom software provided under a license 25 * other than the GPL, without Broadcom's express prior written consent. 26 * 27 * 28 * <<Broadcom-WL-IPTag/Open:>> 29 * 30 * $Id: sdiovar.h 660496 2016-09-20 19:28:50Z $ 31 */ 32 33 #ifndef _sdiovar_h_ 34 #define _sdiovar_h_ 35 36 #include <typedefs.h> 37 38 typedef struct sdreg { 39 int func; 40 int offset; 41 int value; 42 } sdreg_t; 43 44 /* Common msglevel constants */ 45 #define SDH_ERROR_VAL 0x0001 /* Error */ 46 #define SDH_TRACE_VAL 0x0002 /* Trace */ 47 #define SDH_INFO_VAL 0x0004 /* Info */ 48 #define SDH_DEBUG_VAL 0x0008 /* Debug */ 49 #define SDH_DATA_VAL 0x0010 /* Data */ 50 #define SDH_CTRL_VAL 0x0020 /* Control Regs */ 51 #define SDH_LOG_VAL 0x0040 /* Enable bcmlog */ 52 #define SDH_DMA_VAL 0x0080 /* DMA */ 53 54 #define NUM_PREV_TRANSACTIONS 16 55 56 #ifdef BCMSPI 57 /* Error statistics for gSPI */ 58 struct spierrstats_t { 59 uint32 dna; /* The requested data is not available. */ 60 uint32 rdunderflow; /* FIFO underflow happened due to current (F2, F3) rd command */ 61 uint32 wroverflow; /* FIFO underflow happened due to current (F1, F2, F3) wr command */ 62 63 uint32 f2interrupt; /* OR of all F2 related intr status bits. */ 64 uint32 f3interrupt; /* OR of all F3 related intr status bits. */ 65 66 uint32 f2rxnotready; /* F2 FIFO is not ready to receive data (FIFO empty) */ 67 uint32 f3rxnotready; /* F3 FIFO is not ready to receive data (FIFO empty) */ 68 69 uint32 hostcmddataerr; /* Error in command or host data, detected by CRC/checksum 70 * (optional) 71 */ 72 uint32 f2pktavailable; /* Packet is available in F2 TX FIFO */ 73 uint32 f3pktavailable; /* Packet is available in F2 TX FIFO */ 74 75 uint32 dstatus[NUM_PREV_TRANSACTIONS]; /* dstatus bits of last 16 gSPI transactions */ 76 uint32 spicmd[NUM_PREV_TRANSACTIONS]; 77 }; 78 #endif /* BCMSPI */ 79 80 typedef struct sdio_bus_metrics { 81 uint32 active_dur; /* msecs */ 82 83 /* Generic */ 84 uint32 data_intr_cnt; /* data interrupt counter */ 85 uint32 mb_intr_cnt; /* mailbox interrupt counter */ 86 uint32 error_intr_cnt; /* error interrupt counter */ 87 uint32 wakehost_cnt; /* counter for OOB wakehost */ 88 89 /* DS forcewake */ 90 uint32 ds_wake_on_cnt; /* counter for (clock) ON */ 91 uint32 ds_wake_on_dur; /* duration for (clock) ON) */ 92 uint32 ds_wake_off_cnt; /* counter for (clock) OFF */ 93 uint32 ds_wake_off_dur; /* duration for (clock) OFF */ 94 95 /* DS_D0 state */ 96 uint32 ds_d0_cnt; /* counter for DS_D0 state */ 97 uint32 ds_d0_dur; /* duration for DS_D0 state */ 98 99 /* DS_D3 state */ 100 uint32 ds_d3_cnt; /* counter for DS_D3 state */ 101 uint32 ds_d3_dur; /* duration for DS_D3 state */ 102 103 /* DS DEV_WAKE */ 104 uint32 ds_dw_assrt_cnt; /* counter for DW_ASSERT */ 105 uint32 ds_dw_dassrt_cnt; /* counter for DW_DASSERT */ 106 107 /* DS mailbox signals */ 108 uint32 ds_tx_dsreq_cnt; /* counter for tx HMB_DATA_DSREQ */ 109 uint32 ds_tx_dsexit_cnt; /* counter for tx HMB_DATA_DSEXIT */ 110 uint32 ds_tx_d3ack_cnt; /* counter for tx HMB_DATA_D3ACK */ 111 uint32 ds_tx_d3exit_cnt; /* counter for tx HMB_DATA_D3EXIT */ 112 uint32 ds_rx_dsack_cnt; /* counter for rx SMB_DATA_DSACK */ 113 uint32 ds_rx_dsnack_cnt; /* counter for rx SMB_DATA_DSNACK */ 114 uint32 ds_rx_d3inform_cnt; /* counter for rx SMB_DATA_D3INFORM */ 115 } sdio_bus_metrics_t; 116 117 /* Bus interface info for SDIO */ 118 typedef struct wl_pwr_sdio_stats { 119 uint16 type; /* WL_PWRSTATS_TYPE_SDIO */ 120 uint16 len; /* Up to 4K-1, top 4 bits are reserved */ 121 122 sdio_bus_metrics_t sdio; /* stats from SDIO bus driver */ 123 } wl_pwr_sdio_stats_t; 124 125 #endif /* _sdiovar_h_ */ 126