1 /* 2 * SiliconBackplane System Memory core 3 * 4 * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation 5 * 6 * Copyright (C) 1999-2017, Broadcom Corporation 7 * 8 * Unless you and Broadcom execute a separate written software license 9 * agreement governing use of this software, this software is licensed to you 10 * under the terms of the GNU General Public License version 2 (the "GPL"), 11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12 * following added to such license: 13 * 14 * As a special exception, the copyright holders of this software give you 15 * permission to link this software with independent modules, and to copy and 16 * distribute the resulting executable under terms of your choice, provided that 17 * you also meet, for each linked independent module, the terms and conditions of 18 * the license of that module. An independent module is a module which is not 19 * derived from this software. The special exception does not apply to any 20 * modifications of the software. 21 * 22 * Notwithstanding the above, under no circumstances may you combine this 23 * software in any way with any other Broadcom software provided under a license 24 * other than the GPL, without Broadcom's express prior written consent. 25 * 26 * 27 * <<Broadcom-WL-IPTag/Open:>> 28 * 29 * $Id: sbsysmem.h 563229 2015-06-12 04:50:06Z $ 30 */ 31 32 #ifndef _SBSYSMEM_H 33 #define _SBSYSMEM_H 34 35 #ifndef _LANGUAGE_ASSEMBLY 36 37 /* cpp contortions to concatenate w/arg prescan */ 38 #ifndef PAD 39 #define _PADLINE(line) pad ## line 40 #define _XSTR(line) _PADLINE(line) 41 #define PAD _XSTR(__LINE__) 42 #endif /* PAD */ 43 44 /* sysmem core registers */ 45 typedef volatile struct sysmemregs { 46 uint32 coreinfo; 47 uint32 bwalloc; 48 uint32 extracoreinfo; 49 uint32 biststat; 50 uint32 bankidx; 51 uint32 standbyctrl; 52 53 uint32 errlogstatus; 54 uint32 errlogaddr; 55 56 uint32 cambankidx; 57 uint32 cambankstandbyctrl; 58 uint32 cambankpatchctrl; 59 uint32 cambankpatchtblbaseaddr; 60 uint32 cambankcmdreg; 61 uint32 cambankdatareg; 62 uint32 cambankmaskreg; 63 uint32 PAD[1]; 64 uint32 bankinfo; 65 uint32 PAD[15]; 66 uint32 extmemconfig; 67 uint32 extmemparitycsr; 68 uint32 extmemparityerrdata; 69 uint32 extmemparityerrcnt; 70 uint32 extmemwrctrlandsize; 71 uint32 PAD[84]; 72 uint32 workaround; 73 uint32 pwrctl; 74 uint32 PAD[133]; 75 uint32 sr_control; 76 uint32 sr_status; 77 uint32 sr_address; 78 uint32 sr_data; 79 } sysmemregs_t; 80 81 #endif /* _LANGUAGE_ASSEMBLY */ 82 83 /* Register offsets */ 84 #define SR_COREINFO 0x00 85 #define SR_BWALLOC 0x04 86 #define SR_BISTSTAT 0x0c 87 #define SR_BANKINDEX 0x10 88 #define SR_BANKSTBYCTL 0x14 89 #define SR_PWRCTL 0x1e8 90 91 /* Coreinfo register */ 92 #define SRCI_PT_MASK 0x00070000 /* port type[18:16] */ 93 #define SRCI_PT_SHIFT 16 94 /* port types : SRCI_PT_<processorPT>_<backplanePT> */ 95 #define SRCI_PT_OCP_OCP 0 96 #define SRCI_PT_AXI_OCP 1 97 #define SRCI_PT_ARM7AHB_OCP 2 98 #define SRCI_PT_CM3AHB_OCP 3 99 #define SRCI_PT_AXI_AXI 4 100 #define SRCI_PT_AHB_AXI 5 101 102 #define SRCI_LSS_MASK 0x00f00000 103 #define SRCI_LSS_SHIFT 20 104 #define SRCI_LRS_MASK 0x0f000000 105 #define SRCI_LRS_SHIFT 24 106 107 /* In corerev 0, the memory size is 2 to the power of the 108 * base plus 16 plus to the contents of the memsize field plus 1. 109 */ 110 #define SRCI_MS0_MASK 0xf 111 #define SR_MS0_BASE 16 112 113 /* 114 * In corerev 1 the bank size is 2 ^ the bank size field plus 14, 115 * the memory size is number of banks times bank size. 116 * The same applies to rom size. 117 */ 118 #define SYSMEM_SRCI_ROMNB_MASK 0x3e0 119 #define SYSMEM_SRCI_ROMNB_SHIFT 5 120 #define SYSMEM_SRCI_SRNB_MASK 0x1f 121 #define SYSMEM_SRCI_SRNB_SHIFT 0 122 123 /* Standby control register */ 124 #define SRSC_SBYOVR_MASK 0x80000000 125 #define SRSC_SBYOVR_SHIFT 31 126 #define SRSC_SBYOVRVAL_MASK 0x60000000 127 #define SRSC_SBYOVRVAL_SHIFT 29 128 #define SRSC_SBYEN_MASK 0x01000000 129 #define SRSC_SBYEN_SHIFT 24 130 131 /* Power control register */ 132 #define SRPC_PMU_STBYDIS_MASK 0x00000010 133 #define SRPC_PMU_STBYDIS_SHIFT 4 134 #define SRPC_STBYOVRVAL_MASK 0x00000008 135 #define SRPC_STBYOVRVAL_SHIFT 3 136 #define SRPC_STBYOVR_MASK 0x00000007 137 #define SRPC_STBYOVR_SHIFT 0 138 139 /* Extra core capability register */ 140 #define SRECC_NUM_BANKS_MASK 0x000000F0 141 #define SRECC_NUM_BANKS_SHIFT 4 142 #define SRECC_BANKSIZE_MASK 0x0000000F 143 #define SRECC_BANKSIZE_SHIFT 0 144 145 #define SRECC_BANKSIZE(value) (1 << (value)) 146 147 /* CAM bank patch control */ 148 #define SRCBPC_PATCHENABLE 0x80000000 149 150 #define SRP_ADDRESS 0x0001FFFC 151 #define SRP_VALID 0x8000 152 153 /* CAM bank command reg */ 154 #define SRCMD_WRITE 0x00020000 155 #define SRCMD_READ 0x00010000 156 #define SRCMD_DONE 0x80000000 157 158 #define SRCMD_DONE_DLY 1000 159 160 /* bankidx and bankinfo reg defines */ 161 #define SYSMEM_BANKINFO_SZMASK 0x7f 162 #define SYSMEM_BANKIDX_ROM_MASK 0x80 163 164 #define SYSMEM_BANKINFO_REG 0x40 165 #define SYSMEM_BANKIDX_REG 0x10 166 #define SYSMEM_BANKINFO_STDBY_MASK 0x200 167 #define SYSMEM_BANKINFO_STDBY_TIMER 0x400 168 169 #define SYSMEM_BANKINFO_SLPSUPP_SHIFT 14 170 #define SYSMEM_BANKINFO_SLPSUPP_MASK 0x4000 171 #define SYSMEM_BANKINFO_PDASZ_SHIFT 16 172 #define SYSMEM_BANKINFO_PDASZ_MASK 0x001F0000 173 174 /* extracoreinfo register */ 175 #define SYSMEM_DEVRAMBANK_MASK 0xF000 176 #define SYSMEM_DEVRAMBANK_SHIFT 12 177 178 /* bank info to calculate bank size */ 179 #define SYSMEM_BANKINFO_SZBASE 8192 180 #define SYSMEM_BANKSIZE_SHIFT 13 /* SYSMEM_BANKINFO_SZBASE */ 181 182 #endif /* _SBSYSMEM_H */ 183