1 /* 2 * BCM47XX Sonics SiliconBackplane embedded ram core 3 * 4 * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation 5 * 6 * Copyright (C) 1999-2017, Broadcom Corporation 7 * 8 * Unless you and Broadcom execute a separate written software license 9 * agreement governing use of this software, this software is licensed to you 10 * under the terms of the GNU General Public License version 2 (the "GPL"), 11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12 * following added to such license: 13 * 14 * As a special exception, the copyright holders of this software give you 15 * permission to link this software with independent modules, and to copy and 16 * distribute the resulting executable under terms of your choice, provided that 17 * you also meet, for each linked independent module, the terms and conditions of 18 * the license of that module. An independent module is a module which is not 19 * derived from this software. The special exception does not apply to any 20 * modifications of the software. 21 * 22 * Notwithstanding the above, under no circumstances may you combine this 23 * software in any way with any other Broadcom software provided under a license 24 * other than the GPL, without Broadcom's express prior written consent. 25 * 26 * 27 * <<Broadcom-WL-IPTag/Open:>> 28 * 29 * $Id: sbsocram.h 619629 2016-02-17 18:37:56Z $ 30 */ 31 32 #ifndef _SBSOCRAM_H 33 #define _SBSOCRAM_H 34 35 #ifndef _LANGUAGE_ASSEMBLY 36 37 /* cpp contortions to concatenate w/arg prescan */ 38 #ifndef PAD 39 #define _PADLINE(line) pad ## line 40 #define _XSTR(line) _PADLINE(line) 41 #define PAD _XSTR(__LINE__) 42 #endif /* PAD */ 43 44 /* Memcsocram core registers */ 45 typedef volatile struct sbsocramregs { 46 uint32 coreinfo; 47 uint32 bwalloc; 48 uint32 extracoreinfo; 49 uint32 biststat; 50 uint32 bankidx; 51 uint32 standbyctrl; 52 53 uint32 errlogstatus; /* rev 6 */ 54 uint32 errlogaddr; /* rev 6 */ 55 /* used for patching rev 3 & 5 */ 56 uint32 cambankidx; 57 uint32 cambankstandbyctrl; 58 uint32 cambankpatchctrl; 59 uint32 cambankpatchtblbaseaddr; 60 uint32 cambankcmdreg; 61 uint32 cambankdatareg; 62 uint32 cambankmaskreg; 63 uint32 PAD[1]; 64 uint32 bankinfo; /* corev 8 */ 65 uint32 bankpda; 66 uint32 PAD[14]; 67 uint32 extmemconfig; 68 uint32 extmemparitycsr; 69 uint32 extmemparityerrdata; 70 uint32 extmemparityerrcnt; 71 uint32 extmemwrctrlandsize; 72 uint32 PAD[84]; 73 uint32 workaround; 74 uint32 pwrctl; /* corerev >= 2 */ 75 uint32 PAD[133]; 76 uint32 sr_control; /* corerev >= 15 */ 77 uint32 sr_status; /* corerev >= 15 */ 78 uint32 sr_address; /* corerev >= 15 */ 79 uint32 sr_data; /* corerev >= 15 */ 80 } sbsocramregs_t; 81 82 #endif /* _LANGUAGE_ASSEMBLY */ 83 84 /* Register offsets */ 85 #define SR_COREINFO 0x00 86 #define SR_BWALLOC 0x04 87 #define SR_BISTSTAT 0x0c 88 #define SR_BANKINDEX 0x10 89 #define SR_BANKSTBYCTL 0x14 90 #define SR_PWRCTL 0x1e8 91 92 /* Coreinfo register */ 93 #define SRCI_PT_MASK 0x00070000 /* corerev >= 6; port type[18:16] */ 94 #define SRCI_PT_SHIFT 16 95 /* port types : SRCI_PT_<processorPT>_<backplanePT> */ 96 #define SRCI_PT_OCP_OCP 0 97 #define SRCI_PT_AXI_OCP 1 98 #define SRCI_PT_ARM7AHB_OCP 2 99 #define SRCI_PT_CM3AHB_OCP 3 100 #define SRCI_PT_AXI_AXI 4 101 #define SRCI_PT_AHB_AXI 5 102 /* corerev >= 3 */ 103 #define SRCI_LSS_MASK 0x00f00000 104 #define SRCI_LSS_SHIFT 20 105 #define SRCI_LRS_MASK 0x0f000000 106 #define SRCI_LRS_SHIFT 24 107 108 /* In corerev 0, the memory size is 2 to the power of the 109 * base plus 16 plus to the contents of the memsize field plus 1. 110 */ 111 #define SRCI_MS0_MASK 0xf 112 #define SR_MS0_BASE 16 113 114 /* 115 * In corerev 1 the bank size is 2 ^ the bank size field plus 14, 116 * the memory size is number of banks times bank size. 117 * The same applies to rom size. 118 */ 119 #define SRCI_ROMNB_MASK 0xf000 120 #define SRCI_ROMNB_SHIFT 12 121 #define SRCI_ROMBSZ_MASK 0xf00 122 #define SRCI_ROMBSZ_SHIFT 8 123 #define SRCI_SRNB_MASK 0xf0 124 #define SRCI_SRNB_SHIFT 4 125 #define SRCI_SRBSZ_MASK 0xf 126 #define SRCI_SRBSZ_SHIFT 0 127 128 #define SRCI_SRNB_MASK_EXT 0x100 129 130 #define SR_BSZ_BASE 14 131 132 /* Standby control register */ 133 #define SRSC_SBYOVR_MASK 0x80000000 134 #define SRSC_SBYOVR_SHIFT 31 135 #define SRSC_SBYOVRVAL_MASK 0x60000000 136 #define SRSC_SBYOVRVAL_SHIFT 29 137 #define SRSC_SBYEN_MASK 0x01000000 /* rev >= 3 */ 138 #define SRSC_SBYEN_SHIFT 24 139 140 /* Power control register */ 141 #define SRPC_PMU_STBYDIS_MASK 0x00000010 /* rev >= 3 */ 142 #define SRPC_PMU_STBYDIS_SHIFT 4 143 #define SRPC_STBYOVRVAL_MASK 0x00000008 144 #define SRPC_STBYOVRVAL_SHIFT 3 145 #define SRPC_STBYOVR_MASK 0x00000007 146 #define SRPC_STBYOVR_SHIFT 0 147 148 /* Extra core capability register */ 149 #define SRECC_NUM_BANKS_MASK 0x000000F0 150 #define SRECC_NUM_BANKS_SHIFT 4 151 #define SRECC_BANKSIZE_MASK 0x0000000F 152 #define SRECC_BANKSIZE_SHIFT 0 153 154 #define SRECC_BANKSIZE(value) (1 << (value)) 155 156 /* CAM bank patch control */ 157 #define SRCBPC_PATCHENABLE 0x80000000 158 159 #define SRP_ADDRESS 0x0001FFFC 160 #define SRP_VALID 0x8000 161 162 /* CAM bank command reg */ 163 #define SRCMD_WRITE 0x00020000 164 #define SRCMD_READ 0x00010000 165 #define SRCMD_DONE 0x80000000 166 167 #define SRCMD_DONE_DLY 1000 168 169 /* bankidx and bankinfo reg defines corerev >= 8 */ 170 #define SOCRAM_BANKINFO_SZMASK 0x7f 171 #define SOCRAM_BANKIDX_ROM_MASK 0x100 172 173 #define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8 174 /* socram bankinfo memtype */ 175 #define SOCRAM_MEMTYPE_RAM 0 176 #define SOCRAM_MEMTYPE_ROM 1 177 #define SOCRAM_MEMTYPE_DEVRAM 2 178 179 #define SOCRAM_BANKINFO_REG 0x40 180 #define SOCRAM_BANKIDX_REG 0x10 181 #define SOCRAM_BANKINFO_STDBY_MASK 0x400 182 #define SOCRAM_BANKINFO_STDBY_TIMER 0x800 183 184 /* bankinfo rev >= 10 */ 185 #define SOCRAM_BANKINFO_DEVRAMSEL_SHIFT 13 186 #define SOCRAM_BANKINFO_DEVRAMSEL_MASK 0x2000 187 #define SOCRAM_BANKINFO_DEVRAMPRO_SHIFT 14 188 #define SOCRAM_BANKINFO_DEVRAMPRO_MASK 0x4000 189 #define SOCRAM_BANKINFO_SLPSUPP_SHIFT 15 190 #define SOCRAM_BANKINFO_SLPSUPP_MASK 0x8000 191 #define SOCRAM_BANKINFO_RETNTRAM_SHIFT 16 192 #define SOCRAM_BANKINFO_RETNTRAM_MASK 0x00010000 193 #define SOCRAM_BANKINFO_PDASZ_SHIFT 17 194 #define SOCRAM_BANKINFO_PDASZ_MASK 0x003E0000 195 #define SOCRAM_BANKINFO_DEVRAMREMAP_SHIFT 24 196 #define SOCRAM_BANKINFO_DEVRAMREMAP_MASK 0x01000000 197 198 /* extracoreinfo register */ 199 #define SOCRAM_DEVRAMBANK_MASK 0xF000 200 #define SOCRAM_DEVRAMBANK_SHIFT 12 201 202 /* bank info to calculate bank size */ 203 #define SOCRAM_BANKINFO_SZBASE 8192 204 #define SOCRAM_BANKSIZE_SHIFT 13 /* SOCRAM_BANKINFO_SZBASE */ 205 206 #endif /* _SBSOCRAM_H */ 207