xref: /OK3568_Linux_fs/external/rkwifibt/drivers/infineon/include/event_log_payload.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * EVENT_LOG System Definitions
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * This file describes the payloads of event log entries that are data buffers
5*4882a593Smuzhiyun  * rather than formatted string entries. The contents are generally XTLVs.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * Copyright (C) 1999-2017, Broadcom Corporation
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  *      Unless you and Broadcom execute a separate written software license
12*4882a593Smuzhiyun  * agreement governing use of this software, this software is licensed to you
13*4882a593Smuzhiyun  * under the terms of the GNU General Public License version 2 (the "GPL"),
14*4882a593Smuzhiyun  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
15*4882a593Smuzhiyun  * following added to such license:
16*4882a593Smuzhiyun  *
17*4882a593Smuzhiyun  *      As a special exception, the copyright holders of this software give you
18*4882a593Smuzhiyun  * permission to link this software with independent modules, and to copy and
19*4882a593Smuzhiyun  * distribute the resulting executable under terms of your choice, provided that
20*4882a593Smuzhiyun  * you also meet, for each linked independent module, the terms and conditions of
21*4882a593Smuzhiyun  * the license of that module.  An independent module is a module which is not
22*4882a593Smuzhiyun  * derived from this software.  The special exception does not apply to any
23*4882a593Smuzhiyun  * modifications of the software.
24*4882a593Smuzhiyun  *
25*4882a593Smuzhiyun  *      Notwithstanding the above, under no circumstances may you combine this
26*4882a593Smuzhiyun  * software in any way with any other Broadcom software provided under a license
27*4882a593Smuzhiyun  * other than the GPL, without Broadcom's express prior written consent.
28*4882a593Smuzhiyun  *
29*4882a593Smuzhiyun  *
30*4882a593Smuzhiyun  * <<Broadcom-WL-IPTag/Open:>>
31*4882a593Smuzhiyun  *
32*4882a593Smuzhiyun  * $Id$
33*4882a593Smuzhiyun  */
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #ifndef _EVENT_LOG_PAYLOAD_H_
36*4882a593Smuzhiyun #define _EVENT_LOG_PAYLOAD_H_
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #include <typedefs.h>
39*4882a593Smuzhiyun #include <bcmutils.h>
40*4882a593Smuzhiyun #include <ethernet.h>
41*4882a593Smuzhiyun #include <event_log_tag.h>
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #define EVENT_LOG_XTLV_ID_STR                   0  /**< XTLV ID for a string */
44*4882a593Smuzhiyun #define EVENT_LOG_XTLV_ID_TXQ_SUM               1  /**< XTLV ID for txq_summary_t */
45*4882a593Smuzhiyun #define EVENT_LOG_XTLV_ID_SCBDATA_SUM           2  /**< XTLV ID for cb_subq_summary_t */
46*4882a593Smuzhiyun #define EVENT_LOG_XTLV_ID_SCBDATA_AMPDU_TX_SUM  3  /**< XTLV ID for scb_ampdu_tx_summary_t */
47*4882a593Smuzhiyun #define EVENT_LOG_XTLV_ID_BSSCFGDATA_SUM        4  /**< XTLV ID for bsscfg_q_summary_t */
48*4882a593Smuzhiyun #define EVENT_LOG_XTLV_ID_UCTXSTATUS            5  /**< XTLV ID for ucode TxStatus array */
49*4882a593Smuzhiyun #define EVENT_LOG_XTLV_ID_TXQ_SUM_V2            6  /**< XTLV ID for txq_summary_v2_t */
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun /**
52*4882a593Smuzhiyun  * An XTLV holding a string
53*4882a593Smuzhiyun  * String is not null terminated, length is the XTLV len.
54*4882a593Smuzhiyun  */
55*4882a593Smuzhiyun typedef struct xtlv_string {
56*4882a593Smuzhiyun 	uint16 id;              /* XTLV ID: EVENT_LOG_XTLV_ID_STR */
57*4882a593Smuzhiyun 	uint16 len;             /* XTLV Len (String length) */
58*4882a593Smuzhiyun 	char   str[1];          /* var len array characters */
59*4882a593Smuzhiyun } xtlv_string_t;
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun #define XTLV_STRING_FULL_LEN(str_len)     (BCM_XTLV_HDR_SIZE + (str_len) * sizeof(char))
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun /**
64*4882a593Smuzhiyun  * Summary for a single TxQ context
65*4882a593Smuzhiyun  * Two of these will be used per TxQ context---one for the high TxQ, and one for
66*4882a593Smuzhiyun  * the low txq that contains DMA prepared pkts. The high TxQ is a full multi-precidence
67*4882a593Smuzhiyun  * queue and also has a BSSCFG map to identify the BSSCFGS associated with the queue context.
68*4882a593Smuzhiyun  * The low txq counterpart does not populate the BSSCFG map.
69*4882a593Smuzhiyun  * The excursion queue will have no bsscfgs associated and is the first queue dumped.
70*4882a593Smuzhiyun  */
71*4882a593Smuzhiyun typedef struct txq_summary {
72*4882a593Smuzhiyun 	uint16 id;              /* XTLV ID: EVENT_LOG_XTLV_ID_TXQ_SUM */
73*4882a593Smuzhiyun 	uint16 len;             /* XTLV Len */
74*4882a593Smuzhiyun 	uint32 bsscfg_map;      /* bitmap of bsscfg indexes associated with this queue */
75*4882a593Smuzhiyun 	uint32 stopped;         /* flow control bitmap */
76*4882a593Smuzhiyun 	uint8  prec_count;      /* count of precedences/fifos and len of following array */
77*4882a593Smuzhiyun 	uint8  pad;
78*4882a593Smuzhiyun 	uint16 plen[1];         /* var len array of lengths of each prec/fifo in the queue */
79*4882a593Smuzhiyun } txq_summary_t;
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun #define TXQ_SUMMARY_LEN                   (OFFSETOF(txq_summary_t, plen))
82*4882a593Smuzhiyun #define TXQ_SUMMARY_FULL_LEN(num_q)       (TXQ_SUMMARY_LEN + (num_q) * sizeof(uint16))
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun typedef struct txq_summary_v2 {
85*4882a593Smuzhiyun 	uint16 id;              /* XTLV ID: EVENT_LOG_XTLV_ID_TXQ_SUM_V2 */
86*4882a593Smuzhiyun 	uint16 len;             /* XTLV Len */
87*4882a593Smuzhiyun 	uint32 bsscfg_map;      /* bitmap of bsscfg indexes associated with this queue */
88*4882a593Smuzhiyun 	uint32 stopped;         /* flow control bitmap */
89*4882a593Smuzhiyun 	uint32 hw_stopped;      /* flow control bitmap */
90*4882a593Smuzhiyun 	uint8  prec_count;      /* count of precedences/fifos and len of following array */
91*4882a593Smuzhiyun 	uint8  pad;
92*4882a593Smuzhiyun 	uint16 plen[1];         /* var len array of lengths of each prec/fifo in the queue */
93*4882a593Smuzhiyun } txq_summary_v2_t;
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun #define TXQ_SUMMARY_V2_LEN                (OFFSETOF(txq_summary_v2_t, plen))
96*4882a593Smuzhiyun #define TXQ_SUMMARY_V2_FULL_LEN(num_q)    (TXQ_SUMMARY_V2_LEN + (num_q) * sizeof(uint16))
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun /**
99*4882a593Smuzhiyun  * Summary for tx datapath of an SCB cubby
100*4882a593Smuzhiyun  * This is a generic summary structure (one size fits all) with
101*4882a593Smuzhiyun  * a cubby ID and sub-ID to differentiate SCB cubby types and possible sub-queues.
102*4882a593Smuzhiyun  */
103*4882a593Smuzhiyun typedef struct scb_subq_summary {
104*4882a593Smuzhiyun 	uint16 id;             /* XTLV ID: EVENT_LOG_XTLV_ID_SCBDATA_SUM */
105*4882a593Smuzhiyun 	uint16 len;            /* XTLV Len */
106*4882a593Smuzhiyun 	uint32 flags;          /* cubby specficic flags */
107*4882a593Smuzhiyun 	uint8  cubby_id;       /* ID registered for cubby */
108*4882a593Smuzhiyun 	uint8  sub_id;         /* sub ID if a cubby has more than one queue */
109*4882a593Smuzhiyun 	uint8  prec_count;     /* count of precedences/fifos and len of following array */
110*4882a593Smuzhiyun 	uint8  pad;
111*4882a593Smuzhiyun 	uint16 plen[1];        /* var len array of lengths of each prec/fifo in the queue */
112*4882a593Smuzhiyun } scb_subq_summary_t;
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun #define SCB_SUBQ_SUMMARY_LEN              (OFFSETOF(scb_subq_summary_t, plen))
115*4882a593Smuzhiyun #define SCB_SUBQ_SUMMARY_FULL_LEN(num_q)  (SCB_SUBQ_SUMMARY_LEN + (num_q) * sizeof(uint16))
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun /* scb_subq_summary_t.flags for APPS */
118*4882a593Smuzhiyun #define SCBDATA_APPS_F_PS               0x00000001
119*4882a593Smuzhiyun #define SCBDATA_APPS_F_PSPEND           0x00000002
120*4882a593Smuzhiyun #define SCBDATA_APPS_F_INPVB            0x00000004
121*4882a593Smuzhiyun #define SCBDATA_APPS_F_APSD_USP         0x00000008
122*4882a593Smuzhiyun #define SCBDATA_APPS_F_TXBLOCK          0x00000010
123*4882a593Smuzhiyun #define SCBDATA_APPS_F_APSD_HPKT_TMR    0x00000020
124*4882a593Smuzhiyun #define SCBDATA_APPS_F_APSD_TX_PEND     0x00000040
125*4882a593Smuzhiyun #define SCBDATA_APPS_F_INTRANS          0x00000080
126*4882a593Smuzhiyun #define SCBDATA_APPS_F_OFF_PEND         0x00000100
127*4882a593Smuzhiyun #define SCBDATA_APPS_F_OFF_BLOCKED      0x00000200
128*4882a593Smuzhiyun #define SCBDATA_APPS_F_OFF_IN_PROG      0x00000400
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun /**
131*4882a593Smuzhiyun  * Summary for tx datapath AMPDU SCB cubby
132*4882a593Smuzhiyun  * This is a specific data structure to describe the AMPDU datapath state for an SCB
133*4882a593Smuzhiyun  * used instead of scb_subq_summary_t.
134*4882a593Smuzhiyun  * Info is for one TID, so one will be dumped per BA TID active for an SCB.
135*4882a593Smuzhiyun  */
136*4882a593Smuzhiyun typedef struct scb_ampdu_tx_summary {
137*4882a593Smuzhiyun 	uint16 id;              /* XTLV ID: EVENT_LOG_XTLV_ID_SCBDATA_AMPDU_TX_SUM */
138*4882a593Smuzhiyun 	uint16 len;             /* XTLV Len */
139*4882a593Smuzhiyun 	uint32 flags;           /* misc flags */
140*4882a593Smuzhiyun 	uint8  tid;             /* initiator TID (priority) */
141*4882a593Smuzhiyun 	uint8  ba_state;        /* internal BA state */
142*4882a593Smuzhiyun 	uint8  bar_cnt;         /* number of bars sent with no progress */
143*4882a593Smuzhiyun 	uint8  retry_bar;       /* reason code if bar to be retried at watchdog */
144*4882a593Smuzhiyun 	uint16 barpending_seq;  /* seqnum for bar */
145*4882a593Smuzhiyun 	uint16 bar_ackpending_seq; /* seqnum of bar for which ack is pending */
146*4882a593Smuzhiyun 	uint16 start_seq;       /* seqnum of the first unacknowledged packet */
147*4882a593Smuzhiyun 	uint16 max_seq;         /* max unacknowledged seqnum sent */
148*4882a593Smuzhiyun 	uint32 released_bytes_inflight; /* Number of bytes pending in bytes */
149*4882a593Smuzhiyun 	uint32 released_bytes_target;
150*4882a593Smuzhiyun } scb_ampdu_tx_summary_t;
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun /* scb_ampdu_tx_summary.flags defs */
153*4882a593Smuzhiyun #define SCBDATA_AMPDU_TX_F_BAR_ACKPEND          0x00000001 /* bar_ackpending */
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun /** XTLV stuct to summarize a BSSCFG's packet queue */
156*4882a593Smuzhiyun typedef struct bsscfg_q_summary {
157*4882a593Smuzhiyun 	uint16 id;               /* XTLV ID: EVENT_LOG_XTLV_ID_BSSCFGDATA_SUM */
158*4882a593Smuzhiyun 	uint16 len;              /* XTLV Len */
159*4882a593Smuzhiyun 	struct ether_addr BSSID; /* BSSID */
160*4882a593Smuzhiyun 	uint8  bsscfg_idx;       /* bsscfg index */
161*4882a593Smuzhiyun 	uint8  type;             /* bsscfg type enumeration: BSSCFG_TYPE_XXX */
162*4882a593Smuzhiyun 	uint8  subtype;          /* bsscfg subtype enumeration: BSSCFG_SUBTYPE_XXX */
163*4882a593Smuzhiyun 	uint8  prec_count;       /* count of precedences/fifos and len of following array */
164*4882a593Smuzhiyun 	uint16 plen[1];          /* var len array of lengths of each prec/fifo in the queue */
165*4882a593Smuzhiyun } bsscfg_q_summary_t;
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun #define BSSCFG_Q_SUMMARY_LEN              (OFFSETOF(bsscfg_q_summary_t, plen))
168*4882a593Smuzhiyun #define BSSCFG_Q_SUMMARY_FULL_LEN(num_q)  (BSSCFG_Q_SUMMARY_LEN + (num_q) * sizeof(uint16))
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun /**
171*4882a593Smuzhiyun  * An XTLV holding a TxStats array
172*4882a593Smuzhiyun  * TxStatus entries are 8 or 16 bytes, size in words (2 or 4) givent in
173*4882a593Smuzhiyun  * entry_size field.
174*4882a593Smuzhiyun  * Array is uint32 words
175*4882a593Smuzhiyun  */
176*4882a593Smuzhiyun typedef struct xtlv_uc_txs {
177*4882a593Smuzhiyun 	uint16 id;              /* XTLV ID: EVENT_LOG_XTLV_ID_UCTXSTATUS */
178*4882a593Smuzhiyun 	uint16 len;             /* XTLV Len */
179*4882a593Smuzhiyun 	uint8  entry_size;      /* num uint32 words per entry */
180*4882a593Smuzhiyun 	uint8  pad[3];          /* reserved, zero */
181*4882a593Smuzhiyun 	uint32 w[1];            /* var len array of words */
182*4882a593Smuzhiyun } xtlv_uc_txs_t;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun #define XTLV_UCTXSTATUS_LEN                (OFFSETOF(xtlv_uc_txs_t, w))
185*4882a593Smuzhiyun #define XTLV_UCTXSTATUS_FULL_LEN(words)    (XTLV_UCTXSTATUS_LEN + (words) * sizeof(uint32))
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun #define SCAN_SUMMARY_VERSION	1
188*4882a593Smuzhiyun /* Scan flags */
189*4882a593Smuzhiyun #define SCAN_SUM_CHAN_INFO	0x1
190*4882a593Smuzhiyun /* Scan_sum flags */
191*4882a593Smuzhiyun #define BAND5G_SIB_ENAB	0x2
192*4882a593Smuzhiyun #define BAND2G_SIB_ENAB	0x4
193*4882a593Smuzhiyun #define PARALLEL_SCAN	0x8
194*4882a593Smuzhiyun #define SCAN_ABORT	0x10
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun /* scan_channel_info flags */
197*4882a593Smuzhiyun #define ACTIVE_SCAN_SCN_SUM	0x2
198*4882a593Smuzhiyun #define SCAN_SUM_WLC_CORE0	0x4
199*4882a593Smuzhiyun #define SCAN_SUM_WLC_CORE1	0x8
200*4882a593Smuzhiyun #define HOME_CHAN	0x10
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun typedef struct wl_scan_ssid_info
203*4882a593Smuzhiyun {
204*4882a593Smuzhiyun 	uint8		ssid_len;	/* the length of SSID */
205*4882a593Smuzhiyun 	uint8		ssid[32];	/* SSID string */
206*4882a593Smuzhiyun } wl_scan_ssid_info_t;
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun typedef struct wl_scan_channel_info {
209*4882a593Smuzhiyun 	uint16 chanspec;	/* chanspec scanned */
210*4882a593Smuzhiyun 	uint16 reserv;
211*4882a593Smuzhiyun 	uint32 start_time;		/* Scan start time in
212*4882a593Smuzhiyun 				* milliseconds for the chanspec
213*4882a593Smuzhiyun 				* or home_dwell time start
214*4882a593Smuzhiyun 				*/
215*4882a593Smuzhiyun 	uint32 end_time;		/* Scan end time in
216*4882a593Smuzhiyun 				* milliseconds for the chanspec
217*4882a593Smuzhiyun 				* or home_dwell time end
218*4882a593Smuzhiyun 				*/
219*4882a593Smuzhiyun 	uint16 probe_count;	/* No of probes sent out. For future use
220*4882a593Smuzhiyun 				*/
221*4882a593Smuzhiyun 	uint16 scn_res_count;	/* Count of scan_results found per
222*4882a593Smuzhiyun 				* channel. For future use
223*4882a593Smuzhiyun 				*/
224*4882a593Smuzhiyun } wl_scan_channel_info_t;
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun typedef struct wl_scan_summary_info {
227*4882a593Smuzhiyun 	uint32 total_chan_num;	/* Total number of channels scanned */
228*4882a593Smuzhiyun 	uint32 scan_start_time;	/* Scan start time in milliseconds */
229*4882a593Smuzhiyun 	uint32 scan_end_time;	/* Scan end time in milliseconds */
230*4882a593Smuzhiyun 	wl_scan_ssid_info_t ssid[1];	/* SSID being scanned in current
231*4882a593Smuzhiyun 				* channel. For future use
232*4882a593Smuzhiyun 				*/
233*4882a593Smuzhiyun } wl_scan_summary_info_t;
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun struct wl_scan_summary {
236*4882a593Smuzhiyun 	uint8 version;		/* Version */
237*4882a593Smuzhiyun 	uint8 reserved;
238*4882a593Smuzhiyun 	uint16 len;		/* Length of the data buffer including SSID
239*4882a593Smuzhiyun 				 * list.
240*4882a593Smuzhiyun 				 */
241*4882a593Smuzhiyun 	uint16 sync_id;		/* Scan Sync ID */
242*4882a593Smuzhiyun 	uint16 scan_flags;		/* flags [0] or SCAN_SUM_CHAN_INFO = */
243*4882a593Smuzhiyun 				/* channel_info, if not set */
244*4882a593Smuzhiyun 				/* it is scan_summary_info */
245*4882a593Smuzhiyun 				/* when channel_info is used, */
246*4882a593Smuzhiyun 				/* the following flag bits are overridden: */
247*4882a593Smuzhiyun 				/* flags[1] or ACTIVE_SCAN_SCN_SUM = active channel if set */
248*4882a593Smuzhiyun 				/* passive if not set */
249*4882a593Smuzhiyun 				/* flags[2] or WLC_CORE0 = if set, represents wlc_core0 */
250*4882a593Smuzhiyun 				/* flags[3] or WLC_CORE1 = if set, represents wlc_core1 */
251*4882a593Smuzhiyun 				/* flags[4] or HOME_CHAN = if set, represents home-channel */
252*4882a593Smuzhiyun 				/* flags[5:15] = reserved */
253*4882a593Smuzhiyun 				/* when scan_summary_info is used, */
254*4882a593Smuzhiyun 				/* the following flag bits are used: */
255*4882a593Smuzhiyun 				/* flags[1] or BAND5G_SIB_ENAB = */
256*4882a593Smuzhiyun 				/* allowSIBParallelPassiveScan on 5G band */
257*4882a593Smuzhiyun 				/* flags[2] or BAND2G_SIB_ENAB = */
258*4882a593Smuzhiyun 				/* allowSIBParallelPassiveScan on 2G band */
259*4882a593Smuzhiyun 				/* flags[3] or PARALLEL_SCAN = Parallel scan enabled or not */
260*4882a593Smuzhiyun 				/* flags[4] or SCAN_ABORT = SCAN_ABORTED scenario */
261*4882a593Smuzhiyun 				/* flags[5:15] = reserved */
262*4882a593Smuzhiyun 	union {
263*4882a593Smuzhiyun 		wl_scan_channel_info_t scan_chan_info;	/* scan related information
264*4882a593Smuzhiyun 							* for each channel scanned
265*4882a593Smuzhiyun 							*/
266*4882a593Smuzhiyun 		wl_scan_summary_info_t scan_sum_info;	/* Cumulative scan related
267*4882a593Smuzhiyun 							* information.
268*4882a593Smuzhiyun 							*/
269*4882a593Smuzhiyun 	} u;
270*4882a593Smuzhiyun };
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun /* Channel switch log record structure
273*4882a593Smuzhiyun  * Host may map the following structure on channel switch event log record
274*4882a593Smuzhiyun  * received from dongle. Note that all payload entries in event log record are
275*4882a593Smuzhiyun  * uint32/int32.
276*4882a593Smuzhiyun  */
277*4882a593Smuzhiyun typedef struct wl_chansw_event_log_record {
278*4882a593Smuzhiyun 	uint32 time;			/* Time in us */
279*4882a593Smuzhiyun 	uint32 old_chanspec;		/* Old channel spec */
280*4882a593Smuzhiyun 	uint32 new_chanspec;		/* New channel spec */
281*4882a593Smuzhiyun 	uint32 chansw_reason;		/* Reason for channel change */
282*4882a593Smuzhiyun 	int32 dwell_time;
283*4882a593Smuzhiyun } wl_chansw_event_log_record_t;
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun typedef struct wl_chansw_event_log_record_v2 {
286*4882a593Smuzhiyun 	uint32 time;			/* Time in us */
287*4882a593Smuzhiyun 	uint32 old_chanspec;		/* Old channel spec */
288*4882a593Smuzhiyun 	uint32 new_chanspec;		/* New channel spec */
289*4882a593Smuzhiyun 	uint32 chansw_reason;		/* Reason for channel change */
290*4882a593Smuzhiyun 	int32 dwell_time;
291*4882a593Smuzhiyun 	uint32 core;
292*4882a593Smuzhiyun 	int32 phychanswtime;		/* channel switch time */
293*4882a593Smuzhiyun } wl_chansw_event_log_record_v2_t;
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun /* Sub-block type for EVENT_LOG_TAG_AMPDU_DUMP */
296*4882a593Smuzhiyun typedef enum {
297*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_RXMCSx1 = 0,	/* RX MCS rate (Nss = 1) */
298*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_RXMCSx2 = 1,
299*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_RXMCSx3 = 2,
300*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_RXMCSx4 = 3,
301*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_RXVHTx1 = 4, /* RX VHT rate (Nss = 1) */
302*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_RXVHTx2 = 5,
303*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_RXVHTx3 = 6,
304*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_RXVHTx4 = 7,
305*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_TXMCSx1 = 8, /* TX MCS rate (Nss = 1) */
306*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_TXMCSx2 = 9,
307*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_TXMCSx3 = 10,
308*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_TXMCSx4 = 11,
309*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_TXVHTx1 = 12,	/* TX VHT rate (Nss = 1) */
310*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_TXVHTx2 = 13,
311*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_TXVHTx3 = 14,
312*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_TXVHTx4 = 15,
313*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_RXMCSSGI = 16,	/* RX SGI usage (for all MCS rates) */
314*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_TXMCSSGI = 17,	/* TX SGI usage (for all MCS rates) */
315*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_RXVHTSGI = 18,	/* RX SGI usage (for all VHT rates) */
316*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_TXVHTSGI = 19,	/* TX SGI usage (for all VHT rates) */
317*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_RXMCSPER = 20,	/* RX PER (for all MCS rates) */
318*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_TXMCSPER = 21,	/* TX PER (for all MCS rates) */
319*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_RXVHTPER = 22,	/* RX PER (for all VHT rates) */
320*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_TXVHTPER = 23,	/* TX PER (for all VHT rates) */
321*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_RXDENS = 24,	/* RX AMPDU density */
322*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_TXDENS = 25,	/* TX AMPDU density */
323*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_RXMCSOK = 26,	/* RX all MCS rates */
324*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_RXVHTOK = 27,	/* RX all VHT rates */
325*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_TXMCSALL = 28,	/* TX all MCS rates */
326*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_TXVHTALL = 29,	/* TX all VHT rates */
327*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_TXMCSOK = 30,	/* TX all MCS rates */
328*4882a593Smuzhiyun 	WL_AMPDU_STATS_TYPE_TXVHTOK = 31,	/* TX all VHT rates */
329*4882a593Smuzhiyun 	WL_AMPDU_STATS_MAX_CNTS = 64
330*4882a593Smuzhiyun } wl_ampdu_stat_enum_t;
331*4882a593Smuzhiyun typedef struct {
332*4882a593Smuzhiyun 	uint16	type;		/* AMPDU statistics sub-type */
333*4882a593Smuzhiyun 	uint16	len;		/* Number of 32-bit counters */
334*4882a593Smuzhiyun 	uint32	counters[WL_AMPDU_STATS_MAX_CNTS];
335*4882a593Smuzhiyun } wl_ampdu_stats_generic_t;
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun typedef wl_ampdu_stats_generic_t wl_ampdu_stats_rx_t;
338*4882a593Smuzhiyun typedef wl_ampdu_stats_generic_t wl_ampdu_stats_tx_t;
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun typedef struct {
341*4882a593Smuzhiyun 	uint16	type;		/* AMPDU statistics sub-type */
342*4882a593Smuzhiyun 	uint16	len;		/* Number of 32-bit counters + 2 */
343*4882a593Smuzhiyun 	uint32	total_ampdu;
344*4882a593Smuzhiyun 	uint32	total_mpdu;
345*4882a593Smuzhiyun 	uint32	aggr_dist[WL_AMPDU_STATS_MAX_CNTS + 1];
346*4882a593Smuzhiyun } wl_ampdu_stats_aggrsz_t;
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun /* Sub-block type for EVENT_LOG_TAG_MSCHPROFILE */
349*4882a593Smuzhiyun #define WL_MSCH_PROFILER_START		0	/* start event check */
350*4882a593Smuzhiyun #define WL_MSCH_PROFILER_EXIT		1	/* exit event check */
351*4882a593Smuzhiyun #define WL_MSCH_PROFILER_REQ		2	/* request event */
352*4882a593Smuzhiyun #define WL_MSCH_PROFILER_CALLBACK	3	/* call back event */
353*4882a593Smuzhiyun #define WL_MSCH_PROFILER_MESSAGE	4	/* message event */
354*4882a593Smuzhiyun #define WL_MSCH_PROFILER_PROFILE_START	5
355*4882a593Smuzhiyun #define WL_MSCH_PROFILER_PROFILE_END	6
356*4882a593Smuzhiyun #define WL_MSCH_PROFILER_REQ_HANDLE	7
357*4882a593Smuzhiyun #define WL_MSCH_PROFILER_REQ_ENTITY	8
358*4882a593Smuzhiyun #define WL_MSCH_PROFILER_CHAN_CTXT	9
359*4882a593Smuzhiyun #define WL_MSCH_PROFILER_EVENT_LOG	10
360*4882a593Smuzhiyun #define WL_MSCH_PROFILER_REQ_TIMING	11
361*4882a593Smuzhiyun #define WL_MSCH_PROFILER_TYPE_MASK	0x00ff
362*4882a593Smuzhiyun #define WL_MSCH_PROFILER_WLINDEX_SHIFT	8
363*4882a593Smuzhiyun #define WL_MSCH_PROFILER_WLINDEX_MASK	0x0f00
364*4882a593Smuzhiyun #define WL_MSCH_PROFILER_VER_SHIFT	12
365*4882a593Smuzhiyun #define WL_MSCH_PROFILER_VER_MASK	0xf000
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun /* MSCH Event data current verion */
368*4882a593Smuzhiyun #define WL_MSCH_PROFILER_VER		2
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun /* msch version history */
371*4882a593Smuzhiyun #define WL_MSCH_PROFILER_RSDB_VER	1
372*4882a593Smuzhiyun #define WL_MSCH_PROFILER_REPORT_VER	2
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun /* msch collect header size */
375*4882a593Smuzhiyun #define WL_MSCH_PROFILE_HEAD_SIZE	OFFSETOF(msch_collect_tlv_t, value)
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun /* msch event log header size */
378*4882a593Smuzhiyun #define WL_MSCH_EVENT_LOG_HEAD_SIZE	OFFSETOF(msch_event_log_profiler_event_data_t, data)
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun /* MSCH data buffer size */
381*4882a593Smuzhiyun #define WL_MSCH_PROFILER_BUFFER_SIZE	512
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun /* request type used in wlc_msch_req_param_t struct */
384*4882a593Smuzhiyun #define WL_MSCH_RT_BOTH_FIXED	0	/* both start and end time is fixed */
385*4882a593Smuzhiyun #define WL_MSCH_RT_START_FLEX	1	/* start time is flexible and duration is fixed */
386*4882a593Smuzhiyun #define WL_MSCH_RT_DUR_FLEX	2	/* start time is fixed and end time is flexible */
387*4882a593Smuzhiyun #define WL_MSCH_RT_BOTH_FLEX	3	/* Both start and duration is flexible */
388*4882a593Smuzhiyun 
389*4882a593Smuzhiyun /* Flags used in wlc_msch_req_param_t struct */
390*4882a593Smuzhiyun #define WL_MSCH_REQ_FLAGS_CHAN_CONTIGUOUS  (1 << 0) /* Don't break up channels in chanspec_list */
391*4882a593Smuzhiyun #define WL_MSCH_REQ_FLAGS_MERGE_CONT_SLOTS (1 << 1)  /* No slot end if slots are continous */
392*4882a593Smuzhiyun #define WL_MSCH_REQ_FLAGS_PREMTABLE        (1 << 2) /* Req can be pre-empted by PREMT_CURTS req */
393*4882a593Smuzhiyun #define WL_MSCH_REQ_FLAGS_PREMT_CURTS      (1 << 3) /* Pre-empt request at the end of curts */
394*4882a593Smuzhiyun #define WL_MSCH_REQ_FLAGS_PREMT_IMMEDIATE  (1 << 4) /* Pre-empt cur_ts immediately */
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun /* Requested slot Callback states
397*4882a593Smuzhiyun  * req->pend_slot/cur_slot->flags
398*4882a593Smuzhiyun  */
399*4882a593Smuzhiyun #define WL_MSCH_RC_FLAGS_ONCHAN_FIRE		(1 << 0)
400*4882a593Smuzhiyun #define WL_MSCH_RC_FLAGS_START_FIRE_DONE	(1 << 1)
401*4882a593Smuzhiyun #define WL_MSCH_RC_FLAGS_END_FIRE_DONE		(1 << 2)
402*4882a593Smuzhiyun #define WL_MSCH_RC_FLAGS_ONFIRE_DONE		(1 << 3)
403*4882a593Smuzhiyun #define WL_MSCH_RC_FLAGS_SPLIT_SLOT_START	(1 << 4)
404*4882a593Smuzhiyun #define WL_MSCH_RC_FLAGS_SPLIT_SLOT_END		(1 << 5)
405*4882a593Smuzhiyun #define WL_MSCH_RC_FLAGS_PRE_ONFIRE_DONE	(1 << 6)
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun /* Request entity flags */
408*4882a593Smuzhiyun #define WL_MSCH_ENTITY_FLAG_MULTI_INSTANCE	(1 << 0)
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun /* Request Handle flags */
411*4882a593Smuzhiyun #define WL_MSCH_REQ_HDL_FLAGS_NEW_REQ		(1 << 0) /* req_start callback */
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun /* MSCH state flags (msch_info->flags) */
414*4882a593Smuzhiyun #define	WL_MSCH_STATE_IN_TIEMR_CTXT		0x1
415*4882a593Smuzhiyun #define WL_MSCH_STATE_SCHD_PENDING		0x2
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun /* MSCH callback type */
418*4882a593Smuzhiyun #define	WL_MSCH_CT_REQ_START		0x1
419*4882a593Smuzhiyun #define	WL_MSCH_CT_ON_CHAN		0x2
420*4882a593Smuzhiyun #define	WL_MSCH_CT_SLOT_START		0x4
421*4882a593Smuzhiyun #define	WL_MSCH_CT_SLOT_END		0x8
422*4882a593Smuzhiyun #define	WL_MSCH_CT_SLOT_SKIP		0x10
423*4882a593Smuzhiyun #define	WL_MSCH_CT_OFF_CHAN		0x20
424*4882a593Smuzhiyun #define WL_MSCH_CT_OFF_CHAN_DONE	0x40
425*4882a593Smuzhiyun #define	WL_MSCH_CT_REQ_END		0x80
426*4882a593Smuzhiyun #define	WL_MSCH_CT_PARTIAL		0x100
427*4882a593Smuzhiyun #define	WL_MSCH_CT_PRE_ONCHAN		0x200
428*4882a593Smuzhiyun #define	WL_MSCH_CT_PRE_REQ_START	0x400
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun /* MSCH command bits */
431*4882a593Smuzhiyun #define WL_MSCH_CMD_ENABLE_BIT		0x01
432*4882a593Smuzhiyun #define WL_MSCH_CMD_PROFILE_BIT		0x02
433*4882a593Smuzhiyun #define WL_MSCH_CMD_CALLBACK_BIT	0x04
434*4882a593Smuzhiyun #define WL_MSCH_CMD_REGISTER_BIT	0x08
435*4882a593Smuzhiyun #define WL_MSCH_CMD_ERROR_BIT		0x10
436*4882a593Smuzhiyun #define WL_MSCH_CMD_DEBUG_BIT		0x20
437*4882a593Smuzhiyun #define WL_MSCH_CMD_INFOM_BIT		0x40
438*4882a593Smuzhiyun #define WL_MSCH_CMD_TRACE_BIT		0x80
439*4882a593Smuzhiyun #define WL_MSCH_CMD_ALL_BITS		0xfe
440*4882a593Smuzhiyun #define WL_MSCH_CMD_SIZE_MASK		0x00ff0000
441*4882a593Smuzhiyun #define WL_MSCH_CMD_SIZE_SHIFT		16
442*4882a593Smuzhiyun #define WL_MSCH_CMD_VER_MASK		0xff000000
443*4882a593Smuzhiyun #define WL_MSCH_CMD_VER_SHIFT		24
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun /* maximum channels returned by the get valid channels iovar */
446*4882a593Smuzhiyun #define WL_MSCH_NUMCHANNELS		64
447*4882a593Smuzhiyun 
448*4882a593Smuzhiyun typedef struct msch_collect_tlv {
449*4882a593Smuzhiyun 	uint16	type;
450*4882a593Smuzhiyun 	uint16	size;
451*4882a593Smuzhiyun 	char	value[1];
452*4882a593Smuzhiyun } msch_collect_tlv_t;
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun typedef struct msch_profiler_event_data {
455*4882a593Smuzhiyun 	uint32	time_lo;		/* Request time */
456*4882a593Smuzhiyun 	uint32	time_hi;
457*4882a593Smuzhiyun } msch_profiler_event_data_t;
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun typedef struct msch_start_profiler_event_data {
460*4882a593Smuzhiyun 	uint32	time_lo;		/* Request time */
461*4882a593Smuzhiyun 	uint32	time_hi;
462*4882a593Smuzhiyun 	uint32	status;
463*4882a593Smuzhiyun } msch_start_profiler_event_data_t;
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun typedef struct msch_message_profiler_event_data {
466*4882a593Smuzhiyun 	uint32	time_lo;		/* Request time */
467*4882a593Smuzhiyun 	uint32	time_hi;
468*4882a593Smuzhiyun 	char	message[1];		/* message */
469*4882a593Smuzhiyun } msch_message_profiler_event_data_t;
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun typedef struct msch_event_log_profiler_event_data {
472*4882a593Smuzhiyun 	uint32	time_lo;		/* Request time */
473*4882a593Smuzhiyun 	uint32	time_hi;
474*4882a593Smuzhiyun 	event_log_hdr_t hdr;		/* event log header */
475*4882a593Smuzhiyun 	uint32	data[9];		/* event data */
476*4882a593Smuzhiyun } msch_event_log_profiler_event_data_t;
477*4882a593Smuzhiyun 
478*4882a593Smuzhiyun typedef struct msch_req_param_profiler_event_data {
479*4882a593Smuzhiyun 	uint16  flags;			/* Describe various request properties */
480*4882a593Smuzhiyun 	uint8	req_type;		/* Describe start and end time flexiblilty */
481*4882a593Smuzhiyun 	uint8	priority;		/* Define the request priority */
482*4882a593Smuzhiyun 	uint32	start_time_l;		/* Requested start time offset in us unit */
483*4882a593Smuzhiyun 	uint32	start_time_h;
484*4882a593Smuzhiyun 	uint32	duration;		/* Requested duration in us unit */
485*4882a593Smuzhiyun 	uint32	interval;		/* Requested periodic interval in us unit,
486*4882a593Smuzhiyun 					 * 0 means non-periodic
487*4882a593Smuzhiyun 					 */
488*4882a593Smuzhiyun 	union {
489*4882a593Smuzhiyun 		uint32	dur_flex;	/* MSCH_REG_DUR_FLEX, min_dur = duration - dur_flex */
490*4882a593Smuzhiyun 		struct {
491*4882a593Smuzhiyun 			uint32 min_dur;	/* min duration for traffic, maps to home_time */
492*4882a593Smuzhiyun 			uint32 max_away_dur; /* max acceptable away dur, maps to home_away_time */
493*4882a593Smuzhiyun 			uint32 hi_prio_time_l;
494*4882a593Smuzhiyun 			uint32 hi_prio_time_h;
495*4882a593Smuzhiyun 			uint32 hi_prio_interval; /* repeated high priority interval */
496*4882a593Smuzhiyun 		} bf;
497*4882a593Smuzhiyun 	} flex;
498*4882a593Smuzhiyun } msch_req_param_profiler_event_data_t;
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun typedef struct msch_req_timing_profiler_event_data {
501*4882a593Smuzhiyun 	uint32 p_req_timing;
502*4882a593Smuzhiyun 	uint32 p_prev;
503*4882a593Smuzhiyun 	uint32 p_next;
504*4882a593Smuzhiyun 	uint16 flags;
505*4882a593Smuzhiyun 	uint16 timeslot_ptr;
506*4882a593Smuzhiyun 	uint32 fire_time_l;
507*4882a593Smuzhiyun 	uint32 fire_time_h;
508*4882a593Smuzhiyun 	uint32 pre_start_time_l;
509*4882a593Smuzhiyun 	uint32 pre_start_time_h;
510*4882a593Smuzhiyun 	uint32 start_time_l;
511*4882a593Smuzhiyun 	uint32 start_time_h;
512*4882a593Smuzhiyun 	uint32 end_time_l;
513*4882a593Smuzhiyun 	uint32 end_time_h;
514*4882a593Smuzhiyun 	uint32 p_timeslot;
515*4882a593Smuzhiyun } msch_req_timing_profiler_event_data_t;
516*4882a593Smuzhiyun 
517*4882a593Smuzhiyun typedef struct msch_chan_ctxt_profiler_event_data {
518*4882a593Smuzhiyun 	uint32 p_chan_ctxt;
519*4882a593Smuzhiyun 	uint32 p_prev;
520*4882a593Smuzhiyun 	uint32 p_next;
521*4882a593Smuzhiyun 	uint16 chanspec;
522*4882a593Smuzhiyun 	uint16 bf_sch_pending;
523*4882a593Smuzhiyun 	uint32 bf_link_prev;
524*4882a593Smuzhiyun 	uint32 bf_link_next;
525*4882a593Smuzhiyun 	uint32 onchan_time_l;
526*4882a593Smuzhiyun 	uint32 onchan_time_h;
527*4882a593Smuzhiyun 	uint32 actual_onchan_dur_l;
528*4882a593Smuzhiyun 	uint32 actual_onchan_dur_h;
529*4882a593Smuzhiyun 	uint32 pend_onchan_dur_l;
530*4882a593Smuzhiyun 	uint32 pend_onchan_dur_h;
531*4882a593Smuzhiyun 	uint16 req_entity_list_cnt;
532*4882a593Smuzhiyun 	uint16 req_entity_list_ptr;
533*4882a593Smuzhiyun 	uint16 bf_entity_list_cnt;
534*4882a593Smuzhiyun 	uint16 bf_entity_list_ptr;
535*4882a593Smuzhiyun 	uint32 bf_skipped_count;
536*4882a593Smuzhiyun } msch_chan_ctxt_profiler_event_data_t;
537*4882a593Smuzhiyun 
538*4882a593Smuzhiyun typedef struct msch_req_entity_profiler_event_data {
539*4882a593Smuzhiyun 	uint32 p_req_entity;
540*4882a593Smuzhiyun 	uint32 req_hdl_link_prev;
541*4882a593Smuzhiyun 	uint32 req_hdl_link_next;
542*4882a593Smuzhiyun 	uint32 chan_ctxt_link_prev;
543*4882a593Smuzhiyun 	uint32 chan_ctxt_link_next;
544*4882a593Smuzhiyun 	uint32 rt_specific_link_prev;
545*4882a593Smuzhiyun 	uint32 rt_specific_link_next;
546*4882a593Smuzhiyun 	uint32 start_fixed_link_prev;
547*4882a593Smuzhiyun 	uint32 start_fixed_link_next;
548*4882a593Smuzhiyun 	uint32 both_flex_list_prev;
549*4882a593Smuzhiyun 	uint32 both_flex_list_next;
550*4882a593Smuzhiyun 	uint16 chanspec;
551*4882a593Smuzhiyun 	uint16 priority;
552*4882a593Smuzhiyun 	uint16 cur_slot_ptr;
553*4882a593Smuzhiyun 	uint16 pend_slot_ptr;
554*4882a593Smuzhiyun 	uint16 pad;
555*4882a593Smuzhiyun 	uint16 chan_ctxt_ptr;
556*4882a593Smuzhiyun 	uint32 p_chan_ctxt;
557*4882a593Smuzhiyun 	uint32 p_req_hdl;
558*4882a593Smuzhiyun 	uint32 bf_last_serv_time_l;
559*4882a593Smuzhiyun 	uint32 bf_last_serv_time_h;
560*4882a593Smuzhiyun 	uint16 onchan_chn_idx;
561*4882a593Smuzhiyun 	uint16 cur_chn_idx;
562*4882a593Smuzhiyun 	uint32 flags;
563*4882a593Smuzhiyun 	uint32 actual_start_time_l;
564*4882a593Smuzhiyun 	uint32 actual_start_time_h;
565*4882a593Smuzhiyun 	uint32 curts_fire_time_l;
566*4882a593Smuzhiyun 	uint32 curts_fire_time_h;
567*4882a593Smuzhiyun } msch_req_entity_profiler_event_data_t;
568*4882a593Smuzhiyun 
569*4882a593Smuzhiyun typedef struct msch_req_handle_profiler_event_data {
570*4882a593Smuzhiyun 	uint32 p_req_handle;
571*4882a593Smuzhiyun 	uint32 p_prev;
572*4882a593Smuzhiyun 	uint32 p_next;
573*4882a593Smuzhiyun 	uint32 cb_func;
574*4882a593Smuzhiyun 	uint32 cb_ctxt;
575*4882a593Smuzhiyun 	uint16 req_param_ptr;
576*4882a593Smuzhiyun 	uint16 req_entity_list_cnt;
577*4882a593Smuzhiyun 	uint16 req_entity_list_ptr;
578*4882a593Smuzhiyun 	uint16 chan_cnt;
579*4882a593Smuzhiyun 	uint32 flags;
580*4882a593Smuzhiyun 	uint16 chanspec_list;
581*4882a593Smuzhiyun 	uint16 chanspec_cnt;
582*4882a593Smuzhiyun 	uint16 chan_idx;
583*4882a593Smuzhiyun 	uint16 last_chan_idx;
584*4882a593Smuzhiyun 	uint32 req_time_l;
585*4882a593Smuzhiyun 	uint32 req_time_h;
586*4882a593Smuzhiyun } msch_req_handle_profiler_event_data_t;
587*4882a593Smuzhiyun 
588*4882a593Smuzhiyun typedef struct msch_profiler_profiler_event_data {
589*4882a593Smuzhiyun 	uint32 time_lo;			/* Request time */
590*4882a593Smuzhiyun 	uint32 time_hi;
591*4882a593Smuzhiyun 	uint32 free_req_hdl_list;
592*4882a593Smuzhiyun 	uint32 free_req_entity_list;
593*4882a593Smuzhiyun 	uint32 free_chan_ctxt_list;
594*4882a593Smuzhiyun 	uint32 free_chanspec_list;
595*4882a593Smuzhiyun 	uint16 cur_msch_timeslot_ptr;
596*4882a593Smuzhiyun 	uint16 next_timeslot_ptr;
597*4882a593Smuzhiyun 	uint32 p_cur_msch_timeslot;
598*4882a593Smuzhiyun 	uint32 p_next_timeslot;
599*4882a593Smuzhiyun 	uint32 cur_armed_timeslot;
600*4882a593Smuzhiyun 	uint32 flags;
601*4882a593Smuzhiyun 	uint32 ts_id;
602*4882a593Smuzhiyun 	uint32 service_interval;
603*4882a593Smuzhiyun 	uint32 max_lo_prio_interval;
604*4882a593Smuzhiyun 	uint16 flex_list_cnt;
605*4882a593Smuzhiyun 	uint16 msch_chanspec_alloc_cnt;
606*4882a593Smuzhiyun 	uint16 msch_req_entity_alloc_cnt;
607*4882a593Smuzhiyun 	uint16 msch_req_hdl_alloc_cnt;
608*4882a593Smuzhiyun 	uint16 msch_chan_ctxt_alloc_cnt;
609*4882a593Smuzhiyun 	uint16 msch_timeslot_alloc_cnt;
610*4882a593Smuzhiyun 	uint16 msch_req_hdl_list_cnt;
611*4882a593Smuzhiyun 	uint16 msch_req_hdl_list_ptr;
612*4882a593Smuzhiyun 	uint16 msch_chan_ctxt_list_cnt;
613*4882a593Smuzhiyun 	uint16 msch_chan_ctxt_list_ptr;
614*4882a593Smuzhiyun 	uint16 msch_req_timing_list_cnt;
615*4882a593Smuzhiyun 	uint16 msch_req_timing_list_ptr;
616*4882a593Smuzhiyun 	uint16 msch_start_fixed_list_cnt;
617*4882a593Smuzhiyun 	uint16 msch_start_fixed_list_ptr;
618*4882a593Smuzhiyun 	uint16 msch_both_flex_req_entity_list_cnt;
619*4882a593Smuzhiyun 	uint16 msch_both_flex_req_entity_list_ptr;
620*4882a593Smuzhiyun 	uint16 msch_start_flex_list_cnt;
621*4882a593Smuzhiyun 	uint16 msch_start_flex_list_ptr;
622*4882a593Smuzhiyun 	uint16 msch_both_flex_list_cnt;
623*4882a593Smuzhiyun 	uint16 msch_both_flex_list_ptr;
624*4882a593Smuzhiyun 	uint32 slotskip_flag;
625*4882a593Smuzhiyun } msch_profiler_profiler_event_data_t;
626*4882a593Smuzhiyun 
627*4882a593Smuzhiyun typedef struct msch_req_profiler_event_data {
628*4882a593Smuzhiyun 	uint32 time_lo;			/* Request time */
629*4882a593Smuzhiyun 	uint32 time_hi;
630*4882a593Smuzhiyun 	uint16 chanspec_cnt;
631*4882a593Smuzhiyun 	uint16 chanspec_ptr;
632*4882a593Smuzhiyun 	uint16 req_param_ptr;
633*4882a593Smuzhiyun 	uint16 pad;
634*4882a593Smuzhiyun } msch_req_profiler_event_data_t;
635*4882a593Smuzhiyun 
636*4882a593Smuzhiyun typedef struct msch_callback_profiler_event_data {
637*4882a593Smuzhiyun 	uint32 time_lo;			/* Request time */
638*4882a593Smuzhiyun 	uint32 time_hi;
639*4882a593Smuzhiyun 	uint16 type;			/* callback type */
640*4882a593Smuzhiyun 	uint16 chanspec;		/* actual chanspec, may different with requested one */
641*4882a593Smuzhiyun 	uint32 start_time_l;		/* time slot start time low 32bit */
642*4882a593Smuzhiyun 	uint32 start_time_h;		/* time slot start time high 32bit */
643*4882a593Smuzhiyun 	uint32 end_time_l;		/* time slot end time low 32 bit */
644*4882a593Smuzhiyun 	uint32 end_time_h;		/* time slot end time high 32 bit */
645*4882a593Smuzhiyun 	uint32 timeslot_id;		/* unique time slot id */
646*4882a593Smuzhiyun 	uint32 p_req_hdl;
647*4882a593Smuzhiyun 	uint32 onchan_idx;		/* Current channel index */
648*4882a593Smuzhiyun 	uint32 cur_chan_seq_start_time_l; /* start time of current sequence */
649*4882a593Smuzhiyun 	uint32 cur_chan_seq_start_time_h;
650*4882a593Smuzhiyun } msch_callback_profiler_event_data_t;
651*4882a593Smuzhiyun 
652*4882a593Smuzhiyun typedef struct msch_timeslot_profiler_event_data {
653*4882a593Smuzhiyun 	uint32 p_timeslot;
654*4882a593Smuzhiyun 	uint32 timeslot_id;
655*4882a593Smuzhiyun 	uint32 pre_start_time_l;
656*4882a593Smuzhiyun 	uint32 pre_start_time_h;
657*4882a593Smuzhiyun 	uint32 end_time_l;
658*4882a593Smuzhiyun 	uint32 end_time_h;
659*4882a593Smuzhiyun 	uint32 sch_dur_l;
660*4882a593Smuzhiyun 	uint32 sch_dur_h;
661*4882a593Smuzhiyun 	uint32 p_chan_ctxt;
662*4882a593Smuzhiyun 	uint32 fire_time_l;
663*4882a593Smuzhiyun 	uint32 fire_time_h;
664*4882a593Smuzhiyun 	uint32 state;
665*4882a593Smuzhiyun } msch_timeslot_profiler_event_data_t;
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun typedef struct msch_register_params	{
668*4882a593Smuzhiyun 	uint16 wlc_index;		/* Optional wlc index */
669*4882a593Smuzhiyun 	uint16 flags;			/* Describe various request properties */
670*4882a593Smuzhiyun 	uint32 req_type;		/* Describe start and end time flexiblilty */
671*4882a593Smuzhiyun 	uint16 id;			/* register id */
672*4882a593Smuzhiyun 	uint16 priority;		/* Define the request priority */
673*4882a593Smuzhiyun 	uint32 start_time;		/* Requested start time offset in ms unit */
674*4882a593Smuzhiyun 	uint32 duration;		/* Requested duration in ms unit */
675*4882a593Smuzhiyun 	uint32 interval;		/* Requested periodic interval in ms unit,
676*4882a593Smuzhiyun 					 * 0 means non-periodic
677*4882a593Smuzhiyun 					 */
678*4882a593Smuzhiyun 	uint32 dur_flex;		/* MSCH_REG_DUR_FLEX, min_dur = duration - dur_flex */
679*4882a593Smuzhiyun 	uint32 min_dur;			/* min duration for traffic, maps to home_time */
680*4882a593Smuzhiyun 	uint32 max_away_dur;		/* max acceptable away dur, maps to home_away_time */
681*4882a593Smuzhiyun 	uint32 hi_prio_time;
682*4882a593Smuzhiyun 	uint32 hi_prio_interval;	/* repeated high priority interval */
683*4882a593Smuzhiyun 	uint32 chanspec_cnt;
684*4882a593Smuzhiyun 	uint16 chanspec_list[WL_MSCH_NUMCHANNELS];
685*4882a593Smuzhiyun } msch_register_params_t;
686*4882a593Smuzhiyun 
687*4882a593Smuzhiyun typedef struct {
688*4882a593Smuzhiyun 	uint32	txallfrm;	/**< total number of frames sent, incl. Data, ACK, RTS, CTS,
689*4882a593Smuzhiyun 				* Control Management (includes retransmissions)
690*4882a593Smuzhiyun 				*/
691*4882a593Smuzhiyun 	uint32	rxrsptmout;	/**< number of response timeouts for transmitted frames
692*4882a593Smuzhiyun 				* expecting a response
693*4882a593Smuzhiyun 				*/
694*4882a593Smuzhiyun 	uint32	rxstrt;		/**< number of received frames with a good PLCP */
695*4882a593Smuzhiyun 	uint32  rxbadplcp;	/**< number of parity check of the PLCP header failed */
696*4882a593Smuzhiyun 	uint32  rxcrsglitch;	/**< PHY was able to correlate the preamble but not the header */
697*4882a593Smuzhiyun 	uint32  rxnodelim;	/**< number of no valid delimiter detected by ampdu parser */
698*4882a593Smuzhiyun 	uint32  bphy_badplcp;	/**< number of bad PLCP reception on BPHY rate */
699*4882a593Smuzhiyun 	uint32  bphy_rxcrsglitch;	/**< PHY count of bphy glitches */
700*4882a593Smuzhiyun 	uint32  rxbadfcs;	/**< number of frames for which the CRC check failed in the MAC */
701*4882a593Smuzhiyun 	uint32	rxanyerr;	/**< Any RX error that is not counted by other counters. */
702*4882a593Smuzhiyun 	uint32	rxbeaconmbss;	/**< beacons received from member of BSS */
703*4882a593Smuzhiyun 	uint32	rxdtucastmbss;	/**< number of received DATA frames with good FCS and matching RA */
704*4882a593Smuzhiyun 	uint32	rxdtocast;	/**< number of received DATA frames (good FCS and no matching RA) */
705*4882a593Smuzhiyun 	uint32  rxtoolate;	/**< receive too late */
706*4882a593Smuzhiyun 	uint32  goodfcs;        /**< Good fcs counters  */
707*4882a593Smuzhiyun 	uint32  rxf0ovfl;	/** < Rx FIFO0 overflow counters information */
708*4882a593Smuzhiyun 	uint32  rxf1ovfl;	/** < Rx FIFO1 overflow counters information */
709*4882a593Smuzhiyun } phy_periodic_counters_v1_t;
710*4882a593Smuzhiyun 
711*4882a593Smuzhiyun typedef struct phycal_log_cmn {
712*4882a593Smuzhiyun 	uint16 chanspec; /* Current phy chanspec */
713*4882a593Smuzhiyun 	uint8  last_cal_reason;  /* Last Cal Reason */
714*4882a593Smuzhiyun 	uint8  pad1;  /* Padding byte to align with word */
715*4882a593Smuzhiyun 	uint   last_cal_time; /* Last cal time in sec */
716*4882a593Smuzhiyun } phycal_log_cmn_t;
717*4882a593Smuzhiyun 
718*4882a593Smuzhiyun typedef struct phycal_log_core {
719*4882a593Smuzhiyun 	uint16 ofdm_txa; /* OFDM Tx IQ Cal a coeff */
720*4882a593Smuzhiyun 	uint16 ofdm_txb; /* OFDM Tx IQ Cal b coeff */
721*4882a593Smuzhiyun 	uint16 ofdm_txd; /* contain di & dq */
722*4882a593Smuzhiyun 	uint16 bphy_txa; /* BPHY Tx IQ Cal a coeff */
723*4882a593Smuzhiyun 	uint16 bphy_txb; /* BPHY Tx IQ Cal b coeff */
724*4882a593Smuzhiyun 	uint16 bphy_txd; /* contain di & dq */
725*4882a593Smuzhiyun 
726*4882a593Smuzhiyun 	uint16 rxa; /* Rx IQ Cal A coeffecient */
727*4882a593Smuzhiyun 	uint16 rxb; /* Rx IQ Cal B coeffecient */
728*4882a593Smuzhiyun 	int32 rxs;  /* FDIQ Slope coeffecient */
729*4882a593Smuzhiyun 
730*4882a593Smuzhiyun 	uint8 baseidx; /* TPC Base index */
731*4882a593Smuzhiyun 	uint8 adc_coeff_cap0_adcI; /* ADC CAP Cal Cap0 I */
732*4882a593Smuzhiyun 	uint8 adc_coeff_cap1_adcI; /* ADC CAP Cal Cap1 I */
733*4882a593Smuzhiyun 	uint8 adc_coeff_cap2_adcI; /* ADC CAP Cal Cap2 I */
734*4882a593Smuzhiyun 	uint8 adc_coeff_cap0_adcQ; /* ADC CAP Cal Cap0 Q */
735*4882a593Smuzhiyun 	uint8 adc_coeff_cap1_adcQ; /* ADC CAP Cal Cap1 Q */
736*4882a593Smuzhiyun 	uint8 adc_coeff_cap2_adcQ; /* ADC CAP Cal Cap2 Q */
737*4882a593Smuzhiyun 	uint8 pad; /* Padding byte to align with word */
738*4882a593Smuzhiyun } phycal_log_core_t;
739*4882a593Smuzhiyun 
740*4882a593Smuzhiyun #define PHYCAL_LOG_VER1         (1u)
741*4882a593Smuzhiyun 
742*4882a593Smuzhiyun typedef struct phycal_log_v1 {
743*4882a593Smuzhiyun 	uint8  version; /* Logging structure version */
744*4882a593Smuzhiyun 	uint8  numcores; /* Numbe of cores for which core specific data present */
745*4882a593Smuzhiyun 	uint16 length;  /* Length of the entire structure */
746*4882a593Smuzhiyun 	phycal_log_cmn_t phycal_log_cmn; /* Logging common structure */
747*4882a593Smuzhiyun 	/* This will be a variable length based on the numcores field defined above */
748*4882a593Smuzhiyun 	phycal_log_core_t phycal_log_core[1];
749*4882a593Smuzhiyun } phycal_log_v1_t;
750*4882a593Smuzhiyun 
751*4882a593Smuzhiyun typedef struct phy_periodic_log_cmn {
752*4882a593Smuzhiyun 	uint16  chanspec; /* Current phy chanspec */
753*4882a593Smuzhiyun 	uint16  vbatmeas; /* Measured VBAT sense value */
754*4882a593Smuzhiyun 	uint16  featureflag; /* Currently active feature flags */
755*4882a593Smuzhiyun 	int8    chiptemp; /* Chip temparature */
756*4882a593Smuzhiyun 	int8    femtemp;  /* Fem temparature */
757*4882a593Smuzhiyun 
758*4882a593Smuzhiyun 	uint32  nrate; /* Current Tx nrate */
759*4882a593Smuzhiyun 
760*4882a593Smuzhiyun 	uint8   cal_phase_id; /* Current Multi phase cal ID */
761*4882a593Smuzhiyun 	uint8   rxchain; /* Rx Chain */
762*4882a593Smuzhiyun 	uint8   txchain; /* Tx Chain */
763*4882a593Smuzhiyun 	uint8   ofdm_desense; /* OFDM desense */
764*4882a593Smuzhiyun 
765*4882a593Smuzhiyun 	uint8   bphy_desense; /* BPHY desense */
766*4882a593Smuzhiyun 	uint8   pll_lockstatus; /* PLL Lock status */
767*4882a593Smuzhiyun 	uint8   pad1; /* Padding byte to align with word */
768*4882a593Smuzhiyun 	uint8   pad2; /* Padding byte to align with word */
769*4882a593Smuzhiyun 
770*4882a593Smuzhiyun 	uint32 duration;	/**< millisecs spent sampling this channel */
771*4882a593Smuzhiyun 	uint32 congest_ibss;	/**< millisecs in our bss (presumably this traffic will */
772*4882a593Smuzhiyun 				/**<  move if cur bss moves channels) */
773*4882a593Smuzhiyun 	uint32 congest_obss;	/**< traffic not in our bss */
774*4882a593Smuzhiyun 	uint32 interference;	/**< millisecs detecting a non 802.11 interferer. */
775*4882a593Smuzhiyun 
776*4882a593Smuzhiyun } phy_periodic_log_cmn_t;
777*4882a593Smuzhiyun 
778*4882a593Smuzhiyun typedef struct phy_periodic_log_core {
779*4882a593Smuzhiyun 	uint8	baseindxval; /* TPC Base index */
780*4882a593Smuzhiyun 	int8	tgt_pwr; /* Programmed Target power */
781*4882a593Smuzhiyun 	int8	estpwradj; /* Current Est Power Adjust value */
782*4882a593Smuzhiyun 	int8	crsmin_pwr; /* CRS Min/Noise power */
783*4882a593Smuzhiyun 	int8	rssi_per_ant; /* RSSI Per antenna */
784*4882a593Smuzhiyun 	int8	snr_per_ant; /* SNR Per antenna */
785*4882a593Smuzhiyun 	int8	pad1; /* Padding byte to align with word */
786*4882a593Smuzhiyun 	int8	pad2; /* Padding byte to align with word */
787*4882a593Smuzhiyun } phy_periodic_log_core_t;
788*4882a593Smuzhiyun 
789*4882a593Smuzhiyun #define PHY_PERIODIC_LOG_VER1         (1u)
790*4882a593Smuzhiyun 
791*4882a593Smuzhiyun typedef struct phy_periodic_log_v1 {
792*4882a593Smuzhiyun 	uint8  version; /* Logging structure version */
793*4882a593Smuzhiyun 	uint8  numcores; /* Numbe of cores for which core specific data present */
794*4882a593Smuzhiyun 	uint16 length;  /* Length of the entire structure */
795*4882a593Smuzhiyun 	phy_periodic_log_cmn_t phy_perilog_cmn;
796*4882a593Smuzhiyun 	phy_periodic_counters_v1_t counters_peri_log;
797*4882a593Smuzhiyun 	/* This will be a variable length based on the numcores field defined above */
798*4882a593Smuzhiyun 	phy_periodic_log_core_t phy_perilog_core[1];
799*4882a593Smuzhiyun } phy_periodic_log_v1_t;
800*4882a593Smuzhiyun 
801*4882a593Smuzhiyun #endif /* _EVENT_LOG_PAYLOAD_H_ */
802