1 /* 2 * Table that encodes the srom formats for PCI/PCIe NICs. 3 * 4 * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation 5 * 6 * Copyright (C) 1999-2017, Broadcom Corporation 7 * 8 * Unless you and Broadcom execute a separate written software license 9 * agreement governing use of this software, this software is licensed to you 10 * under the terms of the GNU General Public License version 2 (the "GPL"), 11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12 * following added to such license: 13 * 14 * As a special exception, the copyright holders of this software give you 15 * permission to link this software with independent modules, and to copy and 16 * distribute the resulting executable under terms of your choice, provided that 17 * you also meet, for each linked independent module, the terms and conditions of 18 * the license of that module. An independent module is a module which is not 19 * derived from this software. The special exception does not apply to any 20 * modifications of the software. 21 * 22 * Notwithstanding the above, under no circumstances may you combine this 23 * software in any way with any other Broadcom software provided under a license 24 * other than the GPL, without Broadcom's express prior written consent. 25 * 26 * 27 * <<Broadcom-WL-IPTag/Open:>> 28 * 29 * $Id: bcmsrom_tbl.h 700323 2017-05-18 16:12:11Z $ 30 */ 31 32 #ifndef _bcmsrom_tbl_h_ 33 #define _bcmsrom_tbl_h_ 34 35 #include "sbpcmcia.h" 36 #include "wlioctl.h" 37 #include <bcmsrom_fmt.h> 38 39 typedef struct { 40 const char *name; 41 uint32 revmask; 42 uint32 flags; 43 uint16 off; 44 uint16 mask; 45 } sromvar_t; 46 47 #define SRFL_MORE 1 /* value continues as described by the next entry */ 48 #define SRFL_NOFFS 2 /* value bits can't be all one's */ 49 #define SRFL_PRHEX 4 /* value is in hexdecimal format */ 50 #define SRFL_PRSIGN 8 /* value is in signed decimal format */ 51 #define SRFL_CCODE 0x10 /* value is in country code format */ 52 #define SRFL_ETHADDR 0x20 /* value is an Ethernet address */ 53 #define SRFL_LEDDC 0x40 /* value is an LED duty cycle */ 54 #define SRFL_NOVAR 0x80 /* do not generate a nvram param, entry is for mfgc */ 55 #define SRFL_ARRAY 0x100 /* value is in an array. All elements EXCEPT FOR THE LAST 56 * ONE in the array should have this flag set. 57 */ 58 #define PRHEX_N_MORE (SRFL_PRHEX | SRFL_MORE) 59 60 #define SROM_DEVID_PCIE 48 61 62 /** 63 * Assumptions: 64 * - Ethernet address spans across 3 consecutive words 65 * 66 * Table rules: 67 * - Add multiple entries next to each other if a value spans across multiple words 68 * (even multiple fields in the same word) with each entry except the last having 69 * it's SRFL_MORE bit set. 70 * - Ethernet address entry does not follow above rule and must not have SRFL_MORE 71 * bit set. Its SRFL_ETHADDR bit implies it takes multiple words. 72 * - The last entry's name field must be NULL to indicate the end of the table. Other 73 * entries must have non-NULL name. 74 */ 75 #if !defined(SROM15_MEMOPT) 76 static const sromvar_t pci_sromvars[] = { 77 /* name revmask flags off mask */ 78 #if defined(CABLECPE) 79 {"devid", 0xffffff00, SRFL_PRHEX, PCI_F0DEVID, 0xffff}, 80 #elif defined(BCMPCIEDEV) && defined(BCMPCIEDEV_ENABLED) 81 {"devid", 0xffffff00, SRFL_PRHEX, SROM_DEVID_PCIE, 0xffff}, 82 #else 83 {"devid", 0xffffff00, SRFL_PRHEX|SRFL_NOVAR, PCI_F0DEVID, 0xffff}, 84 #endif // endif 85 {"boardrev", 0x0000000e, SRFL_PRHEX, SROM_AABREV, SROM_BR_MASK}, 86 {"boardrev", 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff}, 87 {"boardrev", 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff}, 88 {"boardflags", 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff}, 89 {"boardflags", 0x00000004, SRFL_PRHEX|SRFL_MORE, SROM_BFL, 0xffff}, 90 {"", 0, 0, SROM_BFL2, 0xffff}, 91 {"boardflags", 0x00000008, SRFL_PRHEX|SRFL_MORE, SROM_BFL, 0xffff}, 92 {"", 0, 0, SROM3_BFL2, 0xffff}, 93 {"boardflags", 0x00000010, SRFL_PRHEX|SRFL_MORE, SROM4_BFL0, 0xffff}, 94 {"", 0, 0, SROM4_BFL1, 0xffff}, 95 {"boardflags", 0x000000e0, SRFL_PRHEX|SRFL_MORE, SROM5_BFL0, 0xffff}, 96 {"", 0, 0, SROM5_BFL1, 0xffff}, 97 {"boardflags", 0xffffff00, SRFL_PRHEX|SRFL_MORE, SROM8_BFL0, 0xffff}, 98 {"", 0, 0, SROM8_BFL1, 0xffff}, 99 {"boardflags2", 0x00000010, SRFL_PRHEX|SRFL_MORE, SROM4_BFL2, 0xffff}, 100 {"", 0, 0, SROM4_BFL3, 0xffff}, 101 {"boardflags2", 0x000000e0, SRFL_PRHEX|SRFL_MORE, SROM5_BFL2, 0xffff}, 102 {"", 0, 0, SROM5_BFL3, 0xffff}, 103 {"boardflags2", 0xffffff00, SRFL_PRHEX|SRFL_MORE, SROM8_BFL2, 0xffff}, 104 {"", 0, 0, SROM8_BFL3, 0xffff}, 105 {"boardtype", 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff}, 106 {"subvid", 0xfffffffc, SRFL_PRHEX, SROM_SVID, 0xffff}, 107 {"boardnum", 0x00000006, 0, SROM_MACLO_IL0, 0xffff}, 108 {"boardnum", 0x00000008, 0, SROM3_MACLO, 0xffff}, 109 {"boardnum", 0x00000010, 0, SROM4_MACLO, 0xffff}, 110 {"boardnum", 0x000000e0, 0, SROM5_MACLO, 0xffff}, 111 {"boardnum", 0x00000700, 0, SROM8_MACLO, 0xffff}, 112 {"cc", 0x00000002, 0, SROM_AABREV, SROM_CC_MASK}, 113 {"regrev", 0x00000008, 0, SROM_OPO, 0xff00}, 114 {"regrev", 0x00000010, 0, SROM4_REGREV, 0xffff}, 115 {"regrev", 0x000000e0, 0, SROM5_REGREV, 0xffff}, 116 {"regrev", 0x00000700, 0, SROM8_REGREV, 0xffff}, 117 {"ledbh0", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0x00ff}, 118 {"ledbh1", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00}, 119 {"ledbh2", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0x00ff}, 120 {"ledbh3", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00}, 121 {"ledbh0", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0x00ff}, 122 {"ledbh1", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00}, 123 {"ledbh2", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0x00ff}, 124 {"ledbh3", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00}, 125 {"ledbh0", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0x00ff}, 126 {"ledbh1", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00}, 127 {"ledbh2", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0x00ff}, 128 {"ledbh3", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00}, 129 {"ledbh0", 0x00000700, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff}, 130 {"ledbh1", 0x00000700, SRFL_NOFFS, SROM8_LEDBH10, 0xff00}, 131 {"ledbh2", 0x00000700, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff}, 132 {"ledbh3", 0x00000700, SRFL_NOFFS, SROM8_LEDBH32, 0xff00}, 133 {"pa0b0", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff}, 134 {"pa0b1", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff}, 135 {"pa0b2", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff}, 136 {"pa0itssit", 0x0000000e, 0, SROM_ITT, 0x00ff}, 137 {"pa0maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0x00ff}, 138 {"pa0b0", 0x00000700, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff}, 139 {"pa0b1", 0x00000700, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff}, 140 {"pa0b2", 0x00000700, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff}, 141 {"pa0itssit", 0x00000700, 0, SROM8_W0_ITTMAXP, 0xff00}, 142 {"pa0maxpwr", 0x00000700, 0, SROM8_W0_ITTMAXP, 0x00ff}, 143 {"opo", 0x0000000c, 0, SROM_OPO, 0x00ff}, 144 {"opo", 0x00000700, 0, SROM8_2G_OFDMPO, 0x00ff}, 145 {"aa2g", 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK}, 146 {"aa2g", 0x000000f0, 0, SROM4_AA, 0x00ff}, 147 {"aa2g", 0x00000700, 0, SROM8_AA, 0x00ff}, 148 {"aa5g", 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK}, 149 {"aa5g", 0x000000f0, 0, SROM4_AA, 0xff00}, 150 {"aa5g", 0x00000700, 0, SROM8_AA, 0xff00}, 151 {"ag0", 0x0000000e, 0, SROM_AG10, 0x00ff}, 152 {"ag1", 0x0000000e, 0, SROM_AG10, 0xff00}, 153 {"ag0", 0x000000f0, 0, SROM4_AG10, 0x00ff}, 154 {"ag1", 0x000000f0, 0, SROM4_AG10, 0xff00}, 155 {"ag2", 0x000000f0, 0, SROM4_AG32, 0x00ff}, 156 {"ag3", 0x000000f0, 0, SROM4_AG32, 0xff00}, 157 {"ag0", 0x00000700, 0, SROM8_AG10, 0x00ff}, 158 {"ag1", 0x00000700, 0, SROM8_AG10, 0xff00}, 159 {"ag2", 0x00000700, 0, SROM8_AG32, 0x00ff}, 160 {"ag3", 0x00000700, 0, SROM8_AG32, 0xff00}, 161 {"pa1b0", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff}, 162 {"pa1b1", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff}, 163 {"pa1b2", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff}, 164 {"pa1lob0", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff}, 165 {"pa1lob1", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff}, 166 {"pa1lob2", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff}, 167 {"pa1hib0", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff}, 168 {"pa1hib1", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff}, 169 {"pa1hib2", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff}, 170 {"pa1itssit", 0x0000000e, 0, SROM_ITT, 0xff00}, 171 {"pa1maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0xff00}, 172 {"pa1lomaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00}, 173 {"pa1himaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff}, 174 {"pa1b0", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff}, 175 {"pa1b1", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff}, 176 {"pa1b2", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff}, 177 {"pa1lob0", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff}, 178 {"pa1lob1", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff}, 179 {"pa1lob2", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff}, 180 {"pa1hib0", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff}, 181 {"pa1hib1", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff}, 182 {"pa1hib2", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff}, 183 {"pa1itssit", 0x00000700, 0, SROM8_W1_ITTMAXP, 0xff00}, 184 {"pa1maxpwr", 0x00000700, 0, SROM8_W1_ITTMAXP, 0x00ff}, 185 {"pa1lomaxpwr", 0x00000700, 0, SROM8_W1_MAXP_LCHC, 0xff00}, 186 {"pa1himaxpwr", 0x00000700, 0, SROM8_W1_MAXP_LCHC, 0x00ff}, 187 {"bxa2g", 0x00000008, 0, SROM_BXARSSI2G, 0x1800}, 188 {"rssisav2g", 0x00000008, 0, SROM_BXARSSI2G, 0x0700}, 189 {"rssismc2g", 0x00000008, 0, SROM_BXARSSI2G, 0x00f0}, 190 {"rssismf2g", 0x00000008, 0, SROM_BXARSSI2G, 0x000f}, 191 {"bxa2g", 0x00000700, 0, SROM8_BXARSSI2G, 0x1800}, 192 {"rssisav2g", 0x00000700, 0, SROM8_BXARSSI2G, 0x0700}, 193 {"rssismc2g", 0x00000700, 0, SROM8_BXARSSI2G, 0x00f0}, 194 {"rssismf2g", 0x00000700, 0, SROM8_BXARSSI2G, 0x000f}, 195 {"bxa5g", 0x00000008, 0, SROM_BXARSSI5G, 0x1800}, 196 {"rssisav5g", 0x00000008, 0, SROM_BXARSSI5G, 0x0700}, 197 {"rssismc5g", 0x00000008, 0, SROM_BXARSSI5G, 0x00f0}, 198 {"rssismf5g", 0x00000008, 0, SROM_BXARSSI5G, 0x000f}, 199 {"bxa5g", 0x00000700, 0, SROM8_BXARSSI5G, 0x1800}, 200 {"rssisav5g", 0x00000700, 0, SROM8_BXARSSI5G, 0x0700}, 201 {"rssismc5g", 0x00000700, 0, SROM8_BXARSSI5G, 0x00f0}, 202 {"rssismf5g", 0x00000700, 0, SROM8_BXARSSI5G, 0x000f}, 203 {"tri2g", 0x00000008, 0, SROM_TRI52G, 0x00ff}, 204 {"tri5g", 0x00000008, 0, SROM_TRI52G, 0xff00}, 205 {"tri5gl", 0x00000008, 0, SROM_TRI5GHL, 0x00ff}, 206 {"tri5gh", 0x00000008, 0, SROM_TRI5GHL, 0xff00}, 207 {"tri2g", 0x00000700, 0, SROM8_TRI52G, 0x00ff}, 208 {"tri5g", 0x00000700, 0, SROM8_TRI52G, 0xff00}, 209 {"tri5gl", 0x00000700, 0, SROM8_TRI5GHL, 0x00ff}, 210 {"tri5gh", 0x00000700, 0, SROM8_TRI5GHL, 0xff00}, 211 {"rxpo2g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff}, 212 {"rxpo5g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00}, 213 {"rxpo2g", 0x00000700, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff}, 214 {"rxpo5g", 0x00000700, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00}, 215 {"txchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_TXCHAIN_MASK}, 216 {"rxchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_RXCHAIN_MASK}, 217 {"antswitch", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_SWITCH_MASK}, 218 {"txchain", 0x00000700, SRFL_NOFFS, SROM8_TXRXC, SROM4_TXCHAIN_MASK}, 219 {"rxchain", 0x00000700, SRFL_NOFFS, SROM8_TXRXC, SROM4_RXCHAIN_MASK}, 220 {"antswitch", 0x00000700, SRFL_NOFFS, SROM8_TXRXC, SROM4_SWITCH_MASK}, 221 {"tssipos2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_TSSIPOS_MASK}, 222 {"extpagain2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_EXTPA_GAIN_MASK}, 223 {"pdetrange2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_PDET_RANGE_MASK}, 224 {"triso2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK}, 225 {"antswctl2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_ANTSWLUT_MASK}, 226 {"tssipos5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_TSSIPOS_MASK}, 227 {"extpagain5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_EXTPA_GAIN_MASK}, 228 {"pdetrange5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_PDET_RANGE_MASK}, 229 {"triso5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK}, 230 {"antswctl5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_ANTSWLUT_MASK}, 231 {"txpid2ga0", 0x000000f0, 0, SROM4_TXPID2G, 0x00ff}, 232 {"txpid2ga1", 0x000000f0, 0, SROM4_TXPID2G, 0xff00}, 233 {"txpid2ga2", 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff}, 234 {"txpid2ga3", 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00}, 235 {"txpid5ga0", 0x000000f0, 0, SROM4_TXPID5G, 0x00ff}, 236 {"txpid5ga1", 0x000000f0, 0, SROM4_TXPID5G, 0xff00}, 237 {"txpid5ga2", 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff}, 238 {"txpid5ga3", 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00}, 239 {"txpid5gla0", 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff}, 240 {"txpid5gla1", 0x000000f0, 0, SROM4_TXPID5GL, 0xff00}, 241 {"txpid5gla2", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff}, 242 {"txpid5gla3", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00}, 243 {"txpid5gha0", 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff}, 244 {"txpid5gha1", 0x000000f0, 0, SROM4_TXPID5GH, 0xff00}, 245 {"txpid5gha2", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff}, 246 {"txpid5gha3", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00}, 247 248 {"ccode", 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff}, 249 {"ccode", 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff}, 250 {"ccode", 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff}, 251 {"ccode", 0x00000700, SRFL_CCODE, SROM8_CCODE, 0xffff}, 252 {"macaddr", 0x00000700, SRFL_ETHADDR, SROM8_MACHI, 0xffff}, 253 {"macaddr", 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff}, 254 {"macaddr", 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff}, 255 {"macaddr", 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff}, 256 {"il0macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0, 0xffff}, 257 {"et1macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1, 0xffff}, 258 {"leddc", 0x00000700, SRFL_NOFFS|SRFL_LEDDC, SROM8_LEDDC, 0xffff}, 259 {"leddc", 0x000000e0, SRFL_NOFFS|SRFL_LEDDC, SROM5_LEDDC, 0xffff}, 260 {"leddc", 0x00000010, SRFL_NOFFS|SRFL_LEDDC, SROM4_LEDDC, 0xffff}, 261 {"leddc", 0x00000008, SRFL_NOFFS|SRFL_LEDDC, SROM3_LEDDC, 0xffff}, 262 263 {"tempthresh", 0x00000700, 0, SROM8_THERMAL, 0xff00}, 264 {"tempoffset", 0x00000700, 0, SROM8_THERMAL, 0x00ff}, 265 {"rawtempsense", 0x00000700, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0x01ff}, 266 {"measpower", 0x00000700, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0xfe00}, 267 {"tempsense_slope", 0x00000700, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0x00ff}, 268 {"tempcorrx", 0x00000700, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0xfc00}, 269 {"tempsense_option", 0x00000700, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0x0300}, 270 {"freqoffset_corr", 0x00000700, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x000f}, 271 {"iqcal_swp_dis", 0x00000700, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0010}, 272 {"hw_iqcal_en", 0x00000700, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0020}, 273 {"elna2g", 0x00000700, 0, SROM8_EXTLNAGAIN, 0x00ff}, 274 {"elna5g", 0x00000700, 0, SROM8_EXTLNAGAIN, 0xff00}, 275 {"phycal_tempdelta", 0x00000700, 0, SROM8_PHYCAL_TEMPDELTA, 0x00ff}, 276 {"temps_period", 0x00000700, 0, SROM8_PHYCAL_TEMPDELTA, 0x0f00}, 277 {"temps_hysteresis", 0x00000700, 0, SROM8_PHYCAL_TEMPDELTA, 0xf000}, 278 {"measpower1", 0x00000700, SRFL_PRHEX, SROM8_MPWR_1_AND_2, 0x007f}, 279 {"measpower2", 0x00000700, SRFL_PRHEX, SROM8_MPWR_1_AND_2, 0x3f80}, 280 281 {"cck2gpo", 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff}, 282 {"cck2gpo", 0x00000100, 0, SROM8_2G_CCKPO, 0xffff}, 283 {"ofdm2gpo", 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff}, 284 {"", 0, 0, SROM4_2G_OFDMPO + 1, 0xffff}, 285 {"ofdm5gpo", 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff}, 286 {"", 0, 0, SROM4_5G_OFDMPO + 1, 0xffff}, 287 {"ofdm5glpo", 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff}, 288 {"", 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff}, 289 {"ofdm5ghpo", 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff}, 290 {"", 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff}, 291 {"ofdm2gpo", 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff}, 292 {"", 0, 0, SROM8_2G_OFDMPO + 1, 0xffff}, 293 {"ofdm5gpo", 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff}, 294 {"", 0, 0, SROM8_5G_OFDMPO + 1, 0xffff}, 295 {"ofdm5glpo", 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff}, 296 {"", 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff}, 297 {"ofdm5ghpo", 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff}, 298 {"", 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff}, 299 {"mcs2gpo0", 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff}, 300 {"mcs2gpo1", 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff}, 301 {"mcs2gpo2", 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff}, 302 {"mcs2gpo3", 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff}, 303 {"mcs2gpo4", 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff}, 304 {"mcs2gpo5", 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff}, 305 {"mcs2gpo6", 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff}, 306 {"mcs2gpo7", 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff}, 307 {"mcs5gpo0", 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff}, 308 {"mcs5gpo1", 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff}, 309 {"mcs5gpo2", 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff}, 310 {"mcs5gpo3", 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff}, 311 {"mcs5gpo4", 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff}, 312 {"mcs5gpo5", 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff}, 313 {"mcs5gpo6", 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff}, 314 {"mcs5gpo7", 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff}, 315 {"mcs5glpo0", 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff}, 316 {"mcs5glpo1", 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff}, 317 {"mcs5glpo2", 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff}, 318 {"mcs5glpo3", 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff}, 319 {"mcs5glpo4", 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff}, 320 {"mcs5glpo5", 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff}, 321 {"mcs5glpo6", 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff}, 322 {"mcs5glpo7", 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff}, 323 {"mcs5ghpo0", 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff}, 324 {"mcs5ghpo1", 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff}, 325 {"mcs5ghpo2", 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff}, 326 {"mcs5ghpo3", 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff}, 327 {"mcs5ghpo4", 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff}, 328 {"mcs5ghpo5", 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff}, 329 {"mcs5ghpo6", 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff}, 330 {"mcs5ghpo7", 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff}, 331 {"mcs2gpo0", 0x00000100, 0, SROM8_2G_MCSPO, 0xffff}, 332 {"mcs2gpo1", 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff}, 333 {"mcs2gpo2", 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff}, 334 {"mcs2gpo3", 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff}, 335 {"mcs2gpo4", 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff}, 336 {"mcs2gpo5", 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff}, 337 {"mcs2gpo6", 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff}, 338 {"mcs2gpo7", 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff}, 339 {"mcs5gpo0", 0x00000100, 0, SROM8_5G_MCSPO, 0xffff}, 340 {"mcs5gpo1", 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff}, 341 {"mcs5gpo2", 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff}, 342 {"mcs5gpo3", 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff}, 343 {"mcs5gpo4", 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff}, 344 {"mcs5gpo5", 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff}, 345 {"mcs5gpo6", 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff}, 346 {"mcs5gpo7", 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff}, 347 {"mcs5glpo0", 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff}, 348 {"mcs5glpo1", 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff}, 349 {"mcs5glpo2", 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff}, 350 {"mcs5glpo3", 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff}, 351 {"mcs5glpo4", 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff}, 352 {"mcs5glpo5", 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff}, 353 {"mcs5glpo6", 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff}, 354 {"mcs5glpo7", 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff}, 355 {"mcs5ghpo0", 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff}, 356 {"mcs5ghpo1", 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff}, 357 {"mcs5ghpo2", 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff}, 358 {"mcs5ghpo3", 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff}, 359 {"mcs5ghpo4", 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff}, 360 {"mcs5ghpo5", 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff}, 361 {"mcs5ghpo6", 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff}, 362 {"mcs5ghpo7", 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff}, 363 {"cddpo", 0x000000f0, 0, SROM4_CDDPO, 0xffff}, 364 {"stbcpo", 0x000000f0, 0, SROM4_STBCPO, 0xffff}, 365 {"bw40po", 0x000000f0, 0, SROM4_BW40PO, 0xffff}, 366 {"bwduppo", 0x000000f0, 0, SROM4_BWDUPPO, 0xffff}, 367 {"cddpo", 0x00000100, 0, SROM8_CDDPO, 0xffff}, 368 {"stbcpo", 0x00000100, 0, SROM8_STBCPO, 0xffff}, 369 {"bw40po", 0x00000100, 0, SROM8_BW40PO, 0xffff}, 370 {"bwduppo", 0x00000100, 0, SROM8_BWDUPPO, 0xffff}, 371 372 /* power per rate from sromrev 9 */ 373 {"cckbw202gpo", 0x00000600, 0, SROM9_2GPO_CCKBW20, 0xffff}, 374 {"cckbw20ul2gpo", 0x00000600, 0, SROM9_2GPO_CCKBW20UL, 0xffff}, 375 {"legofdmbw202gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_LOFDMBW20, 0xffff}, 376 {"", 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff}, 377 {"legofdmbw20ul2gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_LOFDMBW20UL, 0xffff}, 378 {"", 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff}, 379 {"legofdmbw205glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_LOFDMBW20, 0xffff}, 380 {"", 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff}, 381 {"legofdmbw20ul5glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_LOFDMBW20UL, 0xffff}, 382 {"", 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff}, 383 {"legofdmbw205gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_LOFDMBW20, 0xffff}, 384 {"", 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff}, 385 {"legofdmbw20ul5gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_LOFDMBW20UL, 0xffff}, 386 {"", 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff}, 387 {"legofdmbw205ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_LOFDMBW20, 0xffff}, 388 {"", 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff}, 389 {"legofdmbw20ul5ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_LOFDMBW20UL, 0xffff}, 390 {"", 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff}, 391 {"mcsbw202gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_MCSBW20, 0xffff}, 392 {"", 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff}, 393 {"mcsbw20ul2gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_MCSBW20UL, 0xffff}, 394 {"", 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff}, 395 {"mcsbw402gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_MCSBW40, 0xffff}, 396 {"", 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff}, 397 {"mcsbw205glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_MCSBW20, 0xffff}, 398 {"", 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff}, 399 {"mcsbw20ul5glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_MCSBW20UL, 0xffff}, 400 {"", 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff}, 401 {"mcsbw405glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_MCSBW40, 0xffff}, 402 {"", 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff}, 403 {"mcsbw205gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_MCSBW20, 0xffff}, 404 {"", 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff}, 405 {"mcsbw20ul5gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_MCSBW20UL, 0xffff}, 406 {"", 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff}, 407 {"mcsbw405gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_MCSBW40, 0xffff}, 408 {"", 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff}, 409 {"mcsbw205ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_MCSBW20, 0xffff}, 410 {"", 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff}, 411 {"mcsbw20ul5ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_MCSBW20UL, 0xffff}, 412 {"", 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff}, 413 {"mcsbw405ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_MCSBW40, 0xffff}, 414 {"", 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff}, 415 {"mcs32po", 0x00000600, 0, SROM9_PO_MCS32, 0xffff}, 416 {"legofdm40duppo", 0x00000600, 0, SROM9_PO_LOFDM40DUP, 0xffff}, 417 {"pcieingress_war", 0x00000700, 0, SROM8_PCIEINGRESS_WAR, 0xf}, 418 {"eu_edthresh2g", 0x00000100, 0, SROM8_EU_EDCRSTH, 0x00ff}, 419 {"eu_edthresh5g", 0x00000100, 0, SROM8_EU_EDCRSTH, 0xff00}, 420 {"eu_edthresh2g", 0x00000200, 0, SROM9_EU_EDCRSTH, 0x00ff}, 421 {"eu_edthresh5g", 0x00000200, 0, SROM9_EU_EDCRSTH, 0xff00}, 422 {"rxgainerr2ga0", 0x00000700, 0, SROM8_RXGAINERR_2G, 0x003f}, 423 {"rxgainerr2ga0", 0x00000700, 0, SROM8_RXGAINERR_2G, 0x003f}, 424 {"rxgainerr2ga1", 0x00000700, 0, SROM8_RXGAINERR_2G, 0x07c0}, 425 {"rxgainerr2ga2", 0x00000700, 0, SROM8_RXGAINERR_2G, 0xf800}, 426 {"rxgainerr5gla0", 0x00000700, 0, SROM8_RXGAINERR_5GL, 0x003f}, 427 {"rxgainerr5gla1", 0x00000700, 0, SROM8_RXGAINERR_5GL, 0x07c0}, 428 {"rxgainerr5gla2", 0x00000700, 0, SROM8_RXGAINERR_5GL, 0xf800}, 429 {"rxgainerr5gma0", 0x00000700, 0, SROM8_RXGAINERR_5GM, 0x003f}, 430 {"rxgainerr5gma1", 0x00000700, 0, SROM8_RXGAINERR_5GM, 0x07c0}, 431 {"rxgainerr5gma2", 0x00000700, 0, SROM8_RXGAINERR_5GM, 0xf800}, 432 {"rxgainerr5gha0", 0x00000700, 0, SROM8_RXGAINERR_5GH, 0x003f}, 433 {"rxgainerr5gha1", 0x00000700, 0, SROM8_RXGAINERR_5GH, 0x07c0}, 434 {"rxgainerr5gha2", 0x00000700, 0, SROM8_RXGAINERR_5GH, 0xf800}, 435 {"rxgainerr5gua0", 0x00000700, 0, SROM8_RXGAINERR_5GU, 0x003f}, 436 {"rxgainerr5gua1", 0x00000700, 0, SROM8_RXGAINERR_5GU, 0x07c0}, 437 {"rxgainerr5gua2", 0x00000700, 0, SROM8_RXGAINERR_5GU, 0xf800}, 438 {"sar2g", 0x00000600, 0, SROM9_SAR, 0x00ff}, 439 {"sar5g", 0x00000600, 0, SROM9_SAR, 0xff00}, 440 {"noiselvl2ga0", 0x00000700, 0, SROM8_NOISELVL_2G, 0x001f}, 441 {"noiselvl2ga1", 0x00000700, 0, SROM8_NOISELVL_2G, 0x03e0}, 442 {"noiselvl2ga2", 0x00000700, 0, SROM8_NOISELVL_2G, 0x7c00}, 443 {"noiselvl5gla0", 0x00000700, 0, SROM8_NOISELVL_5GL, 0x001f}, 444 {"noiselvl5gla1", 0x00000700, 0, SROM8_NOISELVL_5GL, 0x03e0}, 445 {"noiselvl5gla2", 0x00000700, 0, SROM8_NOISELVL_5GL, 0x7c00}, 446 {"noiselvl5gma0", 0x00000700, 0, SROM8_NOISELVL_5GM, 0x001f}, 447 {"noiselvl5gma1", 0x00000700, 0, SROM8_NOISELVL_5GM, 0x03e0}, 448 {"noiselvl5gma2", 0x00000700, 0, SROM8_NOISELVL_5GM, 0x7c00}, 449 {"noiselvl5gha0", 0x00000700, 0, SROM8_NOISELVL_5GH, 0x001f}, 450 {"noiselvl5gha1", 0x00000700, 0, SROM8_NOISELVL_5GH, 0x03e0}, 451 {"noiselvl5gha2", 0x00000700, 0, SROM8_NOISELVL_5GH, 0x7c00}, 452 {"noiselvl5gua0", 0x00000700, 0, SROM8_NOISELVL_5GU, 0x001f}, 453 {"noiselvl5gua1", 0x00000700, 0, SROM8_NOISELVL_5GU, 0x03e0}, 454 {"noiselvl5gua2", 0x00000700, 0, SROM8_NOISELVL_5GU, 0x7c00}, 455 {"noisecaloffset", 0x00000300, 0, SROM8_NOISECALOFFSET, 0x00ff}, 456 {"noisecaloffset5g", 0x00000300, 0, SROM8_NOISECALOFFSET, 0xff00}, 457 {"subband5gver", 0x00000700, 0, SROM8_SUBBAND_PPR, 0x7}, 458 459 {"cckPwrOffset", 0x00000400, 0, SROM10_CCKPWROFFSET, 0xffff}, 460 {"eu_edthresh2g", 0x00000400, 0, SROM10_EU_EDCRSTH, 0x00ff}, 461 {"eu_edthresh5g", 0x00000400, 0, SROM10_EU_EDCRSTH, 0xff00}, 462 /* swctrlmap_2g array, note that the last element doesn't have SRFL_ARRAY flag set */ 463 {"swctrlmap_2g", 0x00000400, SRFL_MORE|SRFL_PRHEX|SRFL_ARRAY, SROM10_SWCTRLMAP_2G, 0xffff}, 464 {"", 0x00000400, SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 1, 0xffff}, 465 {"", 0x00000400, SRFL_MORE|SRFL_PRHEX|SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 2, 0xffff}, 466 {"", 0x00000400, SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 3, 0xffff}, 467 {"", 0x00000400, SRFL_MORE|SRFL_PRHEX|SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 4, 0xffff}, 468 {"", 0x00000400, SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 5, 0xffff}, 469 {"", 0x00000400, SRFL_MORE|SRFL_PRHEX|SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 6, 0xffff}, 470 {"", 0x00000400, SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 7, 0xffff}, 471 {"", 0x00000400, SRFL_PRHEX, SROM10_SWCTRLMAP_2G + 8, 0xffff}, 472 473 /* sromrev 11 */ 474 {"boardflags3", 0xfffff800, SRFL_PRHEX|SRFL_MORE, SROM11_BFL4, 0xffff}, 475 {"", 0, 0, SROM11_BFL5, 0xffff}, 476 {"boardnum", 0xfffff800, 0, SROM11_MACLO, 0xffff}, 477 {"macaddr", 0xfffff800, SRFL_ETHADDR, SROM11_MACHI, 0xffff}, 478 {"ccode", 0xfffff800, SRFL_CCODE, SROM11_CCODE, 0xffff}, 479 {"regrev", 0xfffff800, 0, SROM11_REGREV, 0xffff}, 480 {"ledbh0", 0xfffff800, SRFL_NOFFS, SROM11_LEDBH10, 0x00ff}, 481 {"ledbh1", 0xfffff800, SRFL_NOFFS, SROM11_LEDBH10, 0xff00}, 482 {"ledbh2", 0xfffff800, SRFL_NOFFS, SROM11_LEDBH32, 0x00ff}, 483 {"ledbh3", 0xfffff800, SRFL_NOFFS, SROM11_LEDBH32, 0xff00}, 484 {"leddc", 0xfffff800, SRFL_NOFFS|SRFL_LEDDC, SROM11_LEDDC, 0xffff}, 485 {"aa2g", 0xfffff800, 0, SROM11_AA, 0x00ff}, 486 {"aa5g", 0xfffff800, 0, SROM11_AA, 0xff00}, 487 {"agbg0", 0xfffff800, 0, SROM11_AGBG10, 0xff00}, 488 {"agbg1", 0xfffff800, 0, SROM11_AGBG10, 0x00ff}, 489 {"agbg2", 0xfffff800, 0, SROM11_AGBG2A0, 0xff00}, 490 {"aga0", 0xfffff800, 0, SROM11_AGBG2A0, 0x00ff}, 491 {"aga1", 0xfffff800, 0, SROM11_AGA21, 0xff00}, 492 {"aga2", 0xfffff800, 0, SROM11_AGA21, 0x00ff}, 493 {"txchain", 0xfffff800, SRFL_NOFFS, SROM11_TXRXC, SROM4_TXCHAIN_MASK}, 494 {"rxchain", 0xfffff800, SRFL_NOFFS, SROM11_TXRXC, SROM4_RXCHAIN_MASK}, 495 {"antswitch", 0xfffff800, SRFL_NOFFS, SROM11_TXRXC, SROM4_SWITCH_MASK}, 496 497 {"tssiposslope2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x0001}, 498 {"epagain2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x000e}, 499 {"pdgain2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x01f0}, 500 {"tworangetssi2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x0200}, 501 {"papdcap2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x0400}, 502 {"femctrl", 0xfffff800, 0, SROM11_FEM_CFG1, 0xf800}, 503 504 {"tssiposslope5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x0001}, 505 {"epagain5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x000e}, 506 {"pdgain5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x01f0}, 507 {"tworangetssi5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x0200}, 508 {"papdcap5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x0400}, 509 {"gainctrlsph", 0xfffff800, 0, SROM11_FEM_CFG2, 0xf800}, 510 511 {"tempthresh", 0xfffff800, 0, SROM11_THERMAL, 0xff00}, 512 {"tempoffset", 0xfffff800, 0, SROM11_THERMAL, 0x00ff}, 513 {"rawtempsense", 0xfffff800, SRFL_PRHEX, SROM11_MPWR_RAWTS, 0x01ff}, 514 {"measpower", 0xfffff800, SRFL_PRHEX, SROM11_MPWR_RAWTS, 0xfe00}, 515 {"tempsense_slope", 0xfffff800, SRFL_PRHEX, SROM11_TS_SLP_OPT_CORRX, 0x00ff}, 516 {"tempcorrx", 0xfffff800, SRFL_PRHEX, SROM11_TS_SLP_OPT_CORRX, 0xfc00}, 517 {"tempsense_option", 0xfffff800, SRFL_PRHEX, SROM11_TS_SLP_OPT_CORRX, 0x0300}, 518 {"xtalfreq", 0xfffff800, 0, SROM11_XTAL_FREQ, 0xffff}, 519 {"txpwrbckof", 0x00000800, SRFL_PRHEX, SROM11_PATH0 + SROM11_2G_MAXP, 0xff00}, 520 /* Special PA Params for 4350 5G Band, 40/80 MHz BW Ant #1 */ 521 {"pa5gbw4080a1", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_4080_W0_A1, 0xffff}, 522 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_4080_W1_A1, 0xffff}, 523 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_4080_W2_A1, 0xffff}, 524 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_4080_W0_A1, 0xffff}, 525 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_4080_PA, 0xffff}, 526 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_4080_PA + 1, 0xffff}, 527 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_4080_PA, 0xffff}, 528 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_4080_PA + 1, 0xffff}, 529 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_4080_PA + 2, 0xffff}, 530 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_4080_PA, 0xffff}, 531 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_4080_PA + 1, 0xffff}, 532 {"", 0xfffff800, SRFL_PRHEX, SROM11_PATH2 + SROM11_5GB3_4080_PA + 2, 0xffff}, 533 {"phycal_tempdelta", 0xfffff800, 0, SROM11_PHYCAL_TEMPDELTA, 0x00ff}, 534 {"temps_period", 0xfffff800, 0, SROM11_PHYCAL_TEMPDELTA, 0x0f00}, 535 {"temps_hysteresis", 0xfffff800, 0, SROM11_PHYCAL_TEMPDELTA, 0xf000}, 536 {"measpower1", 0xfffff800, SRFL_PRHEX, SROM11_MPWR_1_AND_2, 0x007f}, 537 {"measpower2", 0xfffff800, SRFL_PRHEX, SROM11_MPWR_1_AND_2, 0x3f80}, 538 {"tssifloor2g", 0xfffff800, SRFL_PRHEX, SROM11_TSSIFLOOR_2G, 0x03ff}, 539 {"tssifloor5g", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_TSSIFLOOR_5GL, 0x03ff}, 540 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_TSSIFLOOR_5GM, 0x03ff}, 541 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_TSSIFLOOR_5GH, 0x03ff}, 542 {"", 0xfffff800, SRFL_PRHEX, SROM11_TSSIFLOOR_5GU, 0x03ff}, 543 {"pdoffset2g40ma0", 0xfffff800, 0, SROM11_PDOFF_2G_40M, 0x000f}, 544 {"pdoffset2g40ma1", 0xfffff800, 0, SROM11_PDOFF_2G_40M, 0x00f0}, 545 {"pdoffset2g40ma2", 0xfffff800, 0, SROM11_PDOFF_2G_40M, 0x0f00}, 546 {"pdoffset2g40mvalid", 0xfffff800, 0, SROM11_PDOFF_2G_40M, 0x8000}, 547 {"pdoffset40ma0", 0xfffff800, 0, SROM11_PDOFF_40M_A0, 0xffff}, 548 {"pdoffset40ma1", 0xfffff800, 0, SROM11_PDOFF_40M_A1, 0xffff}, 549 {"pdoffset40ma2", 0xfffff800, 0, SROM11_PDOFF_40M_A2, 0xffff}, 550 {"pdoffset80ma0", 0xfffff800, 0, SROM11_PDOFF_80M_A0, 0xffff}, 551 {"pdoffset80ma1", 0xfffff800, 0, SROM11_PDOFF_80M_A1, 0xffff}, 552 {"pdoffset80ma2", 0xfffff800, 0, SROM11_PDOFF_80M_A2, 0xffff}, 553 554 {"subband5gver", 0xfffff800, SRFL_PRHEX, SROM11_SUBBAND5GVER, 0xffff}, 555 {"paparambwver", 0xfffff800, 0, SROM11_MCSLR5GLPO, 0xf000}, 556 {"rx5ggainwar", 0xfffff800, 0, SROM11_MCSLR5GMPO, 0x2000}, 557 /* Special PA Params for 4350 5G Band, 40/80 MHz BW Ant #0 */ 558 {"pa5gbw4080a0", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 +SROM11_5GB0_PA, 0xffff}, 559 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA + 1, 0xffff}, 560 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA + 2, 0xffff}, 561 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA, 0xffff}, 562 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA + 1, 0xffff}, 563 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA + 2, 0xffff}, 564 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA, 0xffff}, 565 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA + 1, 0xffff}, 566 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA + 2, 0xffff}, 567 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_PA, 0xffff}, 568 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_PA + 1, 0xffff}, 569 {"", 0xfffff800, SRFL_PRHEX, SROM11_PATH2 + SROM11_5GB3_PA + 2, 0xffff}, 570 /* Special PA Params for 4335 5G Band, 40 MHz BW */ 571 {"pa5gbw40a0", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB0_PA, 0xffff}, 572 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB0_PA + 1, 0xffff}, 573 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB0_PA + 2, 0xffff}, 574 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB1_PA, 0xffff}, 575 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB1_PA + 1, 0xffff}, 576 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB1_PA + 2, 0xffff}, 577 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB2_PA, 0xffff}, 578 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB2_PA + 1, 0xffff}, 579 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB2_PA + 2, 0xffff}, 580 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB3_PA, 0xffff}, 581 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB3_PA + 1, 0xffff}, 582 {"", 0xfffff800, SRFL_PRHEX, SROM11_PATH1 + SROM11_5GB3_PA + 2, 0xffff}, 583 /* Special PA Params for 4335 5G Band, 80 MHz BW */ 584 {"pa5gbw80a0", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA, 0xffff}, 585 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA + 1, 0xffff}, 586 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA + 2, 0xffff}, 587 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA, 0xffff}, 588 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA + 1, 0xffff}, 589 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA + 2, 0xffff}, 590 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA, 0xffff}, 591 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA + 1, 0xffff}, 592 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA + 2, 0xffff}, 593 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_PA, 0xffff}, 594 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_PA + 1, 0xffff}, 595 {"", 0xfffff800, SRFL_PRHEX, SROM11_PATH2 + SROM11_5GB3_PA + 2, 0xffff}, 596 /* Special PA Params for 4335 2G Band, CCK */ 597 {"pa2gccka0", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_2G_PA, 0xffff}, 598 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_2G_PA + 1, 0xffff}, 599 {"", 0xfffff800, SRFL_PRHEX, SROM11_PATH1 + SROM11_2G_PA + 2, 0xffff}, 600 601 /* power per rate */ 602 {"cckbw202gpo", 0xfffff800, 0, SROM11_CCKBW202GPO, 0xffff}, 603 {"cckbw20ul2gpo", 0xfffff800, 0, SROM11_CCKBW20UL2GPO, 0xffff}, 604 {"mcsbw202gpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW202GPO, 0xffff}, 605 {"", 0xfffff800, 0, SROM11_MCSBW202GPO_1, 0xffff}, 606 {"mcsbw402gpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW402GPO, 0xffff}, 607 {"", 0xfffff800, 0, SROM11_MCSBW402GPO_1, 0xffff}, 608 {"dot11agofdmhrbw202gpo", 0xfffff800, 0, SROM11_DOT11AGOFDMHRBW202GPO, 0xffff}, 609 {"ofdmlrbw202gpo", 0xfffff800, 0, SROM11_OFDMLRBW202GPO, 0xffff}, 610 {"mcsbw205glpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW205GLPO, 0xffff}, 611 {"", 0xfffff800, 0, SROM11_MCSBW205GLPO_1, 0xffff}, 612 {"mcsbw405glpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW405GLPO, 0xffff}, 613 {"", 0xfffff800, 0, SROM11_MCSBW405GLPO_1, 0xffff}, 614 {"mcsbw805glpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW805GLPO, 0xffff}, 615 {"", 0xfffff800, 0, SROM11_MCSBW805GLPO_1, 0xffff}, 616 {"mcsbw205gmpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW205GMPO, 0xffff}, 617 {"", 0xfffff800, 0, SROM11_MCSBW205GMPO_1, 0xffff}, 618 {"mcsbw405gmpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW405GMPO, 0xffff}, 619 {"", 0xfffff800, 0, SROM11_MCSBW405GMPO_1, 0xffff}, 620 {"mcsbw805gmpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW805GMPO, 0xffff}, 621 {"", 0xfffff800, 0, SROM11_MCSBW805GMPO_1, 0xffff}, 622 {"mcsbw205ghpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW205GHPO, 0xffff}, 623 {"", 0xfffff800, 0, SROM11_MCSBW205GHPO_1, 0xffff}, 624 {"mcsbw405ghpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW405GHPO, 0xffff}, 625 {"", 0xfffff800, 0, SROM11_MCSBW405GHPO_1, 0xffff}, 626 {"mcsbw805ghpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW805GHPO, 0xffff}, 627 {"", 0xfffff800, 0, SROM11_MCSBW805GHPO_1, 0xffff}, 628 {"mcslr5glpo", 0xfffff800, 0, SROM11_MCSLR5GLPO, 0x0fff}, 629 {"mcslr5gmpo", 0xfffff800, 0, SROM11_MCSLR5GMPO, 0xffff}, 630 {"mcslr5ghpo", 0xfffff800, 0, SROM11_MCSLR5GHPO, 0xffff}, 631 {"sb20in40hrpo", 0xfffff800, 0, SROM11_SB20IN40HRPO, 0xffff}, 632 {"sb20in80and160hr5glpo", 0xfffff800, 0, SROM11_SB20IN80AND160HR5GLPO, 0xffff}, 633 {"sb40and80hr5glpo", 0xfffff800, 0, SROM11_SB40AND80HR5GLPO, 0xffff}, 634 {"sb20in80and160hr5gmpo", 0xfffff800, 0, SROM11_SB20IN80AND160HR5GMPO, 0xffff}, 635 {"sb40and80hr5gmpo", 0xfffff800, 0, SROM11_SB40AND80HR5GMPO, 0xffff}, 636 {"sb20in80and160hr5ghpo", 0xfffff800, 0, SROM11_SB20IN80AND160HR5GHPO, 0xffff}, 637 {"sb40and80hr5ghpo", 0xfffff800, 0, SROM11_SB40AND80HR5GHPO, 0xffff}, 638 {"sb20in40lrpo", 0xfffff800, 0, SROM11_SB20IN40LRPO, 0xffff}, 639 {"sb20in80and160lr5glpo", 0xfffff800, 0, SROM11_SB20IN80AND160LR5GLPO, 0xffff}, 640 {"sb40and80lr5glpo", 0xfffff800, 0, SROM11_SB40AND80LR5GLPO, 0xffff}, 641 {"sb20in80and160lr5gmpo", 0xfffff800, 0, SROM11_SB20IN80AND160LR5GMPO, 0xffff}, 642 {"sb40and80lr5gmpo", 0xfffff800, 0, SROM11_SB40AND80LR5GMPO, 0xffff}, 643 {"sb20in80and160lr5ghpo", 0xfffff800, 0, SROM11_SB20IN80AND160LR5GHPO, 0xffff}, 644 {"sb40and80lr5ghpo", 0xfffff800, 0, SROM11_SB40AND80LR5GHPO, 0xffff}, 645 {"dot11agduphrpo", 0xfffff800, 0, SROM11_DOT11AGDUPHRPO, 0xffff}, 646 {"dot11agduplrpo", 0xfffff800, 0, SROM11_DOT11AGDUPLRPO, 0xffff}, 647 648 /* Misc */ 649 {"sar2g", 0xfffff800, 0, SROM11_SAR, 0x00ff}, 650 {"sar5g", 0xfffff800, 0, SROM11_SAR, 0xff00}, 651 652 {"noiselvl2ga0", 0xfffff800, 0, SROM11_NOISELVL_2G, 0x001f}, 653 {"noiselvl2ga1", 0xfffff800, 0, SROM11_NOISELVL_2G, 0x03e0}, 654 {"noiselvl2ga2", 0xfffff800, 0, SROM11_NOISELVL_2G, 0x7c00}, 655 {"noiselvl5ga0", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GL, 0x001f}, 656 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GM, 0x001f}, 657 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GH, 0x001f}, 658 {"", 0xfffff800, 0, SROM11_NOISELVL_5GU, 0x001f}, 659 {"noiselvl5ga1", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GL, 0x03e0}, 660 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GM, 0x03e0}, 661 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GH, 0x03e0}, 662 {"", 0xfffff800, 0, SROM11_NOISELVL_5GU, 0x03e0}, 663 {"noiselvl5ga2", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GL, 0x7c00}, 664 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GM, 0x7c00}, 665 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GH, 0x7c00}, 666 {"", 0xfffff800, 0, SROM11_NOISELVL_5GU, 0x7c00}, 667 {"eu_edthresh2g", 0x00000800, 0, SROM11_EU_EDCRSTH, 0x00ff}, 668 {"eu_edthresh5g", 0x00000800, 0, SROM11_EU_EDCRSTH, 0xff00}, 669 670 {"rxgainerr2ga0", 0xfffff800, 0, SROM11_RXGAINERR_2G, 0x003f}, 671 {"rxgainerr2ga1", 0xfffff800, 0, SROM11_RXGAINERR_2G, 0x07c0}, 672 {"rxgainerr2ga2", 0xfffff800, 0, SROM11_RXGAINERR_2G, 0xf800}, 673 {"rxgainerr5ga0", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GL, 0x003f}, 674 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GM, 0x003f}, 675 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GH, 0x003f}, 676 {"", 0xfffff800, 0, SROM11_RXGAINERR_5GU, 0x003f}, 677 {"rxgainerr5ga1", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GL, 0x07c0}, 678 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GM, 0x07c0}, 679 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GH, 0x07c0}, 680 {"", 0xfffff800, 0, SROM11_RXGAINERR_5GU, 0x07c0}, 681 {"rxgainerr5ga2", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GL, 0xf800}, 682 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GM, 0xf800}, 683 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GH, 0xf800}, 684 {"", 0xfffff800, 0, SROM11_RXGAINERR_5GU, 0xf800}, 685 {"rpcal2g", 0xfffff800, 0, SROM11_RPCAL_2G, 0xffff}, 686 {"rpcal5gb0", 0xfffff800, 0, SROM11_RPCAL_5GL, 0xffff}, 687 {"rpcal5gb1", 0xfffff800, 0, SROM11_RPCAL_5GM, 0xffff}, 688 {"rpcal5gb2", 0xfffff800, 0, SROM11_RPCAL_5GH, 0xffff}, 689 {"rpcal5gb3", 0xfffff800, 0, SROM11_RPCAL_5GU, 0xffff}, 690 {"txidxcap2g", 0xfffff800, 0, SROM11_TXIDXCAP2G, 0x0ff0}, 691 {"txidxcap5g", 0xfffff800, 0, SROM11_TXIDXCAP5G, 0x0ff0}, 692 {"pdoffsetcckma0", 0xfffff800, 0, SROM11_PDOFF_2G_CCK, 0x000f}, 693 {"pdoffsetcckma1", 0xfffff800, 0, SROM11_PDOFF_2G_CCK, 0x00f0}, 694 {"pdoffsetcckma2", 0xfffff800, 0, SROM11_PDOFF_2G_CCK, 0x0f00}, 695 696 /* sromrev 12 */ 697 {"boardflags4", 0xfffff000, SRFL_PRHEX|SRFL_MORE, SROM12_BFL6, 0xffff}, 698 {"", 0, 0, SROM12_BFL7, 0xffff}, 699 {"pdoffsetcck", 0xfffff000, 0, SROM12_PDOFF_2G_CCK, 0xffff}, 700 {"pdoffset20in40m5gb0", 0xfffff000, 0, SROM12_PDOFF_20in40M_5G_B0, 0xffff}, 701 {"pdoffset20in40m5gb1", 0xfffff000, 0, SROM12_PDOFF_20in40M_5G_B1, 0xffff}, 702 {"pdoffset20in40m5gb2", 0xfffff000, 0, SROM12_PDOFF_20in40M_5G_B2, 0xffff}, 703 {"pdoffset20in40m5gb3", 0xfffff000, 0, SROM12_PDOFF_20in40M_5G_B3, 0xffff}, 704 {"pdoffset20in40m5gb4", 0xfffff000, 0, SROM12_PDOFF_20in40M_5G_B4, 0xffff}, 705 {"pdoffset40in80m5gb0", 0xfffff000, 0, SROM12_PDOFF_40in80M_5G_B0, 0xffff}, 706 {"pdoffset40in80m5gb1", 0xfffff000, 0, SROM12_PDOFF_40in80M_5G_B1, 0xffff}, 707 {"pdoffset40in80m5gb2", 0xfffff000, 0, SROM12_PDOFF_40in80M_5G_B2, 0xffff}, 708 {"pdoffset40in80m5gb3", 0xfffff000, 0, SROM12_PDOFF_40in80M_5G_B3, 0xffff}, 709 {"pdoffset40in80m5gb4", 0xfffff000, 0, SROM12_PDOFF_40in80M_5G_B4, 0xffff}, 710 {"pdoffset20in80m5gb0", 0xfffff000, 0, SROM12_PDOFF_20in80M_5G_B0, 0xffff}, 711 {"pdoffset20in80m5gb1", 0xfffff000, 0, SROM12_PDOFF_20in80M_5G_B1, 0xffff}, 712 {"pdoffset20in80m5gb2", 0xfffff000, 0, SROM12_PDOFF_20in80M_5G_B2, 0xffff}, 713 {"pdoffset20in80m5gb3", 0xfffff000, 0, SROM12_PDOFF_20in80M_5G_B3, 0xffff}, 714 {"pdoffset20in80m5gb4", 0xfffff000, 0, SROM12_PDOFF_20in80M_5G_B4, 0xffff}, 715 716 /* power per rate */ 717 {"mcsbw205gx1po", 0xfffff000, SRFL_MORE, SROM12_MCSBW205GX1PO, 0xffff}, 718 {"", 0xfffff000, 0, SROM12_MCSBW205GX1PO_1, 0xffff}, 719 {"mcsbw405gx1po", 0xfffff000, SRFL_MORE, SROM12_MCSBW405GX1PO, 0xffff}, 720 {"", 0xfffff000, 0, SROM12_MCSBW405GX1PO_1, 0xffff}, 721 {"mcsbw805gx1po", 0xfffff000, SRFL_MORE, SROM12_MCSBW805GX1PO, 0xffff}, 722 {"", 0xfffff000, 0, SROM12_MCSBW805GX1PO_1, 0xffff}, 723 {"mcsbw205gx2po", 0xfffff000, SRFL_MORE, SROM12_MCSBW205GX2PO, 0xffff}, 724 {"", 0xfffff000, 0, SROM12_MCSBW205GX2PO_1, 0xffff}, 725 {"mcsbw405gx2po", 0xfffff000, SRFL_MORE, SROM12_MCSBW405GX2PO, 0xffff}, 726 {"", 0xfffff000, 0, SROM12_MCSBW405GX2PO_1, 0xffff}, 727 {"mcsbw805gx2po", 0xfffff000, SRFL_MORE, SROM12_MCSBW805GX2PO, 0xffff}, 728 {"", 0xfffff000, 0, SROM12_MCSBW805GX2PO_1, 0xffff}, 729 730 {"sb20in80and160hr5gx1po", 0xfffff000, 0, SROM12_SB20IN80AND160HR5GX1PO, 0xffff}, 731 {"sb40and80hr5gx1po", 0xfffff000, 0, SROM12_SB40AND80HR5GX1PO, 0xffff}, 732 {"sb20in80and160lr5gx1po", 0xfffff000, 0, SROM12_SB20IN80AND160LR5GX1PO, 0xffff}, 733 {"sb40and80hr5gx1po", 0xfffff000, 0, SROM12_SB40AND80HR5GX1PO, 0xffff}, 734 {"sb20in80and160hr5gx2po", 0xfffff000, 0, SROM12_SB20IN80AND160HR5GX2PO, 0xffff}, 735 {"sb40and80hr5gx2po", 0xfffff000, 0, SROM12_SB40AND80HR5GX2PO, 0xffff}, 736 {"sb20in80and160lr5gx2po", 0xfffff000, 0, SROM12_SB20IN80AND160LR5GX2PO, 0xffff}, 737 {"sb40and80hr5gx2po", 0xfffff000, 0, SROM12_SB40AND80HR5GX2PO, 0xffff}, 738 739 {"rxgains5gmelnagaina0", 0xfffff000, 0, SROM12_RXGAINS10, 0x0007}, 740 {"rxgains5gmelnagaina1", 0xfffff000, 0, SROM12_RXGAINS11, 0x0007}, 741 {"rxgains5gmelnagaina2", 0xfffff000, 0, SROM12_RXGAINS12, 0x0007}, 742 {"rxgains5gmtrisoa0", 0xfffff000, 0, SROM12_RXGAINS10, 0x0078}, 743 {"rxgains5gmtrisoa1", 0xfffff000, 0, SROM12_RXGAINS11, 0x0078}, 744 {"rxgains5gmtrisoa2", 0xfffff000, 0, SROM12_RXGAINS12, 0x0078}, 745 {"rxgains5gmtrelnabypa0", 0xfffff000, 0, SROM12_RXGAINS10, 0x0080}, 746 {"rxgains5gmtrelnabypa1", 0xfffff000, 0, SROM12_RXGAINS11, 0x0080}, 747 {"rxgains5gmtrelnabypa2", 0xfffff000, 0, SROM12_RXGAINS12, 0x0080}, 748 {"rxgains5ghelnagaina0", 0xfffff000, 0, SROM12_RXGAINS10, 0x0700}, 749 {"rxgains5ghelnagaina1", 0xfffff000, 0, SROM12_RXGAINS11, 0x0700}, 750 {"rxgains5ghelnagaina2", 0xfffff000, 0, SROM12_RXGAINS12, 0x0700}, 751 {"rxgains5ghtrisoa0", 0xfffff000, 0, SROM12_RXGAINS10, 0x7800}, 752 {"rxgains5ghtrisoa1", 0xfffff000, 0, SROM12_RXGAINS11, 0x7800}, 753 {"rxgains5ghtrisoa2", 0xfffff000, 0, SROM12_RXGAINS12, 0x7800}, 754 {"rxgains5ghtrelnabypa0", 0xfffff000, 0, SROM12_RXGAINS10, 0x8000}, 755 {"rxgains5ghtrelnabypa1", 0xfffff000, 0, SROM12_RXGAINS11, 0x8000}, 756 {"rxgains5ghtrelnabypa2", 0xfffff000, 0, SROM12_RXGAINS12, 0x8000}, 757 {"eu_edthresh2g", 0x00001000, 0, SROM12_EU_EDCRSTH, 0x00ff}, 758 {"eu_edthresh5g", 0x00001000, 0, SROM12_EU_EDCRSTH, 0xff00}, 759 760 {"gpdn", 0xfffff000, SRFL_PRHEX|SRFL_MORE, SROM12_GPDN_L, 0xffff}, 761 {"", 0, 0, SROM12_GPDN_H, 0xffff}, 762 763 {"rpcal2gcore3", 0xffffe000, 0, SROM13_RPCAL2GCORE3, 0x00ff}, 764 {"rpcal5gb0core3", 0xffffe000, 0, SROM13_RPCAL5GB01CORE3, 0x00ff}, 765 {"rpcal5gb1core3", 0xffffe000, 0, SROM13_RPCAL5GB01CORE3, 0xff00}, 766 {"rpcal5gb2core3", 0xffffe000, 0, SROM13_RPCAL5GB23CORE3, 0x00ff}, 767 {"rpcal5gb3core3", 0xffffe000, 0, SROM13_RPCAL5GB23CORE3, 0xff00}, 768 769 {"sw_txchain_mask", 0xffffe000, 0, SROM13_SW_TXRX_MASK, 0x000f}, 770 {"sw_rxchain_mask", 0xffffe000, 0, SROM13_SW_TXRX_MASK, 0x00f0}, 771 772 {"eu_edthresh2g", 0x00002000, 0, SROM13_EU_EDCRSTH, 0x00ff}, 773 {"eu_edthresh5g", 0x00002000, 0, SROM13_EU_EDCRSTH, 0xff00}, 774 775 {"agbg3", 0xffffe000, 0, SROM13_ANTGAIN_BANDBGA, 0xff00}, 776 {"aga3", 0xffffe000, 0, SROM13_ANTGAIN_BANDBGA, 0x00ff}, 777 {"noiselvl2ga3", 0xffffe000, 0, SROM13_NOISELVLCORE3, 0x001f}, 778 {"noiselvl5ga3", 0xffffe000, SRFL_ARRAY, SROM13_NOISELVLCORE3, 0x03e0}, 779 {"", 0xffffe000, SRFL_ARRAY, SROM13_NOISELVLCORE3, 0x7c00}, 780 {"", 0xffffe000, SRFL_ARRAY, SROM13_NOISELVLCORE3_1, 0x001f}, 781 {"", 0xffffe000, 0, SROM13_NOISELVLCORE3_1, 0x03e0}, 782 {"rxgainerr2ga3", 0xffffe000, 0, SROM13_RXGAINERRCORE3, 0x001f}, 783 {"rxgainerr5ga3", 0xffffe000, SRFL_ARRAY, SROM13_RXGAINERRCORE3, 0x03e0}, 784 {"", 0xffffe000, SRFL_ARRAY, SROM13_RXGAINERRCORE3, 0x7c00}, 785 {"", 0xffffe000, SRFL_ARRAY, SROM13_RXGAINERRCORE3_1, 0x001f}, 786 {"", 0xffffe000, 0, SROM13_RXGAINERRCORE3_1, 0x03e0}, 787 {"rxgains5gmelnagaina3", 0xffffe000, 0, SROM13_RXGAINS1CORE3, 0x0007}, 788 {"rxgains5gmtrisoa3", 0xffffe000, 0, SROM13_RXGAINS1CORE3, 0x0078}, 789 {"rxgains5gmtrelnabypa3", 0xffffe000, 0, SROM13_RXGAINS1CORE3, 0x0080}, 790 {"rxgains5ghelnagaina3", 0xffffe000, 0, SROM13_RXGAINS1CORE3, 0x0700}, 791 {"rxgains5ghtrisoa3", 0xffffe000, 0, SROM13_RXGAINS1CORE3, 0x7800}, 792 {"rxgains5ghtrelnabypa3", 0xffffe000, 0, SROM13_RXGAINS1CORE3, 0x8000}, 793 794 /* pdoffset */ 795 {"pdoffset20in40m5gcore3", 0xffffe000, 0, SROM13_PDOFFSET20IN40M5GCORE3, 0xffff}, 796 {"pdoffset20in40m5gcore3_1", 0xffffe000, 0, SROM13_PDOFFSET20IN40M5GCORE3_1, 0xffff}, 797 {"pdoffset20in80m5gcore3", 0xffffe000, 0, SROM13_PDOFFSET20IN80M5GCORE3, 0xffff}, 798 {"pdoffset20in80m5gcore3_1", 0xffffe000, 0, SROM13_PDOFFSET20IN80M5GCORE3_1, 0xffff}, 799 {"pdoffset40in80m5gcore3", 0xffffe000, 0, SROM13_PDOFFSET40IN80M5GCORE3, 0xffff}, 800 {"pdoffset40in80m5gcore3_1", 0xffffe000, 0, SROM13_PDOFFSET40IN80M5GCORE3_1, 0xffff}, 801 802 {"pdoffset20in40m2g", 0xffffe000, 0, SROM13_PDOFFSET20IN40M2G, 0xffff}, 803 {"pdoffset20in40m2gcore3", 0xffffe000, 0, SROM13_PDOFFSET20IN40M2GCORE3, 0xffff}, 804 {"pdoffsetcck20m", 0xffffe000, 0, SROM13_PDOFF_2G_CCK_20M, 0xffff}, 805 806 /* power per rate */ 807 {"mcs1024qam2gpo", 0xffffe000, 0, SROM13_MCS1024QAM2GPO, 0xffff}, 808 {"mcs1024qam5glpo", 0xffffe000, SRFL_MORE, SROM13_MCS1024QAM5GLPO, 0xffff}, 809 {"", 0xffffe000, 0, SROM13_MCS1024QAM5GLPO_1, 0xffff}, 810 {"mcs1024qam5gmpo", 0xffffe000, SRFL_MORE, SROM13_MCS1024QAM5GMPO, 0xffff}, 811 {"", 0xffffe000, 0, SROM13_MCS1024QAM5GMPO_1, 0xffff}, 812 {"mcs1024qam5ghpo", 0xffffe000, SRFL_MORE, SROM13_MCS1024QAM5GHPO, 0xffff}, 813 {"", 0xffffe000, 0, SROM13_MCS1024QAM5GHPO_1, 0xffff}, 814 {"mcs1024qam5gx1po", 0xffffe000, SRFL_MORE, SROM13_MCS1024QAM5GX1PO, 0xffff}, 815 {"", 0xffffe000, 0, SROM13_MCS1024QAM5GX1PO_1, 0xffff}, 816 {"mcs1024qam5gx2po", 0xffffe000, SRFL_MORE, SROM13_MCS1024QAM5GX2PO, 0xffff}, 817 {"", 0xffffe000, 0, SROM13_MCS1024QAM5GX2PO_1, 0xffff}, 818 819 {"mcsbw1605glpo", 0xffffe000, SRFL_MORE, SROM13_MCSBW1605GLPO, 0xffff}, 820 {"", 0xffffe000, 0, SROM13_MCSBW1605GLPO_1, 0xffff}, 821 {"mcsbw1605gmpo", 0xffffe000, SRFL_MORE, SROM13_MCSBW1605GMPO, 0xffff}, 822 {"", 0xffffe000, 0, SROM13_MCSBW1605GMPO_1, 0xffff}, 823 {"mcsbw1605ghpo", 0xffffe000, SRFL_MORE, SROM13_MCSBW1605GHPO, 0xffff}, 824 {"", 0xffffe000, 0, SROM13_MCSBW1605GHPO_1, 0xffff}, 825 {"mcsbw1605gx1po", 0xffffe000, SRFL_MORE, SROM13_MCSBW1605GX1PO, 0xffff}, 826 {"", 0xffffe000, 0, SROM13_MCSBW1605GX1PO_1, 0xffff}, 827 {"mcsbw1605gx2po", 0xffffe000, SRFL_MORE, SROM13_MCSBW1605GX2PO, 0xffff}, 828 {"", 0xffffe000, 0, SROM13_MCSBW1605GX2PO_1, 0xffff}, 829 830 {"ulbpproffs2g", 0xffffe000, 0, SROM13_ULBPPROFFS2G, 0xffff}, 831 832 {"mcs8poexp", 0xffffe000, SRFL_MORE, SROM13_MCS8POEXP, 0xffff}, 833 {"", 0xffffe000, 0, SROM13_MCS8POEXP_1, 0xffff}, 834 {"mcs9poexp", 0xffffe000, SRFL_MORE, SROM13_MCS9POEXP, 0xffff}, 835 {"", 0xffffe000, 0, SROM13_MCS9POEXP_1, 0xffff}, 836 {"mcs10poexp", 0xffffe000, SRFL_MORE, SROM13_MCS10POEXP, 0xffff}, 837 {"", 0xffffe000, 0, SROM13_MCS10POEXP_1, 0xffff}, 838 {"mcs11poexp", 0xffffe000, SRFL_MORE, SROM13_MCS11POEXP, 0xffff}, 839 {"", 0xffffe000, 0, SROM13_MCS11POEXP_1, 0xffff}, 840 841 {"ulbpdoffs5gb0a0", 0xffffe000, 0, SROM13_ULBPDOFFS5GB0A0, 0xffff}, 842 {"ulbpdoffs5gb0a1", 0xffffe000, 0, SROM13_ULBPDOFFS5GB0A1, 0xffff}, 843 {"ulbpdoffs5gb0a2", 0xffffe000, 0, SROM13_ULBPDOFFS5GB0A2, 0xffff}, 844 {"ulbpdoffs5gb0a3", 0xffffe000, 0, SROM13_ULBPDOFFS5GB0A3, 0xffff}, 845 {"ulbpdoffs5gb1a0", 0xffffe000, 0, SROM13_ULBPDOFFS5GB1A0, 0xffff}, 846 {"ulbpdoffs5gb1a1", 0xffffe000, 0, SROM13_ULBPDOFFS5GB1A1, 0xffff}, 847 {"ulbpdoffs5gb1a2", 0xffffe000, 0, SROM13_ULBPDOFFS5GB1A2, 0xffff}, 848 {"ulbpdoffs5gb1a3", 0xffffe000, 0, SROM13_ULBPDOFFS5GB1A3, 0xffff}, 849 {"ulbpdoffs5gb2a0", 0xffffe000, 0, SROM13_ULBPDOFFS5GB2A0, 0xffff}, 850 {"ulbpdoffs5gb2a1", 0xffffe000, 0, SROM13_ULBPDOFFS5GB2A1, 0xffff}, 851 {"ulbpdoffs5gb2a2", 0xffffe000, 0, SROM13_ULBPDOFFS5GB2A2, 0xffff}, 852 {"ulbpdoffs5gb2a3", 0xffffe000, 0, SROM13_ULBPDOFFS5GB2A3, 0xffff}, 853 {"ulbpdoffs5gb3a0", 0xffffe000, 0, SROM13_ULBPDOFFS5GB3A0, 0xffff}, 854 {"ulbpdoffs5gb3a1", 0xffffe000, 0, SROM13_ULBPDOFFS5GB3A1, 0xffff}, 855 {"ulbpdoffs5gb3a2", 0xffffe000, 0, SROM13_ULBPDOFFS5GB3A2, 0xffff}, 856 {"ulbpdoffs5gb3a3", 0xffffe000, 0, SROM13_ULBPDOFFS5GB3A3, 0xffff}, 857 {"ulbpdoffs5gb4a0", 0xffffe000, 0, SROM13_ULBPDOFFS5GB4A0, 0xffff}, 858 {"ulbpdoffs5gb4a1", 0xffffe000, 0, SROM13_ULBPDOFFS5GB4A1, 0xffff}, 859 {"ulbpdoffs5gb4a2", 0xffffe000, 0, SROM13_ULBPDOFFS5GB4A2, 0xffff}, 860 {"ulbpdoffs5gb4a3", 0xffffe000, 0, SROM13_ULBPDOFFS5GB4A3, 0xffff}, 861 {"ulbpdoffs2ga0", 0xffffe000, 0, SROM13_ULBPDOFFS2GA0, 0xffff}, 862 {"ulbpdoffs2ga1", 0xffffe000, 0, SROM13_ULBPDOFFS2GA1, 0xffff}, 863 {"ulbpdoffs2ga2", 0xffffe000, 0, SROM13_ULBPDOFFS2GA2, 0xffff}, 864 {"ulbpdoffs2ga3", 0xffffe000, 0, SROM13_ULBPDOFFS2GA3, 0xffff}, 865 866 {"rpcal5gb4", 0xffffe000, 0, SROM13_RPCAL5GB4, 0xffff}, 867 868 {"sb20in40hrlrpox", 0xffffe000, 0, SROM13_SB20IN40HRLRPOX, 0xffff}, 869 870 {"swctrlmap4_cfg", 0xffffe000, 0, SROM13_SWCTRLMAP4_CFG, 0xffff}, 871 {"swctrlmap4_TX2g_fem3to0", 0xffffe000, 0, SROM13_SWCTRLMAP4_TX2G_FEM3TO0, 0xffff}, 872 {"swctrlmap4_RX2g_fem3to0", 0xffffe000, 0, SROM13_SWCTRLMAP4_RX2G_FEM3TO0, 0xffff}, 873 {"swctrlmap4_RXByp2g_fem3to0", 0xffffe000, 0, SROM13_SWCTRLMAP4_RXBYP2G_FEM3TO0, 0xffff}, 874 {"swctrlmap4_misc2g_fem3to0", 0xffffe000, 0, SROM13_SWCTRLMAP4_MISC2G_FEM3TO0, 0xffff}, 875 {"swctrlmap4_TX5g_fem3to0", 0xffffe000, 0, SROM13_SWCTRLMAP4_TX5G_FEM3TO0, 0xffff}, 876 {"swctrlmap4_RX5g_fem3to0", 0xffffe000, 0, SROM13_SWCTRLMAP4_RX5G_FEM3TO0, 0xffff}, 877 {"swctrlmap4_RXByp5g_fem3to0", 0xffffe000, 0, SROM13_SWCTRLMAP4_RXBYP5G_FEM3TO0, 0xffff}, 878 {"swctrlmap4_misc5g_fem3to0", 0xffffe000, 0, SROM13_SWCTRLMAP4_MISC5G_FEM3TO0, 0xffff}, 879 {"swctrlmap4_TX2g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_TX2G_FEM7TO4, 0xffff}, 880 {"swctrlmap4_RX2g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_RX2G_FEM7TO4, 0xffff}, 881 {"swctrlmap4_RXByp2g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_RXBYP2G_FEM7TO4, 0xffff}, 882 {"swctrlmap4_misc2g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_MISC2G_FEM7TO4, 0xffff}, 883 {"swctrlmap4_TX5g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_TX5G_FEM7TO4, 0xffff}, 884 {"swctrlmap4_RX5g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_RX5G_FEM7TO4, 0xffff}, 885 {"swctrlmap4_RXByp5g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_RXBYP5G_FEM7TO4, 0xffff}, 886 {"swctrlmap4_misc5g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_MISC5G_FEM7TO4, 0xffff}, 887 {NULL, 0, 0, 0, 0} 888 }; 889 #endif /* !defined(SROM15_MEMOPT) */ 890 891 static const sromvar_t pci_srom15vars[] = { 892 {"macaddr", 0x00008000, SRFL_ETHADDR, SROM15_MACHI, 0xffff}, 893 {"caldata_offset", 0x00008000, 0, SROM15_CAL_OFFSET_LOC, 0xffff}, 894 {"boardrev", 0x00008000, SRFL_PRHEX, SROM15_BRDREV, 0xffff}, 895 {"ccode", 0x00008000, SRFL_CCODE, SROM15_CCODE, 0xffff}, 896 {"regrev", 0x00008000, 0, SROM15_REGREV, 0xffff}, 897 {NULL, 0, 0, 0, 0} 898 }; 899 900 static const sromvar_t pci_srom16vars[] = { 901 {"macaddr", 0x00010000, SRFL_ETHADDR, SROM16_MACHI, 0xffff}, 902 {"caldata_offset", 0x00010000, 0, SROM16_CALDATA_OFFSET_LOC, 0xffff}, 903 {"boardrev", 0x00010000, 0, SROM16_BOARDREV, 0xffff}, 904 {"ccode", 0x00010000, 0, SROM16_CCODE, 0xffff}, 905 {"regrev", 0x00010000, 0, SROM16_REGREV, 0xffff}, 906 {NULL, 0, 0, 0, 0} 907 }; 908 909 static const sromvar_t pci_srom17vars[] = { 910 {"boardrev", 0x00020000, SRFL_PRHEX, SROM17_BRDREV, 0xffff}, 911 {"macaddr", 0x00020000, SRFL_ETHADDR, SROM17_MACADDR, 0xffff}, 912 {"ccode", 0x00020000, SRFL_CCODE, SROM17_CCODE, 0xffff}, 913 {"caldata_offset", 0x00020000, 0, SROM17_CALDATA, 0xffff}, 914 {"gain_cal_temp", 0x00020000, SRFL_PRHEX, SROM17_GCALTMP, 0xffff}, 915 {"rssi_delta_2gb0_c0", 0x00020000, PRHEX_N_MORE, SROM17_C0SRD202G, 0xffff}, 916 {"", 0x00020000, 0, SROM17_C0SRD202G_1, 0xffff}, 917 {"rssi_delta_5gl_c0", 0x00020000, PRHEX_N_MORE, SROM17_C0SRD205GL, 0xffff}, 918 {"", 0x00020000, 0, SROM17_C0SRD205GL_1, 0xffff}, 919 {"rssi_delta_5gml_c0", 0x00020000, PRHEX_N_MORE, SROM17_C0SRD205GML, 0xffff}, 920 {"", 0x00020000, 0, SROM17_C0SRD205GML_1, 0xffff}, 921 {"rssi_delta_5gmu_c0", 0x00020000, PRHEX_N_MORE, SROM17_C0SRD205GMU, 0xffff}, 922 {"", 0x00020000, 0, SROM17_C0SRD205GMU_1, 0xffff}, 923 {"rssi_delta_5gh_c0", 0x00020000, PRHEX_N_MORE, SROM17_C0SRD205GH, 0xffff}, 924 {"", 0x00020000, 0, SROM17_C0SRD205GH_1, 0xffff}, 925 {"rssi_delta_2gb0_c1", 0x00020000, PRHEX_N_MORE, SROM17_C1SRD202G, 0xffff}, 926 {"", 0x00020000, 0, SROM17_C1SRD202G_1, 0xffff}, 927 {"rssi_delta_5gl_c1", 0x00020000, PRHEX_N_MORE, SROM17_C1SRD205GL, 0xffff}, 928 {"", 0x00020000, 0, SROM17_C1SRD205GL_1, 0xffff}, 929 {"rssi_delta_5gml_c1", 0x00020000, PRHEX_N_MORE, SROM17_C1SRD205GML, 0xffff}, 930 {"", 0x00020000, 0, SROM17_C1SRD205GML_1, 0xffff}, 931 {"rssi_delta_5gmu_c1", 0x00020000, PRHEX_N_MORE, SROM17_C1SRD205GMU, 0xffff}, 932 {"", 0x00020000, 0, SROM17_C1SRD205GMU_1, 0xffff}, 933 {"rssi_delta_5gh_c1", 0x00020000, PRHEX_N_MORE, SROM17_C1SRD205GH, 0xffff}, 934 {"", 0x00020000, 0, SROM17_C1SRD205GH_1, 0xffff}, 935 {"txpa_trim_magic", 0x00020000, PRHEX_N_MORE, SROM17_TRAMMAGIC, 0xffff}, 936 {"", 0x00020000, 0, SROM17_TRAMMAGIC_1, 0xffff}, 937 {"txpa_trim_data", 0x00020000, SRFL_PRHEX, SROM17_TRAMDATA, 0xffff}, 938 {NULL, 0, 0, 0, 0x00} 939 }; 940 941 static const sromvar_t perpath_pci_sromvars[] = { 942 {"maxp2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff}, 943 {"itt2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00}, 944 {"itt5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00}, 945 {"pa2gw0a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff}, 946 {"pa2gw1a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff}, 947 {"pa2gw2a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff}, 948 {"pa2gw3a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff}, 949 {"maxp5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff}, 950 {"maxp5gha", 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff}, 951 {"maxp5gla", 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00}, 952 {"pa5gw0a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff}, 953 {"pa5gw1a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff}, 954 {"pa5gw2a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff}, 955 {"pa5gw3a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff}, 956 {"pa5glw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff}, 957 {"pa5glw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1, 0xffff}, 958 {"pa5glw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2, 0xffff}, 959 {"pa5glw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3, 0xffff}, 960 {"pa5ghw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff}, 961 {"pa5ghw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1, 0xffff}, 962 {"pa5ghw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2, 0xffff}, 963 {"pa5ghw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3, 0xffff}, 964 {"maxp2ga", 0x00000700, 0, SROM8_2G_ITT_MAXP, 0x00ff}, 965 {"itt2ga", 0x00000700, 0, SROM8_2G_ITT_MAXP, 0xff00}, 966 {"itt5ga", 0x00000700, 0, SROM8_5G_ITT_MAXP, 0xff00}, 967 {"pa2gw0a", 0x00000700, SRFL_PRHEX, SROM8_2G_PA, 0xffff}, 968 {"pa2gw1a", 0x00000700, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff}, 969 {"pa2gw2a", 0x00000700, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff}, 970 {"maxp5ga", 0x00000700, 0, SROM8_5G_ITT_MAXP, 0x00ff}, 971 {"maxp5gha", 0x00000700, 0, SROM8_5GLH_MAXP, 0x00ff}, 972 {"maxp5gla", 0x00000700, 0, SROM8_5GLH_MAXP, 0xff00}, 973 {"pa5gw0a", 0x00000700, SRFL_PRHEX, SROM8_5G_PA, 0xffff}, 974 {"pa5gw1a", 0x00000700, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff}, 975 {"pa5gw2a", 0x00000700, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff}, 976 {"pa5glw0a", 0x00000700, SRFL_PRHEX, SROM8_5GL_PA, 0xffff}, 977 {"pa5glw1a", 0x00000700, SRFL_PRHEX, SROM8_5GL_PA + 1, 0xffff}, 978 {"pa5glw2a", 0x00000700, SRFL_PRHEX, SROM8_5GL_PA + 2, 0xffff}, 979 {"pa5ghw0a", 0x00000700, SRFL_PRHEX, SROM8_5GH_PA, 0xffff}, 980 {"pa5ghw1a", 0x00000700, SRFL_PRHEX, SROM8_5GH_PA + 1, 0xffff}, 981 {"pa5ghw2a", 0x00000700, SRFL_PRHEX, SROM8_5GH_PA + 2, 0xffff}, 982 983 /* sromrev 11 */ 984 {"maxp2ga", 0xfffff800, 0, SROM11_2G_MAXP, 0x00ff}, 985 {"pa2ga", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_2G_PA, 0xffff}, 986 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_2G_PA + 1, 0xffff}, 987 {"", 0x00000800, SRFL_PRHEX, SROM11_2G_PA + 2, 0xffff}, 988 {"rxgains5gmelnagaina", 0x00000800, 0, SROM11_RXGAINS1, 0x0007}, 989 {"rxgains5gmtrisoa", 0x00000800, 0, SROM11_RXGAINS1, 0x0078}, 990 {"rxgains5gmtrelnabypa", 0x00000800, 0, SROM11_RXGAINS1, 0x0080}, 991 {"rxgains5ghelnagaina", 0x00000800, 0, SROM11_RXGAINS1, 0x0700}, 992 {"rxgains5ghtrisoa", 0x00000800, 0, SROM11_RXGAINS1, 0x7800}, 993 {"rxgains5ghtrelnabypa", 0x00000800, 0, SROM11_RXGAINS1, 0x8000}, 994 {"rxgains2gelnagaina", 0x00000800, 0, SROM11_RXGAINS, 0x0007}, 995 {"rxgains2gtrisoa", 0x00000800, 0, SROM11_RXGAINS, 0x0078}, 996 {"rxgains2gtrelnabypa", 0x00000800, 0, SROM11_RXGAINS, 0x0080}, 997 {"rxgains5gelnagaina", 0x00000800, 0, SROM11_RXGAINS, 0x0700}, 998 {"rxgains5gtrisoa", 0x00000800, 0, SROM11_RXGAINS, 0x7800}, 999 {"rxgains5gtrelnabypa", 0x00000800, 0, SROM11_RXGAINS, 0x8000}, 1000 {"maxp5ga", 0x00000800, SRFL_ARRAY, SROM11_5GB1B0_MAXP, 0x00ff}, 1001 {"", 0x00000800, SRFL_ARRAY, SROM11_5GB1B0_MAXP, 0xff00}, 1002 {"", 0x00000800, SRFL_ARRAY, SROM11_5GB3B2_MAXP, 0x00ff}, 1003 {"", 0x00000800, 0, SROM11_5GB3B2_MAXP, 0xff00}, 1004 {"pa5ga", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_PA, 0xffff}, 1005 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_PA + 1, 0xffff}, 1006 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_PA + 2, 0xffff}, 1007 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_PA, 0xffff}, 1008 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_PA + 1, 0xffff}, 1009 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_PA + 2, 0xffff}, 1010 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB2_PA, 0xffff}, 1011 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB2_PA + 1, 0xffff}, 1012 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB2_PA + 2, 0xffff}, 1013 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB3_PA, 0xffff}, 1014 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB3_PA + 1, 0xffff}, 1015 {"", 0x00000800, SRFL_PRHEX, SROM11_5GB3_PA + 2, 0xffff}, 1016 1017 /* sromrev 12 */ 1018 {"maxp5gb4a", 0xfffff000, 0, SROM12_5GB42G_MAXP, 0x00ff00}, 1019 {"pa2ga", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_2GB0_PA_W0, 0x00ffff}, 1020 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_2GB0_PA_W1, 0x00ffff}, 1021 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_2GB0_PA_W2, 0x00ffff}, 1022 {"", 0xfffff000, SRFL_PRHEX, SROM12_2GB0_PA_W3, 0x00ffff}, 1023 1024 {"pa2g40a", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_2G40B0_PA_W0, 0x00ffff}, 1025 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_2G40B0_PA_W1, 0x00ffff}, 1026 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_2G40B0_PA_W2, 0x00ffff}, 1027 {"", 0xfffff000, SRFL_PRHEX, SROM12_2G40B0_PA_W3, 0x00ffff}, 1028 {"maxp5gb0a", 0xfffff000, 0, SROM12_5GB1B0_MAXP, 0x00ff}, 1029 {"maxp5gb1a", 0xfffff000, 0, SROM12_5GB1B0_MAXP, 0x00ff00}, 1030 {"maxp5gb2a", 0xfffff000, 0, SROM12_5GB3B2_MAXP, 0x00ff}, 1031 {"maxp5gb3a", 0xfffff000, 0, SROM12_5GB3B2_MAXP, 0x00ff00}, 1032 1033 {"pa5ga", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB0_PA_W0, 0x00ffff}, 1034 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB0_PA_W1, 0x00ffff}, 1035 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB0_PA_W2, 0x00ffff}, 1036 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB0_PA_W3, 0x00ffff}, 1037 1038 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB1_PA_W0, 0x00ffff}, 1039 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB1_PA_W1, 0x00ffff}, 1040 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB1_PA_W2, 0x00ffff}, 1041 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB1_PA_W3, 0x00ffff}, 1042 1043 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB2_PA_W0, 0x00ffff}, 1044 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB2_PA_W1, 0x00ffff}, 1045 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB2_PA_W2, 0x00ffff}, 1046 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB2_PA_W3, 0x00ffff}, 1047 1048 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB3_PA_W0, 0x00ffff}, 1049 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB3_PA_W1, 0x00ffff}, 1050 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB3_PA_W2, 0x00ffff}, 1051 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB3_PA_W3, 0x00ffff}, 1052 1053 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB4_PA_W0, 0x00ffff}, 1054 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB4_PA_W1, 0x00ffff}, 1055 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB4_PA_W2, 0x00ffff}, 1056 {"", 0xfffff000, SRFL_PRHEX, SROM12_5GB4_PA_W3, 0x00ffff}, 1057 1058 {"pa5g40a", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B0_PA_W0, 0x00ffff}, 1059 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B0_PA_W1, 0x00ffff}, 1060 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B0_PA_W2, 0x00ffff}, 1061 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B0_PA_W3, 0x00ffff}, 1062 1063 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B1_PA_W0, 0x00ffff}, 1064 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B1_PA_W1, 0x00ffff}, 1065 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B1_PA_W2, 0x00ffff}, 1066 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B1_PA_W3, 0x00ffff}, 1067 1068 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B2_PA_W0, 0x00ffff}, 1069 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B2_PA_W1, 0x00ffff}, 1070 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B2_PA_W2, 0x00ffff}, 1071 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B2_PA_W3, 0x00ffff}, 1072 1073 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B3_PA_W0, 0x00ffff}, 1074 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B3_PA_W1, 0x00ffff}, 1075 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B3_PA_W2, 0x00ffff}, 1076 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B3_PA_W3, 0x00ffff}, 1077 1078 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B4_PA_W0, 0x00ffff}, 1079 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B4_PA_W1, 0x00ffff}, 1080 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B4_PA_W2, 0x00ffff}, 1081 {"", 0xfffff000, SRFL_PRHEX, SROM12_5G40B4_PA_W3, 0x00ffff}, 1082 1083 {"pa5g80a", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B0_PA_W0, 0x00ffff}, 1084 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B0_PA_W1, 0x00ffff}, 1085 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B0_PA_W2, 0x00ffff}, 1086 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B0_PA_W3, 0x00ffff}, 1087 1088 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B1_PA_W0, 0x00ffff}, 1089 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B1_PA_W1, 0x00ffff}, 1090 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B1_PA_W2, 0x00ffff}, 1091 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B1_PA_W3, 0x00ffff}, 1092 1093 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B2_PA_W0, 0x00ffff}, 1094 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B2_PA_W1, 0x00ffff}, 1095 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B2_PA_W2, 0x00ffff}, 1096 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B2_PA_W3, 0x00ffff}, 1097 1098 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B3_PA_W0, 0x00ffff}, 1099 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B3_PA_W1, 0x00ffff}, 1100 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B3_PA_W2, 0x00ffff}, 1101 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B3_PA_W3, 0x00ffff}, 1102 1103 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B4_PA_W0, 0x00ffff}, 1104 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B4_PA_W1, 0x00ffff}, 1105 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B4_PA_W2, 0x00ffff}, 1106 {"", 0xfffff000, SRFL_PRHEX, SROM12_5G80B4_PA_W3, 0x00ffff}, 1107 /* sromrev 13 */ 1108 {"rxgains2gelnagaina", 0xffffe000, 0, SROM13_RXGAINS, 0x0007}, 1109 {"rxgains2gtrisoa", 0xffffe000, 0, SROM13_RXGAINS, 0x0078}, 1110 {"rxgains2gtrelnabypa", 0xffffe000, 0, SROM13_RXGAINS, 0x0080}, 1111 {"rxgains5gelnagaina", 0xffffe000, 0, SROM13_RXGAINS, 0x0700}, 1112 {"rxgains5gtrisoa", 0xffffe000, 0, SROM13_RXGAINS, 0x7800}, 1113 {"rxgains5gtrelnabypa", 0xffffe000, 0, SROM13_RXGAINS, 0x8000}, 1114 {NULL, 0, 0, 0, 0} 1115 }; 1116 1117 #if !defined(PHY_TYPE_N) 1118 #define PHY_TYPE_N 4 /* N-Phy value */ 1119 #endif /* !(defined(PHY_TYPE_HT) && defined(PHY_TYPE_N)) */ 1120 #if !defined(PHY_TYPE_AC) 1121 #define PHY_TYPE_AC 11 /* AC-Phy value */ 1122 #endif /* !defined(PHY_TYPE_AC) */ 1123 #if !defined(PHY_TYPE_LCN20) 1124 #define PHY_TYPE_LCN20 12 /* LCN20-Phy value */ 1125 #endif /* !defined(PHY_TYPE_LCN20) */ 1126 #if !defined(PHY_TYPE_NULL) 1127 #define PHY_TYPE_NULL 0xf /* Invalid Phy value */ 1128 #endif /* !defined(PHY_TYPE_NULL) */ 1129 1130 typedef struct { 1131 uint16 phy_type; 1132 uint16 bandrange; 1133 uint16 chain; 1134 const char *vars; 1135 } pavars_t; 1136 1137 static const pavars_t pavars[] = { 1138 /* NPHY */ 1139 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 0, "pa2gw0a0 pa2gw1a0 pa2gw2a0"}, 1140 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 1, "pa2gw0a1 pa2gw1a1 pa2gw2a1"}, 1141 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND0, 0, "pa5glw0a0 pa5glw1a0 pa5glw2a0"}, 1142 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND0, 1, "pa5glw0a1 pa5glw1a1 pa5glw2a1"}, 1143 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND1, 0, "pa5gw0a0 pa5gw1a0 pa5gw2a0"}, 1144 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND1, 1, "pa5gw0a1 pa5gw1a1 pa5gw2a1"}, 1145 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND2, 0, "pa5ghw0a0 pa5ghw1a0 pa5ghw2a0"}, 1146 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND2, 1, "pa5ghw0a1 pa5ghw1a1 pa5ghw2a1"}, 1147 /* ACPHY */ 1148 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 0, "pa2ga0"}, 1149 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 1, "pa2ga1"}, 1150 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 2, "pa2ga2"}, 1151 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 0, "pa5ga0"}, 1152 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 1, "pa5ga1"}, 1153 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 2, "pa5ga2"}, 1154 /* LCN20PHY */ 1155 {PHY_TYPE_LCN20, WL_CHAN_FREQ_RANGE_2G, 0, "pa2ga0"}, 1156 {PHY_TYPE_NULL, 0, 0, ""} 1157 }; 1158 1159 static const pavars_t pavars_SROM12[] = { 1160 /* ACPHY */ 1161 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 0, "pa2ga0"}, 1162 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 1, "pa2ga1"}, 1163 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 2, "pa2ga2"}, 1164 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G_40, 0, "pa2g40a0"}, 1165 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G_40, 1, "pa2g40a1"}, 1166 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G_40, 2, "pa2g40a2"}, 1167 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND, 0, "pa5ga0"}, 1168 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND, 1, "pa5ga1"}, 1169 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND, 2, "pa5ga2"}, 1170 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_40, 0, "pa5g40a0"}, 1171 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_40, 1, "pa5g40a1"}, 1172 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_40, 2, "pa5g40a2"}, 1173 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_80, 0, "pa5g80a0"}, 1174 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_80, 1, "pa5g80a1"}, 1175 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_80, 2, "pa5g80a2"}, 1176 {PHY_TYPE_NULL, 0, 0, ""} 1177 }; 1178 1179 static const pavars_t pavars_SROM13[] = { 1180 /* ACPHY */ 1181 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 0, "pa2ga0"}, 1182 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 1, "pa2ga1"}, 1183 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 2, "pa2ga2"}, 1184 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 3, "pa2ga3"}, 1185 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G_40, 0, "pa2g40a0"}, 1186 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G_40, 1, "pa2g40a1"}, 1187 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G_40, 2, "pa2g40a2"}, 1188 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G_40, 3, "pa2g40a3"}, 1189 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND, 0, "pa5ga0"}, 1190 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND, 1, "pa5ga1"}, 1191 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND, 2, "pa5ga2"}, 1192 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND, 3, "pa5ga3"}, 1193 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_40, 0, "pa5g40a0"}, 1194 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_40, 1, "pa5g40a1"}, 1195 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_40, 2, "pa5g40a2"}, 1196 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_40, 3, "pa5g40a3"}, 1197 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_80, 0, "pa5g80a0"}, 1198 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_80, 1, "pa5g80a1"}, 1199 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_80, 2, "pa5g80a2"}, 1200 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_80, 3, "pa5g80a3"}, 1201 {PHY_TYPE_NULL, 0, 0, ""} 1202 }; 1203 1204 /* pavars table when paparambwver is 1 */ 1205 static const pavars_t pavars_bwver_1[] = { 1206 /* ACPHY */ 1207 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 0, "pa2ga0"}, 1208 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 1, "pa2gccka0"}, 1209 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 1, "pa2ga2"}, 1210 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 0, "pa5ga0"}, 1211 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 1, "pa5gbw40a0"}, 1212 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 2, "pa5gbw80a0"}, 1213 {PHY_TYPE_NULL, 0, 0, ""} 1214 }; 1215 1216 /* pavars table when paparambwver is 2 */ 1217 static const pavars_t pavars_bwver_2[] = { 1218 /* ACPHY */ 1219 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 0, "pa2ga0"}, 1220 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 1, "pa2ga1"}, 1221 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 0, "pa5ga0"}, 1222 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 1, "pa5ga1"}, 1223 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 2, "pa5gbw4080a0"}, 1224 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 3, "pa5gbw4080a1"}, 1225 {PHY_TYPE_NULL, 0, 0, ""} 1226 }; 1227 1228 /* pavars table when paparambwver is 3 */ 1229 static const pavars_t pavars_bwver_3[] = { 1230 /* ACPHY */ 1231 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 0, "pa2ga0"}, 1232 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 1, "pa2ga1"}, 1233 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 2, "pa2gccka0"}, 1234 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 3, "pa2gccka1"}, 1235 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 0, "pa5ga0"}, 1236 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 1, "pa5ga1"}, 1237 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 2, "pa5gbw4080a0"}, 1238 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 3, "pa5gbw4080a1"}, 1239 {PHY_TYPE_NULL, 0, 0, ""} 1240 }; 1241 1242 typedef struct { 1243 uint16 phy_type; 1244 uint16 bandrange; 1245 const char *vars; 1246 } povars_t; 1247 1248 static const povars_t povars[] = { 1249 /* NPHY */ 1250 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, "mcs2gpo0 mcs2gpo1 mcs2gpo2 mcs2gpo3 " 1251 "mcs2gpo4 mcs2gpo5 mcs2gpo6 mcs2gpo7"}, 1252 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, "mcs5glpo0 mcs5glpo1 mcs5glpo2 mcs5glpo3 " 1253 "mcs5glpo4 mcs5glpo5 mcs5glpo6 mcs5glpo7"}, 1254 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, "mcs5gpo0 mcs5gpo1 mcs5gpo2 mcs5gpo3 " 1255 "mcs5gpo4 mcs5gpo5 mcs5gpo6 mcs5gpo7"}, 1256 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, "mcs5ghpo0 mcs5ghpo1 mcs5ghpo2 mcs5ghpo3 " 1257 "mcs5ghpo4 mcs5ghpo5 mcs5ghpo6 mcs5ghpo7"}, 1258 {PHY_TYPE_NULL, 0, ""} 1259 }; 1260 1261 typedef struct { 1262 uint8 tag; /* Broadcom subtag name */ 1263 uint32 revmask; /* Supported cis_sromrev bitmask. Some of the parameters in 1264 * different tuples have the same name. Therefore, the MFGc tool 1265 * needs to know which tuple to generate when seeing these 1266 * parameters (given that we know sromrev from user input, like the 1267 * nvram file). 1268 */ 1269 uint8 len; /* Length field of the tuple, note that it includes the 1270 * subtag name (1 byte): 1 + tuple content length 1271 */ 1272 const char *params; 1273 } cis_tuple_t; 1274 1275 #define OTP_RAW (0xff - 1) /* Reserved tuple number for wrvar Raw input */ 1276 #define OTP_VERS_1 (0xff - 2) /* CISTPL_VERS_1 */ 1277 #define OTP_MANFID (0xff - 3) /* CISTPL_MANFID */ 1278 #define OTP_RAW1 (0xff - 4) /* Like RAW, but comes first */ 1279 1280 /** this array is used by CIS creating/writing applications */ 1281 static const cis_tuple_t cis_hnbuvars[] = { 1282 /* tag revmask len params */ 1283 {OTP_RAW1, 0xffffffff, 0, ""}, /* special case */ 1284 {OTP_VERS_1, 0xffffffff, 0, "smanf sproductname"}, /* special case (non BRCM tuple) */ 1285 {OTP_MANFID, 0xffffffff, 4, "2manfid 2prodid"}, /* special case (non BRCM tuple) */ 1286 /* Unified OTP: tupple to embed USB manfid inside SDIO CIS */ 1287 {HNBU_UMANFID, 0xffffffff, 8, "8usbmanfid"}, 1288 {HNBU_SROMREV, 0xffffffff, 2, "1sromrev"}, 1289 /* NOTE: subdevid is also written to boardtype. 1290 * Need to write HNBU_BOARDTYPE to change it if it is different. 1291 */ 1292 {HNBU_CHIPID, 0xffffffff, 11, "2vendid 2devid 2chiprev 2subvendid 2subdevid"}, 1293 {HNBU_BOARDREV, 0xffffffff, 3, "2boardrev"}, 1294 {HNBU_PAPARMS, 0xffffffff, 10, "2pa0b0 2pa0b1 2pa0b2 1pa0itssit 1pa0maxpwr 1opo"}, 1295 {HNBU_AA, 0xffffffff, 3, "1aa2g 1aa5g"}, 1296 {HNBU_AA, 0xffffffff, 3, "1aa0 1aa1"}, /* backward compatibility */ 1297 {HNBU_AG, 0xffffffff, 5, "1ag0 1ag1 1ag2 1ag3"}, 1298 {HNBU_BOARDFLAGS, 0xffffffff, 21, "4boardflags 4boardflags2 4boardflags3 " 1299 "4boardflags4 4boardflags5 "}, 1300 {HNBU_LEDS, 0xffffffff, 17, "1ledbh0 1ledbh1 1ledbh2 1ledbh3 1ledbh4 1ledbh5 " 1301 "1ledbh6 1ledbh7 1ledbh8 1ledbh9 1ledbh10 1ledbh11 1ledbh12 1ledbh13 1ledbh14 1ledbh15"}, 1302 {HNBU_CCODE, 0xffffffff, 4, "2ccode 1cctl"}, 1303 {HNBU_CCKPO, 0xffffffff, 3, "2cckpo"}, 1304 {HNBU_OFDMPO, 0xffffffff, 5, "4ofdmpo"}, 1305 {HNBU_PAPARMS5G, 0xffffffff, 23, "2pa1b0 2pa1b1 2pa1b2 2pa1lob0 2pa1lob1 2pa1lob2 " 1306 "2pa1hib0 2pa1hib1 2pa1hib2 1pa1itssit " 1307 "1pa1maxpwr 1pa1lomaxpwr 1pa1himaxpwr"}, 1308 {HNBU_RDLID, 0xffffffff, 3, "2rdlid"}, 1309 {HNBU_RSSISMBXA2G, 0xffffffff, 3, "0rssismf2g 0rssismc2g " 1310 "0rssisav2g 0bxa2g"}, /* special case */ 1311 {HNBU_RSSISMBXA5G, 0xffffffff, 3, "0rssismf5g 0rssismc5g " 1312 "0rssisav5g 0bxa5g"}, /* special case */ 1313 {HNBU_XTALFREQ, 0xffffffff, 5, "4xtalfreq"}, 1314 {HNBU_TRI2G, 0xffffffff, 2, "1tri2g"}, 1315 {HNBU_TRI5G, 0xffffffff, 4, "1tri5gl 1tri5g 1tri5gh"}, 1316 {HNBU_RXPO2G, 0xffffffff, 2, "1rxpo2g"}, 1317 {HNBU_RXPO5G, 0xffffffff, 2, "1rxpo5g"}, 1318 {HNBU_BOARDNUM, 0xffffffff, 3, "2boardnum"}, 1319 {HNBU_MACADDR, 0xffffffff, 7, "6macaddr"}, /* special case */ 1320 {HNBU_RDLSN, 0xffffffff, 3, "2rdlsn"}, 1321 {HNBU_BOARDTYPE, 0xffffffff, 3, "2boardtype"}, 1322 {HNBU_LEDDC, 0xffffffff, 3, "2leddc"}, 1323 {HNBU_RDLRNDIS, 0xffffffff, 2, "1rdlndis"}, 1324 {HNBU_CHAINSWITCH, 0xffffffff, 5, "1txchain 1rxchain 2antswitch"}, 1325 {HNBU_REGREV, 0xffffffff, 3, "2regrev"}, 1326 {HNBU_FEM, 0x000007fe, 5, "0antswctl2g 0triso2g 0pdetrange2g 0extpagain2g " 1327 "0tssipos2g 0antswctl5g 0triso5g 0pdetrange5g 0extpagain5g 0tssipos5g"}, /* special case */ 1328 {HNBU_PAPARMS_C0, 0x000007fe, 31, "1maxp2ga0 1itt2ga0 2pa2gw0a0 2pa2gw1a0 " 1329 "2pa2gw2a0 1maxp5ga0 1itt5ga0 1maxp5gha0 1maxp5gla0 2pa5gw0a0 2pa5gw1a0 2pa5gw2a0 " 1330 "2pa5glw0a0 2pa5glw1a0 2pa5glw2a0 2pa5ghw0a0 2pa5ghw1a0 2pa5ghw2a0"}, 1331 {HNBU_PAPARMS_C1, 0x000007fe, 31, "1maxp2ga1 1itt2ga1 2pa2gw0a1 2pa2gw1a1 " 1332 "2pa2gw2a1 1maxp5ga1 1itt5ga1 1maxp5gha1 1maxp5gla1 2pa5gw0a1 2pa5gw1a1 2pa5gw2a1 " 1333 "2pa5glw0a1 2pa5glw1a1 2pa5glw2a1 2pa5ghw0a1 2pa5ghw1a1 2pa5ghw2a1"}, 1334 {HNBU_PO_CCKOFDM, 0xffffffff, 19, "2cck2gpo 4ofdm2gpo 4ofdm5gpo 4ofdm5glpo " 1335 "4ofdm5ghpo"}, 1336 {HNBU_PO_MCS2G, 0xffffffff, 17, "2mcs2gpo0 2mcs2gpo1 2mcs2gpo2 2mcs2gpo3 " 1337 "2mcs2gpo4 2mcs2gpo5 2mcs2gpo6 2mcs2gpo7"}, 1338 {HNBU_PO_MCS5GM, 0xffffffff, 17, "2mcs5gpo0 2mcs5gpo1 2mcs5gpo2 2mcs5gpo3 " 1339 "2mcs5gpo4 2mcs5gpo5 2mcs5gpo6 2mcs5gpo7"}, 1340 {HNBU_PO_MCS5GLH, 0xffffffff, 33, "2mcs5glpo0 2mcs5glpo1 2mcs5glpo2 2mcs5glpo3 " 1341 "2mcs5glpo4 2mcs5glpo5 2mcs5glpo6 2mcs5glpo7 " 1342 "2mcs5ghpo0 2mcs5ghpo1 2mcs5ghpo2 2mcs5ghpo3 " 1343 "2mcs5ghpo4 2mcs5ghpo5 2mcs5ghpo6 2mcs5ghpo7"}, 1344 {HNBU_CCKFILTTYPE, 0xffffffff, 2, "1cckdigfilttype"}, 1345 {HNBU_PO_CDD, 0xffffffff, 3, "2cddpo"}, 1346 {HNBU_PO_STBC, 0xffffffff, 3, "2stbcpo"}, 1347 {HNBU_PO_40M, 0xffffffff, 3, "2bw40po"}, 1348 {HNBU_PO_40MDUP, 0xffffffff, 3, "2bwduppo"}, 1349 {HNBU_RDLRWU, 0xffffffff, 2, "1rdlrwu"}, 1350 {HNBU_WPS, 0xffffffff, 3, "1wpsgpio 1wpsled"}, 1351 {HNBU_USBFS, 0xffffffff, 2, "1usbfs"}, 1352 {HNBU_ELNA2G, 0xffffffff, 2, "1elna2g"}, 1353 {HNBU_ELNA5G, 0xffffffff, 2, "1elna5g"}, 1354 {HNBU_CUSTOM1, 0xffffffff, 5, "4customvar1"}, 1355 {OTP_RAW, 0xffffffff, 0, ""}, /* special case */ 1356 {HNBU_OFDMPO5G, 0xffffffff, 13, "4ofdm5gpo 4ofdm5glpo 4ofdm5ghpo"}, 1357 {HNBU_USBEPNUM, 0xffffffff, 3, "2usbepnum"}, 1358 {HNBU_CCKBW202GPO, 0xffffffff, 7, "2cckbw202gpo 2cckbw20ul2gpo 2cckbw20in802gpo"}, 1359 {HNBU_LEGOFDMBW202GPO, 0xffffffff, 9, "4legofdmbw202gpo 4legofdmbw20ul2gpo"}, 1360 {HNBU_LEGOFDMBW205GPO, 0xffffffff, 25, "4legofdmbw205glpo 4legofdmbw20ul5glpo " 1361 "4legofdmbw205gmpo 4legofdmbw20ul5gmpo 4legofdmbw205ghpo 4legofdmbw20ul5ghpo"}, 1362 {HNBU_MCS2GPO, 0xffffffff, 17, "4mcsbw202gpo 4mcsbw20ul2gpo 4mcsbw402gpo 4mcsbw802gpo"}, 1363 {HNBU_MCS5GLPO, 0xffffffff, 13, "4mcsbw205glpo 4mcsbw20ul5glpo 4mcsbw405glpo"}, 1364 {HNBU_MCS5GMPO, 0xffffffff, 13, "4mcsbw205gmpo 4mcsbw20ul5gmpo 4mcsbw405gmpo"}, 1365 {HNBU_MCS5GHPO, 0xffffffff, 13, "4mcsbw205ghpo 4mcsbw20ul5ghpo 4mcsbw405ghpo"}, 1366 {HNBU_MCS32PO, 0xffffffff, 3, "2mcs32po"}, 1367 {HNBU_LEG40DUPPO, 0xffffffff, 3, "2legofdm40duppo"}, 1368 {HNBU_TEMPTHRESH, 0xffffffff, 7, "1tempthresh 0temps_period 0temps_hysteresis " 1369 "1tempoffset 1tempsense_slope 0tempcorrx 0tempsense_option " 1370 "1phycal_tempdelta"}, /* special case */ 1371 {HNBU_MUXENAB, 0xffffffff, 2, "1muxenab"}, 1372 {HNBU_FEM_CFG, 0xfffff800, 5, "0femctrl 0papdcap2g 0tworangetssi2g 0pdgain2g " 1373 "0epagain2g 0tssiposslope2g 0gainctrlsph 0papdcap5g 0tworangetssi5g 0pdgain5g 0epagain5g " 1374 "0tssiposslope5g"}, /* special case */ 1375 {HNBU_ACPA_C0, 0x00001800, 39, "2subband5gver 2maxp2ga0 2*3pa2ga0 " 1376 "1*4maxp5ga0 2*12pa5ga0"}, 1377 {HNBU_ACPA_C1, 0x00001800, 37, "2maxp2ga1 2*3pa2ga1 1*4maxp5ga1 2*12pa5ga1"}, 1378 {HNBU_ACPA_C2, 0x00001800, 37, "2maxp2ga2 2*3pa2ga2 1*4maxp5ga2 2*12pa5ga2"}, 1379 {HNBU_MEAS_PWR, 0xfffff800, 5, "1measpower 1measpower1 1measpower2 2rawtempsense"}, 1380 {HNBU_PDOFF, 0xfffff800, 13, "2pdoffset40ma0 2pdoffset40ma1 2pdoffset40ma2 " 1381 "2pdoffset80ma0 2pdoffset80ma1 2pdoffset80ma2"}, 1382 {HNBU_ACPPR_2GPO, 0xfffff800, 13, "2dot11agofdmhrbw202gpo 2ofdmlrbw202gpo " 1383 "2sb20in40dot11agofdm2gpo 2sb20in80dot11agofdm2gpo 2sb20in40ofdmlrbw202gpo " 1384 "2sb20in80ofdmlrbw202gpo"}, 1385 {HNBU_ACPPR_5GPO, 0xfffff800, 59, "4mcsbw805glpo 4mcsbw1605glpo 4mcsbw805gmpo " 1386 "4mcsbw1605gmpo 4mcsbw805ghpo 4mcsbw1605ghpo 2mcslr5glpo 2mcslr5gmpo 2mcslr5ghpo " 1387 "4mcsbw80p805glpo 4mcsbw80p805gmpo 4mcsbw80p805ghpo 4mcsbw80p805gx1po 2mcslr5gx1po " 1388 "2mcslr5g80p80po 4mcsbw805gx1po 4mcsbw1605gx1po"}, 1389 {HNBU_MCS5Gx1PO, 0xfffff800, 9, "4mcsbw205gx1po 4mcsbw405gx1po"}, 1390 {HNBU_ACPPR_SBPO, 0xfffff800, 49, "2sb20in40hrpo 2sb20in80and160hr5glpo " 1391 "2sb40and80hr5glpo 2sb20in80and160hr5gmpo 2sb40and80hr5gmpo 2sb20in80and160hr5ghpo " 1392 "2sb40and80hr5ghpo 2sb20in40lrpo 2sb20in80and160lr5glpo 2sb40and80lr5glpo " 1393 "2sb20in80and160lr5gmpo 2sb40and80lr5gmpo 2sb20in80and160lr5ghpo 2sb40and80lr5ghpo " 1394 "4dot11agduphrpo 4dot11agduplrpo 2sb20in40and80hrpo 2sb20in40and80lrpo " 1395 "2sb20in80and160hr5gx1po 2sb20in80and160lr5gx1po 2sb40and80hr5gx1po 2sb40and80lr5gx1po " 1396 }, 1397 {HNBU_ACPPR_SB8080_PO, 0xfffff800, 23, "2sb2040and80in80p80hr5glpo " 1398 "2sb2040and80in80p80lr5glpo 2sb2040and80in80p80hr5gmpo " 1399 "2sb2040and80in80p80lr5gmpo 2sb2040and80in80p80hr5ghpo 2sb2040and80in80p80lr5ghpo " 1400 "2sb2040and80in80p80hr5gx1po 2sb2040and80in80p80lr5gx1po 2sb20in80p80hr5gpo " 1401 "2sb20in80p80lr5gpo 2dot11agduppo"}, 1402 {HNBU_NOISELVL, 0xfffff800, 16, "1noiselvl2ga0 1noiselvl2ga1 1noiselvl2ga2 " 1403 "1*4noiselvl5ga0 1*4noiselvl5ga1 1*4noiselvl5ga2"}, 1404 {HNBU_RXGAIN_ERR, 0xfffff800, 16, "1rxgainerr2ga0 1rxgainerr2ga1 1rxgainerr2ga2 " 1405 "1*4rxgainerr5ga0 1*4rxgainerr5ga1 1*4rxgainerr5ga2"}, 1406 {HNBU_AGBGA, 0xfffff800, 7, "1agbg0 1agbg1 1agbg2 1aga0 1aga1 1aga2"}, 1407 {HNBU_USBDESC_COMPOSITE, 0xffffffff, 3, "2usbdesc_composite"}, 1408 {HNBU_UUID, 0xffffffff, 17, "16uuid"}, 1409 {HNBU_WOWLGPIO, 0xffffffff, 2, "1wowl_gpio"}, 1410 {HNBU_ACRXGAINS_C0, 0xfffff800, 5, "0rxgains5gtrelnabypa0 0rxgains5gtrisoa0 " 1411 "0rxgains5gelnagaina0 0rxgains2gtrelnabypa0 0rxgains2gtrisoa0 0rxgains2gelnagaina0 " 1412 "0rxgains5ghtrelnabypa0 0rxgains5ghtrisoa0 0rxgains5ghelnagaina0 0rxgains5gmtrelnabypa0 " 1413 "0rxgains5gmtrisoa0 0rxgains5gmelnagaina0"}, /* special case */ 1414 {HNBU_ACRXGAINS_C1, 0xfffff800, 5, "0rxgains5gtrelnabypa1 0rxgains5gtrisoa1 " 1415 "0rxgains5gelnagaina1 0rxgains2gtrelnabypa1 0rxgains2gtrisoa1 0rxgains2gelnagaina1 " 1416 "0rxgains5ghtrelnabypa1 0rxgains5ghtrisoa1 0rxgains5ghelnagaina1 0rxgains5gmtrelnabypa1 " 1417 "0rxgains5gmtrisoa1 0rxgains5gmelnagaina1"}, /* special case */ 1418 {HNBU_ACRXGAINS_C2, 0xfffff800, 5, "0rxgains5gtrelnabypa2 0rxgains5gtrisoa2 " 1419 "0rxgains5gelnagaina2 0rxgains2gtrelnabypa2 0rxgains2gtrisoa2 0rxgains2gelnagaina2 " 1420 "0rxgains5ghtrelnabypa2 0rxgains5ghtrisoa2 0rxgains5ghelnagaina2 0rxgains5gmtrelnabypa2 " 1421 "0rxgains5gmtrisoa2 0rxgains5gmelnagaina2"}, /* special case */ 1422 {HNBU_TXDUTY, 0xfffff800, 9, "2tx_duty_cycle_ofdm_40_5g " 1423 "2tx_duty_cycle_thresh_40_5g 2tx_duty_cycle_ofdm_80_5g 2tx_duty_cycle_thresh_80_5g"}, 1424 {HNBU_PDOFF_2G, 0xfffff800, 3, "0pdoffset2g40ma0 0pdoffset2g40ma1 " 1425 "0pdoffset2g40ma2 0pdoffset2g40mvalid"}, 1426 {HNBU_ACPA_CCK_C0, 0xfffff800, 7, "2*3pa2gccka0"}, 1427 {HNBU_ACPA_CCK_C1, 0xfffff800, 7, "2*3pa2gccka1"}, 1428 {HNBU_ACPA_40, 0xfffff800, 25, "2*12pa5gbw40a0"}, 1429 {HNBU_ACPA_80, 0xfffff800, 25, "2*12pa5gbw80a0"}, 1430 {HNBU_ACPA_4080, 0xfffff800, 49, "2*12pa5gbw4080a0 2*12pa5gbw4080a1"}, 1431 {HNBU_ACPA_4X4C0, 0xffffe000, 23, "1maxp2ga0 2*4pa2ga0 2*4pa2g40a0 " 1432 "1maxp5gb0a0 1maxp5gb1a0 1maxp5gb2a0 1maxp5gb3a0 1maxp5gb4a0"}, 1433 {HNBU_ACPA_4X4C1, 0xffffe000, 23, "1maxp2ga1 2*4pa2ga1 2*4pa2g40a1 " 1434 "1maxp5gb0a1 1maxp5gb1a1 1maxp5gb2a1 1maxp5gb3a1 1maxp5gb4a1"}, 1435 {HNBU_ACPA_4X4C2, 0xffffe000, 23, "1maxp2ga2 2*4pa2ga2 2*4pa2g40a2 " 1436 "1maxp5gb0a2 1maxp5gb1a2 1maxp5gb2a2 1maxp5gb3a2 1maxp5gb4a2"}, 1437 {HNBU_ACPA_4X4C3, 0xffffe000, 23, "1maxp2ga3 2*4pa2ga3 2*4pa2g40a3 " 1438 "1maxp5gb0a3 1maxp5gb1a3 1maxp5gb2a3 1maxp5gb3a3 1maxp5gb4a3"}, 1439 {HNBU_ACPA_BW20_4X4C0, 0xffffe000, 41, "2*20pa5ga0"}, 1440 {HNBU_ACPA_BW40_4X4C0, 0xffffe000, 41, "2*20pa5g40a0"}, 1441 {HNBU_ACPA_BW80_4X4C0, 0xffffe000, 41, "2*20pa5g80a0"}, 1442 {HNBU_ACPA_BW20_4X4C1, 0xffffe000, 41, "2*20pa5ga1"}, 1443 {HNBU_ACPA_BW40_4X4C1, 0xffffe000, 41, "2*20pa5g40a1"}, 1444 {HNBU_ACPA_BW80_4X4C1, 0xffffe000, 41, "2*20pa5g80a1"}, 1445 {HNBU_ACPA_BW20_4X4C2, 0xffffe000, 41, "2*20pa5ga2"}, 1446 {HNBU_ACPA_BW40_4X4C2, 0xffffe000, 41, "2*20pa5g40a2"}, 1447 {HNBU_ACPA_BW80_4X4C2, 0xffffe000, 41, "2*20pa5g80a2"}, 1448 {HNBU_ACPA_BW20_4X4C3, 0xffffe000, 41, "2*20pa5ga3"}, 1449 {HNBU_ACPA_BW40_4X4C3, 0xffffe000, 41, "2*20pa5g40a3"}, 1450 {HNBU_ACPA_BW80_4X4C3, 0xffffe000, 41, "2*20pa5g80a3"}, 1451 {HNBU_SUBBAND5GVER, 0xfffff800, 3, "2subband5gver"}, 1452 {HNBU_PAPARAMBWVER, 0xfffff800, 2, "1paparambwver"}, 1453 {HNBU_TXBFRPCALS, 0xfffff800, 11, 1454 "2rpcal2g 2rpcal5gb0 2rpcal5gb1 2rpcal5gb2 2rpcal5gb3"}, /* txbf rpcalvars */ 1455 {HNBU_GPIO_PULL_DOWN, 0xffffffff, 5, "4gpdn"}, 1456 {HNBU_MACADDR2, 0xffffffff, 7, "6macaddr2"}, /* special case */ 1457 {0xFF, 0xffffffff, 0, ""} 1458 }; 1459 1460 #endif /* _bcmsrom_tbl_h_ */ 1461