1 /* 2 * SROM format definition. 3 * 4 * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation 5 * 6 * Copyright (C) 1999-2017, Broadcom Corporation 7 * 8 * Unless you and Broadcom execute a separate written software license 9 * agreement governing use of this software, this software is licensed to you 10 * under the terms of the GNU General Public License version 2 (the "GPL"), 11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12 * following added to such license: 13 * 14 * As a special exception, the copyright holders of this software give you 15 * permission to link this software with independent modules, and to copy and 16 * distribute the resulting executable under terms of your choice, provided that 17 * you also meet, for each linked independent module, the terms and conditions of 18 * the license of that module. An independent module is a module which is not 19 * derived from this software. The special exception does not apply to any 20 * modifications of the software. 21 * 22 * Notwithstanding the above, under no circumstances may you combine this 23 * software in any way with any other Broadcom software provided under a license 24 * other than the GPL, without Broadcom's express prior written consent. 25 * 26 * 27 * <<Broadcom-WL-IPTag/Open:>> 28 * 29 * $Id: bcmsrom_fmt.h 688657 2017-03-07 10:12:56Z $ 30 */ 31 32 #ifndef _bcmsrom_fmt_h_ 33 #define _bcmsrom_fmt_h_ 34 35 #define SROM_MAXREV 16 /* max revision supported by driver */ 36 37 /* Maximum srom: 16 Kilobits == 2048 bytes */ 38 39 #define SROM_MAX 2048 40 #define SROM_MAXW 1024 41 42 #ifdef LARGE_NVRAM_MAXSZ 43 #define VARS_MAX LARGE_NVRAM_MAXSZ 44 #else 45 #define LARGE_NVRAM_MAXSZ 8192 46 #define VARS_MAX LARGE_NVRAM_MAXSZ 47 #endif /* LARGE_NVRAM_MAXSZ */ 48 49 /* PCI fields */ 50 #define PCI_F0DEVID 48 51 52 #define SROM_WORDS 64 53 #define SROM_SIGN_MINWORDS 128 54 #define SROM3_SWRGN_OFF 28 /* s/w region offset in words */ 55 56 #define SROM_SSID 2 57 #define SROM_SVID 3 58 59 #define SROM_WL1LHMAXP 29 60 61 #define SROM_WL1LPAB0 30 62 #define SROM_WL1LPAB1 31 63 #define SROM_WL1LPAB2 32 64 65 #define SROM_WL1HPAB0 33 66 #define SROM_WL1HPAB1 34 67 #define SROM_WL1HPAB2 35 68 69 #define SROM_MACHI_IL0 36 70 #define SROM_MACMID_IL0 37 71 #define SROM_MACLO_IL0 38 72 #define SROM_MACHI_ET0 39 73 #define SROM_MACMID_ET0 40 74 #define SROM_MACLO_ET0 41 75 #define SROM_MACHI_ET1 42 76 #define SROM_MACMID_ET1 43 77 #define SROM_MACLO_ET1 44 78 #define SROM3_MACHI 37 79 #define SROM3_MACMID 38 80 #define SROM3_MACLO 39 81 82 #define SROM_BXARSSI2G 40 83 #define SROM_BXARSSI5G 41 84 85 #define SROM_TRI52G 42 86 #define SROM_TRI5GHL 43 87 88 #define SROM_RXPO52G 45 89 90 #define SROM2_ENETPHY 45 91 92 #define SROM_AABREV 46 93 /* Fields in AABREV */ 94 #define SROM_BR_MASK 0x00ff 95 #define SROM_CC_MASK 0x0f00 96 #define SROM_CC_SHIFT 8 97 #define SROM_AA0_MASK 0x3000 98 #define SROM_AA0_SHIFT 12 99 #define SROM_AA1_MASK 0xc000 100 #define SROM_AA1_SHIFT 14 101 102 #define SROM_WL0PAB0 47 103 #define SROM_WL0PAB1 48 104 #define SROM_WL0PAB2 49 105 106 #define SROM_LEDBH10 50 107 #define SROM_LEDBH32 51 108 109 #define SROM_WL10MAXP 52 110 111 #define SROM_WL1PAB0 53 112 #define SROM_WL1PAB1 54 113 #define SROM_WL1PAB2 55 114 115 #define SROM_ITT 56 116 117 #define SROM_BFL 57 118 #define SROM_BFL2 28 119 #define SROM3_BFL2 61 120 121 #define SROM_AG10 58 122 123 #define SROM_CCODE 59 124 125 #define SROM_OPO 60 126 127 #define SROM3_LEDDC 62 128 129 #define SROM_CRCREV 63 130 131 /* SROM Rev 4: Reallocate the software part of the srom to accomodate 132 * MIMO features. It assumes up to two PCIE functions and 440 bytes 133 * of useable srom i.e. the useable storage in chips with OTP that 134 * implements hardware redundancy. 135 */ 136 137 #define SROM4_WORDS 220 138 139 #define SROM4_SIGN 32 140 #define SROM4_SIGNATURE 0x5372 141 142 #define SROM4_BREV 33 143 144 #define SROM4_BFL0 34 145 #define SROM4_BFL1 35 146 #define SROM4_BFL2 36 147 #define SROM4_BFL3 37 148 #define SROM5_BFL0 37 149 #define SROM5_BFL1 38 150 #define SROM5_BFL2 39 151 #define SROM5_BFL3 40 152 153 #define SROM4_MACHI 38 154 #define SROM4_MACMID 39 155 #define SROM4_MACLO 40 156 #define SROM5_MACHI 41 157 #define SROM5_MACMID 42 158 #define SROM5_MACLO 43 159 160 #define SROM4_CCODE 41 161 #define SROM4_REGREV 42 162 #define SROM5_CCODE 34 163 #define SROM5_REGREV 35 164 165 #define SROM4_LEDBH10 43 166 #define SROM4_LEDBH32 44 167 #define SROM5_LEDBH10 59 168 #define SROM5_LEDBH32 60 169 170 #define SROM4_LEDDC 45 171 #define SROM5_LEDDC 45 172 173 #define SROM4_AA 46 174 #define SROM4_AA2G_MASK 0x00ff 175 #define SROM4_AA2G_SHIFT 0 176 #define SROM4_AA5G_MASK 0xff00 177 #define SROM4_AA5G_SHIFT 8 178 179 #define SROM4_AG10 47 180 #define SROM4_AG32 48 181 182 #define SROM4_TXPID2G 49 183 #define SROM4_TXPID5G 51 184 #define SROM4_TXPID5GL 53 185 #define SROM4_TXPID5GH 55 186 187 #define SROM4_TXRXC 61 188 #define SROM4_TXCHAIN_MASK 0x000f 189 #define SROM4_TXCHAIN_SHIFT 0 190 #define SROM4_RXCHAIN_MASK 0x00f0 191 #define SROM4_RXCHAIN_SHIFT 4 192 #define SROM4_SWITCH_MASK 0xff00 193 #define SROM4_SWITCH_SHIFT 8 194 195 /* Per-path fields */ 196 #define MAX_PATH_SROM 4 197 #define SROM4_PATH0 64 198 #define SROM4_PATH1 87 199 #define SROM4_PATH2 110 200 #define SROM4_PATH3 133 201 202 #define SROM4_2G_ITT_MAXP 0 203 #define SROM4_2G_PA 1 204 #define SROM4_5G_ITT_MAXP 5 205 #define SROM4_5GLH_MAXP 6 206 #define SROM4_5G_PA 7 207 #define SROM4_5GL_PA 11 208 #define SROM4_5GH_PA 15 209 210 /* Fields in the ITT_MAXP and 5GLH_MAXP words */ 211 #define B2G_MAXP_MASK 0xff 212 #define B2G_ITT_SHIFT 8 213 #define B5G_MAXP_MASK 0xff 214 #define B5G_ITT_SHIFT 8 215 #define B5GH_MAXP_MASK 0xff 216 #define B5GL_MAXP_SHIFT 8 217 218 /* All the miriad power offsets */ 219 #define SROM4_2G_CCKPO 156 220 #define SROM4_2G_OFDMPO 157 221 #define SROM4_5G_OFDMPO 159 222 #define SROM4_5GL_OFDMPO 161 223 #define SROM4_5GH_OFDMPO 163 224 #define SROM4_2G_MCSPO 165 225 #define SROM4_5G_MCSPO 173 226 #define SROM4_5GL_MCSPO 181 227 #define SROM4_5GH_MCSPO 189 228 #define SROM4_CDDPO 197 229 #define SROM4_STBCPO 198 230 #define SROM4_BW40PO 199 231 #define SROM4_BWDUPPO 200 232 233 #define SROM4_CRCREV 219 234 235 /* SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6. 236 * This is acombined srom for both MIMO and SISO boards, usable in 237 * the .130 4Kilobit OTP with hardware redundancy. 238 */ 239 240 #define SROM8_SIGN 64 241 242 #define SROM8_BREV 65 243 244 #define SROM8_BFL0 66 245 #define SROM8_BFL1 67 246 #define SROM8_BFL2 68 247 #define SROM8_BFL3 69 248 249 #define SROM8_MACHI 70 250 #define SROM8_MACMID 71 251 #define SROM8_MACLO 72 252 253 #define SROM8_CCODE 73 254 #define SROM8_REGREV 74 255 256 #define SROM8_LEDBH10 75 257 #define SROM8_LEDBH32 76 258 259 #define SROM8_LEDDC 77 260 261 #define SROM8_AA 78 262 263 #define SROM8_AG10 79 264 #define SROM8_AG32 80 265 266 #define SROM8_TXRXC 81 267 268 #define SROM8_BXARSSI2G 82 269 #define SROM8_BXARSSI5G 83 270 #define SROM8_TRI52G 84 271 #define SROM8_TRI5GHL 85 272 #define SROM8_RXPO52G 86 273 274 #define SROM8_FEM2G 87 275 #define SROM8_FEM5G 88 276 #define SROM8_FEM_ANTSWLUT_MASK 0xf800 277 #define SROM8_FEM_ANTSWLUT_SHIFT 11 278 #define SROM8_FEM_TR_ISO_MASK 0x0700 279 #define SROM8_FEM_TR_ISO_SHIFT 8 280 #define SROM8_FEM_PDET_RANGE_MASK 0x00f8 281 #define SROM8_FEM_PDET_RANGE_SHIFT 3 282 #define SROM8_FEM_EXTPA_GAIN_MASK 0x0006 283 #define SROM8_FEM_EXTPA_GAIN_SHIFT 1 284 #define SROM8_FEM_TSSIPOS_MASK 0x0001 285 #define SROM8_FEM_TSSIPOS_SHIFT 0 286 287 #define SROM8_THERMAL 89 288 289 /* Temp sense related entries */ 290 #define SROM8_MPWR_RAWTS 90 291 #define SROM8_TS_SLP_OPT_CORRX 91 292 /* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */ 293 #define SROM8_FOC_HWIQ_IQSWP 92 294 295 #define SROM8_EXTLNAGAIN 93 296 297 /* Temperature delta for PHY calibration */ 298 #define SROM8_PHYCAL_TEMPDELTA 94 299 300 /* Measured power 1 & 2, 0-13 bits at offset 95, MSB 2 bits are unused for now. */ 301 #define SROM8_MPWR_1_AND_2 95 302 303 /* Per-path offsets & fields */ 304 #define SROM8_PATH0 96 305 #define SROM8_PATH1 112 306 #define SROM8_PATH2 128 307 #define SROM8_PATH3 144 308 309 #define SROM8_2G_ITT_MAXP 0 310 #define SROM8_2G_PA 1 311 #define SROM8_5G_ITT_MAXP 4 312 #define SROM8_5GLH_MAXP 5 313 #define SROM8_5G_PA 6 314 #define SROM8_5GL_PA 9 315 #define SROM8_5GH_PA 12 316 317 /* All the miriad power offsets */ 318 #define SROM8_2G_CCKPO 160 319 320 #define SROM8_2G_OFDMPO 161 321 #define SROM8_5G_OFDMPO 163 322 #define SROM8_5GL_OFDMPO 165 323 #define SROM8_5GH_OFDMPO 167 324 325 #define SROM8_2G_MCSPO 169 326 #define SROM8_5G_MCSPO 177 327 #define SROM8_5GL_MCSPO 185 328 #define SROM8_5GH_MCSPO 193 329 330 #define SROM8_CDDPO 201 331 #define SROM8_STBCPO 202 332 #define SROM8_BW40PO 203 333 #define SROM8_BWDUPPO 204 334 335 /* SISO PA parameters are in the path0 spaces */ 336 #define SROM8_SISO 96 337 338 /* Legacy names for SISO PA paramters */ 339 #define SROM8_W0_ITTMAXP (SROM8_SISO + SROM8_2G_ITT_MAXP) 340 #define SROM8_W0_PAB0 (SROM8_SISO + SROM8_2G_PA) 341 #define SROM8_W0_PAB1 (SROM8_SISO + SROM8_2G_PA + 1) 342 #define SROM8_W0_PAB2 (SROM8_SISO + SROM8_2G_PA + 2) 343 #define SROM8_W1_ITTMAXP (SROM8_SISO + SROM8_5G_ITT_MAXP) 344 #define SROM8_W1_MAXP_LCHC (SROM8_SISO + SROM8_5GLH_MAXP) 345 #define SROM8_W1_PAB0 (SROM8_SISO + SROM8_5G_PA) 346 #define SROM8_W1_PAB1 (SROM8_SISO + SROM8_5G_PA + 1) 347 #define SROM8_W1_PAB2 (SROM8_SISO + SROM8_5G_PA + 2) 348 #define SROM8_W1_PAB0_LC (SROM8_SISO + SROM8_5GL_PA) 349 #define SROM8_W1_PAB1_LC (SROM8_SISO + SROM8_5GL_PA + 1) 350 #define SROM8_W1_PAB2_LC (SROM8_SISO + SROM8_5GL_PA + 2) 351 #define SROM8_W1_PAB0_HC (SROM8_SISO + SROM8_5GH_PA) 352 #define SROM8_W1_PAB1_HC (SROM8_SISO + SROM8_5GH_PA + 1) 353 #define SROM8_W1_PAB2_HC (SROM8_SISO + SROM8_5GH_PA + 2) 354 355 #define SROM8_CRCREV 219 356 357 /* SROM REV 9 */ 358 #define SROM9_2GPO_CCKBW20 160 359 #define SROM9_2GPO_CCKBW20UL 161 360 #define SROM9_2GPO_LOFDMBW20 162 361 #define SROM9_2GPO_LOFDMBW20UL 164 362 363 #define SROM9_5GLPO_LOFDMBW20 166 364 #define SROM9_5GLPO_LOFDMBW20UL 168 365 #define SROM9_5GMPO_LOFDMBW20 170 366 #define SROM9_5GMPO_LOFDMBW20UL 172 367 #define SROM9_5GHPO_LOFDMBW20 174 368 #define SROM9_5GHPO_LOFDMBW20UL 176 369 370 #define SROM9_2GPO_MCSBW20 178 371 #define SROM9_2GPO_MCSBW20UL 180 372 #define SROM9_2GPO_MCSBW40 182 373 374 #define SROM9_5GLPO_MCSBW20 184 375 #define SROM9_5GLPO_MCSBW20UL 186 376 #define SROM9_5GLPO_MCSBW40 188 377 #define SROM9_5GMPO_MCSBW20 190 378 #define SROM9_5GMPO_MCSBW20UL 192 379 #define SROM9_5GMPO_MCSBW40 194 380 #define SROM9_5GHPO_MCSBW20 196 381 #define SROM9_5GHPO_MCSBW20UL 198 382 #define SROM9_5GHPO_MCSBW40 200 383 384 #define SROM9_PO_MCS32 202 385 #define SROM9_PO_LOFDM40DUP 203 386 #define SROM9_EU_EDCRSTH 204 387 #define SROM10_EU_EDCRSTH 204 388 #define SROM8_RXGAINERR_2G 205 389 #define SROM8_RXGAINERR_5GL 206 390 #define SROM8_RXGAINERR_5GM 207 391 #define SROM8_RXGAINERR_5GH 208 392 #define SROM8_RXGAINERR_5GU 209 393 #define SROM8_SUBBAND_PPR 210 394 #define SROM8_PCIEINGRESS_WAR 211 395 #define SROM8_EU_EDCRSTH 212 396 #define SROM9_SAR 212 397 398 #define SROM8_NOISELVL_2G 213 399 #define SROM8_NOISELVL_5GL 214 400 #define SROM8_NOISELVL_5GM 215 401 #define SROM8_NOISELVL_5GH 216 402 #define SROM8_NOISELVL_5GU 217 403 #define SROM8_NOISECALOFFSET 218 404 405 #define SROM9_REV_CRC 219 406 407 #define SROM10_CCKPWROFFSET 218 408 #define SROM10_SIGN 219 409 #define SROM10_SWCTRLMAP_2G 220 410 #define SROM10_CRCREV 229 411 412 #define SROM10_WORDS 230 413 #define SROM10_SIGNATURE SROM4_SIGNATURE 414 415 /* SROM REV 11 */ 416 #define SROM11_BREV 65 417 418 #define SROM11_BFL0 66 419 #define SROM11_BFL1 67 420 #define SROM11_BFL2 68 421 #define SROM11_BFL3 69 422 #define SROM11_BFL4 70 423 #define SROM11_BFL5 71 424 425 #define SROM11_MACHI 72 426 #define SROM11_MACMID 73 427 #define SROM11_MACLO 74 428 429 #define SROM11_CCODE 75 430 #define SROM11_REGREV 76 431 432 #define SROM11_LEDBH10 77 433 #define SROM11_LEDBH32 78 434 435 #define SROM11_LEDDC 79 436 437 #define SROM11_AA 80 438 439 #define SROM11_AGBG10 81 440 #define SROM11_AGBG2A0 82 441 #define SROM11_AGA21 83 442 443 #define SROM11_TXRXC 84 444 445 #define SROM11_FEM_CFG1 85 446 #define SROM11_FEM_CFG2 86 447 448 /* Masks and offsets for FEM_CFG */ 449 #define SROM11_FEMCTRL_MASK 0xf800 450 #define SROM11_FEMCTRL_SHIFT 11 451 #define SROM11_PAPDCAP_MASK 0x0400 452 #define SROM11_PAPDCAP_SHIFT 10 453 #define SROM11_TWORANGETSSI_MASK 0x0200 454 #define SROM11_TWORANGETSSI_SHIFT 9 455 #define SROM11_PDGAIN_MASK 0x01f0 456 #define SROM11_PDGAIN_SHIFT 4 457 #define SROM11_EPAGAIN_MASK 0x000e 458 #define SROM11_EPAGAIN_SHIFT 1 459 #define SROM11_TSSIPOSSLOPE_MASK 0x0001 460 #define SROM11_TSSIPOSSLOPE_SHIFT 0 461 #define SROM11_GAINCTRLSPH_MASK 0xf800 462 #define SROM11_GAINCTRLSPH_SHIFT 11 463 464 #define SROM11_THERMAL 87 465 #define SROM11_MPWR_RAWTS 88 466 #define SROM11_TS_SLP_OPT_CORRX 89 467 #define SROM11_XTAL_FREQ 90 468 #define SROM11_5GB0_4080_W0_A1 91 469 #define SROM11_PHYCAL_TEMPDELTA 92 470 #define SROM11_MPWR_1_AND_2 93 471 #define SROM11_5GB0_4080_W1_A1 94 472 #define SROM11_TSSIFLOOR_2G 95 473 #define SROM11_TSSIFLOOR_5GL 96 474 #define SROM11_TSSIFLOOR_5GM 97 475 #define SROM11_TSSIFLOOR_5GH 98 476 #define SROM11_TSSIFLOOR_5GU 99 477 478 /* Masks and offsets for Thermal parameters */ 479 #define SROM11_TEMPS_PERIOD_MASK 0xf0 480 #define SROM11_TEMPS_PERIOD_SHIFT 4 481 #define SROM11_TEMPS_HYSTERESIS_MASK 0x0f 482 #define SROM11_TEMPS_HYSTERESIS_SHIFT 0 483 #define SROM11_TEMPCORRX_MASK 0xfc 484 #define SROM11_TEMPCORRX_SHIFT 2 485 #define SROM11_TEMPSENSE_OPTION_MASK 0x3 486 #define SROM11_TEMPSENSE_OPTION_SHIFT 0 487 488 #define SROM11_PDOFF_2G_40M_A0_MASK 0x000f 489 #define SROM11_PDOFF_2G_40M_A0_SHIFT 0 490 #define SROM11_PDOFF_2G_40M_A1_MASK 0x00f0 491 #define SROM11_PDOFF_2G_40M_A1_SHIFT 4 492 #define SROM11_PDOFF_2G_40M_A2_MASK 0x0f00 493 #define SROM11_PDOFF_2G_40M_A2_SHIFT 8 494 #define SROM11_PDOFF_2G_40M_VALID_MASK 0x8000 495 #define SROM11_PDOFF_2G_40M_VALID_SHIFT 15 496 497 #define SROM11_PDOFF_2G_40M 100 498 #define SROM11_PDOFF_40M_A0 101 499 #define SROM11_PDOFF_40M_A1 102 500 #define SROM11_PDOFF_40M_A2 103 501 #define SROM11_5GB0_4080_W2_A1 103 502 #define SROM11_PDOFF_80M_A0 104 503 #define SROM11_PDOFF_80M_A1 105 504 #define SROM11_PDOFF_80M_A2 106 505 #define SROM11_5GB1_4080_W0_A1 106 506 507 #define SROM11_SUBBAND5GVER 107 508 509 /* Per-path fields and offset */ 510 #define MAX_PATH_SROM_11 3 511 #define SROM11_PATH0 108 512 #define SROM11_PATH1 128 513 #define SROM11_PATH2 148 514 515 #define SROM11_2G_MAXP 0 516 #define SROM11_5GB1_4080_PA 0 517 #define SROM11_2G_PA 1 518 #define SROM11_5GB2_4080_PA 2 519 #define SROM11_RXGAINS1 4 520 #define SROM11_RXGAINS 5 521 #define SROM11_5GB3_4080_PA 5 522 #define SROM11_5GB1B0_MAXP 6 523 #define SROM11_5GB3B2_MAXP 7 524 #define SROM11_5GB0_PA 8 525 #define SROM11_5GB1_PA 11 526 #define SROM11_5GB2_PA 14 527 #define SROM11_5GB3_PA 17 528 529 /* Masks and offsets for rxgains */ 530 #define SROM11_RXGAINS5GTRELNABYPA_MASK 0x8000 531 #define SROM11_RXGAINS5GTRELNABYPA_SHIFT 15 532 #define SROM11_RXGAINS5GTRISOA_MASK 0x7800 533 #define SROM11_RXGAINS5GTRISOA_SHIFT 11 534 #define SROM11_RXGAINS5GELNAGAINA_MASK 0x0700 535 #define SROM11_RXGAINS5GELNAGAINA_SHIFT 8 536 #define SROM11_RXGAINS2GTRELNABYPA_MASK 0x0080 537 #define SROM11_RXGAINS2GTRELNABYPA_SHIFT 7 538 #define SROM11_RXGAINS2GTRISOA_MASK 0x0078 539 #define SROM11_RXGAINS2GTRISOA_SHIFT 3 540 #define SROM11_RXGAINS2GELNAGAINA_MASK 0x0007 541 #define SROM11_RXGAINS2GELNAGAINA_SHIFT 0 542 #define SROM11_RXGAINS5GHTRELNABYPA_MASK 0x8000 543 #define SROM11_RXGAINS5GHTRELNABYPA_SHIFT 15 544 #define SROM11_RXGAINS5GHTRISOA_MASK 0x7800 545 #define SROM11_RXGAINS5GHTRISOA_SHIFT 11 546 #define SROM11_RXGAINS5GHELNAGAINA_MASK 0x0700 547 #define SROM11_RXGAINS5GHELNAGAINA_SHIFT 8 548 #define SROM11_RXGAINS5GMTRELNABYPA_MASK 0x0080 549 #define SROM11_RXGAINS5GMTRELNABYPA_SHIFT 7 550 #define SROM11_RXGAINS5GMTRISOA_MASK 0x0078 551 #define SROM11_RXGAINS5GMTRISOA_SHIFT 3 552 #define SROM11_RXGAINS5GMELNAGAINA_MASK 0x0007 553 #define SROM11_RXGAINS5GMELNAGAINA_SHIFT 0 554 555 /* Power per rate */ 556 #define SROM11_CCKBW202GPO 168 557 #define SROM11_CCKBW20UL2GPO 169 558 #define SROM11_MCSBW202GPO 170 559 #define SROM11_MCSBW202GPO_1 171 560 #define SROM11_MCSBW402GPO 172 561 #define SROM11_MCSBW402GPO_1 173 562 #define SROM11_DOT11AGOFDMHRBW202GPO 174 563 #define SROM11_OFDMLRBW202GPO 175 564 565 #define SROM11_MCSBW205GLPO 176 566 #define SROM11_MCSBW205GLPO_1 177 567 #define SROM11_MCSBW405GLPO 178 568 #define SROM11_MCSBW405GLPO_1 179 569 #define SROM11_MCSBW805GLPO 180 570 #define SROM11_MCSBW805GLPO_1 181 571 #define SROM11_RPCAL_2G 182 572 #define SROM11_RPCAL_5GL 183 573 #define SROM11_MCSBW205GMPO 184 574 #define SROM11_MCSBW205GMPO_1 185 575 #define SROM11_MCSBW405GMPO 186 576 #define SROM11_MCSBW405GMPO_1 187 577 #define SROM11_MCSBW805GMPO 188 578 #define SROM11_MCSBW805GMPO_1 189 579 #define SROM11_RPCAL_5GM 190 580 #define SROM11_RPCAL_5GH 191 581 #define SROM11_MCSBW205GHPO 192 582 #define SROM11_MCSBW205GHPO_1 193 583 #define SROM11_MCSBW405GHPO 194 584 #define SROM11_MCSBW405GHPO_1 195 585 #define SROM11_MCSBW805GHPO 196 586 #define SROM11_MCSBW805GHPO_1 197 587 #define SROM11_RPCAL_5GU 198 588 #define SROM11_PDOFF_2G_CCK 199 589 #define SROM11_MCSLR5GLPO 200 590 #define SROM11_MCSLR5GMPO 201 591 #define SROM11_MCSLR5GHPO 202 592 593 #define SROM11_SB20IN40HRPO 203 594 #define SROM11_SB20IN80AND160HR5GLPO 204 595 #define SROM11_SB40AND80HR5GLPO 205 596 #define SROM11_SB20IN80AND160HR5GMPO 206 597 #define SROM11_SB40AND80HR5GMPO 207 598 #define SROM11_SB20IN80AND160HR5GHPO 208 599 #define SROM11_SB40AND80HR5GHPO 209 600 #define SROM11_SB20IN40LRPO 210 601 #define SROM11_SB20IN80AND160LR5GLPO 211 602 #define SROM11_SB40AND80LR5GLPO 212 603 #define SROM11_TXIDXCAP2G 212 604 #define SROM11_SB20IN80AND160LR5GMPO 213 605 #define SROM11_SB40AND80LR5GMPO 214 606 #define SROM11_TXIDXCAP5G 214 607 #define SROM11_SB20IN80AND160LR5GHPO 215 608 #define SROM11_SB40AND80LR5GHPO 216 609 610 #define SROM11_DOT11AGDUPHRPO 217 611 #define SROM11_DOT11AGDUPLRPO 218 612 613 /* MISC */ 614 #define SROM11_PCIEINGRESS_WAR 220 615 #define SROM11_SAR 221 616 617 #define SROM11_NOISELVL_2G 222 618 #define SROM11_NOISELVL_5GL 223 619 #define SROM11_NOISELVL_5GM 224 620 #define SROM11_NOISELVL_5GH 225 621 #define SROM11_NOISELVL_5GU 226 622 623 #define SROM11_RXGAINERR_2G 227 624 #define SROM11_RXGAINERR_5GL 228 625 #define SROM11_RXGAINERR_5GM 229 626 #define SROM11_RXGAINERR_5GH 230 627 #define SROM11_RXGAINERR_5GU 231 628 629 #define SROM11_EU_EDCRSTH 232 630 #define SROM12_EU_EDCRSTH 232 631 632 #define SROM11_SIGN 64 633 #define SROM11_CRCREV 233 634 635 #define SROM11_WORDS 234 636 #define SROM11_SIGNATURE 0x0634 637 638 /* SROM REV 12 */ 639 #define SROM12_SIGN 64 640 #define SROM12_WORDS 512 641 #define SROM12_SIGNATURE 0x8888 642 #define SROM12_CRCREV 511 643 644 #define SROM12_BFL6 486 645 #define SROM12_BFL7 487 646 647 #define SROM12_MCSBW205GX1PO 234 648 #define SROM12_MCSBW205GX1PO_1 235 649 #define SROM12_MCSBW405GX1PO 236 650 #define SROM12_MCSBW405GX1PO_1 237 651 #define SROM12_MCSBW805GX1PO 238 652 #define SROM12_MCSBW805GX1PO_1 239 653 #define SROM12_MCSLR5GX1PO 240 654 #define SROM12_SB40AND80LR5GX1PO 241 655 #define SROM12_SB20IN80AND160LR5GX1PO 242 656 #define SROM12_SB20IN80AND160HR5GX1PO 243 657 #define SROM12_SB40AND80HR5GX1PO 244 658 659 #define SROM12_MCSBW205GX2PO 245 660 #define SROM12_MCSBW205GX2PO_1 246 661 #define SROM12_MCSBW405GX2PO 247 662 #define SROM12_MCSBW405GX2PO_1 248 663 #define SROM12_MCSBW805GX2PO 249 664 #define SROM12_MCSBW805GX2PO_1 250 665 #define SROM12_MCSLR5GX2PO 251 666 #define SROM12_SB40AND80LR5GX2PO 252 667 #define SROM12_SB20IN80AND160LR5GX2PO 253 668 #define SROM12_SB20IN80AND160HR5GX2PO 254 669 #define SROM12_SB40AND80HR5GX2PO 255 670 671 /* MISC */ 672 #define SROM12_RXGAINS10 483 673 #define SROM12_RXGAINS11 484 674 #define SROM12_RXGAINS12 485 675 676 /* Per-path fields and offset */ 677 #define MAX_PATH_SROM_12 3 678 #define SROM12_PATH0 256 679 #define SROM12_PATH1 328 680 #define SROM12_PATH2 400 681 682 #define SROM12_5GB42G_MAXP 0 683 #define SROM12_2GB0_PA 1 684 #define SROM12_2GB0_PA_W0 1 685 #define SROM12_2GB0_PA_W1 2 686 #define SROM12_2GB0_PA_W2 3 687 #define SROM12_2GB0_PA_W3 4 688 689 #define SROM12_RXGAINS 5 690 #define SROM12_5GB1B0_MAXP 6 691 #define SROM12_5GB3B2_MAXP 7 692 693 #define SROM12_5GB0_PA 8 694 #define SROM12_5GB0_PA_W0 8 695 #define SROM12_5GB0_PA_W1 9 696 #define SROM12_5GB0_PA_W2 10 697 #define SROM12_5GB0_PA_W3 11 698 699 #define SROM12_5GB1_PA 12 700 #define SROM12_5GB1_PA_W0 12 701 #define SROM12_5GB1_PA_W1 13 702 #define SROM12_5GB1_PA_W2 14 703 #define SROM12_5GB1_PA_W3 15 704 705 #define SROM12_5GB2_PA 16 706 #define SROM12_5GB2_PA_W0 16 707 #define SROM12_5GB2_PA_W1 17 708 #define SROM12_5GB2_PA_W2 18 709 #define SROM12_5GB2_PA_W3 19 710 711 #define SROM12_5GB3_PA 20 712 #define SROM12_5GB3_PA_W0 20 713 #define SROM12_5GB3_PA_W1 21 714 #define SROM12_5GB3_PA_W2 22 715 #define SROM12_5GB3_PA_W3 23 716 717 #define SROM12_5GB4_PA 24 718 #define SROM12_5GB4_PA_W0 24 719 #define SROM12_5GB4_PA_W1 25 720 #define SROM12_5GB4_PA_W2 26 721 #define SROM12_5GB4_PA_W3 27 722 723 #define SROM12_2G40B0_PA 28 724 #define SROM12_2G40B0_PA_W0 28 725 #define SROM12_2G40B0_PA_W1 29 726 #define SROM12_2G40B0_PA_W2 30 727 #define SROM12_2G40B0_PA_W3 31 728 729 #define SROM12_5G40B0_PA 32 730 #define SROM12_5G40B0_PA_W0 32 731 #define SROM12_5G40B0_PA_W1 33 732 #define SROM12_5G40B0_PA_W2 34 733 #define SROM12_5G40B0_PA_W3 35 734 735 #define SROM12_5G40B1_PA 36 736 #define SROM12_5G40B1_PA_W0 36 737 #define SROM12_5G40B1_PA_W1 37 738 #define SROM12_5G40B1_PA_W2 38 739 #define SROM12_5G40B1_PA_W3 39 740 741 #define SROM12_5G40B2_PA 40 742 #define SROM12_5G40B2_PA_W0 40 743 #define SROM12_5G40B2_PA_W1 41 744 #define SROM12_5G40B2_PA_W2 42 745 #define SROM12_5G40B2_PA_W3 43 746 747 #define SROM12_5G40B3_PA 44 748 #define SROM12_5G40B3_PA_W0 44 749 #define SROM12_5G40B3_PA_W1 45 750 #define SROM12_5G40B3_PA_W2 46 751 #define SROM12_5G40B3_PA_W3 47 752 753 #define SROM12_5G40B4_PA 48 754 #define SROM12_5G40B4_PA_W0 48 755 #define SROM12_5G40B4_PA_W1 49 756 #define SROM12_5G40B4_PA_W2 50 757 #define SROM12_5G40B4_PA_W3 51 758 759 #define SROM12_5G80B0_PA 52 760 #define SROM12_5G80B0_PA_W0 52 761 #define SROM12_5G80B0_PA_W1 53 762 #define SROM12_5G80B0_PA_W2 54 763 #define SROM12_5G80B0_PA_W3 55 764 765 #define SROM12_5G80B1_PA 56 766 #define SROM12_5G80B1_PA_W0 56 767 #define SROM12_5G80B1_PA_W1 57 768 #define SROM12_5G80B1_PA_W2 58 769 #define SROM12_5G80B1_PA_W3 59 770 771 #define SROM12_5G80B2_PA 60 772 #define SROM12_5G80B2_PA_W0 60 773 #define SROM12_5G80B2_PA_W1 61 774 #define SROM12_5G80B2_PA_W2 62 775 #define SROM12_5G80B2_PA_W3 63 776 777 #define SROM12_5G80B3_PA 64 778 #define SROM12_5G80B3_PA_W0 64 779 #define SROM12_5G80B3_PA_W1 65 780 #define SROM12_5G80B3_PA_W2 66 781 #define SROM12_5G80B3_PA_W3 67 782 783 #define SROM12_5G80B4_PA 68 784 #define SROM12_5G80B4_PA_W0 68 785 #define SROM12_5G80B4_PA_W1 69 786 #define SROM12_5G80B4_PA_W2 70 787 #define SROM12_5G80B4_PA_W3 71 788 789 /* PD offset */ 790 #define SROM12_PDOFF_2G_CCK 472 791 792 #define SROM12_PDOFF_20in40M_5G_B0 473 793 #define SROM12_PDOFF_20in40M_5G_B1 474 794 #define SROM12_PDOFF_20in40M_5G_B2 475 795 #define SROM12_PDOFF_20in40M_5G_B3 476 796 #define SROM12_PDOFF_20in40M_5G_B4 477 797 798 #define SROM12_PDOFF_40in80M_5G_B0 478 799 #define SROM12_PDOFF_40in80M_5G_B1 479 800 #define SROM12_PDOFF_40in80M_5G_B2 480 801 #define SROM12_PDOFF_40in80M_5G_B3 481 802 #define SROM12_PDOFF_40in80M_5G_B4 482 803 804 #define SROM12_PDOFF_20in80M_5G_B0 488 805 #define SROM12_PDOFF_20in80M_5G_B1 489 806 #define SROM12_PDOFF_20in80M_5G_B2 490 807 #define SROM12_PDOFF_20in80M_5G_B3 491 808 #define SROM12_PDOFF_20in80M_5G_B4 492 809 810 #define SROM12_GPDN_L 91 /* GPIO pull down bits [15:0] */ 811 #define SROM12_GPDN_H 233 /* GPIO pull down bits [31:16] */ 812 813 #define SROM13_SIGN 64 814 #define SROM13_WORDS 590 815 #define SROM13_SIGNATURE 0x4d55 816 #define SROM13_CRCREV 589 817 818 /* Per-path fields and offset */ 819 #define MAX_PATH_SROM_13 4 820 #define SROM13_PATH0 256 821 #define SROM13_PATH1 328 822 #define SROM13_PATH2 400 823 #define SROM13_PATH3 512 824 #define SROM13_RXGAINS 5 825 826 #define SROM13_XTALFREQ 90 827 828 #define SROM13_PDOFFSET20IN40M2G 94 829 #define SROM13_PDOFFSET20IN40M2GCORE3 95 830 #define SROM13_SB20IN40HRLRPOX 96 831 832 #define SROM13_RXGAINS1CORE3 97 833 834 #define SROM13_PDOFFSET20IN40M5GCORE3 98 835 #define SROM13_PDOFFSET20IN40M5GCORE3_1 99 836 837 #define SROM13_ANTGAIN_BANDBGA 100 838 839 #define SROM13_PDOFFSET40IN80M5GCORE3 105 840 #define SROM13_PDOFFSET40IN80M5GCORE3_1 106 841 842 /* power per rate */ 843 #define SROM13_MCS1024QAM2GPO 108 844 #define SROM13_MCS1024QAM5GLPO 109 845 #define SROM13_MCS1024QAM5GLPO_1 110 846 #define SROM13_MCS1024QAM5GMPO 111 847 #define SROM13_MCS1024QAM5GMPO_1 112 848 #define SROM13_MCS1024QAM5GHPO 113 849 #define SROM13_MCS1024QAM5GHPO_1 114 850 #define SROM13_MCS1024QAM5GX1PO 115 851 #define SROM13_MCS1024QAM5GX1PO_1 116 852 #define SROM13_MCS1024QAM5GX2PO 117 853 #define SROM13_MCS1024QAM5GX2PO_1 118 854 855 #define SROM13_MCSBW1605GLPO 119 856 #define SROM13_MCSBW1605GLPO_1 120 857 #define SROM13_MCSBW1605GMPO 121 858 #define SROM13_MCSBW1605GMPO_1 122 859 #define SROM13_MCSBW1605GHPO 123 860 #define SROM13_MCSBW1605GHPO_1 124 861 862 #define SROM13_MCSBW1605GX1PO 125 863 #define SROM13_MCSBW1605GX1PO_1 126 864 #define SROM13_MCSBW1605GX2PO 127 865 #define SROM13_MCSBW1605GX2PO_1 128 866 867 #define SROM13_ULBPPROFFS5GB0 129 868 #define SROM13_ULBPPROFFS5GB1 130 869 #define SROM13_ULBPPROFFS5GB2 131 870 #define SROM13_ULBPPROFFS5GB3 132 871 #define SROM13_ULBPPROFFS5GB4 133 872 #define SROM13_ULBPPROFFS2G 134 873 874 #define SROM13_MCS8POEXP 135 875 #define SROM13_MCS8POEXP_1 136 876 #define SROM13_MCS9POEXP 137 877 #define SROM13_MCS9POEXP_1 138 878 #define SROM13_MCS10POEXP 139 879 #define SROM13_MCS10POEXP_1 140 880 #define SROM13_MCS11POEXP 141 881 #define SROM13_MCS11POEXP_1 142 882 #define SROM13_ULBPDOFFS5GB0A0 143 883 #define SROM13_ULBPDOFFS5GB0A1 144 884 #define SROM13_ULBPDOFFS5GB0A2 145 885 #define SROM13_ULBPDOFFS5GB0A3 146 886 #define SROM13_ULBPDOFFS5GB1A0 147 887 #define SROM13_ULBPDOFFS5GB1A1 148 888 #define SROM13_ULBPDOFFS5GB1A2 149 889 #define SROM13_ULBPDOFFS5GB1A3 150 890 #define SROM13_ULBPDOFFS5GB2A0 151 891 #define SROM13_ULBPDOFFS5GB2A1 152 892 #define SROM13_ULBPDOFFS5GB2A2 153 893 #define SROM13_ULBPDOFFS5GB2A3 154 894 #define SROM13_ULBPDOFFS5GB3A0 155 895 #define SROM13_ULBPDOFFS5GB3A1 156 896 #define SROM13_ULBPDOFFS5GB3A2 157 897 #define SROM13_ULBPDOFFS5GB3A3 158 898 #define SROM13_ULBPDOFFS5GB4A0 159 899 #define SROM13_ULBPDOFFS5GB4A1 160 900 #define SROM13_ULBPDOFFS5GB4A2 161 901 #define SROM13_ULBPDOFFS5GB4A3 162 902 #define SROM13_ULBPDOFFS2GA0 163 903 #define SROM13_ULBPDOFFS2GA1 164 904 #define SROM13_ULBPDOFFS2GA2 165 905 #define SROM13_ULBPDOFFS2GA3 166 906 907 #define SROM13_RPCAL5GB4 199 908 #define SROM13_RPCAL2GCORE3 101 909 #define SROM13_RPCAL5GB01CORE3 102 910 #define SROM13_RPCAL5GB23CORE3 103 911 912 #define SROM13_SW_TXRX_MASK 104 913 914 #define SROM13_EU_EDCRSTH 232 915 916 #define SROM13_SWCTRLMAP4_CFG 493 917 #define SROM13_SWCTRLMAP4_TX2G_FEM3TO0 494 918 #define SROM13_SWCTRLMAP4_RX2G_FEM3TO0 495 919 #define SROM13_SWCTRLMAP4_RXBYP2G_FEM3TO0 496 920 #define SROM13_SWCTRLMAP4_MISC2G_FEM3TO0 497 921 #define SROM13_SWCTRLMAP4_TX5G_FEM3TO0 498 922 #define SROM13_SWCTRLMAP4_RX5G_FEM3TO0 499 923 #define SROM13_SWCTRLMAP4_RXBYP5G_FEM3TO0 500 924 #define SROM13_SWCTRLMAP4_MISC5G_FEM3TO0 501 925 #define SROM13_SWCTRLMAP4_TX2G_FEM7TO4 502 926 #define SROM13_SWCTRLMAP4_RX2G_FEM7TO4 503 927 #define SROM13_SWCTRLMAP4_RXBYP2G_FEM7TO4 504 928 #define SROM13_SWCTRLMAP4_MISC2G_FEM7TO4 505 929 #define SROM13_SWCTRLMAP4_TX5G_FEM7TO4 506 930 #define SROM13_SWCTRLMAP4_RX5G_FEM7TO4 507 931 #define SROM13_SWCTRLMAP4_RXBYP5G_FEM7TO4 508 932 #define SROM13_SWCTRLMAP4_MISC5G_FEM7TO4 509 933 934 #define SROM13_PDOFFSET20IN80M5GCORE3 510 935 #define SROM13_PDOFFSET20IN80M5GCORE3_1 511 936 937 #define SROM13_NOISELVLCORE3 584 938 #define SROM13_NOISELVLCORE3_1 585 939 #define SROM13_RXGAINERRCORE3 586 940 #define SROM13_RXGAINERRCORE3_1 587 941 942 #define SROM13_PDOFF_2G_CCK_20M 167 943 944 #define SROM15_CALDATA_WORDS 943 945 #define SROM15_CAL_OFFSET_LOC 68 946 #define MAX_IOCTL_TXCHUNK_SIZE 1500 947 #define SROM15_MAX_CAL_SIZE 1886 948 #define SROM15_SIGNATURE 0x110c 949 #define SROM15_WORDS 1024 950 #define SROM15_MACHI 65 951 #define SROM15_CRCREV 1023 952 #define SROM15_BRDREV 69 953 #define SROM15_CCODE 70 954 #define SROM15_REGREV 71 955 #define SROM15_SIGN 64 956 957 #define SROM16_SIGN 128 958 #define SROM16_WORDS 1024 959 #define SROM16_SIGNATURE 0x4357 960 #define SROM16_CRCREV 1023 961 #define SROM16_MACHI 129 962 #define SROM16_CALDATA_OFFSET_LOC 132 963 #define SROM16_BOARDREV 133 964 #define SROM16_CCODE 134 965 #define SROM16_REGREV 135 966 967 #define SROM_CALDATA_WORDS 832 968 969 #define SROM17_SIGN 64 970 #define SROM17_BRDREV 65 971 #define SROM17_MACADDR 66 972 #define SROM17_CCODE 69 973 #define SROM17_CALDATA 70 974 #define SROM17_GCALTMP 71 975 976 #define SROM17_C0SRD202G 72 977 #define SROM17_C0SRD202G_1 73 978 #define SROM17_C0SRD205GL 74 979 #define SROM17_C0SRD205GL_1 75 980 #define SROM17_C0SRD205GML 76 981 #define SROM17_C0SRD205GML_1 77 982 #define SROM17_C0SRD205GMU 78 983 #define SROM17_C0SRD205GMU_1 79 984 #define SROM17_C0SRD205GH 80 985 #define SROM17_C0SRD205GH_1 81 986 987 #define SROM17_C1SRD202G 82 988 #define SROM17_C1SRD202G_1 83 989 #define SROM17_C1SRD205GL 84 990 #define SROM17_C1SRD205GL_1 85 991 #define SROM17_C1SRD205GML 86 992 #define SROM17_C1SRD205GML_1 87 993 #define SROM17_C1SRD205GMU 88 994 #define SROM17_C1SRD205GMU_1 89 995 #define SROM17_C1SRD205GH 90 996 #define SROM17_C1SRD205GH_1 91 997 998 #define SROM17_TRAMMAGIC 92 999 #define SROM17_TRAMMAGIC_1 93 1000 #define SROM17_TRAMDATA 94 1001 1002 #define SROM17_WORDS 256 1003 #define SROM17_CRCREV 255 1004 #define SROM17_CALDATA_WORDS 161 1005 #define SROM17_SIGNATURE 0x1103 /* 4355 in hex format */ 1006 1007 typedef struct { 1008 uint8 tssipos; /* TSSI positive slope, 1: positive, 0: negative */ 1009 uint8 extpagain; /* Ext PA gain-type: full-gain: 0, pa-lite: 1, no_pa: 2 */ 1010 uint8 pdetrange; /* support 32 combinations of different Pdet dynamic ranges */ 1011 uint8 triso; /* TR switch isolation */ 1012 uint8 antswctrllut; /* antswctrl lookup table configuration: 32 possible choices */ 1013 } srom_fem_t; 1014 1015 #endif /* _bcmsrom_fmt_h_ */ 1016