1 /*
2 * Broadcom BCMSDH to gSPI Protocol Conversion Layer
3 *
4 * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation
5 *
6 * Copyright (C) 1999-2017, Broadcom Corporation
7 *
8 * Unless you and Broadcom execute a separate written software license
9 * agreement governing use of this software, this software is licensed to you
10 * under the terms of the GNU General Public License version 2 (the "GPL"),
11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
12 * following added to such license:
13 *
14 * As a special exception, the copyright holders of this software give you
15 * permission to link this software with independent modules, and to copy and
16 * distribute the resulting executable under terms of your choice, provided that
17 * you also meet, for each linked independent module, the terms and conditions of
18 * the license of that module. An independent module is a module which is not
19 * derived from this software. The special exception does not apply to any
20 * modifications of the software.
21 *
22 * Notwithstanding the above, under no circumstances may you combine this
23 * software in any way with any other Broadcom software provided under a license
24 * other than the GPL, without Broadcom's express prior written consent.
25 *
26 *
27 * <<Broadcom-WL-IPTag/Open:>>
28 *
29 * $Id: bcmspibrcm.c 700323 2017-05-18 16:12:11Z $
30 */
31
32 #define HSMODE
33
34 #include <typedefs.h>
35
36 #include <bcmdevs.h>
37 #include <bcmendian.h>
38 #include <bcmutils.h>
39 #include <osl.h>
40 #include <hndsoc.h>
41 #include <siutils.h>
42 #include <sbchipc.h>
43 #include <sbsdio.h> /* SDIO device core hardware definitions. */
44 #include <spid.h>
45
46 #include <bcmsdbus.h> /* bcmsdh to/from specific controller APIs */
47 #include <sdiovar.h> /* ioctl/iovars */
48 #include <sdio.h> /* SDIO Device and Protocol Specs */
49
50 #include <pcicfg.h>
51
52 #include <bcmspibrcm.h>
53 #ifdef BCMSPI_ANDROID
54 extern void spi_sendrecv(sdioh_info_t *sd, uint8 *msg_out, uint8 *msg_in, int msglen);
55 #else
56 #include <bcmspi.h>
57 #endif /* BCMSPI_ANDROID */
58
59 /* these are for the older cores... for newer cores we have control for each of them */
60 #define F0_RESPONSE_DELAY 16
61 #define F1_RESPONSE_DELAY 16
62 #define F2_RESPONSE_DELAY F0_RESPONSE_DELAY
63
64 #define GSPI_F0_RESP_DELAY 0
65 #define GSPI_F1_RESP_DELAY F1_RESPONSE_DELAY
66 #define GSPI_F2_RESP_DELAY 0
67 #define GSPI_F3_RESP_DELAY 0
68
69 #define CMDLEN 4
70
71 /* Globals */
72 #if defined(DHD_DEBUG)
73 uint sd_msglevel = SDH_ERROR_VAL;
74 #else
75 uint sd_msglevel = 0;
76 #endif // endif
77
78 uint sd_hiok = FALSE; /* Use hi-speed mode if available? */
79 uint sd_sdmode = SDIOH_MODE_SPI; /* Use SD4 mode by default */
80 uint sd_f1_blocksize = 64; /* Default blocksize */
81 uint sd_f2_blocksize = 64; /* Default blocksize */
82
83 uint sd_divisor = 1;
84 uint sd_power = 1; /* Default to SD Slot powered ON */
85 uint sd_clock = 1; /* Default to SD Clock turned ON */
86 uint sd_crc = 0; /* Default to SPI CRC Check turned OFF */
87 uint sd_pci_slot = 0xFFFFffff; /* Used to force selection of a particular PCI slot */
88
89 uint8 spi_outbuf[SPI_MAX_PKT_LEN];
90 uint8 spi_inbuf[SPI_MAX_PKT_LEN];
91
92 /* 128bytes buffer is enough to clear data-not-available and program response-delay F0 bits
93 * assuming we will not exceed F0 response delay > 100 bytes at 48MHz.
94 */
95 #define BUF2_PKT_LEN 128
96 uint8 spi_outbuf2[BUF2_PKT_LEN];
97 uint8 spi_inbuf2[BUF2_PKT_LEN];
98 #ifdef BCMSPI_ANDROID
99 uint *dhd_spi_lockcount = NULL;
100 #endif /* BCMSPI_ANDROID */
101
102 #if !(defined(SPI_PIO_RW_BIGENDIAN) && defined(SPI_PIO_32BIT_RW))
103 #define SPISWAP_WD4(x) bcmswap32(x);
104 #define SPISWAP_WD2(x) (bcmswap16(x & 0xffff)) | \
105 (bcmswap16((x & 0xffff0000) >> 16) << 16);
106 #else
107 #define SPISWAP_WD4(x) x;
108 #define SPISWAP_WD2(x) bcmswap32by16(x);
109 #endif // endif
110
111 /* Prototypes */
112 static bool bcmspi_test_card(sdioh_info_t *sd);
113 static bool bcmspi_host_device_init_adapt(sdioh_info_t *sd);
114 static int bcmspi_set_highspeed_mode(sdioh_info_t *sd, bool hsmode);
115 static int bcmspi_cmd_issue(sdioh_info_t *sd, bool use_dma, uint32 cmd_arg,
116 uint32 *data, uint32 datalen);
117 static int bcmspi_card_regread(sdioh_info_t *sd, int func, uint32 regaddr,
118 int regsize, uint32 *data);
119 static int bcmspi_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr,
120 int regsize, uint32 data);
121 static int bcmspi_card_bytewrite(sdioh_info_t *sd, int func, uint32 regaddr,
122 uint8 *data);
123 static int bcmspi_driver_init(sdioh_info_t *sd);
124 static int bcmspi_card_buf(sdioh_info_t *sd, int rw, int func, bool fifo,
125 uint32 addr, int nbytes, uint32 *data);
126 static int bcmspi_card_regread_fixedaddr(sdioh_info_t *sd, int func, uint32 regaddr, int regsize,
127 uint32 *data);
128 static void bcmspi_cmd_getdstatus(sdioh_info_t *sd, uint32 *dstatus_buffer);
129 static int bcmspi_update_stats(sdioh_info_t *sd, uint32 cmd_arg);
130
131 /*
132 * Public entry points & extern's
133 */
134 extern sdioh_info_t *
sdioh_attach(osl_t * osh,void * bar0,uint irq)135 sdioh_attach(osl_t *osh, void *bar0, uint irq)
136 {
137 sdioh_info_t *sd;
138
139 sd_trace(("%s\n", __FUNCTION__));
140 if ((sd = (sdioh_info_t *)MALLOC(osh, sizeof(sdioh_info_t))) == NULL) {
141 sd_err(("%s: out of memory, malloced %d bytes\n", __FUNCTION__, MALLOCED(osh)));
142 return NULL;
143 }
144 bzero((char *)sd, sizeof(sdioh_info_t));
145 sd->osh = osh;
146 if (spi_osinit(sd) != 0) {
147 sd_err(("%s: spi_osinit() failed\n", __FUNCTION__));
148 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
149 return NULL;
150 }
151
152 #ifndef BCMSPI_ANDROID
153 sd->bar0 = bar0;
154 #endif /* !BCMSPI_ANDROID */
155 sd->irq = irq;
156 #ifndef BCMSPI_ANDROID
157 sd->intr_handler = NULL;
158 sd->intr_handler_arg = NULL;
159 sd->intr_handler_valid = FALSE;
160 #endif /* !BCMSPI_ANDROID */
161
162 /* Set defaults */
163 sd->use_client_ints = TRUE;
164 sd->sd_use_dma = FALSE; /* DMA Not supported */
165
166 /* Spi device default is 16bit mode, change to 4 when device is changed to 32bit
167 * mode
168 */
169 sd->wordlen = 2;
170
171 #ifdef BCMSPI_ANDROID
172 dhd_spi_lockcount = &sd->lockcount;
173 #endif /* BCMSPI_ANDROID */
174
175 #ifndef BCMSPI_ANDROID
176 if (!spi_hw_attach(sd)) {
177 sd_err(("%s: spi_hw_attach() failed\n", __FUNCTION__));
178 spi_osfree(sd);
179 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
180 return (NULL);
181 }
182 #endif /* !BCMSPI_ANDROID */
183
184 if (bcmspi_driver_init(sd) != SUCCESS) {
185 sd_err(("%s: bcmspi_driver_init() failed()\n", __FUNCTION__));
186 #ifndef BCMSPI_ANDROID
187 spi_hw_detach(sd);
188 #endif /* !BCMSPI_ANDROID */
189 spi_osfree(sd);
190 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
191 return (NULL);
192 }
193
194 if (spi_register_irq(sd, irq) != SUCCESS) {
195 sd_err(("%s: spi_register_irq() failed for irq = %d\n", __FUNCTION__, irq));
196 #ifndef BCMSPI_ANDROID
197 spi_hw_detach(sd);
198 #endif /* !BCMSPI_ANDROID */
199 spi_osfree(sd);
200 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
201 return (NULL);
202 }
203
204 sd_trace(("%s: Done\n", __FUNCTION__));
205
206 return sd;
207 }
208
209 extern SDIOH_API_RC
sdioh_detach(osl_t * osh,sdioh_info_t * sd)210 sdioh_detach(osl_t *osh, sdioh_info_t *sd)
211 {
212 sd_trace(("%s\n", __FUNCTION__));
213 if (sd) {
214 sd_err(("%s: detaching from hardware\n", __FUNCTION__));
215 spi_free_irq(sd->irq, sd);
216 #ifndef BCMSPI_ANDROID
217 spi_hw_detach(sd);
218 #endif /* !BCMSPI_ANDROID */
219 spi_osfree(sd);
220 #ifdef BCMSPI_ANDROID
221 dhd_spi_lockcount = NULL;
222 #endif /* !BCMSPI_ANDROID */
223 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
224 }
225 return SDIOH_API_RC_SUCCESS;
226 }
227
228 /* Configure callback to client when we recieve client interrupt */
229 extern SDIOH_API_RC
sdioh_interrupt_register(sdioh_info_t * sd,sdioh_cb_fn_t fn,void * argh)230 sdioh_interrupt_register(sdioh_info_t *sd, sdioh_cb_fn_t fn, void *argh)
231 {
232 sd_trace(("%s: Entering\n", __FUNCTION__));
233 #if !defined(OOB_INTR_ONLY)
234 sd->intr_handler = fn;
235 sd->intr_handler_arg = argh;
236 sd->intr_handler_valid = TRUE;
237 #endif /* !defined(OOB_INTR_ONLY) */
238 return SDIOH_API_RC_SUCCESS;
239 }
240
241 extern SDIOH_API_RC
sdioh_interrupt_deregister(sdioh_info_t * sd)242 sdioh_interrupt_deregister(sdioh_info_t *sd)
243 {
244 sd_trace(("%s: Entering\n", __FUNCTION__));
245 #if !defined(OOB_INTR_ONLY)
246 sd->intr_handler_valid = FALSE;
247 sd->intr_handler = NULL;
248 sd->intr_handler_arg = NULL;
249 #endif /* !defined(OOB_INTR_ONLY) */
250 return SDIOH_API_RC_SUCCESS;
251 }
252
253 extern SDIOH_API_RC
sdioh_interrupt_query(sdioh_info_t * sd,bool * onoff)254 sdioh_interrupt_query(sdioh_info_t *sd, bool *onoff)
255 {
256 #ifndef BCMSPI_ANDROID
257 sd_trace(("%s: Entering\n", __FUNCTION__));
258 *onoff = sd->client_intr_enabled;
259 #endif /* !BCMSPI_ANDROID */
260 return SDIOH_API_RC_SUCCESS;
261 }
262
263 #if defined(DHD_DEBUG)
264 extern bool
sdioh_interrupt_pending(sdioh_info_t * sd)265 sdioh_interrupt_pending(sdioh_info_t *sd)
266 {
267 return 0;
268 }
269 #endif // endif
270
271 /* Provide dstatus bits of spi-transaction for dhd layers. */
272 extern uint32
sdioh_get_dstatus(sdioh_info_t * sd)273 sdioh_get_dstatus(sdioh_info_t *sd)
274 {
275 return sd->card_dstatus;
276 }
277
278 extern void
sdioh_chipinfo(sdioh_info_t * sd,uint32 chip,uint32 chiprev)279 sdioh_chipinfo(sdioh_info_t *sd, uint32 chip, uint32 chiprev)
280 {
281 sd->chip = chip;
282 sd->chiprev = chiprev;
283 }
284
285 extern void
sdioh_dwordmode(sdioh_info_t * sd,bool set)286 sdioh_dwordmode(sdioh_info_t *sd, bool set)
287 {
288 uint8 reg = 0;
289 int status;
290
291 if ((status = sdioh_request_byte(sd, SDIOH_READ, SPI_FUNC_0, SPID_STATUS_ENABLE, ®)) !=
292 SUCCESS) {
293 sd_err(("%s: Failed to set dwordmode in gSPI\n", __FUNCTION__));
294 return;
295 }
296
297 if (set) {
298 reg |= DWORD_PKT_LEN_EN;
299 sd->dwordmode = TRUE;
300 sd->client_block_size[SPI_FUNC_2] = 4096; /* h2spi's limit is 4KB, we support 8KB */
301 } else {
302 reg &= ~DWORD_PKT_LEN_EN;
303 sd->dwordmode = FALSE;
304 sd->client_block_size[SPI_FUNC_2] = 2048;
305 }
306
307 if ((status = sdioh_request_byte(sd, SDIOH_WRITE, SPI_FUNC_0, SPID_STATUS_ENABLE, ®)) !=
308 SUCCESS) {
309 sd_err(("%s: Failed to set dwordmode in gSPI\n", __FUNCTION__));
310 return;
311 }
312 }
313
314 uint
sdioh_query_iofnum(sdioh_info_t * sd)315 sdioh_query_iofnum(sdioh_info_t *sd)
316 {
317 return sd->num_funcs;
318 }
319
320 /* IOVar table */
321 enum {
322 IOV_MSGLEVEL = 1,
323 IOV_BLOCKMODE,
324 IOV_BLOCKSIZE,
325 IOV_DMA,
326 IOV_USEINTS,
327 IOV_NUMINTS,
328 IOV_NUMLOCALINTS,
329 IOV_HOSTREG,
330 IOV_DEVREG,
331 IOV_DIVISOR,
332 IOV_SDMODE,
333 IOV_HISPEED,
334 IOV_HCIREGS,
335 IOV_POWER,
336 IOV_CLOCK,
337 IOV_SPIERRSTATS,
338 IOV_RESP_DELAY_ALL
339 };
340
341 const bcm_iovar_t sdioh_iovars[] = {
342 {"sd_msglevel", IOV_MSGLEVEL, 0, 0, IOVT_UINT32, 0 },
343 {"sd_blocksize", IOV_BLOCKSIZE, 0, 0, IOVT_UINT32, 0 },
344 {"sd_dma", IOV_DMA, 0, 0, IOVT_BOOL, 0 },
345 {"sd_ints", IOV_USEINTS, 0, 0, IOVT_BOOL, 0 },
346 {"sd_numints", IOV_NUMINTS, 0, 0, IOVT_UINT32, 0 },
347 {"sd_numlocalints", IOV_NUMLOCALINTS, 0, 0, IOVT_UINT32, 0 },
348 {"sd_hostreg", IOV_HOSTREG, 0, 0, IOVT_BUFFER, sizeof(sdreg_t) },
349 {"sd_devreg", IOV_DEVREG, 0, 0, IOVT_BUFFER, sizeof(sdreg_t) },
350 {"sd_divisor", IOV_DIVISOR, 0, 0, IOVT_UINT32, 0 },
351 {"sd_power", IOV_POWER, 0, 0, IOVT_UINT32, 0 },
352 {"sd_clock", IOV_CLOCK, 0, 0, IOVT_UINT32, 0 },
353 {"sd_mode", IOV_SDMODE, 0, 0, IOVT_UINT32, 100},
354 {"sd_highspeed", IOV_HISPEED, 0, 0, IOVT_UINT32, 0},
355 {"spi_errstats", IOV_SPIERRSTATS, 0, 0, IOVT_BUFFER, sizeof(struct spierrstats_t) },
356 {"spi_respdelay", IOV_RESP_DELAY_ALL, 0, 0, IOVT_BOOL, 0 },
357 {NULL, 0, 0, 0, 0, 0 }
358 };
359
360 int
sdioh_iovar_op(sdioh_info_t * si,const char * name,void * params,int plen,void * arg,int len,bool set)361 sdioh_iovar_op(sdioh_info_t *si, const char *name,
362 void *params, int plen, void *arg, int len, bool set)
363 {
364 const bcm_iovar_t *vi = NULL;
365 int bcmerror = 0;
366 int val_size;
367 int32 int_val = 0;
368 uint32 actionid;
369 /*
370 sdioh_regs_t *regs;
371 */
372
373 ASSERT(name);
374 ASSERT(len >= 0);
375
376 /* Get must have return space; Set does not take qualifiers */
377 ASSERT(set || (arg && len));
378 ASSERT(!set || (!params && !plen));
379
380 sd_trace(("%s: Enter (%s %s)\n", __FUNCTION__, (set ? "set" : "get"), name));
381
382 if ((vi = bcm_iovar_lookup(sdioh_iovars, name)) == NULL) {
383 bcmerror = BCME_UNSUPPORTED;
384 goto exit;
385 }
386
387 if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, set)) != 0)
388 goto exit;
389
390 /* Set up params so get and set can share the convenience variables */
391 if (params == NULL) {
392 params = arg;
393 plen = len;
394 }
395
396 if (vi->type == IOVT_VOID)
397 val_size = 0;
398 else if (vi->type == IOVT_BUFFER)
399 val_size = len;
400 else
401 val_size = sizeof(int);
402
403 if (plen >= (int)sizeof(int_val))
404 bcopy(params, &int_val, sizeof(int_val));
405
406 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
407 switch (actionid) {
408 case IOV_GVAL(IOV_MSGLEVEL):
409 int_val = (int32)sd_msglevel;
410 bcopy(&int_val, arg, val_size);
411 break;
412
413 case IOV_SVAL(IOV_MSGLEVEL):
414 sd_msglevel = int_val;
415 break;
416
417 case IOV_GVAL(IOV_BLOCKSIZE):
418 if ((uint32)int_val > si->num_funcs) {
419 bcmerror = BCME_BADARG;
420 break;
421 }
422 int_val = (int32)si->client_block_size[int_val];
423 bcopy(&int_val, arg, val_size);
424 break;
425
426 case IOV_GVAL(IOV_DMA):
427 int_val = (int32)si->sd_use_dma;
428 bcopy(&int_val, arg, val_size);
429 break;
430
431 case IOV_SVAL(IOV_DMA):
432 si->sd_use_dma = (bool)int_val;
433 break;
434
435 case IOV_GVAL(IOV_USEINTS):
436 int_val = (int32)si->use_client_ints;
437 bcopy(&int_val, arg, val_size);
438 break;
439
440 case IOV_SVAL(IOV_USEINTS):
441 break;
442
443 case IOV_GVAL(IOV_DIVISOR):
444 int_val = (uint32)sd_divisor;
445 bcopy(&int_val, arg, val_size);
446 break;
447
448 #ifndef BCMSPI_ANDROID
449 case IOV_SVAL(IOV_DIVISOR):
450 sd_divisor = int_val;
451 if (!spi_start_clock(si, (uint16)sd_divisor)) {
452 sd_err(("%s: set clock failed\n", __FUNCTION__));
453 bcmerror = BCME_ERROR;
454 }
455 break;
456 #endif /* !BCMSPI_ANDROID */
457
458 case IOV_GVAL(IOV_POWER):
459 int_val = (uint32)sd_power;
460 bcopy(&int_val, arg, val_size);
461 break;
462
463 case IOV_SVAL(IOV_POWER):
464 sd_power = int_val;
465 break;
466
467 case IOV_GVAL(IOV_CLOCK):
468 int_val = (uint32)sd_clock;
469 bcopy(&int_val, arg, val_size);
470 break;
471
472 case IOV_SVAL(IOV_CLOCK):
473 sd_clock = int_val;
474 break;
475
476 case IOV_GVAL(IOV_SDMODE):
477 int_val = (uint32)sd_sdmode;
478 bcopy(&int_val, arg, val_size);
479 break;
480
481 case IOV_SVAL(IOV_SDMODE):
482 sd_sdmode = int_val;
483 break;
484
485 case IOV_GVAL(IOV_HISPEED):
486 int_val = (uint32)sd_hiok;
487 bcopy(&int_val, arg, val_size);
488 break;
489
490 case IOV_SVAL(IOV_HISPEED):
491 sd_hiok = int_val;
492
493 if (!bcmspi_set_highspeed_mode(si, (bool)sd_hiok)) {
494 sd_err(("%s: Failed changing highspeed mode to %d.\n",
495 __FUNCTION__, sd_hiok));
496 bcmerror = BCME_ERROR;
497 return ERROR;
498 }
499 break;
500
501 case IOV_GVAL(IOV_NUMINTS):
502 int_val = (int32)si->intrcount;
503 bcopy(&int_val, arg, val_size);
504 break;
505
506 case IOV_GVAL(IOV_NUMLOCALINTS):
507 int_val = (int32)si->local_intrcount;
508 bcopy(&int_val, arg, val_size);
509 break;
510 case IOV_GVAL(IOV_DEVREG):
511 {
512 sdreg_t *sd_ptr = (sdreg_t *)params;
513 uint8 data;
514
515 if (sdioh_cfg_read(si, sd_ptr->func, sd_ptr->offset, &data)) {
516 bcmerror = BCME_SDIO_ERROR;
517 break;
518 }
519
520 int_val = (int)data;
521 bcopy(&int_val, arg, sizeof(int_val));
522 break;
523 }
524
525 case IOV_SVAL(IOV_DEVREG):
526 {
527 sdreg_t *sd_ptr = (sdreg_t *)params;
528 uint8 data = (uint8)sd_ptr->value;
529
530 if (sdioh_cfg_write(si, sd_ptr->func, sd_ptr->offset, &data)) {
531 bcmerror = BCME_SDIO_ERROR;
532 break;
533 }
534 break;
535 }
536
537 case IOV_GVAL(IOV_SPIERRSTATS):
538 {
539 bcopy(&si->spierrstats, arg, sizeof(struct spierrstats_t));
540 break;
541 }
542
543 case IOV_SVAL(IOV_SPIERRSTATS):
544 {
545 bzero(&si->spierrstats, sizeof(struct spierrstats_t));
546 break;
547 }
548
549 case IOV_GVAL(IOV_RESP_DELAY_ALL):
550 int_val = (int32)si->resp_delay_all;
551 bcopy(&int_val, arg, val_size);
552 break;
553
554 case IOV_SVAL(IOV_RESP_DELAY_ALL):
555 si->resp_delay_all = (bool)int_val;
556 int_val = STATUS_ENABLE|INTR_WITH_STATUS;
557 if (si->resp_delay_all)
558 int_val |= RESP_DELAY_ALL;
559 else {
560 if (bcmspi_card_regwrite(si, SPI_FUNC_0, SPID_RESPONSE_DELAY, 1,
561 F1_RESPONSE_DELAY) != SUCCESS) {
562 sd_err(("%s: Unable to set response delay.\n", __FUNCTION__));
563 bcmerror = BCME_SDIO_ERROR;
564 break;
565 }
566 }
567
568 if (bcmspi_card_regwrite(si, SPI_FUNC_0, SPID_STATUS_ENABLE, 1, int_val)
569 != SUCCESS) {
570 sd_err(("%s: Unable to set response delay.\n", __FUNCTION__));
571 bcmerror = BCME_SDIO_ERROR;
572 break;
573 }
574 break;
575
576 default:
577 bcmerror = BCME_UNSUPPORTED;
578 break;
579 }
580 exit:
581
582 return bcmerror;
583 }
584
585 extern SDIOH_API_RC
sdioh_cfg_read(sdioh_info_t * sd,uint fnc_num,uint32 addr,uint8 * data)586 sdioh_cfg_read(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
587 {
588 SDIOH_API_RC status;
589 /* No lock needed since sdioh_request_byte does locking */
590 status = sdioh_request_byte(sd, SDIOH_READ, fnc_num, addr, data);
591 return status;
592 }
593
594 extern SDIOH_API_RC
sdioh_cfg_write(sdioh_info_t * sd,uint fnc_num,uint32 addr,uint8 * data)595 sdioh_cfg_write(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
596 {
597 /* No lock needed since sdioh_request_byte does locking */
598 SDIOH_API_RC status;
599
600 if ((fnc_num == SPI_FUNC_1) && (addr == SBSDIO_FUNC1_FRAMECTRL)) {
601 uint8 dummy_data;
602 status = sdioh_cfg_read(sd, fnc_num, addr, &dummy_data);
603 if (status) {
604 sd_err(("sdioh_cfg_read() failed.\n"));
605 return status;
606 }
607 }
608
609 status = sdioh_request_byte(sd, SDIOH_WRITE, fnc_num, addr, data);
610 return status;
611 }
612
613 extern SDIOH_API_RC
sdioh_cis_read(sdioh_info_t * sd,uint func,uint8 * cisd,uint32 length)614 sdioh_cis_read(sdioh_info_t *sd, uint func, uint8 *cisd, uint32 length)
615 {
616 uint32 count;
617 int offset;
618 uint32 cis_byte;
619 uint16 *cis = (uint16 *)cisd;
620 uint bar0 = SI_ENUM_BASE_DEFAULT;
621 int status;
622 uint8 data;
623
624 sd_trace(("%s: Func %d\n", __FUNCTION__, func));
625
626 spi_lock(sd);
627
628 /* Set sb window address to 0x18000000 */
629 data = (bar0 >> 8) & SBSDIO_SBADDRLOW_MASK;
630 status = bcmspi_card_bytewrite(sd, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW, &data);
631 if (status == SUCCESS) {
632 data = (bar0 >> 16) & SBSDIO_SBADDRMID_MASK;
633 status = bcmspi_card_bytewrite(sd, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID, &data);
634 } else {
635 sd_err(("%s: Unable to set sb-addr-windows\n", __FUNCTION__));
636 spi_unlock(sd);
637 return (BCME_ERROR);
638 }
639 if (status == SUCCESS) {
640 data = (bar0 >> 24) & SBSDIO_SBADDRHIGH_MASK;
641 status = bcmspi_card_bytewrite(sd, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH, &data);
642 } else {
643 sd_err(("%s: Unable to set sb-addr-windows\n", __FUNCTION__));
644 spi_unlock(sd);
645 return (BCME_ERROR);
646 }
647
648 offset = CC_SROM_OTP; /* OTP offset in chipcommon. */
649 for (count = 0; count < length/2; count++) {
650 if (bcmspi_card_regread (sd, SDIO_FUNC_1, offset, 2, &cis_byte) < 0) {
651 sd_err(("%s: regread failed: Can't read CIS\n", __FUNCTION__));
652 spi_unlock(sd);
653 return (BCME_ERROR);
654 }
655
656 *cis = (uint16)cis_byte;
657 cis++;
658 offset += 2;
659 }
660
661 spi_unlock(sd);
662
663 return (BCME_OK);
664 }
665
666 extern SDIOH_API_RC
sdioh_request_byte(sdioh_info_t * sd,uint rw,uint func,uint regaddr,uint8 * byte)667 sdioh_request_byte(sdioh_info_t *sd, uint rw, uint func, uint regaddr, uint8 *byte)
668 {
669 int status;
670 uint32 cmd_arg;
671 uint32 dstatus;
672 uint32 data = (uint32)(*byte);
673
674 spi_lock(sd);
675
676 cmd_arg = 0;
677 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
678 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1); /* Incremental access */
679 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
680 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, rw == SDIOH_READ ? 0 : 1);
681 cmd_arg = SFIELD(cmd_arg, SPI_LEN, 1);
682
683 if (rw == SDIOH_READ) {
684 sd_trace(("%s: RD cmd_arg=0x%x func=%d regaddr=0x%x\n",
685 __FUNCTION__, cmd_arg, func, regaddr));
686 } else {
687 sd_trace(("%s: WR cmd_arg=0x%x func=%d regaddr=0x%x data=0x%x\n",
688 __FUNCTION__, cmd_arg, func, regaddr, data));
689 }
690
691 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, &data, 1)) != SUCCESS) {
692 spi_unlock(sd);
693 return status;
694 }
695
696 if (rw == SDIOH_READ) {
697 *byte = (uint8)data;
698 sd_trace(("%s: RD result=0x%x\n", __FUNCTION__, *byte));
699 }
700
701 bcmspi_cmd_getdstatus(sd, &dstatus);
702 if (dstatus)
703 sd_trace(("dstatus=0x%x\n", dstatus));
704
705 spi_unlock(sd);
706 return SDIOH_API_RC_SUCCESS;
707 }
708
709 extern SDIOH_API_RC
sdioh_request_word(sdioh_info_t * sd,uint cmd_type,uint rw,uint func,uint addr,uint32 * word,uint nbytes)710 sdioh_request_word(sdioh_info_t *sd, uint cmd_type, uint rw, uint func, uint addr,
711 uint32 *word, uint nbytes)
712 {
713 int status;
714
715 spi_lock(sd);
716
717 if (rw == SDIOH_READ)
718 status = bcmspi_card_regread(sd, func, addr, nbytes, word);
719 else
720 status = bcmspi_card_regwrite(sd, func, addr, nbytes, *word);
721
722 spi_unlock(sd);
723 return (status == SUCCESS ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
724 }
725
726 extern SDIOH_API_RC
sdioh_request_buffer(sdioh_info_t * sd,uint pio_dma,uint fix_inc,uint rw,uint func,uint addr,uint reg_width,uint buflen_u,uint8 * buffer,void * pkt)727 sdioh_request_buffer(sdioh_info_t *sd, uint pio_dma, uint fix_inc, uint rw, uint func,
728 uint addr, uint reg_width, uint buflen_u, uint8 *buffer, void *pkt)
729 {
730 int len;
731 int buflen = (int)buflen_u;
732 bool fifo = (fix_inc == SDIOH_DATA_FIX);
733
734 spi_lock(sd);
735
736 ASSERT(reg_width == 4);
737 ASSERT(buflen_u < (1 << 30));
738 ASSERT(sd->client_block_size[func]);
739
740 sd_data(("%s: %c len %d r_cnt %d t_cnt %d, pkt @0x%p\n",
741 __FUNCTION__, rw == SDIOH_READ ? 'R' : 'W',
742 buflen_u, sd->r_cnt, sd->t_cnt, pkt));
743
744 /* Break buffer down into blocksize chunks. */
745 while (buflen > 0) {
746 len = MIN(sd->client_block_size[func], buflen);
747 if (bcmspi_card_buf(sd, rw, func, fifo, addr, len, (uint32 *)buffer) != SUCCESS) {
748 sd_err(("%s: bcmspi_card_buf %s failed\n",
749 __FUNCTION__, rw == SDIOH_READ ? "Read" : "Write"));
750 spi_unlock(sd);
751 return SDIOH_API_RC_FAIL;
752 }
753 buffer += len;
754 buflen -= len;
755 if (!fifo)
756 addr += len;
757 }
758 spi_unlock(sd);
759 return SDIOH_API_RC_SUCCESS;
760 }
761
762 /* This function allows write to gspi bus when another rd/wr function is deep down the call stack.
763 * Its main aim is to have simpler spi writes rather than recursive writes.
764 * e.g. When there is a need to program response delay on the fly after detecting the SPI-func
765 * this call will allow to program the response delay.
766 */
767 static int
bcmspi_card_byterewrite(sdioh_info_t * sd,int func,uint32 regaddr,uint8 byte)768 bcmspi_card_byterewrite(sdioh_info_t *sd, int func, uint32 regaddr, uint8 byte)
769 {
770 uint32 cmd_arg;
771 uint32 datalen = 1;
772 uint32 hostlen;
773
774 cmd_arg = 0;
775
776 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 1);
777 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1); /* Incremental access */
778 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
779 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
780 cmd_arg = SFIELD(cmd_arg, SPI_LEN, datalen);
781
782 sd_trace(("%s cmd_arg = 0x%x\n", __FUNCTION__, cmd_arg));
783
784 /* Set up and issue the SPI command. MSByte goes out on bus first. Increase datalen
785 * according to the wordlen mode(16/32bit) the device is in.
786 */
787 ASSERT(sd->wordlen == 4 || sd->wordlen == 2);
788 datalen = ROUNDUP(datalen, sd->wordlen);
789
790 /* Start by copying command in the spi-outbuffer */
791 if (sd->wordlen == 4) { /* 32bit spid */
792 *(uint32 *)spi_outbuf2 = SPISWAP_WD4(cmd_arg);
793 if (datalen & 0x3)
794 datalen += (4 - (datalen & 0x3));
795 } else if (sd->wordlen == 2) { /* 16bit spid */
796 *(uint32 *)spi_outbuf2 = SPISWAP_WD2(cmd_arg);
797 if (datalen & 0x1)
798 datalen++;
799 } else {
800 sd_err(("%s: Host is %d bit spid, could not create SPI command.\n",
801 __FUNCTION__, 8 * sd->wordlen));
802 return ERROR;
803 }
804
805 /* for Write, put the data into the output buffer */
806 if (datalen != 0) {
807 if (sd->wordlen == 4) { /* 32bit spid */
808 *(uint32 *)&spi_outbuf2[CMDLEN] = SPISWAP_WD4(byte);
809 } else if (sd->wordlen == 2) { /* 16bit spid */
810 *(uint32 *)&spi_outbuf2[CMDLEN] = SPISWAP_WD2(byte);
811 }
812 }
813
814 /* +4 for cmd, +4 for dstatus */
815 hostlen = datalen + 8;
816 hostlen += (4 - (hostlen & 0x3));
817 spi_sendrecv(sd, spi_outbuf2, spi_inbuf2, hostlen);
818
819 /* Last 4bytes are dstatus. Device is configured to return status bits. */
820 if (sd->wordlen == 4) { /* 32bit spid */
821 sd->card_dstatus = SPISWAP_WD4(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
822 } else if (sd->wordlen == 2) { /* 16bit spid */
823 sd->card_dstatus = SPISWAP_WD2(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
824 } else {
825 sd_err(("%s: Host is %d bit machine, could not read SPI dstatus.\n",
826 __FUNCTION__, 8 * sd->wordlen));
827 return ERROR;
828 }
829
830 if (sd->card_dstatus)
831 sd_trace(("dstatus after byte rewrite = 0x%x\n", sd->card_dstatus));
832
833 return (BCME_OK);
834 }
835
836 /* Program the response delay corresponding to the spi function */
837 static int
bcmspi_prog_resp_delay(sdioh_info_t * sd,int func,uint8 resp_delay)838 bcmspi_prog_resp_delay(sdioh_info_t *sd, int func, uint8 resp_delay)
839 {
840 if (sd->resp_delay_all == FALSE)
841 return (BCME_OK);
842
843 if (sd->prev_fun == func)
844 return (BCME_OK);
845
846 if (F0_RESPONSE_DELAY == F1_RESPONSE_DELAY)
847 return (BCME_OK);
848
849 bcmspi_card_byterewrite(sd, SPI_FUNC_0, SPID_RESPONSE_DELAY, resp_delay);
850
851 /* Remember function for which to avoid reprogramming resp-delay in next iteration */
852 sd->prev_fun = func;
853
854 return (BCME_OK);
855
856 }
857
858 #define GSPI_RESYNC_PATTERN 0x0
859
860 /* A resync pattern is a 32bit MOSI line with all zeros. Its a special command in gSPI.
861 * It resets the spi-bkplane logic so that all F1 related ping-pong buffer logic is
862 * synchronised and all queued resuests are cancelled.
863 */
864 static int
bcmspi_resync_f1(sdioh_info_t * sd)865 bcmspi_resync_f1(sdioh_info_t *sd)
866 {
867 uint32 cmd_arg = GSPI_RESYNC_PATTERN, data = 0, datalen = 0;
868
869 /* Set up and issue the SPI command. MSByte goes out on bus first. Increase datalen
870 * according to the wordlen mode(16/32bit) the device is in.
871 */
872 ASSERT(sd->wordlen == 4 || sd->wordlen == 2);
873 datalen = ROUNDUP(datalen, sd->wordlen);
874
875 /* Start by copying command in the spi-outbuffer */
876 *(uint32 *)spi_outbuf2 = cmd_arg;
877
878 /* for Write, put the data into the output buffer */
879 *(uint32 *)&spi_outbuf2[CMDLEN] = data;
880
881 /* +4 for cmd, +4 for dstatus */
882 spi_sendrecv(sd, spi_outbuf2, spi_inbuf2, datalen + 8);
883
884 /* Last 4bytes are dstatus. Device is configured to return status bits. */
885 if (sd->wordlen == 4) { /* 32bit spid */
886 sd->card_dstatus = SPISWAP_WD4(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
887 } else if (sd->wordlen == 2) { /* 16bit spid */
888 sd->card_dstatus = SPISWAP_WD2(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
889 } else {
890 sd_err(("%s: Host is %d bit machine, could not read SPI dstatus.\n",
891 __FUNCTION__, 8 * sd->wordlen));
892 return ERROR;
893 }
894
895 if (sd->card_dstatus)
896 sd_trace(("dstatus after resync pattern write = 0x%x\n", sd->card_dstatus));
897
898 return (BCME_OK);
899 }
900
901 uint32 dstatus_count = 0;
902
903 static int
bcmspi_update_stats(sdioh_info_t * sd,uint32 cmd_arg)904 bcmspi_update_stats(sdioh_info_t *sd, uint32 cmd_arg)
905 {
906 uint32 dstatus = sd->card_dstatus;
907 struct spierrstats_t *spierrstats = &sd->spierrstats;
908 int err = SUCCESS;
909
910 sd_trace(("cmd = 0x%x, dstatus = 0x%x\n", cmd_arg, dstatus));
911
912 /* Store dstatus of last few gSPI transactions */
913 spierrstats->dstatus[dstatus_count % NUM_PREV_TRANSACTIONS] = dstatus;
914 spierrstats->spicmd[dstatus_count % NUM_PREV_TRANSACTIONS] = cmd_arg;
915 dstatus_count++;
916
917 if (sd->card_init_done == FALSE)
918 return err;
919
920 if (dstatus & STATUS_DATA_NOT_AVAILABLE) {
921 spierrstats->dna++;
922 sd_trace(("Read data not available on F1 addr = 0x%x\n",
923 GFIELD(cmd_arg, SPI_REG_ADDR)));
924 /* Clear dna bit */
925 bcmspi_card_byterewrite(sd, SPI_FUNC_0, SPID_INTR_REG, DATA_UNAVAILABLE);
926 }
927
928 if (dstatus & STATUS_UNDERFLOW) {
929 spierrstats->rdunderflow++;
930 sd_err(("FIFO underflow happened due to current F2 read command.\n"));
931 }
932
933 if (dstatus & STATUS_OVERFLOW) {
934 spierrstats->wroverflow++;
935 sd_err(("FIFO overflow happened due to current (F1/F2) write command.\n"));
936 bcmspi_card_byterewrite(sd, SPI_FUNC_0, SPID_INTR_REG, F1_OVERFLOW);
937 bcmspi_resync_f1(sd);
938 sd_err(("Recovering from F1 FIFO overflow.\n"));
939 }
940
941 if (dstatus & STATUS_F2_INTR) {
942 spierrstats->f2interrupt++;
943 sd_trace(("Interrupt from F2. SW should clear corresponding IntStatus bits\n"));
944 }
945
946 if (dstatus & STATUS_F3_INTR) {
947 spierrstats->f3interrupt++;
948 sd_err(("Interrupt from F3. SW should clear corresponding IntStatus bits\n"));
949 }
950
951 if (dstatus & STATUS_HOST_CMD_DATA_ERR) {
952 spierrstats->hostcmddataerr++;
953 sd_err(("Error in CMD or Host data, detected by CRC/Checksum (optional)\n"));
954 }
955
956 if (dstatus & STATUS_F2_PKT_AVAILABLE) {
957 spierrstats->f2pktavailable++;
958 sd_trace(("Packet is available/ready in F2 TX FIFO\n"));
959 sd_trace(("Packet length = %d\n", sd->dwordmode ?
960 ((dstatus & STATUS_F2_PKT_LEN_MASK) >> (STATUS_F2_PKT_LEN_SHIFT - 2)) :
961 ((dstatus & STATUS_F2_PKT_LEN_MASK) >> STATUS_F2_PKT_LEN_SHIFT)));
962 }
963
964 if (dstatus & STATUS_F3_PKT_AVAILABLE) {
965 spierrstats->f3pktavailable++;
966 sd_err(("Packet is available/ready in F3 TX FIFO\n"));
967 sd_err(("Packet length = %d\n",
968 (dstatus & STATUS_F3_PKT_LEN_MASK) >> STATUS_F3_PKT_LEN_SHIFT));
969 }
970
971 return err;
972 }
973
974 extern int
sdioh_abort(sdioh_info_t * sd,uint func)975 sdioh_abort(sdioh_info_t *sd, uint func)
976 {
977 return 0;
978 }
979
980 int
sdioh_start(sdioh_info_t * sd,int stage)981 sdioh_start(sdioh_info_t *sd, int stage)
982 {
983 return SUCCESS;
984 }
985
986 int
sdioh_stop(sdioh_info_t * sd)987 sdioh_stop(sdioh_info_t *sd)
988 {
989 return SUCCESS;
990 }
991
992 int
sdioh_waitlockfree(sdioh_info_t * sd)993 sdioh_waitlockfree(sdioh_info_t *sd)
994 {
995 return SUCCESS;
996 }
997
998 /*
999 * Private/Static work routines
1000 */
1001 static int
bcmspi_host_init(sdioh_info_t * sd)1002 bcmspi_host_init(sdioh_info_t *sd)
1003 {
1004
1005 /* Default power on mode */
1006 sd->sd_mode = SDIOH_MODE_SPI;
1007 sd->polled_mode = TRUE;
1008 sd->host_init_done = TRUE;
1009 sd->card_init_done = FALSE;
1010 sd->adapter_slot = 1;
1011
1012 return (SUCCESS);
1013 }
1014
1015 static int
get_client_blocksize(sdioh_info_t * sd)1016 get_client_blocksize(sdioh_info_t *sd)
1017 {
1018 uint32 regdata[2];
1019 int status;
1020
1021 /* Find F1/F2/F3 max packet size */
1022 if ((status = bcmspi_card_regread(sd, 0, SPID_F1_INFO_REG,
1023 8, regdata)) != SUCCESS) {
1024 return status;
1025 }
1026
1027 sd_trace(("pkt_size regdata[0] = 0x%x, regdata[1] = 0x%x\n",
1028 regdata[0], regdata[1]));
1029
1030 sd->client_block_size[1] = (regdata[0] & F1_MAX_PKT_SIZE) >> 2;
1031 sd_trace(("Func1 blocksize = %d\n", sd->client_block_size[1]));
1032 ASSERT(sd->client_block_size[1] == BLOCK_SIZE_F1);
1033
1034 sd->client_block_size[2] = ((regdata[0] >> 16) & F2_MAX_PKT_SIZE) >> 2;
1035 sd_trace(("Func2 blocksize = %d\n", sd->client_block_size[2]));
1036 ASSERT(sd->client_block_size[2] == BLOCK_SIZE_F2);
1037
1038 sd->client_block_size[3] = (regdata[1] & F3_MAX_PKT_SIZE) >> 2;
1039 sd_trace(("Func3 blocksize = %d\n", sd->client_block_size[3]));
1040 ASSERT(sd->client_block_size[3] == BLOCK_SIZE_F3);
1041
1042 return 0;
1043 }
1044
1045 static int
bcmspi_client_init(sdioh_info_t * sd)1046 bcmspi_client_init(sdioh_info_t *sd)
1047 {
1048 uint32 status_en_reg = 0;
1049 sd_trace(("%s: Powering up slot %d\n", __FUNCTION__, sd->adapter_slot));
1050
1051 #ifndef BCMSPI_ANDROID
1052 #ifdef HSMODE
1053 if (!spi_start_clock(sd, (uint16)sd_divisor)) {
1054 sd_err(("spi_start_clock failed\n"));
1055 return ERROR;
1056 }
1057 #else
1058 /* Start at ~400KHz clock rate for initialization */
1059 if (!spi_start_clock(sd, 128)) {
1060 sd_err(("spi_start_clock failed\n"));
1061 return ERROR;
1062 }
1063 #endif /* HSMODE */
1064 #endif /* !BCMSPI_ANDROID */
1065
1066 if (!bcmspi_host_device_init_adapt(sd)) {
1067 sd_err(("bcmspi_host_device_init_adapt failed\n"));
1068 return ERROR;
1069 }
1070
1071 if (!bcmspi_test_card(sd)) {
1072 sd_err(("bcmspi_test_card failed\n"));
1073 return ERROR;
1074 }
1075
1076 sd->num_funcs = SPI_MAX_IOFUNCS;
1077
1078 get_client_blocksize(sd);
1079
1080 /* Apply resync pattern cmd with all zeros to reset spi-bkplane F1 logic */
1081 bcmspi_resync_f1(sd);
1082
1083 sd->dwordmode = FALSE;
1084
1085 bcmspi_card_regread(sd, 0, SPID_STATUS_ENABLE, 1, &status_en_reg);
1086
1087 sd_trace(("%s: Enabling interrupt with dstatus \n", __FUNCTION__));
1088 status_en_reg |= INTR_WITH_STATUS;
1089
1090 if (bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_STATUS_ENABLE, 1,
1091 status_en_reg & 0xff) != SUCCESS) {
1092 sd_err(("%s: Unable to set response delay for all fun's.\n", __FUNCTION__));
1093 return ERROR;
1094 }
1095
1096 #ifndef HSMODE
1097 #ifndef BCMSPI_ANDROID
1098 /* After configuring for High-Speed mode, set the desired clock rate. */
1099 if (!spi_start_clock(sd, 4)) {
1100 sd_err(("spi_start_clock failed\n"));
1101 return ERROR;
1102 }
1103 #endif /* !BCMSPI_ANDROID */
1104 #endif /* HSMODE */
1105
1106 /* check to see if the response delay needs to be programmed properly */
1107 {
1108 uint32 f1_respdelay = 0;
1109 bcmspi_card_regread(sd, 0, SPID_RESP_DELAY_F1, 1, &f1_respdelay);
1110 if ((f1_respdelay == 0) || (f1_respdelay == 0xFF)) {
1111 /* older sdiodevice core and has no separte resp delay for each of */
1112 sd_err(("older corerev < 4 so use the same resp delay for all funcs\n"));
1113 sd->resp_delay_new = FALSE;
1114 }
1115 else {
1116 /* older sdiodevice core and has no separte resp delay for each of */
1117 int ret_val;
1118 sd->resp_delay_new = TRUE;
1119 sd_err(("new corerev >= 4 so set the resp delay for each of the funcs\n"));
1120 sd_trace(("resp delay for funcs f0(%d), f1(%d), f2(%d), f3(%d)\n",
1121 GSPI_F0_RESP_DELAY, GSPI_F1_RESP_DELAY,
1122 GSPI_F2_RESP_DELAY, GSPI_F3_RESP_DELAY));
1123 ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F0, 1,
1124 GSPI_F0_RESP_DELAY);
1125 if (ret_val != SUCCESS) {
1126 sd_err(("%s: Unable to set response delay for F0\n", __FUNCTION__));
1127 return ERROR;
1128 }
1129 ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F1, 1,
1130 GSPI_F1_RESP_DELAY);
1131 if (ret_val != SUCCESS) {
1132 sd_err(("%s: Unable to set response delay for F1\n", __FUNCTION__));
1133 return ERROR;
1134 }
1135 ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F2, 1,
1136 GSPI_F2_RESP_DELAY);
1137 if (ret_val != SUCCESS) {
1138 sd_err(("%s: Unable to set response delay for F2\n", __FUNCTION__));
1139 return ERROR;
1140 }
1141 ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F3, 1,
1142 GSPI_F3_RESP_DELAY);
1143 if (ret_val != SUCCESS) {
1144 sd_err(("%s: Unable to set response delay for F2\n", __FUNCTION__));
1145 return ERROR;
1146 }
1147 }
1148 }
1149
1150 sd->card_init_done = TRUE;
1151
1152 /* get the device rev to program the prop respdelays */
1153
1154 return SUCCESS;
1155 }
1156
1157 static int
bcmspi_set_highspeed_mode(sdioh_info_t * sd,bool hsmode)1158 bcmspi_set_highspeed_mode(sdioh_info_t *sd, bool hsmode)
1159 {
1160 uint32 regdata;
1161 int status;
1162
1163 if ((status = bcmspi_card_regread(sd, 0, SPID_CONFIG,
1164 4, ®data)) != SUCCESS)
1165 return status;
1166
1167 sd_trace(("In %s spih-ctrl = 0x%x \n", __FUNCTION__, regdata));
1168
1169 if (hsmode == TRUE) {
1170 sd_trace(("Attempting to enable High-Speed mode.\n"));
1171
1172 if (regdata & HIGH_SPEED_MODE) {
1173 sd_trace(("Device is already in High-Speed mode.\n"));
1174 return status;
1175 } else {
1176 regdata |= HIGH_SPEED_MODE;
1177 sd_trace(("Writing %08x to device at %08x\n", regdata, SPID_CONFIG));
1178 if ((status = bcmspi_card_regwrite(sd, 0, SPID_CONFIG,
1179 4, regdata)) != SUCCESS) {
1180 return status;
1181 }
1182 }
1183 } else {
1184 sd_trace(("Attempting to disable High-Speed mode.\n"));
1185
1186 if (regdata & HIGH_SPEED_MODE) {
1187 regdata &= ~HIGH_SPEED_MODE;
1188 regdata |= CLOCK_POLARITY;
1189 sd_trace(("Writing %08x to device at %08x\n", regdata, SPID_CONFIG));
1190 if ((status = bcmspi_card_regwrite(sd, 0, SPID_CONFIG,
1191 4, regdata)) != SUCCESS)
1192 return status;
1193 }
1194 else {
1195 sd_trace(("Device is already in Low-Speed mode.\n"));
1196 return status;
1197 }
1198 }
1199 #ifndef BCMSPI_ANDROID
1200 spi_controller_highspeed_mode(sd, hsmode);
1201 #endif /* !BCMSPI_ANDROID */
1202
1203 return TRUE;
1204 }
1205
1206 #define bcmspi_find_curr_mode(sd) { \
1207 sd->wordlen = 2; \
1208 status = bcmspi_card_regread_fixedaddr(sd, 0, SPID_TEST_READ, 4, ®data); \
1209 regdata &= 0xff; \
1210 if ((regdata == 0xad) || (regdata == 0x5b) || \
1211 (regdata == 0x5d) || (regdata == 0x5a)) \
1212 break; \
1213 sd->wordlen = 4; \
1214 status = bcmspi_card_regread_fixedaddr(sd, 0, SPID_TEST_READ, 4, ®data); \
1215 regdata &= 0xff; \
1216 if ((regdata == 0xad) || (regdata == 0x5b) || \
1217 (regdata == 0x5d) || (regdata == 0x5a)) \
1218 break; \
1219 sd_trace(("Silicon testability issue: regdata = 0x%x." \
1220 " Expected 0xad, 0x5a, 0x5b or 0x5d.\n", regdata)); \
1221 OSL_DELAY(100000); \
1222 }
1223
1224 #define INIT_ADAPT_LOOP 100
1225
1226 /* Adapt clock-phase-speed-bitwidth between host and device */
1227 static bool
bcmspi_host_device_init_adapt(sdioh_info_t * sd)1228 bcmspi_host_device_init_adapt(sdioh_info_t *sd)
1229 {
1230 uint32 wrregdata, regdata = 0;
1231 int status;
1232 int i;
1233
1234 /* Due to a silicon testability issue, the first command from the Host
1235 * to the device will get corrupted (first bit will be lost). So the
1236 * Host should poll the device with a safe read request. ie: The Host
1237 * should try to read F0 addr 0x14 using the Fixed address mode
1238 * (This will prevent a unintended write command to be detected by device)
1239 */
1240 for (i = 0; i < INIT_ADAPT_LOOP; i++) {
1241 /* If device was not power-cycled it will stay in 32bit mode with
1242 * response-delay-all bit set. Alternate the iteration so that
1243 * read either with or without response-delay for F0 to succeed.
1244 */
1245 bcmspi_find_curr_mode(sd);
1246 sd->resp_delay_all = (i & 0x1) ? TRUE : FALSE;
1247
1248 bcmspi_find_curr_mode(sd);
1249 sd->dwordmode = TRUE;
1250
1251 bcmspi_find_curr_mode(sd);
1252 sd->dwordmode = FALSE;
1253 }
1254
1255 /* Bail out, device not detected */
1256 if (i == INIT_ADAPT_LOOP)
1257 return FALSE;
1258
1259 /* Softreset the spid logic */
1260 if ((sd->dwordmode) || (sd->wordlen == 4)) {
1261 bcmspi_card_regwrite(sd, 0, SPID_RESET_BP, 1, RESET_ON_WLAN_BP_RESET|RESET_SPI);
1262 bcmspi_card_regread(sd, 0, SPID_RESET_BP, 1, ®data);
1263 sd_trace(("reset reg read = 0x%x\n", regdata));
1264 sd_trace(("dwordmode = %d, wordlen = %d, resp_delay_all = %d\n", sd->dwordmode,
1265 sd->wordlen, sd->resp_delay_all));
1266 /* Restore default state after softreset */
1267 sd->wordlen = 2;
1268 sd->dwordmode = FALSE;
1269 }
1270
1271 if (sd->wordlen == 4) {
1272 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, ®data)) !=
1273 SUCCESS)
1274 return FALSE;
1275 if (regdata == TEST_RO_DATA_32BIT_LE) {
1276 sd_trace(("Spid is already in 32bit LE mode. Value read = 0x%x\n",
1277 regdata));
1278 sd_trace(("Spid power was left on.\n"));
1279 } else {
1280 sd_err(("Spid power was left on but signature read failed."
1281 " Value read = 0x%x\n", regdata));
1282 return FALSE;
1283 }
1284 } else {
1285 sd->wordlen = 2;
1286
1287 #define CTRL_REG_DEFAULT 0x00010430 /* according to the host m/c */
1288
1289 wrregdata = (CTRL_REG_DEFAULT);
1290
1291 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, ®data)) != SUCCESS)
1292 return FALSE;
1293 sd_trace(("(we are still in 16bit mode) 32bit READ LE regdata = 0x%x\n", regdata));
1294
1295 #ifndef HSMODE
1296 wrregdata |= (CLOCK_PHASE | CLOCK_POLARITY);
1297 wrregdata &= ~HIGH_SPEED_MODE;
1298 bcmspi_card_regwrite(sd, 0, SPID_CONFIG, 4, wrregdata);
1299 #endif /* HSMODE */
1300
1301 for (i = 0; i < INIT_ADAPT_LOOP; i++) {
1302 if ((regdata == 0xfdda7d5b) || (regdata == 0xfdda7d5a)) {
1303 sd_trace(("0xfeedbead was leftshifted by 1-bit.\n"));
1304 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4,
1305 ®data)) != SUCCESS)
1306 return FALSE;
1307 }
1308 OSL_DELAY(1000);
1309 }
1310
1311 #if defined(CHANGE_SPI_INTR_POLARITY_ACTIVE_HIGH)
1312 /* Change to host controller intr-polarity of active-high */
1313 wrregdata |= INTR_POLARITY;
1314 #else
1315 /* Change to host controller intr-polarity of active-low */
1316 wrregdata &= ~INTR_POLARITY;
1317 #endif /* CHANGE_SPI_INTR_POLARITY_ACTIVE_HIGH */
1318
1319 sd_trace(("(we are still in 16bit mode) 32bit Write LE reg-ctrl-data = 0x%x\n",
1320 wrregdata));
1321 /* Change to 32bit mode */
1322 wrregdata |= WORD_LENGTH_32;
1323 bcmspi_card_regwrite(sd, 0, SPID_CONFIG, 4, wrregdata);
1324
1325 /* Change command/data packaging in 32bit LE mode */
1326 sd->wordlen = 4;
1327
1328 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, ®data)) != SUCCESS)
1329 return FALSE;
1330
1331 if (regdata == TEST_RO_DATA_32BIT_LE) {
1332 sd_trace(("Read spid passed. Value read = 0x%x\n", regdata));
1333 sd_trace(("Spid had power-on cycle OR spi was soft-resetted \n"));
1334 } else {
1335 sd_err(("Stale spid reg values read as it was kept powered. Value read ="
1336 "0x%x\n", regdata));
1337 return FALSE;
1338 }
1339 }
1340
1341 return TRUE;
1342 }
1343
1344 static bool
bcmspi_test_card(sdioh_info_t * sd)1345 bcmspi_test_card(sdioh_info_t *sd)
1346 {
1347 uint32 regdata;
1348 int status;
1349
1350 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, ®data)) != SUCCESS)
1351 return FALSE;
1352
1353 if (regdata == (TEST_RO_DATA_32BIT_LE))
1354 sd_trace(("32bit LE regdata = 0x%x\n", regdata));
1355 else {
1356 sd_trace(("Incorrect 32bit LE regdata = 0x%x\n", regdata));
1357 return FALSE;
1358 }
1359
1360 #define RW_PATTERN1 0xA0A1A2A3
1361 #define RW_PATTERN2 0x4B5B6B7B
1362
1363 regdata = RW_PATTERN1;
1364 if ((status = bcmspi_card_regwrite(sd, 0, SPID_TEST_RW, 4, regdata)) != SUCCESS)
1365 return FALSE;
1366 regdata = 0;
1367 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_RW, 4, ®data)) != SUCCESS)
1368 return FALSE;
1369 if (regdata != RW_PATTERN1) {
1370 sd_err(("Write-Read spid failed. Value wrote = 0x%x, Value read = 0x%x\n",
1371 RW_PATTERN1, regdata));
1372 return FALSE;
1373 } else
1374 sd_trace(("R/W spid passed. Value read = 0x%x\n", regdata));
1375
1376 regdata = RW_PATTERN2;
1377 if ((status = bcmspi_card_regwrite(sd, 0, SPID_TEST_RW, 4, regdata)) != SUCCESS)
1378 return FALSE;
1379 regdata = 0;
1380 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_RW, 4, ®data)) != SUCCESS)
1381 return FALSE;
1382 if (regdata != RW_PATTERN2) {
1383 sd_err(("Write-Read spid failed. Value wrote = 0x%x, Value read = 0x%x\n",
1384 RW_PATTERN2, regdata));
1385 return FALSE;
1386 } else
1387 sd_trace(("R/W spid passed. Value read = 0x%x\n", regdata));
1388
1389 return TRUE;
1390 }
1391
1392 static int
bcmspi_driver_init(sdioh_info_t * sd)1393 bcmspi_driver_init(sdioh_info_t *sd)
1394 {
1395 sd_trace(("%s\n", __FUNCTION__));
1396 if ((bcmspi_host_init(sd)) != SUCCESS) {
1397 return ERROR;
1398 }
1399
1400 if (bcmspi_client_init(sd) != SUCCESS) {
1401 return ERROR;
1402 }
1403
1404 return SUCCESS;
1405 }
1406
1407 /* Read device reg */
1408 static int
bcmspi_card_regread(sdioh_info_t * sd,int func,uint32 regaddr,int regsize,uint32 * data)1409 bcmspi_card_regread(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 *data)
1410 {
1411 int status;
1412 uint32 cmd_arg, dstatus;
1413
1414 ASSERT(regsize);
1415
1416 if (func == 2)
1417 sd_trace(("Reg access on F2 will generate error indication in dstatus bits.\n"));
1418
1419 cmd_arg = 0;
1420 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 0);
1421 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1); /* Incremental access */
1422 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
1423 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
1424 cmd_arg = SFIELD(cmd_arg, SPI_LEN, regsize == BLOCK_SIZE_F2 ? 0 : regsize);
1425
1426 sd_trace(("%s: RD cmd_arg=0x%x func=%d regaddr=0x%x regsize=%d\n",
1427 __FUNCTION__, cmd_arg, func, regaddr, regsize));
1428
1429 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, data, regsize)) != SUCCESS)
1430 return status;
1431
1432 bcmspi_cmd_getdstatus(sd, &dstatus);
1433 if (dstatus)
1434 sd_trace(("dstatus =0x%x\n", dstatus));
1435
1436 return SUCCESS;
1437 }
1438
1439 static int
bcmspi_card_regread_fixedaddr(sdioh_info_t * sd,int func,uint32 regaddr,int regsize,uint32 * data)1440 bcmspi_card_regread_fixedaddr(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 *data)
1441 {
1442
1443 int status;
1444 uint32 cmd_arg;
1445 uint32 dstatus;
1446
1447 ASSERT(regsize);
1448
1449 if (func == 2)
1450 sd_trace(("Reg access on F2 will generate error indication in dstatus bits.\n"));
1451
1452 cmd_arg = 0;
1453 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 0);
1454 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 0); /* Fixed access */
1455 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
1456 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
1457 cmd_arg = SFIELD(cmd_arg, SPI_LEN, regsize);
1458
1459 sd_trace(("%s: RD cmd_arg=0x%x func=%d regaddr=0x%x regsize=%d\n",
1460 __FUNCTION__, cmd_arg, func, regaddr, regsize));
1461
1462 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, data, regsize)) != SUCCESS)
1463 return status;
1464
1465 sd_trace(("%s: RD result=0x%x\n", __FUNCTION__, *data));
1466
1467 bcmspi_cmd_getdstatus(sd, &dstatus);
1468 sd_trace(("dstatus =0x%x\n", dstatus));
1469 return SUCCESS;
1470 }
1471
1472 /* write a device register */
1473 static int
bcmspi_card_regwrite(sdioh_info_t * sd,int func,uint32 regaddr,int regsize,uint32 data)1474 bcmspi_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 data)
1475 {
1476 int status;
1477 uint32 cmd_arg, dstatus;
1478
1479 ASSERT(regsize);
1480
1481 cmd_arg = 0;
1482
1483 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 1);
1484 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1); /* Incremental access */
1485 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
1486 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
1487 cmd_arg = SFIELD(cmd_arg, SPI_LEN, regsize == BLOCK_SIZE_F2 ? 0 : regsize);
1488
1489 sd_trace(("%s: WR cmd_arg=0x%x func=%d regaddr=0x%x regsize=%d data=0x%x\n",
1490 __FUNCTION__, cmd_arg, func, regaddr, regsize, data));
1491
1492 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, &data, regsize)) != SUCCESS)
1493 return status;
1494
1495 bcmspi_cmd_getdstatus(sd, &dstatus);
1496 if (dstatus)
1497 sd_trace(("dstatus=0x%x\n", dstatus));
1498
1499 return SUCCESS;
1500 }
1501
1502 /* write a device register - 1 byte */
1503 static int
bcmspi_card_bytewrite(sdioh_info_t * sd,int func,uint32 regaddr,uint8 * byte)1504 bcmspi_card_bytewrite(sdioh_info_t *sd, int func, uint32 regaddr, uint8 *byte)
1505 {
1506 int status;
1507 uint32 cmd_arg;
1508 uint32 dstatus;
1509 uint32 data = (uint32)(*byte);
1510
1511 cmd_arg = 0;
1512 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
1513 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1); /* Incremental access */
1514 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
1515 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 1);
1516 cmd_arg = SFIELD(cmd_arg, SPI_LEN, 1);
1517
1518 sd_trace(("%s: WR cmd_arg=0x%x func=%d regaddr=0x%x data=0x%x\n",
1519 __FUNCTION__, cmd_arg, func, regaddr, data));
1520
1521 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, &data, 1)) != SUCCESS)
1522 return status;
1523
1524 bcmspi_cmd_getdstatus(sd, &dstatus);
1525 if (dstatus)
1526 sd_trace(("dstatus =0x%x\n", dstatus));
1527
1528 return SUCCESS;
1529 }
1530
1531 void
bcmspi_cmd_getdstatus(sdioh_info_t * sd,uint32 * dstatus_buffer)1532 bcmspi_cmd_getdstatus(sdioh_info_t *sd, uint32 *dstatus_buffer)
1533 {
1534 *dstatus_buffer = sd->card_dstatus;
1535 }
1536
1537 /* 'data' is of type uint32 whereas other buffers are of type uint8 */
1538 static int
bcmspi_cmd_issue(sdioh_info_t * sd,bool use_dma,uint32 cmd_arg,uint32 * data,uint32 datalen)1539 bcmspi_cmd_issue(sdioh_info_t *sd, bool use_dma, uint32 cmd_arg,
1540 uint32 *data, uint32 datalen)
1541 {
1542 uint32 i, j;
1543 uint8 resp_delay = 0;
1544 int err = SUCCESS;
1545 uint32 hostlen;
1546 uint32 dstatus_idx = 0;
1547 // uint16 templen, buslen, len;
1548
1549 sd_trace(("spi cmd = 0x%x\n", cmd_arg));
1550
1551 /* Set up and issue the SPI command. MSByte goes out on bus first. Increase datalen
1552 * according to the wordlen mode(16/32bit) the device is in.
1553 */
1554 if (sd->wordlen == 4) { /* 32bit spid */
1555 *(uint32 *)spi_outbuf = SPISWAP_WD4(cmd_arg);
1556 if (datalen & 0x3)
1557 datalen += (4 - (datalen & 0x3));
1558 } else if (sd->wordlen == 2) { /* 16bit spid */
1559 *(uint32 *)spi_outbuf = SPISWAP_WD2(cmd_arg);
1560 if (datalen & 0x1)
1561 datalen++;
1562 if (datalen < 4)
1563 datalen = ROUNDUP(datalen, 4);
1564 } else {
1565 sd_err(("Host is %d bit spid, could not create SPI command.\n",
1566 8 * sd->wordlen));
1567 return ERROR;
1568 }
1569
1570 /* for Write, put the data into the output buffer */
1571 if (GFIELD(cmd_arg, SPI_RW_FLAG) == 1) {
1572 /* We send len field of hw-header always a mod16 size, both from host and dongle */
1573 if (datalen != 0) {
1574 for (i = 0; i < datalen/4; i++) {
1575 if (sd->wordlen == 4) { /* 32bit spid */
1576 *(uint32 *)&spi_outbuf[i * 4 + CMDLEN] =
1577 SPISWAP_WD4(data[i]);
1578 } else if (sd->wordlen == 2) { /* 16bit spid */
1579 *(uint32 *)&spi_outbuf[i * 4 + CMDLEN] =
1580 SPISWAP_WD2(data[i]);
1581 }
1582 }
1583 }
1584 }
1585
1586 /* Append resp-delay number of bytes and clock them out for F0/1/2 reads. */
1587 if ((GFIELD(cmd_arg, SPI_RW_FLAG) == 0)) {
1588 int func = GFIELD(cmd_arg, SPI_FUNCTION);
1589 switch (func) {
1590 case 0:
1591 if (sd->resp_delay_new)
1592 resp_delay = GSPI_F0_RESP_DELAY;
1593 else
1594 resp_delay = sd->resp_delay_all ? F0_RESPONSE_DELAY : 0;
1595 break;
1596 case 1:
1597 if (sd->resp_delay_new)
1598 resp_delay = GSPI_F1_RESP_DELAY;
1599 else
1600 resp_delay = F1_RESPONSE_DELAY;
1601 break;
1602 case 2:
1603 if (sd->resp_delay_new)
1604 resp_delay = GSPI_F2_RESP_DELAY;
1605 else
1606 resp_delay = sd->resp_delay_all ? F2_RESPONSE_DELAY : 0;
1607 break;
1608 default:
1609 ASSERT(0);
1610 break;
1611 }
1612 /* Program response delay */
1613 if (sd->resp_delay_new == FALSE)
1614 bcmspi_prog_resp_delay(sd, func, resp_delay);
1615 }
1616
1617 /* +4 for cmd and +4 for dstatus */
1618 hostlen = datalen + 8 + resp_delay;
1619 hostlen += dstatus_idx;
1620 #ifdef BCMSPI_ANDROID
1621 if (hostlen%4) {
1622 sd_err(("Unaligned data len %d, hostlen %d\n",
1623 datalen, hostlen));
1624 #endif /* BCMSPI_ANDROID */
1625 hostlen += (4 - (hostlen & 0x3));
1626 #ifdef BCMSPI_ANDROID
1627 }
1628 #endif /* BCMSPI_ANDROID */
1629 spi_sendrecv(sd, spi_outbuf, spi_inbuf, hostlen);
1630
1631 /* for Read, get the data into the input buffer */
1632 if (datalen != 0) {
1633 if (GFIELD(cmd_arg, SPI_RW_FLAG) == 0) { /* if read cmd */
1634 for (j = 0; j < datalen/4; j++) {
1635 if (sd->wordlen == 4) { /* 32bit spid */
1636 data[j] = SPISWAP_WD4(*(uint32 *)&spi_inbuf[j * 4 +
1637 CMDLEN + resp_delay]);
1638 } else if (sd->wordlen == 2) { /* 16bit spid */
1639 data[j] = SPISWAP_WD2(*(uint32 *)&spi_inbuf[j * 4 +
1640 CMDLEN + resp_delay]);
1641 }
1642 }
1643 }
1644 }
1645
1646 dstatus_idx += (datalen + CMDLEN + resp_delay);
1647 /* Last 4bytes are dstatus. Device is configured to return status bits. */
1648 if (sd->wordlen == 4) { /* 32bit spid */
1649 sd->card_dstatus = SPISWAP_WD4(*(uint32 *)&spi_inbuf[dstatus_idx]);
1650 } else if (sd->wordlen == 2) { /* 16bit spid */
1651 sd->card_dstatus = SPISWAP_WD2(*(uint32 *)&spi_inbuf[dstatus_idx]);
1652 } else {
1653 sd_err(("Host is %d bit machine, could not read SPI dstatus.\n",
1654 8 * sd->wordlen));
1655 return ERROR;
1656 }
1657 if (sd->card_dstatus == 0xffffffff) {
1658 sd_err(("looks like not a GSPI device or device is not powered.\n"));
1659 }
1660
1661 err = bcmspi_update_stats(sd, cmd_arg);
1662
1663 return err;
1664
1665 }
1666
1667 static int
bcmspi_card_buf(sdioh_info_t * sd,int rw,int func,bool fifo,uint32 addr,int nbytes,uint32 * data)1668 bcmspi_card_buf(sdioh_info_t *sd, int rw, int func, bool fifo,
1669 uint32 addr, int nbytes, uint32 *data)
1670 {
1671 int status;
1672 uint32 cmd_arg;
1673 bool write = rw == SDIOH_READ ? 0 : 1;
1674 uint retries = 0;
1675
1676 bool enable;
1677 uint32 spilen;
1678
1679 cmd_arg = 0;
1680
1681 ASSERT(nbytes);
1682 ASSERT(nbytes <= sd->client_block_size[func]);
1683
1684 if (write) sd->t_cnt++; else sd->r_cnt++;
1685
1686 if (func == 2) {
1687 /* Frame len check limited by gSPI. */
1688 if ((nbytes > 2000) && write) {
1689 sd_trace((">2KB write: F2 wr of %d bytes\n", nbytes));
1690 }
1691 /* ASSERT(nbytes <= 2048); Fix bigger len gspi issue and uncomment. */
1692 /* If F2 fifo on device is not ready to receive data, don't do F2 transfer */
1693 if (write) {
1694 uint32 dstatus;
1695 /* check F2 ready with cached one */
1696 bcmspi_cmd_getdstatus(sd, &dstatus);
1697 if ((dstatus & STATUS_F2_RX_READY) == 0) {
1698 retries = WAIT_F2RXFIFORDY;
1699 enable = 0;
1700 while (retries-- && !enable) {
1701 OSL_DELAY(WAIT_F2RXFIFORDY_DELAY * 1000);
1702 bcmspi_card_regread(sd, SPI_FUNC_0, SPID_STATUS_REG, 4,
1703 &dstatus);
1704 if (dstatus & STATUS_F2_RX_READY)
1705 enable = TRUE;
1706 }
1707 if (!enable) {
1708 struct spierrstats_t *spierrstats = &sd->spierrstats;
1709 spierrstats->f2rxnotready++;
1710 sd_err(("F2 FIFO is not ready to receive data.\n"));
1711 return ERROR;
1712 }
1713 sd_trace(("No of retries on F2 ready %d\n",
1714 (WAIT_F2RXFIFORDY - retries)));
1715 }
1716 }
1717 }
1718
1719 /* F2 transfers happen on 0 addr */
1720 addr = (func == 2) ? 0 : addr;
1721
1722 /* In pio mode buffer is read using fixed address fifo in func 1 */
1723 if ((func == 1) && (fifo))
1724 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 0);
1725 else
1726 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1);
1727
1728 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
1729 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, addr);
1730 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, write);
1731 spilen = sd->data_xfer_count = MIN(sd->client_block_size[func], nbytes);
1732 if ((sd->dwordmode == TRUE) && (GFIELD(cmd_arg, SPI_FUNCTION) == SPI_FUNC_2)) {
1733 /* convert len to mod4 size */
1734 spilen = spilen + ((spilen & 0x3) ? (4 - (spilen & 0x3)): 0);
1735 cmd_arg = SFIELD(cmd_arg, SPI_LEN, (spilen >> 2));
1736 } else
1737 cmd_arg = SFIELD(cmd_arg, SPI_LEN, spilen);
1738
1739 if ((func == 2) && (fifo == 1)) {
1740 sd_data(("%s: %s func %d, %s, addr 0x%x, len %d bytes, r_cnt %d t_cnt %d\n",
1741 __FUNCTION__, write ? "Wr" : "Rd", func, "INCR",
1742 addr, nbytes, sd->r_cnt, sd->t_cnt));
1743 }
1744
1745 sd_trace(("%s cmd_arg = 0x%x\n", __FUNCTION__, cmd_arg));
1746 sd_data(("%s: %s func %d, %s, addr 0x%x, len %d bytes, r_cnt %d t_cnt %d\n",
1747 __FUNCTION__, write ? "Wd" : "Rd", func, "INCR",
1748 addr, nbytes, sd->r_cnt, sd->t_cnt));
1749
1750 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, data, nbytes)) != SUCCESS) {
1751 sd_err(("%s: cmd_issue failed for %s\n", __FUNCTION__,
1752 (write ? "write" : "read")));
1753 return status;
1754 }
1755
1756 if ((nbytes > 2000) && !write) {
1757 sd_trace((">2KB read: F2 rd of %d bytes\n", nbytes));
1758 }
1759
1760 return SUCCESS;
1761 }
1762
1763 /* Reset and re-initialize the device */
1764 int
sdioh_sdio_reset(sdioh_info_t * si)1765 sdioh_sdio_reset(sdioh_info_t *si)
1766 {
1767 si->card_init_done = FALSE;
1768 return bcmspi_client_init(si);
1769 }
1770
1771 SDIOH_API_RC
sdioh_gpioouten(sdioh_info_t * sd,uint32 gpio)1772 sdioh_gpioouten(sdioh_info_t *sd, uint32 gpio)
1773 {
1774 return SDIOH_API_RC_FAIL;
1775 }
1776
1777 SDIOH_API_RC
sdioh_gpioout(sdioh_info_t * sd,uint32 gpio,bool enab)1778 sdioh_gpioout(sdioh_info_t *sd, uint32 gpio, bool enab)
1779 {
1780 return SDIOH_API_RC_FAIL;
1781 }
1782
1783 bool
sdioh_gpioin(sdioh_info_t * sd,uint32 gpio)1784 sdioh_gpioin(sdioh_info_t *sd, uint32 gpio)
1785 {
1786 return FALSE;
1787 }
1788
1789 SDIOH_API_RC
sdioh_gpio_init(sdioh_info_t * sd)1790 sdioh_gpio_init(sdioh_info_t *sd)
1791 {
1792 return SDIOH_API_RC_FAIL;
1793 }
1794