1 /* 2 * Structure used by apps whose drivers access SDIO drivers. 3 * Pulled out separately so dhdu and wlu can both use it. 4 * 5 * Copyright (C) 2020, Broadcom. 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions of 17 * the license of that module. An independent module is a module which is not 18 * derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * 22 * <<Broadcom-WL-IPTag/Dual:>> 23 */ 24 25 #ifndef _sdiovar_h_ 26 #define _sdiovar_h_ 27 28 #include <typedefs.h> 29 30 typedef struct sdreg { 31 int func; 32 int offset; 33 int value; 34 } sdreg_t; 35 36 typedef struct sdreg_64 { 37 int func; 38 int offset; 39 uint64 value; 40 } sdreg_64_t; 41 42 /* Common msglevel constants */ 43 #define SDH_ERROR_VAL 0x0001 /* Error */ 44 #define SDH_TRACE_VAL 0x0002 /* Trace */ 45 #define SDH_INFO_VAL 0x0004 /* Info */ 46 #define SDH_DEBUG_VAL 0x0008 /* Debug */ 47 #define SDH_DATA_VAL 0x0010 /* Data */ 48 #define SDH_CTRL_VAL 0x0020 /* Control Regs */ 49 #define SDH_LOG_VAL 0x0040 /* Enable bcmlog */ 50 #define SDH_DMA_VAL 0x0080 /* DMA */ 51 #define SDH_COST_VAL 0x8000 /* Control Regs */ 52 53 #define NUM_PREV_TRANSACTIONS 16 54 55 #ifdef BCMSPI 56 /* Error statistics for gSPI */ 57 struct spierrstats_t { 58 uint32 dna; /* The requested data is not available. */ 59 uint32 rdunderflow; /* FIFO underflow happened due to current (F2, F3) rd command */ 60 uint32 wroverflow; /* FIFO underflow happened due to current (F1, F2, F3) wr command */ 61 62 uint32 f2interrupt; /* OR of all F2 related intr status bits. */ 63 uint32 f3interrupt; /* OR of all F3 related intr status bits. */ 64 65 uint32 f2rxnotready; /* F2 FIFO is not ready to receive data (FIFO empty) */ 66 uint32 f3rxnotready; /* F3 FIFO is not ready to receive data (FIFO empty) */ 67 68 uint32 hostcmddataerr; /* Error in command or host data, detected by CRC/checksum 69 * (optional) 70 */ 71 uint32 f2pktavailable; /* Packet is available in F2 TX FIFO */ 72 uint32 f3pktavailable; /* Packet is available in F2 TX FIFO */ 73 74 uint32 dstatus[NUM_PREV_TRANSACTIONS]; /* dstatus bits of last 16 gSPI transactions */ 75 uint32 spicmd[NUM_PREV_TRANSACTIONS]; 76 }; 77 #endif /* BCMSPI */ 78 79 typedef struct sdio_bus_metrics { 80 uint32 active_dur; /* msecs */ 81 82 /* Generic */ 83 uint32 data_intr_cnt; /* data interrupt counter */ 84 uint32 mb_intr_cnt; /* mailbox interrupt counter */ 85 uint32 error_intr_cnt; /* error interrupt counter */ 86 uint32 wakehost_cnt; /* counter for OOB wakehost */ 87 88 /* DS forcewake */ 89 uint32 ds_wake_on_cnt; /* counter for (clock) ON */ 90 uint32 ds_wake_on_dur; /* duration for (clock) ON) */ 91 uint32 ds_wake_off_cnt; /* counter for (clock) OFF */ 92 uint32 ds_wake_off_dur; /* duration for (clock) OFF */ 93 94 /* DS_D0 state */ 95 uint32 ds_d0_cnt; /* counter for DS_D0 state */ 96 uint32 ds_d0_dur; /* duration for DS_D0 state */ 97 98 /* DS_D3 state */ 99 uint32 ds_d3_cnt; /* counter for DS_D3 state */ 100 uint32 ds_d3_dur; /* duration for DS_D3 state */ 101 102 /* DS DEV_WAKE */ 103 uint32 ds_dw_assrt_cnt; /* counter for DW_ASSERT */ 104 uint32 ds_dw_dassrt_cnt; /* counter for DW_DASSERT */ 105 106 /* DS mailbox signals */ 107 uint32 ds_tx_dsreq_cnt; /* counter for tx HMB_DATA_DSREQ */ 108 uint32 ds_tx_dsexit_cnt; /* counter for tx HMB_DATA_DSEXIT */ 109 uint32 ds_tx_d3ack_cnt; /* counter for tx HMB_DATA_D3ACK */ 110 uint32 ds_tx_d3exit_cnt; /* counter for tx HMB_DATA_D3EXIT */ 111 uint32 ds_rx_dsack_cnt; /* counter for rx SMB_DATA_DSACK */ 112 uint32 ds_rx_dsnack_cnt; /* counter for rx SMB_DATA_DSNACK */ 113 uint32 ds_rx_d3inform_cnt; /* counter for rx SMB_DATA_D3INFORM */ 114 } sdio_bus_metrics_t; 115 116 /* Bus interface info for SDIO */ 117 typedef struct wl_pwr_sdio_stats { 118 uint16 type; /* WL_PWRSTATS_TYPE_SDIO */ 119 uint16 len; /* Up to 4K-1, top 4 bits are reserved */ 120 121 sdio_bus_metrics_t sdio; /* stats from SDIO bus driver */ 122 } wl_pwr_sdio_stats_t; 123 124 #endif /* _sdiovar_h_ */ 125