1 /* 2 * SDIO spec header file 3 * Protocol and standard (common) device definitions 4 * 5 * Copyright (C) 2020, Broadcom. 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions of 17 * the license of that module. An independent module is a module which is not 18 * derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * 22 * <<Broadcom-WL-IPTag/Dual:>> 23 */ 24 25 #ifndef _SDIO_H 26 #define _SDIO_H 27 28 #ifdef BCMSDIO 29 /* 30 * Standard SD Device Register Map. 31 * 32 * Reference definitions from: 33 * SD Specifications, Part E1: SDIO Specification 34 * Version 1.10 35 * August 18, 2004 36 * http://www.sdcard.org 37 * 38 * EXCEPTION: The speed_control register defined here is based on a 39 * draft of the next version, and is thus nonstandard. 40 */ 41 42 /* CCCR structure for function 0 */ 43 typedef volatile struct { 44 uint8 cccr_sdio_rev; /* RO, cccr and sdio revision */ 45 uint8 sd_rev; /* RO, sd spec revision */ 46 uint8 io_en; /* I/O enable */ 47 uint8 io_rdy; /* I/O ready reg */ 48 uint8 intr_ctl; /* Master and per function interrupt enable control */ 49 uint8 intr_status; /* RO, interrupt pending status */ 50 uint8 io_abort; /* read/write abort or reset all functions */ 51 uint8 bus_inter; /* bus interface control */ 52 uint8 capability; /* RO, card capability */ 53 54 uint8 cis_base_low; /* 0x9 RO, common CIS base address, LSB */ 55 uint8 cis_base_mid; 56 uint8 cis_base_high; /* 0xB RO, common CIS base address, MSB */ 57 58 /* suspend/resume registers */ 59 uint8 bus_suspend; /* 0xC */ 60 uint8 func_select; /* 0xD */ 61 uint8 exec_flag; /* 0xE */ 62 uint8 ready_flag; /* 0xF */ 63 64 uint8 fn0_blk_size[2]; /* 0x10(LSB), 0x11(MSB) */ 65 66 uint8 power_control; /* 0x12 (SDIO version 1.10) */ 67 68 uint8 speed_control; /* 0x13 */ 69 } sdio_regs_t; 70 71 /* SDIO Device CCCR offsets */ 72 #define SDIOD_CCCR_REV 0x00 73 #define SDIOD_CCCR_SDREV 0x01 74 #define SDIOD_CCCR_IOEN 0x02 75 #define SDIOD_CCCR_IORDY 0x03 76 #define SDIOD_CCCR_INTEN 0x04 77 #define SDIOD_CCCR_INTPEND 0x05 78 #define SDIOD_CCCR_IOABORT 0x06 79 #define SDIOD_CCCR_BICTRL 0x07 80 #define SDIOD_CCCR_CAPABLITIES 0x08 81 #define SDIOD_CCCR_CISPTR_0 0x09 82 #define SDIOD_CCCR_CISPTR_1 0x0A 83 #define SDIOD_CCCR_CISPTR_2 0x0B 84 #define SDIOD_CCCR_BUSSUSP 0x0C 85 #define SDIOD_CCCR_FUNCSEL 0x0D 86 #define SDIOD_CCCR_EXECFLAGS 0x0E 87 #define SDIOD_CCCR_RDYFLAGS 0x0F 88 #define SDIOD_CCCR_BLKSIZE_0 0x10 89 #define SDIOD_CCCR_BLKSIZE_1 0x11 90 #define SDIOD_CCCR_POWER_CONTROL 0x12 91 #define SDIOD_CCCR_SPEED_CONTROL 0x13 92 #define SDIOD_CCCR_UHSI_SUPPORT 0x14 93 #define SDIOD_CCCR_DRIVER_STRENGTH 0x15 94 #define SDIOD_CCCR_INTR_EXTN 0x16 95 96 /* Broadcom extensions (corerev >= 1) */ 97 #define SDIOD_CCCR_BRCM_CARDCAP 0xf0 98 #define SDIOD_CCCR_BRCM_CARDCAP_CMD14_SUPPORT 0x02 99 #define SDIOD_CCCR_BRCM_CARDCAP_CMD14_EXT 0x04 100 #define SDIOD_CCCR_BRCM_CARDCAP_CMD_NODEC 0x08 101 #define SDIOD_CCCR_BRCM_CARDCTL 0xf1 102 #define SDIOD_CCCR_BRCM_SEPINT 0xf2 103 104 /* cccr_sdio_rev */ 105 #define SDIO_REV_SDIOID_MASK 0xf0 /* SDIO spec revision number */ 106 #define SDIO_REV_CCCRID_MASK 0x0f /* CCCR format version number */ 107 #define SDIO_SPEC_VERSION_3_0 0x40 /* SDIO spec version 3.0 */ 108 109 /* sd_rev */ 110 #define SD_REV_PHY_MASK 0x0f /* SD format version number */ 111 112 /* io_en */ 113 #define SDIO_FUNC_ENABLE_1 0x02 /* function 1 I/O enable */ 114 #define SDIO_FUNC_ENABLE_2 0x04 /* function 2 I/O enable */ 115 #if defined (BT_OVER_SDIO) 116 #define SDIO_FUNC_ENABLE_3 0x08 /* function 2 I/O enable */ 117 #define SDIO_FUNC_DISABLE_3 0xF0 /* function 2 I/O enable */ 118 #endif /* defined (BT_OVER_SDIO) */ 119 120 /* io_rdys */ 121 #define SDIO_FUNC_READY_1 0x02 /* function 1 I/O ready */ 122 #define SDIO_FUNC_READY_2 0x04 /* function 2 I/O ready */ 123 124 /* intr_ctl */ 125 #define INTR_CTL_MASTER_EN 0x1 /* interrupt enable master */ 126 #define INTR_CTL_FUNC1_EN 0x2 /* interrupt enable for function 1 */ 127 #define INTR_CTL_FUNC2_EN 0x4 /* interrupt enable for function 2 */ 128 #if defined (BT_OVER_SDIO) 129 #define INTR_CTL_FUNC3_EN 0x8 /* interrupt enable for function 3 */ 130 #endif /* defined (BT_OVER_SDIO) */ 131 /* intr_status */ 132 #define INTR_STATUS_FUNC1 0x2 /* interrupt pending for function 1 */ 133 #define INTR_STATUS_FUNC2 0x4 /* interrupt pending for function 2 */ 134 135 /* io_abort */ 136 #define IO_ABORT_RESET_ALL 0x08 /* I/O card reset */ 137 #define IO_ABORT_FUNC_MASK 0x07 /* abort selction: function x */ 138 139 /* bus_inter */ 140 #define BUS_CARD_DETECT_DIS 0x80 /* Card Detect disable */ 141 #define BUS_SPI_CONT_INTR_CAP 0x40 /* support continuous SPI interrupt */ 142 #define BUS_SPI_CONT_INTR_EN 0x20 /* continuous SPI interrupt enable */ 143 #define BUS_SD_DATA_WIDTH_MASK 0x03 /* bus width mask */ 144 #define BUS_SD_DATA_WIDTH_4BIT 0x02 /* bus width 4-bit mode */ 145 #define BUS_SD_DATA_WIDTH_1BIT 0x00 /* bus width 1-bit mode */ 146 147 /* capability */ 148 #define SDIO_CAP_4BLS 0x80 /* 4-bit support for low speed card */ 149 #define SDIO_CAP_LSC 0x40 /* low speed card */ 150 #define SDIO_CAP_E4MI 0x20 /* enable interrupt between block of data in 4-bit mode */ 151 #define SDIO_CAP_S4MI 0x10 /* support interrupt between block of data in 4-bit mode */ 152 #define SDIO_CAP_SBS 0x08 /* support suspend/resume */ 153 #define SDIO_CAP_SRW 0x04 /* support read wait */ 154 #define SDIO_CAP_SMB 0x02 /* support multi-block transfer */ 155 #define SDIO_CAP_SDC 0x01 /* Support Direct commands during multi-byte transfer */ 156 157 /* power_control */ 158 #define SDIO_POWER_SMPC 0x01 /* supports master power control (RO) */ 159 #define SDIO_POWER_EMPC 0x02 /* enable master power control (allow > 200mA) (RW) */ 160 161 /* speed_control (control device entry into high-speed clocking mode) */ 162 #define SDIO_SPEED_SHS 0x01 /* supports high-speed [clocking] mode (RO) */ 163 #define SDIO_SPEED_EHS 0x02 /* enable high-speed [clocking] mode (RW) */ 164 #define SDIO_SPEED_UHSI_DDR50 0x08 165 166 /* for setting bus speed in card: 0x13h */ 167 #define SDIO_BUS_SPEED_UHSISEL_M BITFIELD_MASK(3) 168 #define SDIO_BUS_SPEED_UHSISEL_S 1 169 170 /* for getting bus speed cap in card: 0x14h */ 171 #define SDIO_BUS_SPEED_UHSICAP_M BITFIELD_MASK(3) 172 #define SDIO_BUS_SPEED_UHSICAP_S 0 173 174 /* for getting driver type CAP in card: 0x15h */ 175 #define SDIO_BUS_DRVR_TYPE_CAP_M BITFIELD_MASK(3) 176 #define SDIO_BUS_DRVR_TYPE_CAP_S 0 177 178 /* for setting driver type selection in card: 0x15h */ 179 #define SDIO_BUS_DRVR_TYPE_SEL_M BITFIELD_MASK(2) 180 #define SDIO_BUS_DRVR_TYPE_SEL_S 4 181 182 /* for getting async int support in card: 0x16h */ 183 #define SDIO_BUS_ASYNCINT_CAP_M BITFIELD_MASK(1) 184 #define SDIO_BUS_ASYNCINT_CAP_S 0 185 186 /* for setting async int selection in card: 0x16h */ 187 #define SDIO_BUS_ASYNCINT_SEL_M BITFIELD_MASK(1) 188 #define SDIO_BUS_ASYNCINT_SEL_S 1 189 190 /* brcm sepint */ 191 #define SDIO_SEPINT_MASK 0x01 /* route sdpcmdev intr onto separate pad (chip-specific) */ 192 #define SDIO_SEPINT_OE 0x02 /* 1 asserts output enable for above pad */ 193 #define SDIO_SEPINT_ACT_HI 0x04 /* use active high interrupt level instead of active low */ 194 195 /* FBR structure for function 1-7, FBR addresses and register offsets */ 196 typedef volatile struct { 197 uint8 devctr; /* device interface, CSA control */ 198 uint8 ext_dev; /* extended standard I/O device type code */ 199 uint8 pwr_sel; /* power selection support */ 200 uint8 PAD[6]; /* reserved */ 201 202 uint8 cis_low; /* CIS LSB */ 203 uint8 cis_mid; 204 uint8 cis_high; /* CIS MSB */ 205 uint8 csa_low; /* code storage area, LSB */ 206 uint8 csa_mid; 207 uint8 csa_high; /* code storage area, MSB */ 208 uint8 csa_dat_win; /* data access window to function */ 209 210 uint8 fnx_blk_size[2]; /* block size, little endian */ 211 } sdio_fbr_t; 212 213 /* Maximum number of I/O funcs */ 214 #define SDIOD_MAX_FUNCS 8 215 #define SDIOD_MAX_IOFUNCS 7 216 217 /* SDIO Device FBR Start Address */ 218 #define SDIOD_FBR_STARTADDR 0x100 219 220 /* SDIO Device FBR Size */ 221 #define SDIOD_FBR_SIZE 0x100 222 223 /* Macro to calculate FBR register base */ 224 #define SDIOD_FBR_BASE(n) ((n) * 0x100) 225 226 /* Function register offsets */ 227 #define SDIOD_FBR_DEVCTR 0x00 /* basic info for function */ 228 #define SDIOD_FBR_EXT_DEV 0x01 /* extended I/O device code */ 229 #define SDIOD_FBR_PWR_SEL 0x02 /* power selection bits */ 230 231 /* SDIO Function CIS ptr offset */ 232 #define SDIOD_FBR_CISPTR_0 0x09 233 #define SDIOD_FBR_CISPTR_1 0x0A 234 #define SDIOD_FBR_CISPTR_2 0x0B 235 236 /* Code Storage Area pointer */ 237 #define SDIOD_FBR_CSA_ADDR_0 0x0C 238 #define SDIOD_FBR_CSA_ADDR_1 0x0D 239 #define SDIOD_FBR_CSA_ADDR_2 0x0E 240 #define SDIOD_FBR_CSA_DATA 0x0F 241 242 /* SDIO Function I/O Block Size */ 243 #define SDIOD_FBR_BLKSIZE_0 0x10 244 #define SDIOD_FBR_BLKSIZE_1 0x11 245 246 /* devctr */ 247 #define SDIOD_FBR_DEVCTR_DIC 0x0f /* device interface code */ 248 #define SDIOD_FBR_DECVTR_CSA 0x40 /* CSA support flag */ 249 #define SDIOD_FBR_DEVCTR_CSA_EN 0x80 /* CSA enabled */ 250 /* interface codes */ 251 #define SDIOD_DIC_NONE 0 /* SDIO standard interface is not supported */ 252 #define SDIOD_DIC_UART 1 253 #define SDIOD_DIC_BLUETOOTH_A 2 254 #define SDIOD_DIC_BLUETOOTH_B 3 255 #define SDIOD_DIC_GPS 4 256 #define SDIOD_DIC_CAMERA 5 257 #define SDIOD_DIC_PHS 6 258 #define SDIOD_DIC_WLAN 7 259 #define SDIOD_DIC_EXT 0xf /* extended device interface, read ext_dev register */ 260 261 /* pwr_sel */ 262 #define SDIOD_PWR_SEL_SPS 0x01 /* supports power selection */ 263 #define SDIOD_PWR_SEL_EPS 0x02 /* enable power selection (low-current mode) */ 264 265 /* misc defines */ 266 #define SDIO_FUNC_0 0 267 #define SDIO_FUNC_1 1 268 #define SDIO_FUNC_2 2 269 #define SDIO_FUNC_4 4 270 #define SDIO_FUNC_5 5 271 #define SDIO_FUNC_6 6 272 #define SDIO_FUNC_7 7 273 274 #define SD_CARD_TYPE_UNKNOWN 0 /* bad type or unrecognized */ 275 #define SD_CARD_TYPE_IO 1 /* IO only card */ 276 #define SD_CARD_TYPE_MEMORY 2 /* memory only card */ 277 #define SD_CARD_TYPE_COMBO 3 /* IO and memory combo card */ 278 279 #define SDIO_MAX_BLOCK_SIZE 2048 /* maximum block size for block mode operation */ 280 #define SDIO_MIN_BLOCK_SIZE 1 /* minimum block size for block mode operation */ 281 282 /* Card registers: status bit position */ 283 #define CARDREG_STATUS_BIT_OUTOFRANGE 31 284 #define CARDREG_STATUS_BIT_COMCRCERROR 23 285 #define CARDREG_STATUS_BIT_ILLEGALCOMMAND 22 286 #define CARDREG_STATUS_BIT_ERROR 19 287 #define CARDREG_STATUS_BIT_IOCURRENTSTATE3 12 288 #define CARDREG_STATUS_BIT_IOCURRENTSTATE2 11 289 #define CARDREG_STATUS_BIT_IOCURRENTSTATE1 10 290 #define CARDREG_STATUS_BIT_IOCURRENTSTATE0 9 291 #define CARDREG_STATUS_BIT_FUN_NUM_ERROR 4 292 293 /* ---------------------------------------------------- 294 * SDIO Protocol Definitions -- commands and responses 295 * 296 * Reference definitions from SDIO Specification v1.10 297 * of August 18, 2004; and SD Physical Layer v1.10 of 298 * October 15, 2004. 299 * ---------------------------------------------------- 300 */ 301 302 /* Straight defines, mostly used by older driver(s). */ 303 304 #define SD_CMD_GO_IDLE_STATE 0 /* mandatory for SDIO */ 305 #define SD_CMD_SEND_OPCOND 1 306 #define SD_CMD_MMC_SET_RCA 3 307 #define SD_CMD_IO_SEND_OP_COND 5 /* mandatory for SDIO */ 308 #define SD_CMD_SELECT_DESELECT_CARD 7 309 #define SD_CMD_SEND_CSD 9 310 #define SD_CMD_SEND_CID 10 311 #define SD_CMD_STOP_TRANSMISSION 12 312 #define SD_CMD_SEND_STATUS 13 313 #define SD_CMD_GO_INACTIVE_STATE 15 314 #define SD_CMD_SET_BLOCKLEN 16 315 #define SD_CMD_READ_SINGLE_BLOCK 17 316 #define SD_CMD_READ_MULTIPLE_BLOCK 18 317 #define SD_CMD_WRITE_BLOCK 24 318 #define SD_CMD_WRITE_MULTIPLE_BLOCK 25 319 #define SD_CMD_PROGRAM_CSD 27 320 #define SD_CMD_SET_WRITE_PROT 28 321 #define SD_CMD_CLR_WRITE_PROT 29 322 #define SD_CMD_SEND_WRITE_PROT 30 323 #define SD_CMD_ERASE_WR_BLK_START 32 324 #define SD_CMD_ERASE_WR_BLK_END 33 325 #define SD_CMD_ERASE 38 326 #define SD_CMD_LOCK_UNLOCK 42 327 #define SD_CMD_IO_RW_DIRECT 52 /* mandatory for SDIO */ 328 #define SD_CMD_IO_RW_EXTENDED 53 /* mandatory for SDIO */ 329 #define SD_CMD_APP_CMD 55 330 #define SD_CMD_GEN_CMD 56 331 #define SD_CMD_READ_OCR 58 332 #define SD_CMD_CRC_ON_OFF 59 /* mandatory for SDIO */ 333 #define SD_ACMD_SD_STATUS 13 334 #define SD_ACMD_SEND_NUM_WR_BLOCKS 22 335 #define SD_ACMD_SET_WR_BLOCK_ERASE_CNT 23 336 #define SD_ACMD_SD_SEND_OP_COND 41 337 #define SD_ACMD_SET_CLR_CARD_DETECT 42 338 #define SD_ACMD_SEND_SCR 51 339 340 /* argument for SD_CMD_IO_RW_DIRECT and SD_CMD_IO_RW_EXTENDED */ 341 #define SD_IO_OP_READ 0 /* Read_Write: Read */ 342 #define SD_IO_OP_WRITE 1 /* Read_Write: Write */ 343 #define SD_IO_RW_NORMAL 0 /* no RAW */ 344 #define SD_IO_RW_RAW 1 /* RAW */ 345 #define SD_IO_BYTE_MODE 0 /* Byte Mode */ 346 #define SD_IO_BLOCK_MODE 1 /* BlockMode */ 347 #define SD_IO_FIXED_ADDRESS 0 /* fix Address */ 348 #define SD_IO_INCREMENT_ADDRESS 1 /* IncrementAddress */ 349 350 /* build SD_CMD_IO_RW_DIRECT Argument */ 351 #define SDIO_IO_RW_DIRECT_ARG(rw, raw, func, addr, data) \ 352 ((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((raw) & 1) << 27) | \ 353 (((addr) & 0x1FFFF) << 9) | ((data) & 0xFF)) 354 355 /* build SD_CMD_IO_RW_EXTENDED Argument */ 356 #define SDIO_IO_RW_EXTENDED_ARG(rw, blk, func, addr, inc_addr, count) \ 357 ((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((blk) & 1) << 27) | \ 358 (((inc_addr) & 1) << 26) | (((addr) & 0x1FFFF) << 9) | ((count) & 0x1FF)) 359 360 /* SDIO response parameters */ 361 #define SD_RSP_NO_NONE 0 362 #define SD_RSP_NO_1 1 363 #define SD_RSP_NO_2 2 364 #define SD_RSP_NO_3 3 365 #define SD_RSP_NO_4 4 366 #define SD_RSP_NO_5 5 367 #define SD_RSP_NO_6 6 368 369 /* Modified R6 response (to CMD3) */ 370 #define SD_RSP_MR6_COM_CRC_ERROR 0x8000 371 #define SD_RSP_MR6_ILLEGAL_COMMAND 0x4000 372 #define SD_RSP_MR6_ERROR 0x2000 373 374 /* Modified R1 in R4 Response (to CMD5) */ 375 #define SD_RSP_MR1_SBIT 0x80 376 #define SD_RSP_MR1_PARAMETER_ERROR 0x40 377 #define SD_RSP_MR1_RFU5 0x20 378 #define SD_RSP_MR1_FUNC_NUM_ERROR 0x10 379 #define SD_RSP_MR1_COM_CRC_ERROR 0x08 380 #define SD_RSP_MR1_ILLEGAL_COMMAND 0x04 381 #define SD_RSP_MR1_RFU1 0x02 382 #define SD_RSP_MR1_IDLE_STATE 0x01 383 384 /* R5 response (to CMD52 and CMD53) */ 385 #define SD_RSP_R5_COM_CRC_ERROR 0x80 386 #define SD_RSP_R5_ILLEGAL_COMMAND 0x40 387 #define SD_RSP_R5_IO_CURRENTSTATE1 0x20 388 #define SD_RSP_R5_IO_CURRENTSTATE0 0x10 389 #define SD_RSP_R5_ERROR 0x08 390 #define SD_RSP_R5_RFU 0x04 391 #define SD_RSP_R5_FUNC_NUM_ERROR 0x02 392 #define SD_RSP_R5_OUT_OF_RANGE 0x01 393 394 #define SD_RSP_R5_ERRBITS 0xCB 395 396 /* Mask/shift form, commonly used in newer driver(s) */ 397 398 /* ------------------------------------------------ 399 * SDIO Commands and responses 400 * 401 * I/O only commands are: 402 * CMD0, CMD3, CMD5, CMD7, CMD14, CMD15, CMD52, CMD53 403 * ------------------------------------------------ 404 */ 405 406 /* SDIO Commands */ 407 #define SDIOH_CMD_0 0 408 #define SDIOH_CMD_3 3 409 #define SDIOH_CMD_5 5 410 #define SDIOH_CMD_7 7 411 #define SDIOH_CMD_11 11 412 #define SDIOH_CMD_14 14 413 #define SDIOH_CMD_15 15 414 #define SDIOH_CMD_19 19 415 #define SDIOH_CMD_52 52 416 #define SDIOH_CMD_53 53 417 #define SDIOH_CMD_59 59 418 419 /* SDIO Command Responses */ 420 #define SDIOH_RSP_NONE 0 421 #define SDIOH_RSP_R1 1 422 #define SDIOH_RSP_R2 2 423 #define SDIOH_RSP_R3 3 424 #define SDIOH_RSP_R4 4 425 #define SDIOH_RSP_R5 5 426 #define SDIOH_RSP_R6 6 427 428 /* 429 * SDIO Response Error flags 430 */ 431 #define SDIOH_RSP5_ERROR_FLAGS 0xCB 432 433 /* ------------------------------------------------ 434 * SDIO Command structures. I/O only commands are: 435 * 436 * CMD0, CMD3, CMD5, CMD7, CMD15, CMD52, CMD53 437 * ------------------------------------------------ 438 */ 439 440 #define CMD5_OCR_M BITFIELD_MASK(24) 441 #define CMD5_OCR_S 0 442 443 #define CMD5_S18R_M BITFIELD_MASK(1) 444 #define CMD5_S18R_S 24 445 446 #define CMD7_RCA_M BITFIELD_MASK(16) 447 #define CMD7_RCA_S 16 448 449 #define CMD14_RCA_M BITFIELD_MASK(16) 450 #define CMD14_RCA_S 16 451 #define CMD14_SLEEP_M BITFIELD_MASK(1) 452 #define CMD14_SLEEP_S 15 453 454 #define CMD_15_RCA_M BITFIELD_MASK(16) 455 #define CMD_15_RCA_S 16 456 457 #define CMD52_DATA_M BITFIELD_MASK(8) /* Bits [7:0] - Write Data/Stuff bits of CMD52 458 */ 459 #define CMD52_DATA_S 0 460 #define CMD52_REG_ADDR_M BITFIELD_MASK(17) /* Bits [25:9] - register address */ 461 #define CMD52_REG_ADDR_S 9 462 #define CMD52_RAW_M BITFIELD_MASK(1) /* Bit 27 - Read after Write flag */ 463 #define CMD52_RAW_S 27 464 #define CMD52_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number */ 465 #define CMD52_FUNCTION_S 28 466 #define CMD52_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */ 467 #define CMD52_RW_FLAG_S 31 468 469 #define CMD53_BYTE_BLK_CNT_M BITFIELD_MASK(9) /* Bits [8:0] - Byte/Block Count of CMD53 */ 470 #define CMD53_BYTE_BLK_CNT_S 0 471 #define CMD53_REG_ADDR_M BITFIELD_MASK(17) /* Bits [25:9] - register address */ 472 #define CMD53_REG_ADDR_S 9 473 #define CMD53_OP_CODE_M BITFIELD_MASK(1) /* Bit 26 - R/W Operation Code */ 474 #define CMD53_OP_CODE_S 26 475 #define CMD53_BLK_MODE_M BITFIELD_MASK(1) /* Bit 27 - Block Mode */ 476 #define CMD53_BLK_MODE_S 27 477 #define CMD53_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number */ 478 #define CMD53_FUNCTION_S 28 479 #define CMD53_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */ 480 #define CMD53_RW_FLAG_S 31 481 482 /* ------------------------------------------------------ 483 * SDIO Command Response structures for SD1 and SD4 modes 484 * ----------------------------------------------------- 485 */ 486 #define RSP4_IO_OCR_M BITFIELD_MASK(24) /* Bits [23:0] - Card's OCR Bits [23:0] */ 487 #define RSP4_IO_OCR_S 0 488 489 #define RSP4_S18A_M BITFIELD_MASK(1) /* Bits [23:0] - Card's OCR Bits [23:0] */ 490 #define RSP4_S18A_S 24 491 492 #define RSP4_STUFF_M BITFIELD_MASK(3) /* Bits [26:24] - Stuff bits */ 493 #define RSP4_STUFF_S 24 494 #define RSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 27 - Memory present */ 495 #define RSP4_MEM_PRESENT_S 27 496 #define RSP4_NUM_FUNCS_M BITFIELD_MASK(3) /* Bits [30:28] - Number of I/O funcs */ 497 #define RSP4_NUM_FUNCS_S 28 498 #define RSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 31 - SDIO card ready */ 499 #define RSP4_CARD_READY_S 31 500 501 #define RSP6_STATUS_M BITFIELD_MASK(16) /* Bits [15:0] - Card status bits [19,22,23,12:0] 502 */ 503 #define RSP6_STATUS_S 0 504 #define RSP6_IO_RCA_M BITFIELD_MASK(16) /* Bits [31:16] - RCA bits[31-16] */ 505 #define RSP6_IO_RCA_S 16 506 507 #define RSP1_AKE_SEQ_ERROR_M BITFIELD_MASK(1) /* Bit 3 - Authentication seq error */ 508 #define RSP1_AKE_SEQ_ERROR_S 3 509 #define RSP1_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */ 510 #define RSP1_APP_CMD_S 5 511 #define RSP1_READY_FOR_DATA_M BITFIELD_MASK(1) /* Bit 8 - Ready for data (buff empty) */ 512 #define RSP1_READY_FOR_DATA_S 8 513 #define RSP1_CURR_STATE_M BITFIELD_MASK(4) /* Bits [12:9] - State of card 514 * when Cmd was received 515 */ 516 #define RSP1_CURR_STATE_S 9 517 #define RSP1_EARSE_RESET_M BITFIELD_MASK(1) /* Bit 13 - Erase seq cleared */ 518 #define RSP1_EARSE_RESET_S 13 519 #define RSP1_CARD_ECC_DISABLE_M BITFIELD_MASK(1) /* Bit 14 - Card ECC disabled */ 520 #define RSP1_CARD_ECC_DISABLE_S 14 521 #define RSP1_WP_ERASE_SKIP_M BITFIELD_MASK(1) /* Bit 15 - Partial blocks erased due to W/P */ 522 #define RSP1_WP_ERASE_SKIP_S 15 523 #define RSP1_CID_CSD_OVERW_M BITFIELD_MASK(1) /* Bit 16 - Illegal write to CID or R/O bits 524 * of CSD 525 */ 526 #define RSP1_CID_CSD_OVERW_S 16 527 #define RSP1_ERROR_M BITFIELD_MASK(1) /* Bit 19 - General/Unknown error */ 528 #define RSP1_ERROR_S 19 529 #define RSP1_CC_ERROR_M BITFIELD_MASK(1) /* Bit 20 - Internal Card Control error */ 530 #define RSP1_CC_ERROR_S 20 531 #define RSP1_CARD_ECC_FAILED_M BITFIELD_MASK(1) /* Bit 21 - Card internal ECC failed 532 * to correct data 533 */ 534 #define RSP1_CARD_ECC_FAILED_S 21 535 #define RSP1_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 22 - Cmd not legal for the card state */ 536 #define RSP1_ILLEGAL_CMD_S 22 537 #define RSP1_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 23 - CRC check of previous command failed 538 */ 539 #define RSP1_COM_CRC_ERROR_S 23 540 #define RSP1_LOCK_UNLOCK_FAIL_M BITFIELD_MASK(1) /* Bit 24 - Card lock-unlock Cmd Seq error */ 541 #define RSP1_LOCK_UNLOCK_FAIL_S 24 542 #define RSP1_CARD_LOCKED_M BITFIELD_MASK(1) /* Bit 25 - Card locked by the host */ 543 #define RSP1_CARD_LOCKED_S 25 544 #define RSP1_WP_VIOLATION_M BITFIELD_MASK(1) /* Bit 26 - Attempt to program 545 * write-protected blocks 546 */ 547 #define RSP1_WP_VIOLATION_S 26 548 #define RSP1_ERASE_PARAM_M BITFIELD_MASK(1) /* Bit 27 - Invalid erase blocks */ 549 #define RSP1_ERASE_PARAM_S 27 550 #define RSP1_ERASE_SEQ_ERR_M BITFIELD_MASK(1) /* Bit 28 - Erase Cmd seq error */ 551 #define RSP1_ERASE_SEQ_ERR_S 28 552 #define RSP1_BLK_LEN_ERR_M BITFIELD_MASK(1) /* Bit 29 - Block length error */ 553 #define RSP1_BLK_LEN_ERR_S 29 554 #define RSP1_ADDR_ERR_M BITFIELD_MASK(1) /* Bit 30 - Misaligned address */ 555 #define RSP1_ADDR_ERR_S 30 556 #define RSP1_OUT_OF_RANGE_M BITFIELD_MASK(1) /* Bit 31 - Cmd arg was out of range */ 557 #define RSP1_OUT_OF_RANGE_S 31 558 559 #define RSP5_DATA_M BITFIELD_MASK(8) /* Bits [0:7] - data */ 560 #define RSP5_DATA_S 0 561 #define RSP5_FLAGS_M BITFIELD_MASK(8) /* Bit [15:8] - Rsp flags */ 562 #define RSP5_FLAGS_S 8 563 #define RSP5_STUFF_M BITFIELD_MASK(16) /* Bits [31:16] - Stuff bits */ 564 #define RSP5_STUFF_S 16 565 566 /* ---------------------------------------------- 567 * SDIO Command Response structures for SPI mode 568 * ---------------------------------------------- 569 */ 570 #define SPIRSP4_IO_OCR_M BITFIELD_MASK(16) /* Bits [15:0] - Card's OCR Bits [23:8] */ 571 #define SPIRSP4_IO_OCR_S 0 572 #define SPIRSP4_STUFF_M BITFIELD_MASK(3) /* Bits [18:16] - Stuff bits */ 573 #define SPIRSP4_STUFF_S 16 574 #define SPIRSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 19 - Memory present */ 575 #define SPIRSP4_MEM_PRESENT_S 19 576 #define SPIRSP4_NUM_FUNCS_M BITFIELD_MASK(3) /* Bits [22:20] - Number of I/O funcs */ 577 #define SPIRSP4_NUM_FUNCS_S 20 578 #define SPIRSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 23 - SDIO card ready */ 579 #define SPIRSP4_CARD_READY_S 23 580 #define SPIRSP4_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - idle state */ 581 #define SPIRSP4_IDLE_STATE_S 24 582 #define SPIRSP4_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */ 583 #define SPIRSP4_ILLEGAL_CMD_S 26 584 #define SPIRSP4_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 27 - COM CRC error */ 585 #define SPIRSP4_COM_CRC_ERROR_S 27 586 #define SPIRSP4_FUNC_NUM_ERROR_M BITFIELD_MASK(1) /* Bit 28 - Function number error 587 */ 588 #define SPIRSP4_FUNC_NUM_ERROR_S 28 589 #define SPIRSP4_PARAM_ERROR_M BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */ 590 #define SPIRSP4_PARAM_ERROR_S 30 591 #define SPIRSP4_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */ 592 #define SPIRSP4_START_BIT_S 31 593 594 #define SPIRSP5_DATA_M BITFIELD_MASK(8) /* Bits [23:16] - R/W Data */ 595 #define SPIRSP5_DATA_S 16 596 #define SPIRSP5_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - Idle state */ 597 #define SPIRSP5_IDLE_STATE_S 24 598 #define SPIRSP5_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */ 599 #define SPIRSP5_ILLEGAL_CMD_S 26 600 #define SPIRSP5_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 27 - COM CRC error */ 601 #define SPIRSP5_COM_CRC_ERROR_S 27 602 #define SPIRSP5_FUNC_NUM_ERROR_M BITFIELD_MASK(1) /* Bit 28 - Function number error 603 */ 604 #define SPIRSP5_FUNC_NUM_ERROR_S 28 605 #define SPIRSP5_PARAM_ERROR_M BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */ 606 #define SPIRSP5_PARAM_ERROR_S 30 607 #define SPIRSP5_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */ 608 #define SPIRSP5_START_BIT_S 31 609 610 /* RSP6 card status format; Pg 68 Physical Layer spec v 1.10 */ 611 #define RSP6STAT_AKE_SEQ_ERROR_M BITFIELD_MASK(1) /* Bit 3 - Authentication seq error 612 */ 613 #define RSP6STAT_AKE_SEQ_ERROR_S 3 614 #define RSP6STAT_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */ 615 #define RSP6STAT_APP_CMD_S 5 616 #define RSP6STAT_READY_FOR_DATA_M BITFIELD_MASK(1) /* Bit 8 - Ready for data 617 * (buff empty) 618 */ 619 #define RSP6STAT_READY_FOR_DATA_S 8 620 #define RSP6STAT_CURR_STATE_M BITFIELD_MASK(4) /* Bits [12:9] - Card state at 621 * Cmd reception 622 */ 623 #define RSP6STAT_CURR_STATE_S 9 624 #define RSP6STAT_ERROR_M BITFIELD_MASK(1) /* Bit 13 - General/Unknown error Bit 19 625 */ 626 #define RSP6STAT_ERROR_S 13 627 #define RSP6STAT_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 14 - Illegal cmd for 628 * card state Bit 22 629 */ 630 #define RSP6STAT_ILLEGAL_CMD_S 14 631 #define RSP6STAT_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 15 - CRC previous command 632 * failed Bit 23 633 */ 634 #define RSP6STAT_COM_CRC_ERROR_S 15 635 636 #define SDIOH_XFER_TYPE_READ SD_IO_OP_READ 637 #define SDIOH_XFER_TYPE_WRITE SD_IO_OP_WRITE 638 639 /* command issue options */ 640 #define CMD_OPTION_DEFAULT 0 641 #define CMD_OPTION_TUNING 1 642 643 #endif /* def BCMSDIO */ 644 #endif /* _SDIO_H */ 645