1 /* 2 * SiliconBackplane System Memory core 3 * 4 * Copyright (C) 2020, Broadcom. 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * 21 * <<Broadcom-WL-IPTag/Dual:>> 22 */ 23 24 #ifndef _SBSYSMEM_H 25 #define _SBSYSMEM_H 26 27 #ifndef _LANGUAGE_ASSEMBLY 28 29 /* cpp contortions to concatenate w/arg prescan */ 30 #ifndef PAD 31 #define _PADLINE(line) pad ## line 32 #define _XSTR(line) _PADLINE(line) 33 #define PAD _XSTR(__LINE__) 34 #endif /* PAD */ 35 36 /* sysmem core registers */ 37 typedef volatile struct sysmemregs { 38 uint32 coreinfo; 39 uint32 bwalloc; 40 uint32 extracoreinfo; 41 uint32 biststat; 42 uint32 bankidx; 43 uint32 standbyctrl; 44 45 uint32 errlogstatus; 46 uint32 errlogaddr; 47 48 uint32 cambankidx; 49 uint32 cambankstandbyctrl; 50 uint32 cambankpatchctrl; 51 uint32 cambankpatchtblbaseaddr; 52 uint32 cambankcmdreg; 53 uint32 cambankdatareg; 54 uint32 standbywait; 55 uint32 PAD[1]; 56 uint32 bankinfo; 57 uint32 PAD[7]; 58 uint32 region_n_regs[32]; 59 uint32 initiat_n_masks[31]; 60 uint32 PAD[1]; 61 uint32 mpucontrol; 62 uint32 mpucapabilities; 63 uint32 PAD[31]; 64 uint32 workaround; 65 uint32 pwrctl; 66 uint32 PAD[133]; 67 uint32 sr_control; 68 uint32 sr_status; 69 uint32 sr_address; 70 uint32 sr_data; 71 } sysmemregs_t; 72 73 /* bus MPU region count mask of sysmemregs_t->mpucapabilities */ 74 #define ACC_MPU_REGION_CNT_MASK 0x7u 75 /* bus MPU disable mask of sysmemregs_t->mpucontrol */ 76 #define BUSMPU_DISABLE_MASK 0xfu 77 78 #endif /* _LANGUAGE_ASSEMBLY */ 79 80 /* Register offsets */ 81 #define SR_COREINFO 0x00 82 #define SR_BWALLOC 0x04 83 #define SR_BISTSTAT 0x0c 84 #define SR_BANKINDEX 0x10 85 #define SR_BANKSTBYCTL 0x14 86 #define SR_PWRCTL 0x1e8 87 88 /* Coreinfo register */ 89 #define SRCI_PT_MASK 0x00070000 /* port type[18:16] */ 90 #define SRCI_PT_SHIFT 16 91 /* port types : SRCI_PT_<processorPT>_<backplanePT> */ 92 #define SRCI_PT_OCP_OCP 0 93 #define SRCI_PT_AXI_OCP 1 94 #define SRCI_PT_ARM7AHB_OCP 2 95 #define SRCI_PT_CM3AHB_OCP 3 96 #define SRCI_PT_AXI_AXI 4 97 #define SRCI_PT_AHB_AXI 5 98 99 #define SRCI_LSS_MASK 0x00f00000 100 #define SRCI_LSS_SHIFT 20 101 #define SRCI_LRS_MASK 0x0f000000 102 #define SRCI_LRS_SHIFT 24 103 104 /* In corerev 0, the memory size is 2 to the power of the 105 * base plus 16 plus to the contents of the memsize field plus 1. 106 */ 107 #define SRCI_MS0_MASK 0xf 108 #define SR_MS0_BASE 16 109 110 /* 111 * In corerev 1 the bank size is 2 ^ the bank size field plus 14, 112 * the memory size is number of banks times bank size. 113 * The same applies to rom size. 114 */ 115 #define SYSMEM_SRCI_ROMNB_MASK 0x3e0 116 #define SYSMEM_SRCI_ROMNB_SHIFT 5 117 #define SYSMEM_SRCI_SRNB_MASK 0x1f 118 #define SYSMEM_SRCI_SRNB_SHIFT 0 119 /* Above bits are obsolete and replaced with below in rev 12 */ 120 #define SYSMEM_SRCI_NEW_ROMNB_MASK 0xff000000u 121 #define SYSMEM_SRCI_NEW_ROMNB_SHIFT 24u 122 #define SYSMEM_SRCI_NEW_SRNB_MASK 0xff0000u 123 #define SYSMEM_SRCI_NEW_SRNB_SHIFT 16u 124 125 /* Standby control register */ 126 #define SRSC_SBYOVR_MASK 0x80000000 127 #define SRSC_SBYOVR_SHIFT 31 128 #define SRSC_SBYOVRVAL_MASK 0x60000000 129 #define SRSC_SBYOVRVAL_SHIFT 29 130 #define SRSC_SBYEN_MASK 0x01000000 131 #define SRSC_SBYEN_SHIFT 24 132 133 /* Power control register */ 134 #define SRPC_PMU_STBYDIS_MASK 0x00000010 135 #define SRPC_PMU_STBYDIS_SHIFT 4 136 #define SRPC_STBYOVRVAL_MASK 0x00000008 137 #define SRPC_STBYOVRVAL_SHIFT 3 138 #define SRPC_STBYOVR_MASK 0x00000007 139 #define SRPC_STBYOVR_SHIFT 0 140 141 /* Extra core capability register */ 142 #define SRECC_NUM_BANKS_MASK 0x000000F0 143 #define SRECC_NUM_BANKS_SHIFT 4 144 #define SRECC_BANKSIZE_MASK 0x0000000F 145 #define SRECC_BANKSIZE_SHIFT 0 146 147 #define SRECC_BANKSIZE(value) (1 << (value)) 148 149 /* CAM bank patch control */ 150 #define SRCBPC_PATCHENABLE 0x80000000 151 152 #define SRP_ADDRESS 0x0001FFFC 153 #define SRP_VALID 0x8000 154 155 /* CAM bank command reg */ 156 #define SRCMD_WRITE 0x00020000 157 #define SRCMD_READ 0x00010000 158 #define SRCMD_DONE 0x80000000 159 160 #define SRCMD_DONE_DLY 1000 161 162 /* bankidx and bankinfo reg defines */ 163 #define SYSMEM_BANKINFO_SZMASK 0x7f 164 #define SYSMEM_BANKIDX_ROM_MASK 0x80 165 166 #define SYSMEM_BANKINFO_REG 0x40 167 #define SYSMEM_BANKIDX_REG 0x10 168 #define SYSMEM_BANKINFO_STDBY_MASK 0x200 169 #define SYSMEM_BANKINFO_STDBY_TIMER 0x400 170 171 #define SYSMEM_BANKINFO_SLPSUPP_SHIFT 14 172 #define SYSMEM_BANKINFO_SLPSUPP_MASK 0x4000 173 #define SYSMEM_BANKINFO_PDASZ_SHIFT 16 174 #define SYSMEM_BANKINFO_PDASZ_MASK 0x001F0000 175 176 /* extracoreinfo register */ 177 #define SYSMEM_DEVRAMBANK_MASK 0xF000 178 #define SYSMEM_DEVRAMBANK_SHIFT 12 179 180 /* bank info to calculate bank size */ 181 #define SYSMEM_BANKINFO_SZBASE 8192 182 #define SYSMEM_BANKSIZE_SHIFT 13 /* SYSMEM_BANKINFO_SZBASE */ 183 184 /* standbycontrol register default values */ 185 #define SYSMEM_SBYCNTRL_TIMEVAL 0x100000u /* standbycontrol timeval[23:0] */ 186 #define SYSMEM_SBYCNTRL_TIMEVAL_MASK 0xffffffu 187 188 /* sbywaitcycle register default values (sysme rev 8) */ 189 #define SYSMEM_SBYWAIT_RAM_TIMEVAL 0xau /* RAM memory access after standby exit */ 190 191 #endif /* _SBSYSMEM_H */ 192