1 /* 2 * Generic Broadcom Home Networking Division (HND) DMA engine HW interface 3 * This supports the following chips: BCM42xx, 44xx, 47xx . 4 * 5 * Copyright (C) 2020, Broadcom. 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions of 17 * the license of that module. An independent module is a module which is not 18 * derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * 22 * <<Broadcom-WL-IPTag/Dual:>> 23 */ 24 25 #ifndef _sbhnddma_h_ 26 #define _sbhnddma_h_ 27 28 /* DMA structure: 29 * support two DMA engines: 32 bits address or 64 bit addressing 30 * basic DMA register set is per channel(transmit or receive) 31 * a pair of channels is defined for convenience 32 */ 33 34 /* 32 bits addressing */ 35 36 /** dma registers per channel(xmt or rcv) */ 37 typedef volatile struct { 38 uint32 control; /**< enable, et al */ 39 uint32 addr; /**< descriptor ring base address (4K aligned) */ 40 uint32 ptr; /**< last descriptor posted to chip */ 41 uint32 status; /**< current active descriptor, et al */ 42 } dma32regs_t; 43 44 typedef volatile struct { 45 dma32regs_t xmt; /**< dma tx channel */ 46 dma32regs_t rcv; /**< dma rx channel */ 47 } dma32regp_t; 48 49 typedef volatile struct { /* diag access */ 50 uint32 fifoaddr; /**< diag address */ 51 uint32 fifodatalow; /**< low 32bits of data */ 52 uint32 fifodatahigh; /**< high 32bits of data */ 53 uint32 pad; /**< reserved */ 54 } dma32diag_t; 55 56 /** 57 * DMA Descriptor 58 * Descriptors are only read by the hardware, never written back. 59 */ 60 typedef volatile struct { 61 uint32 ctrl; /**< misc control bits & bufcount */ 62 uint32 addr; /**< data buffer address */ 63 } dma32dd_t; 64 65 /** Each descriptor ring must be 4096byte aligned, and fit within a single 4096byte page. */ 66 #define D32RINGALIGN_BITS 12 67 #define D32MAXRINGSZ (1 << D32RINGALIGN_BITS) 68 #define D32RINGALIGN (1 << D32RINGALIGN_BITS) 69 70 #define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t)) 71 72 /* transmit channel control */ 73 #define XC_XE ((uint32)1 << 0) /**< transmit enable */ 74 #define XC_SE ((uint32)1 << 1) /**< transmit suspend request */ 75 #define XC_LE ((uint32)1 << 2) /**< loopback enable */ 76 #define XC_FL ((uint32)1 << 4) /**< flush request */ 77 #define XC_MR_MASK 0x000001C0 /**< Multiple outstanding reads */ 78 #define XC_MR_SHIFT 6 79 #define XC_PD ((uint32)1 << 11) /**< parity check disable */ 80 #define XC_AE ((uint32)3 << 16) /**< address extension bits */ 81 #define XC_AE_SHIFT 16 82 #define XC_BL_MASK 0x001C0000 /**< BurstLen bits */ 83 #define XC_BL_SHIFT 18 84 #define XC_PC_MASK 0x00E00000 /**< Prefetch control */ 85 #define XC_PC_SHIFT 21 86 #define XC_PT_MASK 0x03000000 /**< Prefetch threshold */ 87 #define XC_PT_SHIFT 24 88 89 /** Multiple outstanding reads */ 90 #define DMA_MR_1 0 91 #define DMA_MR_2 1 92 #define DMA_MR_4 2 93 #define DMA_MR_8 3 94 #define DMA_MR_12 4 95 #define DMA_MR_16 5 96 #define DMA_MR_20 6 97 #define DMA_MR_32 7 98 99 /** DMA Burst Length in bytes */ 100 #define DMA_BL_16 0 101 #define DMA_BL_32 1 102 #define DMA_BL_64 2 103 #define DMA_BL_128 3 104 #define DMA_BL_256 4 105 #define DMA_BL_512 5 106 #define DMA_BL_1024 6 107 #define DMA_BL_INVALID 0xFF 108 109 /** Prefetch control */ 110 #define DMA_PC_0 0 111 #define DMA_PC_4 1 112 #define DMA_PC_8 2 113 #define DMA_PC_16 3 114 #define DMA_PC_32 4 115 /* others: reserved */ 116 117 /** Prefetch threshold */ 118 #define DMA_PT_1 0 119 #define DMA_PT_2 1 120 #define DMA_PT_4 2 121 #define DMA_PT_8 3 122 123 /** Channel Switch */ 124 #define DMA_CS_OFF 0 125 #define DMA_CS_ON 1 126 127 /* transmit descriptor table pointer */ 128 #define XP_LD_MASK 0xfff /**< last valid descriptor */ 129 130 /* transmit channel status */ 131 #define XS_CD_MASK 0x0fff /**< current descriptor pointer */ 132 #define XS_XS_MASK 0xf000 /**< transmit state */ 133 #define XS_XS_SHIFT 12 134 #define XS_XS_DISABLED 0x0000 /**< disabled */ 135 #define XS_XS_ACTIVE 0x1000 /**< active */ 136 #define XS_XS_IDLE 0x2000 /**< idle wait */ 137 #define XS_XS_STOPPED 0x3000 /**< stopped */ 138 #define XS_XS_SUSP 0x4000 /**< suspend pending */ 139 #define XS_XE_MASK 0xf0000 /**< transmit errors */ 140 #define XS_XE_SHIFT 16 141 #define XS_XE_NOERR 0x00000 /**< no error */ 142 #define XS_XE_DPE 0x10000 /**< descriptor protocol error */ 143 #define XS_XE_DFU 0x20000 /**< data fifo underrun */ 144 #define XS_XE_BEBR 0x30000 /**< bus error on buffer read */ 145 #define XS_XE_BEDA 0x40000 /**< bus error on descriptor access */ 146 #define XS_AD_MASK 0xfff00000 /**< active descriptor */ 147 #define XS_AD_SHIFT 20 148 149 /* receive channel control */ 150 #define RC_RE ((uint32)1 << 0) /**< receive enable */ 151 #define RC_RO_MASK 0xfe /**< receive frame offset */ 152 #define RC_RO_SHIFT 1 153 #define RC_FM ((uint32)1 << 8) /**< direct fifo receive (pio) mode */ 154 #define RC_SH ((uint32)1 << 9) /**< separate rx header descriptor enable */ 155 #define RC_OC ((uint32)1 << 10) /**< overflow continue */ 156 #define RC_PD ((uint32)1 << 11) /**< parity check disable */ 157 #define RC_AE ((uint32)3 << 16) /**< address extension bits */ 158 #define RC_AE_SHIFT 16 159 #define RC_BL_MASK 0x001C0000 /**< BurstLen bits */ 160 #define RC_BL_SHIFT 18 161 #define RC_PC_MASK 0x00E00000 /**< Prefetch control */ 162 #define RC_PC_SHIFT 21 163 #define RC_PT_MASK 0x03000000 /**< Prefetch threshold */ 164 #define RC_PT_SHIFT 24 165 #define RC_WAITCMP_MASK 0x00001000 166 #define RC_WAITCMP_SHIFT 12 167 /* receive descriptor table pointer */ 168 #define RP_LD_MASK 0xfff /**< last valid descriptor */ 169 170 /* receive channel status */ 171 #define RS_CD_MASK 0x0fff /**< current descriptor pointer */ 172 #define RS_RS_MASK 0xf000 /**< receive state */ 173 #define RS_RS_SHIFT 12 174 #define RS_RS_DISABLED 0x0000 /**< disabled */ 175 #define RS_RS_ACTIVE 0x1000 /**< active */ 176 #define RS_RS_IDLE 0x2000 /**< idle wait */ 177 #define RS_RS_STOPPED 0x3000 /**< reserved */ 178 #define RS_RE_MASK 0xf0000 /**< receive errors */ 179 #define RS_RE_SHIFT 16 180 #define RS_RE_NOERR 0x00000 /**< no error */ 181 #define RS_RE_DPE 0x10000 /**< descriptor protocol error */ 182 #define RS_RE_DFO 0x20000 /**< data fifo overflow */ 183 #define RS_RE_BEBW 0x30000 /**< bus error on buffer write */ 184 #define RS_RE_BEDA 0x40000 /**< bus error on descriptor access */ 185 #define RS_AD_MASK 0xfff00000 /**< active descriptor */ 186 #define RS_AD_SHIFT 20 187 188 /* fifoaddr */ 189 #define FA_OFF_MASK 0xffff /**< offset */ 190 #define FA_SEL_MASK 0xf0000 /**< select */ 191 #define FA_SEL_SHIFT 16 192 #define FA_SEL_XDD 0x00000 /**< transmit dma data */ 193 #define FA_SEL_XDP 0x10000 /**< transmit dma pointers */ 194 #define FA_SEL_RDD 0x40000 /**< receive dma data */ 195 #define FA_SEL_RDP 0x50000 /**< receive dma pointers */ 196 #define FA_SEL_XFD 0x80000 /**< transmit fifo data */ 197 #define FA_SEL_XFP 0x90000 /**< transmit fifo pointers */ 198 #define FA_SEL_RFD 0xc0000 /**< receive fifo data */ 199 #define FA_SEL_RFP 0xd0000 /**< receive fifo pointers */ 200 #define FA_SEL_RSD 0xe0000 /**< receive frame status data */ 201 #define FA_SEL_RSP 0xf0000 /**< receive frame status pointers */ 202 203 /* descriptor control flags */ 204 #define CTRL_BC_MASK 0x00001fff /**< buffer byte count, real data len must <= 4KB */ 205 #define CTRL_AE ((uint32)3 << 16) /**< address extension bits */ 206 #define CTRL_AE_SHIFT 16 207 #define CTRL_PARITY ((uint32)3 << 18) /**< parity bit */ 208 #define CTRL_EOT ((uint32)1 << 28) /**< end of descriptor table */ 209 #define CTRL_IOC ((uint32)1 << 29) /**< interrupt on completion */ 210 #define CTRL_EOF ((uint32)1 << 30) /**< end of frame */ 211 #define CTRL_SOF ((uint32)1 << 31) /**< start of frame */ 212 213 /** control flags in the range [27:20] are core-specific and not defined here */ 214 #define CTRL_CORE_MASK 0x0ff00000 215 216 /* 64 bits addressing */ 217 218 /** dma registers per channel(xmt or rcv) */ 219 typedef volatile struct { 220 uint32 control; /**< enable, et al */ 221 uint32 ptr; /**< last descriptor posted to chip */ 222 uint32 addrlow; /**< descriptor ring base address low 32-bits (8K aligned) */ 223 uint32 addrhigh; /**< descriptor ring base address bits 63:32 (8K aligned) */ 224 uint32 status0; /**< current descriptor, xmt state */ 225 uint32 status1; /**< active descriptor, xmt error */ 226 } dma64regs_t; 227 228 typedef volatile struct { 229 dma64regs_t tx; /**< dma64 tx channel */ 230 dma64regs_t rx; /**< dma64 rx channel */ 231 } dma64regp_t; 232 233 typedef volatile struct { /**< diag access */ 234 uint32 fifoaddr; /**< diag address */ 235 uint32 fifodatalow; /**< low 32bits of data */ 236 uint32 fifodatahigh; /**< high 32bits of data */ 237 uint32 pad; /**< reserved */ 238 } dma64diag_t; 239 240 /** 241 * DMA Descriptor 242 * Descriptors are only read by the hardware, never written back. 243 */ 244 typedef volatile struct { 245 uint32 ctrl1; /**< misc control bits */ 246 uint32 ctrl2; /**< buffer count and address extension */ 247 uint32 addrlow; /**< memory address of the date buffer, bits 31:0 */ 248 uint32 addrhigh; /**< memory address of the date buffer, bits 63:32 */ 249 } dma64dd_t; 250 251 /** 252 * Pool implementation: each pool is 64KB max. Align it to maximize ability to grow 253 */ 254 #define D64POOLALIGN_BITS 15u 255 #define D64POOLALIGN_BITS_MAX 16u 256 /** 257 * Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical addresss. 258 */ 259 #define D64RINGALIGN_BITS 13 260 #define D64MAXRINGSZ (1 << D64RINGALIGN_BITS) 261 #define D64RINGBOUNDARY (1 << D64RINGALIGN_BITS) 262 263 #define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t)) 264 265 /** for cores with large descriptor ring support, descriptor ring size can be up to 4096 */ 266 #define D64MAXDD_LARGE ((1 << 16) / sizeof (dma64dd_t)) 267 268 /** 269 * for cores with large descriptor ring support (4k descriptors), descriptor ring cannot cross 270 * 64K boundary 271 */ 272 #define D64RINGBOUNDARY_LARGE (1 << 16) 273 274 /* 275 * Default DMA Burstlen values for USBRev >= 12 and SDIORev >= 11. 276 * When this field contains the value N, the burst length is 2**(N + 4) bytes. 277 */ 278 #define D64_DEF_USBBURSTLEN 2 279 #define D64_DEF_SDIOBURSTLEN 1 280 281 #ifndef D64_USBBURSTLEN 282 #define D64_USBBURSTLEN DMA_BL_64 283 #endif 284 #ifndef D64_SDIOBURSTLEN 285 #define D64_SDIOBURSTLEN DMA_BL_32 286 #endif 287 288 /* transmit channel control */ 289 #define D64_XC_XE 0x00000001 /**< transmit enable */ 290 #define D64_XC_SE 0x00000002 /**< transmit suspend request */ 291 #define D64_XC_LE 0x00000004 /**< loopback enable */ 292 #define D64_XC_FL 0x00000010 /**< flush request */ 293 #define D64_XC_MR_MASK 0x000001C0 /**< Multiple outstanding reads */ 294 #define D64_XC_MR_SHIFT 6 295 #define D64_XC_CS_SHIFT 9 /**< channel switch enable */ 296 #define D64_XC_CS_MASK 0x00000200 /**< channel switch enable */ 297 #define D64_XC_PD 0x00000800 /**< parity check disable */ 298 #define D64_XC_AE 0x00030000 /**< address extension bits */ 299 #define D64_XC_AE_SHIFT 16 300 #define D64_XC_BL_MASK 0x001C0000 /**< BurstLen bits */ 301 #define D64_XC_BL_SHIFT 18 302 #define D64_XC_PC_MASK 0x00E00000 /**< Prefetch control */ 303 #define D64_XC_PC_SHIFT 21 304 #define D64_XC_PT_MASK 0x03000000 /**< Prefetch threshold */ 305 #define D64_XC_PT_SHIFT 24 306 #define D64_XC_CO_MASK 0x04000000 /**< coherent transactions for descriptors */ 307 #define D64_XC_CO_SHIFT 26 308 309 /* transmit descriptor table pointer */ 310 #define D64_XP_LD_MASK 0x00001fff /**< last valid descriptor */ 311 312 /* transmit channel status */ 313 #define D64_XS0_CD_MASK (di->d64_xs0_cd_mask) /**< current descriptor pointer */ 314 #define D64_XS0_XS_MASK 0xf0000000 /**< transmit state */ 315 #define D64_XS0_XS_SHIFT 28 316 #define D64_XS0_XS_DISABLED 0x00000000 /**< disabled */ 317 #define D64_XS0_XS_ACTIVE 0x10000000 /**< active */ 318 #define D64_XS0_XS_IDLE 0x20000000 /**< idle wait */ 319 #define D64_XS0_XS_STOPPED 0x30000000 /**< stopped */ 320 #define D64_XS0_XS_SUSP 0x40000000 /**< suspend pending */ 321 322 #define D64_XS1_AD_MASK (di->d64_xs1_ad_mask) /**< active descriptor */ 323 #define D64_XS1_XE_MASK 0xf0000000 /**< transmit errors */ 324 #define D64_XS1_XE_SHIFT 28 325 #define D64_XS1_XE_NOERR 0x00000000 /**< no error */ 326 #define D64_XS1_XE_DPE 0x10000000 /**< descriptor protocol error */ 327 #define D64_XS1_XE_DFU 0x20000000 /**< data fifo underrun */ 328 #define D64_XS1_XE_DTE 0x30000000 /**< data transfer error */ 329 #define D64_XS1_XE_DESRE 0x40000000 /**< descriptor read error */ 330 #define D64_XS1_XE_COREE 0x50000000 /**< core error */ 331 332 /* receive channel control */ 333 #define D64_RC_RE 0x00000001 /**< receive enable */ 334 #define D64_RC_RO_MASK 0x000000fe /**< receive frame offset */ 335 #define D64_RC_RO_SHIFT 1 336 #define D64_RC_FM 0x00000100 /**< direct fifo receive (pio) mode */ 337 #define D64_RC_SH 0x00000200 /**< separate rx header descriptor enable */ 338 #define D64_RC_SHIFT 9 /**< separate rx header descriptor enable */ 339 #define D64_RC_OC 0x00000400 /**< overflow continue */ 340 #define D64_RC_PD 0x00000800 /**< parity check disable */ 341 #define D64_RC_WAITCMP_MASK 0x00001000 342 #define D64_RC_WAITCMP_SHIFT 12 343 #define D64_RC_SA 0x00002000 /**< select active */ 344 #define D64_RC_GE 0x00004000 /**< Glom enable */ 345 #define D64_RC_AE 0x00030000 /**< address extension bits */ 346 #define D64_RC_AE_SHIFT 16 347 #define D64_RC_BL_MASK 0x001C0000 /**< BurstLen bits */ 348 #define D64_RC_BL_SHIFT 18 349 #define D64_RC_PC_MASK 0x00E00000 /**< Prefetch control */ 350 #define D64_RC_PC_SHIFT 21 351 #define D64_RC_PT_MASK 0x03000000 /**< Prefetch threshold */ 352 #define D64_RC_PT_SHIFT 24 353 #define D64_RC_CO_MASK 0x04000000 /**< coherent transactions for descriptors */ 354 #define D64_RC_CO_SHIFT 26 355 #define D64_RC_ROEXT_MASK 0x08000000 /**< receive frame offset extension bit */ 356 #define D64_RC_ROEXT_SHIFT 27 357 #define D64_RC_MOW_SHIFT (28u) /**< multiple outstanding write */ 358 #define D64_RC_MOW_MASK ((0x3u) << D64_RC_MOW_SHIFT) 359 360 /* receive control values */ 361 /* RcvCtrl.MultipleOutstandingWrites(MOW) valid values(N) listed below. 362 * (N + 1) out standing write(s) supported 363 */ 364 #define D64_RC_MOW_1 (0u) /**< 1 outstanding write */ 365 #define D64_RC_MOW_2 (1u) /**< 2 outstanding writes */ 366 #define D64_RC_MOW_3 (2u) /**< 3 outstanding writes */ 367 #define D64_RC_MOW_4 (3u) /**< 4 outstanding writes */ 368 369 /* flags for dma controller */ 370 #define DMA_CTRL_PEN (1u << 0u) /**< partity enable */ 371 #define DMA_CTRL_ROC (1u << 1u) /**< rx overflow continue */ 372 #define DMA_CTRL_RXMULTI (1u << 2u) /**< allow rx scatter to multiple descriptors */ 373 #define DMA_CTRL_UNFRAMED (1u << 3u) /**< Unframed Rx/Tx data */ 374 #define DMA_CTRL_USB_BOUNDRY4KB_WAR (1u << 4u) /**< USB core REV9's SETUP dma channel's 375 * buffer can not crossed 4K boundary PR80468 376 */ 377 #define DMA_CTRL_DMA_AVOIDANCE_WAR (1u << 5u) /**< DMA avoidance WAR for 4331 */ 378 #define DMA_CTRL_RXSINGLE (1u << 6u) /**< always single buffer */ 379 #define DMA_CTRL_SDIO_RXGLOM (1u << 7u) /**< DMA Rx glome is enabled */ 380 #define DMA_CTRL_DESC_ONLY_FLAG (1u << 8u) /**< For DMA which posts only descriptors, 381 * no packets 382 */ 383 #define DMA_CTRL_DESC_CD_WAR (1u << 9u) /**< WAR for descriptor only DMA's CD not being 384 * updated correctly by HW in CT mode. 385 */ 386 #define DMA_CTRL_CS (1u << 10u) /* channel switch enable */ 387 #define DMA_CTRL_ROEXT (1u << 11u) /* receive frame offset extension support */ 388 #define DMA_CTRL_RX_ALIGN_8BYTE (1u << 12u) /* RXDMA address 8-byte aligned */ 389 #define DMA_CTRL_SHARED_POOL (1u << 15u) /** shared descriptor pool */ 390 #define DMA_CTRL_COREUNIT_SHIFT (17u) /* Core unit shift */ 391 #define DMA_CTRL_COREUNIT_MASK (0x3u << 17u) /* Core unit mask */ 392 393 #define DMA_CTRL_SET_COREUNIT(di, coreunit) \ 394 ((di)->hnddma.dmactrlflags |= \ 395 (((coreunit) << DMA_CTRL_COREUNIT_SHIFT) & DMA_CTRL_COREUNIT_MASK)) 396 397 #define DMA_CTRL_GET_COREUNIT(di) \ 398 (((di)->hnddma.dmactrlflags & DMA_CTRL_COREUNIT_MASK) >> DMA_CTRL_COREUNIT_SHIFT) 399 400 /* receive descriptor table pointer */ 401 #define D64_RP_LD_MASK 0x00001fff /**< last valid descriptor */ 402 403 /* receive channel status */ 404 #define D64_RS0_CD_MASK (di->d64_rs0_cd_mask) /**< current descriptor pointer */ 405 #define D64_RS0_RS_MASK 0xf0000000 /**< receive state */ 406 #define D64_RS0_RS_SHIFT 28 407 #define D64_RS0_RS_DISABLED 0x00000000 /**< disabled */ 408 #define D64_RS0_RS_ACTIVE 0x10000000 /**< active */ 409 #define D64_RS0_RS_IDLE 0x20000000 /**< idle wait */ 410 #define D64_RS0_RS_STOPPED 0x30000000 /**< stopped */ 411 #define D64_RS0_RS_SUSP 0x40000000 /**< suspend pending */ 412 413 #define D64_RS1_AD_MASK (di->d64_rs1_ad_mask) /* active descriptor pointer */ 414 #define D64_RS1_RE_MASK 0xf0000000 /* receive errors */ 415 #define D64_RS1_RE_SHIFT 28 416 #define D64_RS1_RE_NOERR 0x00000000 /**< no error */ 417 #define D64_RS1_RE_DPO 0x10000000 /**< descriptor protocol error */ 418 #define D64_RS1_RE_DFU 0x20000000 /**< data fifo overflow */ 419 #define D64_RS1_RE_DTE 0x30000000 /**< data transfer error */ 420 #define D64_RS1_RE_DESRE 0x40000000 /**< descriptor read error */ 421 #define D64_RS1_RE_COREE 0x50000000 /**< core error */ 422 423 /* fifoaddr */ 424 #define D64_FA_OFF_MASK 0xffff /**< offset */ 425 #define D64_FA_SEL_MASK 0xf0000 /**< select */ 426 #define D64_FA_SEL_SHIFT 16 427 #define D64_FA_SEL_XDD 0x00000 /**< transmit dma data */ 428 #define D64_FA_SEL_XDP 0x10000 /**< transmit dma pointers */ 429 #define D64_FA_SEL_RDD 0x40000 /**< receive dma data */ 430 #define D64_FA_SEL_RDP 0x50000 /**< receive dma pointers */ 431 #define D64_FA_SEL_XFD 0x80000 /**< transmit fifo data */ 432 #define D64_FA_SEL_XFP 0x90000 /**< transmit fifo pointers */ 433 #define D64_FA_SEL_RFD 0xc0000 /**< receive fifo data */ 434 #define D64_FA_SEL_RFP 0xd0000 /**< receive fifo pointers */ 435 #define D64_FA_SEL_RSD 0xe0000 /**< receive frame status data */ 436 #define D64_FA_SEL_RSP 0xf0000 /**< receive frame status pointers */ 437 438 /* descriptor control flags 1 */ 439 #define D64_CTRL_COREFLAGS 0x0ff00000 /**< core specific flags */ 440 441 /**< bzero operation for receive channels or a compare-to-zero operation for transmit engines */ 442 #define D64_CTRL1_BIT_BZEROBCMP (15u) 443 /* WAR for JIRA CRWLDMA-245 */ 444 #define D64_DMA_COREFLAGS_WAR_BIT (25u) 445 446 #define D64_CTRL1_COHERENT ((uint32)1 << 17) /**< cache coherent per transaction */ 447 #define D64_CTRL1_NOTPCIE ((uint32)1 << 18) /**< buirst size control */ 448 #define D64_CTRL1_EOT ((uint32)1 << 28) /**< end of descriptor table */ 449 #define D64_CTRL1_IOC ((uint32)1 << 29) /**< interrupt on completion */ 450 #define D64_CTRL1_EOF ((uint32)1 << 30) /**< end of frame */ 451 #define D64_CTRL1_SOF ((uint32)1 << 31) /**< start of frame */ 452 #define D64_CTRL1_SOFPTR 0x0000FFFFu 453 #define D64_CTRL1_NUMD_MASK 0x00F00000u 454 #define D64_CTRL1_NUMD_SHIFT 20u 455 456 /* descriptor control flags 2 */ 457 #define D64_CTRL2_MAX_LEN 0x0000fff7 /* Max transfer length (buffer byte count) <= 65527 */ 458 #define D64_CTRL2_BC_MASK 0x0000ffff /**< mask for buffer byte count */ 459 #define D64_CTRL2_AE 0x00030000 /**< address extension bits */ 460 #define D64_CTRL2_AE_SHIFT 16 461 #define D64_CTRL2_PARITY 0x00040000 /* parity bit */ 462 463 /** control flags in the range [27:20] are core-specific and not defined here */ 464 #define D64_CTRL_CORE_MASK 0x0ff00000 465 466 #define D64_RX_FRM_STS_LEN 0x0000ffff /**< frame length mask */ 467 #define D64_RX_FRM_STS_OVFL 0x00800000 /**< RxOverFlow */ 468 #define D64_RX_FRM_STS_DSCRCNT 0x0f000000 /**< no. of descriptors used - 1, d11corerev >= 22 */ 469 #define D64_RX_FRM_STS_DSCRCNT_SHIFT 24 /* Shift for no .of dma descriptor field */ 470 #define D64_RX_FRM_STS_DATATYPE 0xf0000000 /**< core-dependent data type */ 471 472 #define BCM_D64_CTRL2_BOUND_DMA_LENGTH(len) \ 473 (((len) > D64_CTRL2_MAX_LEN) ? D64_CTRL2_MAX_LEN : (len)) 474 475 /** receive frame status */ 476 typedef volatile struct { 477 uint16 len; 478 uint16 flags; 479 } dma_rxh_t; 480 481 #endif /* _sbhnddma_h_ */ 482