1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * HND SiliconBackplane PMU support. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2020, Broadcom. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Unless you and Broadcom execute a separate written software license 7*4882a593Smuzhiyun * agreement governing use of this software, this software is licensed to you 8*4882a593Smuzhiyun * under the terms of the GNU General Public License version 2 (the "GPL"), 9*4882a593Smuzhiyun * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10*4882a593Smuzhiyun * following added to such license: 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * As a special exception, the copyright holders of this software give you 13*4882a593Smuzhiyun * permission to link this software with independent modules, and to copy and 14*4882a593Smuzhiyun * distribute the resulting executable under terms of your choice, provided that 15*4882a593Smuzhiyun * you also meet, for each linked independent module, the terms and conditions of 16*4882a593Smuzhiyun * the license of that module. An independent module is a module which is not 17*4882a593Smuzhiyun * derived from this software. The special exception does not apply to any 18*4882a593Smuzhiyun * modifications of the software. 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * <<Broadcom-WL-IPTag/Dual:>> 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #ifndef _hndlhl_h_ 25*4882a593Smuzhiyun #define _hndlhl_h_ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun enum { 28*4882a593Smuzhiyun LHL_MAC_TIMER = 0, 29*4882a593Smuzhiyun LHL_ARM_TIMER = 1 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun typedef struct { 33*4882a593Smuzhiyun uint16 offset; 34*4882a593Smuzhiyun uint32 mask; 35*4882a593Smuzhiyun uint32 val; 36*4882a593Smuzhiyun } lhl_reg_set_t; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define LHL_REG_OFF(reg) OFFSETOF(gciregs_t, reg) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun extern void si_lhl_timer_config(si_t *sih, osl_t *osh, int timer_type); 41*4882a593Smuzhiyun extern void si_lhl_timer_enable(si_t *sih); 42*4882a593Smuzhiyun extern void si_lhl_timer_reset(si_t *sih, uint coreid, uint coreunit); 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun extern void si_lhl_setup(si_t *sih, osl_t *osh); 45*4882a593Smuzhiyun extern void si_lhl_enable(si_t *sih, osl_t *osh, bool enable); 46*4882a593Smuzhiyun extern void si_lhl_ilp_config(si_t *sih, osl_t *osh, uint32 ilp_period); 47*4882a593Smuzhiyun extern void si_lhl_enable_sdio_wakeup(si_t *sih, osl_t *osh); 48*4882a593Smuzhiyun extern void si_lhl_disable_sdio_wakeup(si_t *sih); 49*4882a593Smuzhiyun extern int si_lhl_set_lpoclk(si_t *sih, osl_t *osh, uint32 lpo_force); 50*4882a593Smuzhiyun extern void si_set_lv_sleep_mode_lhl_config_4369(si_t *sih); 51*4882a593Smuzhiyun extern void si_set_lv_sleep_mode_lhl_config_4362(si_t *sih); 52*4882a593Smuzhiyun extern void si_set_lv_sleep_mode_lhl_config_4378(si_t *sih); 53*4882a593Smuzhiyun extern void si_set_lv_sleep_mode_lhl_config_4387(si_t *sih); 54*4882a593Smuzhiyun extern void si_set_lv_sleep_mode_lhl_config_4389(si_t *sih); 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define HIB_EXT_WAKEUP_CAP(sih) (PMUREV(sih->pmurev) >= 33) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #ifdef WL_FWSIGN 59*4882a593Smuzhiyun #define LHL_IS_PSMODE_0(sih) (1) 60*4882a593Smuzhiyun #define LHL_IS_PSMODE_1(sih) (0) 61*4882a593Smuzhiyun #else 62*4882a593Smuzhiyun #define LHL_IS_PSMODE_0(sih) (si_lhl_ps_mode(sih) == LHL_PS_MODE_0) 63*4882a593Smuzhiyun #define LHL_IS_PSMODE_1(sih) (si_lhl_ps_mode(sih) == LHL_PS_MODE_1) 64*4882a593Smuzhiyun #endif /* WL_FWSIGN */ 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* LHL revid in capabilities register */ 67*4882a593Smuzhiyun #define LHL_CAP_REV_MASK 0x000000ff 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* LHL rev 6 requires this bit to be set first */ 70*4882a593Smuzhiyun #define LHL_PWRSEQCTL_WL_FLLPU_EN (1 << 7) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define LHL_CBUCK_VOLT_SLEEP_SHIFT 12u 73*4882a593Smuzhiyun #define LHL_CBUCK_VOLT_SLEEP_MASK 0x0000F000 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define LHL_ABUCK_VOLT_SLEEP_SHIFT 0u 76*4882a593Smuzhiyun #define LHL_ABUCK_VOLT_SLEEP_MASK 0x0000000F 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun extern void si_lhl_mactim0_set(si_t *sih, uint32 val); 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* LHL Chip Control 1 Register */ 81*4882a593Smuzhiyun #define LHL_1MHZ_FLL_DAC_EXT_SHIFT (9u) 82*4882a593Smuzhiyun #define LHL_1MHZ_FLL_DAC_EXT_MASK (0xffu << 9u) 83*4882a593Smuzhiyun #define LHL_1MHZ_FLL_PRELOAD_MASK (1u << 17u) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* LHL Top Level Power Sequence Control Register */ 86*4882a593Smuzhiyun #define LHL_TOP_PWRSEQ_SLEEP_ENAB_MASK (1u << 0) 87*4882a593Smuzhiyun #define LHL_TOP_PWRSEQ_TOP_ISO_EN_MASK (1u << 3u) 88*4882a593Smuzhiyun #define LHL_TOP_PWRSEQ_TOP_SLB_EN_MASK (1u << 4u) 89*4882a593Smuzhiyun #define LHL_TOP_PWRSEQ_TOP_PWRSW_EN_MASK (1u << 5u) 90*4882a593Smuzhiyun #define LHL_TOP_PWRSEQ_MISCLDO_PU_EN_MASK (1u << 6u) 91*4882a593Smuzhiyun #define LHL_TOP_PWRSEQ_SERDES_SLB_EN_MASK (1u << 9u) 92*4882a593Smuzhiyun #define LHL_TOP_PWRSEQ_SERDES_CLK_DIS_EN_MASK (1u << 10u) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #endif /* _hndlhl_h_ */ 95