1 /* 2 * Extended Trap data component interface file. 3 * 4 * Copyright (C) 2020, Broadcom. 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * 21 * <<Broadcom-WL-IPTag/Dual:>> 22 */ 23 24 #ifndef _ETD_H_ 25 #define _ETD_H_ 26 27 #if defined(ETD) && !defined(WLETD) 28 #include <hnd_trap.h> 29 #endif 30 #include <bcmutils.h> 31 /* Tags for structures being used by etd info iovar. 32 * Related structures are defined in wlioctl.h. 33 */ 34 #define ETD_TAG_JOIN_CLASSIFICATION_INFO 10 /* general information about join request */ 35 #define ETD_TAG_JOIN_TARGET_CLASSIFICATION_INFO 11 /* per target (AP) join information */ 36 #define ETD_TAG_ASSOC_STATE 12 /* current state of the Device association state machine */ 37 #define ETD_TAG_CHANNEL 13 /* current channel on which the association was performed */ 38 #define ETD_TAG_TOTAL_NUM_OF_JOIN_ATTEMPTS 14 /* number of join attempts (bss_retries) */ 39 40 #define PSMDBG_REG_READ_CNT_FOR_PSMWDTRAP_V1 3 41 #define PSMDBG_REG_READ_CNT_FOR_PSMWDTRAP_V2 6 42 43 #ifndef _LANGUAGE_ASSEMBLY 44 45 #define HND_EXTENDED_TRAP_VERSION 1 46 #define HND_EXTENDED_TRAP_BUFLEN 512 47 48 typedef struct hnd_ext_trap_hdr { 49 uint8 version; /* Extended trap version info */ 50 uint8 reserved; /* currently unused */ 51 uint16 len; /* Length of data excluding this header */ 52 uint8 data[]; /* TLV data */ 53 } hnd_ext_trap_hdr_t; 54 55 typedef enum { 56 TAG_TRAP_NONE = 0u, /* None trap type */ 57 TAG_TRAP_SIGNATURE = 1u, /* Processor register dumps */ 58 TAG_TRAP_STACK = 2u, /* Processor stack dump (possible code locations) */ 59 TAG_TRAP_MEMORY = 3u, /* Memory subsystem dump */ 60 TAG_TRAP_DEEPSLEEP = 4u, /* Deep sleep health check failures */ 61 TAG_TRAP_PSM_WD = 5u, /* PSM watchdog information */ 62 TAG_TRAP_PHY = 6u, /* Phy related issues */ 63 TAG_TRAP_BUS = 7u, /* Bus level issues */ 64 TAG_TRAP_MAC_SUSP = 8u, /* Mac level suspend issues */ 65 TAG_TRAP_BACKPLANE = 9u, /* Backplane related errors */ 66 /* Values 10 through 14 are in use by etd_data info iovar */ 67 TAG_TRAP_PCIE_Q = 15u, /* PCIE Queue state during memory trap */ 68 TAG_TRAP_WLC_STATE = 16u, /* WLAN state during memory trap */ 69 TAG_TRAP_MAC_WAKE = 17u, /* Mac level wake issues */ 70 TAG_TRAP_PHYTXERR_THRESH = 18u, /* Phy Tx Err */ 71 TAG_TRAP_HC_DATA = 19u, /* Data collected by HC module */ 72 TAG_TRAP_LOG_DATA = 20u, 73 TAG_TRAP_CODE = 21u, /* The trap type */ 74 TAG_TRAP_HMAP = 22u, /* HMAP violation Address and Info */ 75 TAG_TRAP_PCIE_ERR_ATTN = 23u, /* PCIE error attn log */ 76 TAG_TRAP_AXI_ERROR = 24u, /* AXI Error */ 77 TAG_TRAP_AXI_HOST_INFO = 25u, /* AXI Host log */ 78 TAG_TRAP_AXI_SR_ERROR = 26u, /* AXI SR error log */ 79 TAG_TRAP_MEM_BIT_FLIP = 27u, /* Memory 1-Bit Flip error */ 80 TAG_TRAP_LAST /* This must be the last entry */ 81 } hnd_ext_tag_trap_t; 82 83 typedef struct hnd_ext_trap_bp_err 84 { 85 uint32 error; 86 uint32 coreid; 87 uint32 baseaddr; 88 uint32 ioctrl; 89 uint32 iostatus; 90 uint32 resetctrl; 91 uint32 resetstatus; 92 uint32 resetreadid; 93 uint32 resetwriteid; 94 uint32 errlogctrl; 95 uint32 errlogdone; 96 uint32 errlogstatus; 97 uint32 errlogaddrlo; 98 uint32 errlogaddrhi; 99 uint32 errlogid; 100 uint32 errloguser; 101 uint32 errlogflags; 102 uint32 itipoobaout; 103 uint32 itipoobbout; 104 uint32 itipoobcout; 105 uint32 itipoobdout; 106 } hnd_ext_trap_bp_err_t; 107 108 #define HND_EXT_TRAP_AXISR_INFO_VER_1 1 109 typedef struct hnd_ext_trap_axi_sr_err_v1 110 { 111 uint8 version; 112 uint8 pad[3]; 113 uint32 error; 114 uint32 coreid; 115 uint32 baseaddr; 116 uint32 ioctrl; 117 uint32 iostatus; 118 uint32 resetctrl; 119 uint32 resetstatus; 120 uint32 resetreadid; 121 uint32 resetwriteid; 122 uint32 errlogctrl; 123 uint32 errlogdone; 124 uint32 errlogstatus; 125 uint32 errlogaddrlo; 126 uint32 errlogaddrhi; 127 uint32 errlogid; 128 uint32 errloguser; 129 uint32 errlogflags; 130 uint32 itipoobaout; 131 uint32 itipoobbout; 132 uint32 itipoobcout; 133 uint32 itipoobdout; 134 135 /* axi_sr_issue_debug */ 136 uint32 sr_pwr_control; 137 uint32 sr_corereset_wrapper_main; 138 uint32 sr_corereset_wrapper_aux; 139 uint32 sr_main_gci_status_0; 140 uint32 sr_aux_gci_status_0; 141 uint32 sr_dig_gci_status_0; 142 } hnd_ext_trap_axi_sr_err_v1_t; 143 144 #define HND_EXT_TRAP_PSMWD_INFO_VER 1 145 typedef struct hnd_ext_trap_psmwd_v1 { 146 uint16 xtag; 147 uint16 version; /* version of the information following this */ 148 uint32 i32_maccontrol; 149 uint32 i32_maccommand; 150 uint32 i32_macintstatus; 151 uint32 i32_phydebug; 152 uint32 i32_clk_ctl_st; 153 uint32 i32_psmdebug[PSMDBG_REG_READ_CNT_FOR_PSMWDTRAP_V1]; 154 uint16 i16_0x1a8; /* gated clock en */ 155 uint16 i16_0x406; /* Rcv Fifo Ctrl */ 156 uint16 i16_0x408; /* Rx ctrl 1 */ 157 uint16 i16_0x41a; /* Rxe Status 1 */ 158 uint16 i16_0x41c; /* Rxe Status 2 */ 159 uint16 i16_0x424; /* rcv wrd count 0 */ 160 uint16 i16_0x426; /* rcv wrd count 1 */ 161 uint16 i16_0x456; /* RCV_LFIFO_STS */ 162 uint16 i16_0x480; /* PSM_SLP_TMR */ 163 uint16 i16_0x490; /* PSM BRC */ 164 uint16 i16_0x500; /* TXE CTRL */ 165 uint16 i16_0x50e; /* TXE Status */ 166 uint16 i16_0x55e; /* TXE_xmtdmabusy */ 167 uint16 i16_0x566; /* TXE_XMTfifosuspflush */ 168 uint16 i16_0x690; /* IFS Stat */ 169 uint16 i16_0x692; /* IFS_MEDBUSY_CTR */ 170 uint16 i16_0x694; /* IFS_TX_DUR */ 171 uint16 i16_0x6a0; /* SLow_CTL */ 172 uint16 i16_0x838; /* TXE_AQM fifo Ready */ 173 uint16 i16_0x8c0; /* Dagg ctrl */ 174 uint16 shm_prewds_cnt; 175 uint16 shm_txtplufl_cnt; 176 uint16 shm_txphyerr_cnt; 177 uint16 pad; 178 } hnd_ext_trap_psmwd_v1_t; 179 180 typedef struct hnd_ext_trap_psmwd { 181 uint16 xtag; 182 uint16 version; /* version of the information following this */ 183 uint32 i32_maccontrol; 184 uint32 i32_maccommand; 185 uint32 i32_macintstatus; 186 uint32 i32_phydebug; 187 uint32 i32_clk_ctl_st; 188 uint32 i32_psmdebug[PSMDBG_REG_READ_CNT_FOR_PSMWDTRAP_V2]; 189 uint16 i16_0x4b8; /* psm_brwk_0 */ 190 uint16 i16_0x4ba; /* psm_brwk_1 */ 191 uint16 i16_0x4bc; /* psm_brwk_2 */ 192 uint16 i16_0x4be; /* psm_brwk_2 */ 193 uint16 i16_0x1a8; /* gated clock en */ 194 uint16 i16_0x406; /* Rcv Fifo Ctrl */ 195 uint16 i16_0x408; /* Rx ctrl 1 */ 196 uint16 i16_0x41a; /* Rxe Status 1 */ 197 uint16 i16_0x41c; /* Rxe Status 2 */ 198 uint16 i16_0x424; /* rcv wrd count 0 */ 199 uint16 i16_0x426; /* rcv wrd count 1 */ 200 uint16 i16_0x456; /* RCV_LFIFO_STS */ 201 uint16 i16_0x480; /* PSM_SLP_TMR */ 202 uint16 i16_0x500; /* TXE CTRL */ 203 uint16 i16_0x50e; /* TXE Status */ 204 uint16 i16_0x55e; /* TXE_xmtdmabusy */ 205 uint16 i16_0x566; /* TXE_XMTfifosuspflush */ 206 uint16 i16_0x690; /* IFS Stat */ 207 uint16 i16_0x692; /* IFS_MEDBUSY_CTR */ 208 uint16 i16_0x694; /* IFS_TX_DUR */ 209 uint16 i16_0x6a0; /* SLow_CTL */ 210 uint16 i16_0x490; /* psm_brc */ 211 uint16 i16_0x4da; /* psm_brc_1 */ 212 uint16 i16_0x838; /* TXE_AQM fifo Ready */ 213 uint16 i16_0x8c0; /* Dagg ctrl */ 214 uint16 shm_prewds_cnt; 215 uint16 shm_txtplufl_cnt; 216 uint16 shm_txphyerr_cnt; 217 } hnd_ext_trap_psmwd_t; 218 219 #define HEAP_HISTOGRAM_DUMP_LEN 6 220 #define HEAP_MAX_SZ_BLKS_LEN 2 221 222 /* Ignore chunks for which there are fewer than this many instances, irrespective of size */ 223 #define HEAP_HISTOGRAM_INSTANCE_MIN 4 224 225 /* 226 * Use the last two length values for chunks larger than this, or when we run out of 227 * histogram entries (because we have too many different sized chunks) to store "other" 228 */ 229 #define HEAP_HISTOGRAM_SPECIAL 0xfffeu 230 231 #define HEAP_HISTOGRAM_GRTR256K 0xffffu 232 233 typedef struct hnd_ext_trap_heap_err { 234 uint32 arena_total; 235 uint32 heap_free; 236 uint32 heap_inuse; 237 uint32 mf_count; 238 uint32 stack_lwm; 239 uint16 heap_histogm[HEAP_HISTOGRAM_DUMP_LEN * 2]; /* size/number */ 240 uint16 max_sz_free_blk[HEAP_MAX_SZ_BLKS_LEN]; 241 } hnd_ext_trap_heap_err_t; 242 243 #define MEM_TRAP_NUM_WLC_TX_QUEUES 6 244 #define HND_EXT_TRAP_WLC_MEM_ERR_VER_V2 2 245 246 /* already there are quite a few chips which are ROM'ed wth this structure 247 * Will not be adding version. This will be the V1 structure. 248 */ 249 typedef struct hnd_ext_trap_wlc_mem_err { 250 uint8 instance; 251 uint8 associated; 252 uint8 soft_ap_client_cnt; 253 uint8 peer_cnt; 254 uint16 txqueue_len[MEM_TRAP_NUM_WLC_TX_QUEUES]; 255 } hnd_ext_trap_wlc_mem_err_t; 256 257 typedef struct hnd_ext_trap_wlc_mem_err_v2 { 258 uint16 version; 259 uint16 pad; 260 uint8 instance; 261 uint8 stas_associated; 262 uint8 aps_associated; 263 uint8 soft_ap_client_cnt; 264 uint16 txqueue_len[MEM_TRAP_NUM_WLC_TX_QUEUES]; 265 } hnd_ext_trap_wlc_mem_err_v2_t; 266 267 #define HND_EXT_TRAP_WLC_MEM_ERR_VER_V3 3 268 269 typedef struct hnd_ext_trap_wlc_mem_err_v3 { 270 uint8 version; 271 uint8 instance; 272 uint8 stas_associated; 273 uint8 aps_associated; 274 uint8 soft_ap_client_cnt; 275 uint8 peer_cnt; 276 uint16 txqueue_len[MEM_TRAP_NUM_WLC_TX_QUEUES]; 277 } hnd_ext_trap_wlc_mem_err_v3_t; 278 279 typedef struct hnd_ext_trap_pcie_mem_err { 280 uint16 d2h_queue_len; 281 uint16 d2h_req_queue_len; 282 } hnd_ext_trap_pcie_mem_err_t; 283 284 #define MAX_DMAFIFO_ENTRIES_V1 1 285 #define MAX_DMAFIFO_DESC_ENTRIES_V1 2 286 #define HND_EXT_TRAP_AXIERROR_SIGNATURE 0xbabebabe 287 #define HND_EXT_TRAP_AXIERROR_VERSION_1 1 288 289 /* Structure to collect debug info of descriptor entry for dma channel on encountering AXI Error */ 290 /* Below three structures are dependant, any change will bump version of all the three */ 291 292 typedef struct hnd_ext_trap_desc_entry_v1 { 293 uint32 ctrl1; /* descriptor entry at din < misc control bits > */ 294 uint32 ctrl2; /* descriptor entry at din <buffer count and address extension> */ 295 uint32 addrlo; /* descriptor entry at din <address of data buffer, bits 31:0> */ 296 uint32 addrhi; /* descriptor entry at din <address of data buffer, bits 63:32> */ 297 } dma_dentry_v1_t; 298 299 /* Structure to collect debug info about a dma channel on encountering AXI Error */ 300 typedef struct hnd_ext_trap_dma_fifo_v1 { 301 uint8 valid; /* no of valid desc entries filled, non zero = fifo entry valid */ 302 uint8 direction; /* TX=1, RX=2, currently only using TX */ 303 uint16 index; /* Index of the DMA channel in system */ 304 uint32 dpa; /* Expected Address of Descriptor table from software state */ 305 uint32 desc_lo; /* Low Address of Descriptor table programmed in DMA register */ 306 uint32 desc_hi; /* High Address of Descriptor table programmed in DMA register */ 307 uint16 din; /* rxin / txin */ 308 uint16 dout; /* rxout / txout */ 309 dma_dentry_v1_t dentry[MAX_DMAFIFO_DESC_ENTRIES_V1]; /* Descriptor Entires */ 310 } dma_fifo_v1_t; 311 312 typedef struct hnd_ext_trap_axi_error_v1 { 313 uint8 version; /* version = 1 */ 314 uint8 dma_fifo_valid_count; /* Number of valid dma_fifo entries */ 315 uint16 length; /* length of whole structure */ 316 uint32 signature; /* indicate that its filled with AXI Error data */ 317 uint32 axi_errorlog_status; /* errlog_status from slave wrapper */ 318 uint32 axi_errorlog_core; /* errlog_core from slave wrapper */ 319 uint32 axi_errorlog_lo; /* errlog_lo from slave wrapper */ 320 uint32 axi_errorlog_hi; /* errlog_hi from slave wrapper */ 321 uint32 axi_errorlog_id; /* errlog_id from slave wrapper */ 322 dma_fifo_v1_t dma_fifo[MAX_DMAFIFO_ENTRIES_V1]; 323 } hnd_ext_trap_axi_error_v1_t; 324 325 #define HND_EXT_TRAP_MACSUSP_INFO_VER 1 326 typedef struct hnd_ext_trap_macsusp { 327 uint16 xtag; 328 uint8 version; /* version of the information following this */ 329 uint8 trap_reason; 330 uint32 i32_maccontrol; 331 uint32 i32_maccommand; 332 uint32 i32_macintstatus; 333 uint32 i32_phydebug[4]; 334 uint32 i32_psmdebug[8]; 335 uint16 i16_0x41a; /* Rxe Status 1 */ 336 uint16 i16_0x41c; /* Rxe Status 2 */ 337 uint16 i16_0x490; /* PSM BRC */ 338 uint16 i16_0x50e; /* TXE Status */ 339 uint16 i16_0x55e; /* TXE_xmtdmabusy */ 340 uint16 i16_0x566; /* TXE_XMTfifosuspflush */ 341 uint16 i16_0x690; /* IFS Stat */ 342 uint16 i16_0x692; /* IFS_MEDBUSY_CTR */ 343 uint16 i16_0x694; /* IFS_TX_DUR */ 344 uint16 i16_0x7c0; /* WEP CTL */ 345 uint16 i16_0x838; /* TXE_AQM fifo Ready */ 346 uint16 i16_0x880; /* MHP_status */ 347 uint16 shm_prewds_cnt; 348 uint16 shm_ucode_dbgst; 349 } hnd_ext_trap_macsusp_t; 350 351 #define HND_EXT_TRAP_MACENAB_INFO_VER 1 352 typedef struct hnd_ext_trap_macenab { 353 uint16 xtag; 354 uint8 version; /* version of the information following this */ 355 uint8 trap_reason; 356 uint32 i32_maccontrol; 357 uint32 i32_maccommand; 358 uint32 i32_macintstatus; 359 uint32 i32_psmdebug[8]; 360 uint32 i32_clk_ctl_st; 361 uint32 i32_powerctl; 362 uint16 i16_0x1a8; /* gated clock en */ 363 uint16 i16_0x480; /* PSM_SLP_TMR */ 364 uint16 i16_0x490; /* PSM BRC */ 365 uint16 i16_0x600; /* TSF CTL */ 366 uint16 i16_0x690; /* IFS Stat */ 367 uint16 i16_0x692; /* IFS_MEDBUSY_CTR */ 368 uint16 i16_0x6a0; /* SLow_CTL */ 369 uint16 i16_0x6a6; /* SLow_FRAC */ 370 uint16 i16_0x6a8; /* fast power up delay */ 371 uint16 i16_0x6aa; /* SLow_PER */ 372 uint16 shm_ucode_dbgst; 373 uint16 PAD; 374 } hnd_ext_trap_macenab_t; 375 376 #define HND_EXT_TRAP_PHY_INFO_VER_1 (1) 377 typedef struct hnd_ext_trap_phydbg { 378 uint16 err; 379 uint16 RxFeStatus; 380 uint16 TxFIFOStatus0; 381 uint16 TxFIFOStatus1; 382 uint16 RfseqMode; 383 uint16 RfseqStatus0; 384 uint16 RfseqStatus1; 385 uint16 RfseqStatus_Ocl; 386 uint16 RfseqStatus_Ocl1; 387 uint16 OCLControl1; 388 uint16 TxError; 389 uint16 bphyTxError; 390 uint16 TxCCKError; 391 uint16 TxCtrlWrd0; 392 uint16 TxCtrlWrd1; 393 uint16 TxCtrlWrd2; 394 uint16 TxLsig0; 395 uint16 TxLsig1; 396 uint16 TxVhtSigA10; 397 uint16 TxVhtSigA11; 398 uint16 TxVhtSigA20; 399 uint16 TxVhtSigA21; 400 uint16 txPktLength; 401 uint16 txPsdulengthCtr; 402 uint16 gpioClkControl; 403 uint16 gpioSel; 404 uint16 pktprocdebug; 405 uint16 PAD; 406 uint32 gpioOut[3]; 407 } hnd_ext_trap_phydbg_t; 408 409 /* unique IDs for separate cores in SI */ 410 #define REGDUMP_MASK_MAC0 BCM_BIT(1) 411 #define REGDUMP_MASK_ARM BCM_BIT(2) 412 #define REGDUMP_MASK_PCIE BCM_BIT(3) 413 #define REGDUMP_MASK_MAC1 BCM_BIT(4) 414 #define REGDUMP_MASK_PMU BCM_BIT(5) 415 416 typedef struct { 417 uint16 reg_offset; 418 uint16 core_mask; 419 } reg_dump_config_t; 420 421 #define HND_EXT_TRAP_PHY_INFO_VER 2 422 typedef struct hnd_ext_trap_phydbg_v2 { 423 uint8 version; 424 uint8 len; 425 uint16 err; 426 uint16 RxFeStatus; 427 uint16 TxFIFOStatus0; 428 uint16 TxFIFOStatus1; 429 uint16 RfseqMode; 430 uint16 RfseqStatus0; 431 uint16 RfseqStatus1; 432 uint16 RfseqStatus_Ocl; 433 uint16 RfseqStatus_Ocl1; 434 uint16 OCLControl1; 435 uint16 TxError; 436 uint16 bphyTxError; 437 uint16 TxCCKError; 438 uint16 TxCtrlWrd0; 439 uint16 TxCtrlWrd1; 440 uint16 TxCtrlWrd2; 441 uint16 TxLsig0; 442 uint16 TxLsig1; 443 uint16 TxVhtSigA10; 444 uint16 TxVhtSigA11; 445 uint16 TxVhtSigA20; 446 uint16 TxVhtSigA21; 447 uint16 txPktLength; 448 uint16 txPsdulengthCtr; 449 uint16 gpioClkControl; 450 uint16 gpioSel; 451 uint16 pktprocdebug; 452 uint32 gpioOut[3]; 453 uint32 additional_regs[1]; 454 } hnd_ext_trap_phydbg_v2_t; 455 456 #define HND_EXT_TRAP_PHY_INFO_VER_3 (3) 457 typedef struct hnd_ext_trap_phydbg_v3 { 458 uint8 version; 459 uint8 len; 460 uint16 err; 461 uint16 RxFeStatus; 462 uint16 TxFIFOStatus0; 463 uint16 TxFIFOStatus1; 464 uint16 RfseqMode; 465 uint16 RfseqStatus0; 466 uint16 RfseqStatus1; 467 uint16 RfseqStatus_Ocl; 468 uint16 RfseqStatus_Ocl1; 469 uint16 OCLControl1; 470 uint16 TxError; 471 uint16 bphyTxError; 472 uint16 TxCCKError; 473 uint16 TxCtrlWrd0; 474 uint16 TxCtrlWrd1; 475 uint16 TxCtrlWrd2; 476 uint16 TxLsig0; 477 uint16 TxLsig1; 478 uint16 TxVhtSigA10; 479 uint16 TxVhtSigA11; 480 uint16 TxVhtSigA20; 481 uint16 TxVhtSigA21; 482 uint16 txPktLength; 483 uint16 txPsdulengthCtr; 484 uint16 gpioClkControl; 485 uint16 gpioSel; 486 uint16 pktprocdebug; 487 uint32 gpioOut[3]; 488 uint16 HESigURateFlagStatus; 489 uint16 HESigUsRateFlagStatus; 490 uint32 additional_regs[1]; 491 } hnd_ext_trap_phydbg_v3_t; 492 493 /* Phy TxErr Dump Structure */ 494 #define HND_EXT_TRAP_PHYTXERR_INFO_VER 1 495 #define HND_EXT_TRAP_PHYTXERR_INFO_VER_V2 2 496 typedef struct hnd_ext_trap_macphytxerr { 497 uint8 version; /* version of the information following this */ 498 uint8 trap_reason; 499 uint16 i16_0x63E; /* tsf_tmr_rx_ts */ 500 uint16 i16_0x640; /* tsf_tmr_tx_ts */ 501 uint16 i16_0x642; /* tsf_tmr_rx_end_ts */ 502 uint16 i16_0x846; /* TDC_FrmLen0 */ 503 uint16 i16_0x848; /* TDC_FrmLen1 */ 504 uint16 i16_0x84a; /* TDC_Txtime */ 505 uint16 i16_0xa5a; /* TXE_BytCntInTxFrmLo */ 506 uint16 i16_0xa5c; /* TXE_BytCntInTxFrmHi */ 507 uint16 i16_0x856; /* TDC_VhtPsduLen0 */ 508 uint16 i16_0x858; /* TDC_VhtPsduLen1 */ 509 uint16 i16_0x490; /* psm_brc */ 510 uint16 i16_0x4d8; /* psm_brc_1 */ 511 uint16 shm_txerr_reason; 512 uint16 shm_pctl0; 513 uint16 shm_pctl1; 514 uint16 shm_pctl2; 515 uint16 shm_lsig0; 516 uint16 shm_lsig1; 517 uint16 shm_plcp0; 518 uint16 shm_plcp1; 519 uint16 shm_plcp2; 520 uint16 shm_vht_sigb0; 521 uint16 shm_vht_sigb1; 522 uint16 shm_tx_tst; 523 uint16 shm_txerr_tm; 524 uint16 shm_curchannel; 525 uint16 shm_crx_rxtsf_pos; 526 uint16 shm_lasttx_tsf; 527 uint16 shm_s_rxtsftmrval; 528 uint16 i16_0x29; /* Phy indirect address */ 529 uint16 i16_0x2a; /* Phy indirect address */ 530 } hnd_ext_trap_macphytxerr_t; 531 532 typedef struct hnd_ext_trap_macphytxerr_v2 { 533 uint8 version; /* version of the information following this */ 534 uint8 trap_reason; 535 uint16 i16_0x63E; /* tsf_tmr_rx_ts */ 536 uint16 i16_0x640; /* tsf_tmr_tx_ts */ 537 uint16 i16_0x642; /* tsf_tmr_rx_end_ts */ 538 uint16 i16_0x846; /* TDC_FrmLen0 */ 539 uint16 i16_0x848; /* TDC_FrmLen1 */ 540 uint16 i16_0x84a; /* TDC_Txtime */ 541 uint16 i16_0xa5a; /* TXE_BytCntInTxFrmLo */ 542 uint16 i16_0xa5c; /* TXE_BytCntInTxFrmHi */ 543 uint16 i16_0x856; /* TDC_VhtPsduLen0 */ 544 uint16 i16_0x858; /* TDC_VhtPsduLen1 */ 545 uint16 i16_0x490; /* psm_brc */ 546 uint16 i16_0x4d8; /* psm_brc_1 */ 547 uint16 shm_txerr_reason; 548 uint16 shm_pctl0; 549 uint16 shm_pctl1; 550 uint16 shm_pctl2; 551 uint16 shm_lsig0; 552 uint16 shm_lsig1; 553 uint16 shm_plcp0; 554 uint16 shm_plcp1; 555 uint16 shm_plcp2; 556 uint16 shm_vht_sigb0; 557 uint16 shm_vht_sigb1; 558 uint16 shm_tx_tst; 559 uint16 shm_txerr_tm; 560 uint16 shm_curchannel; 561 uint16 shm_crx_rxtsf_pos; 562 uint16 shm_lasttx_tsf; 563 uint16 shm_s_rxtsftmrval; 564 uint16 i16_0x29; /* Phy indirect address */ 565 uint16 i16_0x2a; /* Phy indirect address */ 566 uint8 phyerr_bmac_cnt; /* number of times bmac raised phy tx err */ 567 uint8 phyerr_bmac_rsn; /* bmac reason for phy tx error */ 568 uint16 pad; 569 uint32 recv_fifo_status[3][2]; /* Rcv Status0 & Rcv Status1 for 3 Rx fifos */ 570 } hnd_ext_trap_macphytxerr_v2_t; 571 572 #define HND_EXT_TRAP_PCIE_ERR_ATTN_VER_1 (1u) 573 #define MAX_AER_HDR_LOG_REGS (4u) 574 typedef struct hnd_ext_trap_pcie_err_attn_v1 { 575 uint8 version; 576 uint8 pad[3]; 577 uint32 err_hdr_logreg1; 578 uint32 err_hdr_logreg2; 579 uint32 err_hdr_logreg3; 580 uint32 err_hdr_logreg4; 581 uint32 err_code_logreg; 582 uint32 err_type; 583 uint32 err_code_state; 584 uint32 last_err_attn_ts; 585 uint32 cfg_tlp_hdr[MAX_AER_HDR_LOG_REGS]; 586 } hnd_ext_trap_pcie_err_attn_v1_t; 587 588 #define MAX_EVENTLOG_BUFFERS 48 589 typedef struct eventlog_trapdata_info { 590 uint32 num_elements; 591 uint32 seq_num; 592 uint32 log_arr_addr; 593 } eventlog_trapdata_info_t; 594 595 typedef struct eventlog_trap_buf_info { 596 uint32 len; 597 uint32 buf_addr; 598 } eventlog_trap_buf_info_t; 599 600 #define HND_MEM_HC_FB_MEM_VER_1 (1u) 601 typedef struct hnd_ext_trap_fb_mem_err { 602 uint16 version; 603 uint16 reserved; 604 uint32 flip_bit_err_time; 605 } hnd_ext_trap_fb_mem_err_t; 606 607 #if defined(ETD) && !defined(WLETD) 608 #define ETD_SW_FLAG_MEM 0x00000001 609 610 int etd_init(osl_t *osh); 611 int etd_register_trap_ext_callback(void *cb, void *arg); 612 int (etd_register_trap_ext_callback_late)(void *cb, void *arg); 613 uint32 *etd_get_trap_ext_data(void); 614 uint32 etd_get_trap_ext_swflags(void); 615 void etd_set_trap_ext_swflag(uint32 flag); 616 void etd_notify_trap_ext_callback(trap_t *tr); 617 reg_dump_config_t *etd_get_reg_dump_config_tbl(void); 618 uint etd_get_reg_dump_config_len(void); 619 620 extern bool _etd_enab; 621 622 #if defined(ROM_ENAB_RUNTIME_CHECK) 623 #define ETD_ENAB(pub) (_etd_enab) 624 #elif defined(ETD_DISABLED) 625 #define ETD_ENAB(pub) (0) 626 #else 627 #define ETD_ENAB(pub) (1) 628 #endif 629 630 #else 631 #define ETD_ENAB(pub) (0) 632 #endif /* WLETD */ 633 634 #endif /* !LANGUAGE_ASSEMBLY */ 635 636 #endif /* _ETD_H_ */ 637