1 /* 2 * Table that encodes the srom formats for PCI/PCIe NICs. 3 * 4 * Copyright (C) 2020, Broadcom. 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * 21 * <<Broadcom-WL-IPTag/Dual:>> 22 */ 23 24 #ifndef _bcmsrom_tbl_h_ 25 #define _bcmsrom_tbl_h_ 26 27 #include <sbpcmcia.h> 28 #include <bcmsrom_fmt.h> 29 30 typedef struct { 31 const char *name; 32 uint32 revmask; 33 uint32 flags; 34 uint16 off; 35 uint16 mask; 36 } sromvar_t; 37 38 #define SRFL_MORE 1 /* value continues as described by the next entry */ 39 #define SRFL_NOFFS 2 /* value bits can't be all one's */ 40 #define SRFL_PRHEX 4 /* value is in hexdecimal format */ 41 #define SRFL_PRSIGN 8 /* value is in signed decimal format */ 42 #define SRFL_CCODE 0x10 /* value is in country code format */ 43 #define SRFL_ETHADDR 0x20 /* value is an Ethernet address */ 44 #define SRFL_UNUSED 0x40 /* unused, was SRFL_LEDDC */ 45 #define SRFL_NOVAR 0x80 /* do not generate a nvram param, entry is for mfgc */ 46 #define SRFL_ARRAY 0x100 /* value is in an array. All elements EXCEPT FOR THE LAST 47 * ONE in the array should have this flag set. 48 */ 49 #define PRHEX_N_MORE (SRFL_PRHEX | SRFL_MORE) 50 51 #define SROM_DEVID_PCIE 48 52 53 /** 54 * Assumptions: 55 * - Ethernet address spans across 3 consecutive words 56 * 57 * Table rules: 58 * - Add multiple entries next to each other if a value spans across multiple words 59 * (even multiple fields in the same word) with each entry except the last having 60 * it's SRFL_MORE bit set. 61 * - Ethernet address entry does not follow above rule and must not have SRFL_MORE 62 * bit set. Its SRFL_ETHADDR bit implies it takes multiple words. 63 * - The last entry's name field must be NULL to indicate the end of the table. Other 64 * entries must have non-NULL name. 65 */ 66 #if !defined(SROM15_MEMOPT) 67 static const sromvar_t BCMATTACHDATA(pci_sromvars)[] = { 68 /* name revmask flags off mask */ 69 #if defined(BCMPCIEDEV) && defined(BCMPCIEDEV_ENABLED) 70 {"devid", 0xffffff00, SRFL_PRHEX, SROM_DEVID_PCIE, 0xffff}, 71 #else 72 {"devid", 0xffffff00, SRFL_PRHEX|SRFL_NOVAR, PCI_F0DEVID, 0xffff}, 73 #endif /* BCMPCIEDEV && BCMPCIEDEV_ENABLED */ 74 {"boardrev", 0x0000000e, SRFL_PRHEX, SROM_AABREV, SROM_BR_MASK}, 75 {"boardrev", 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff}, 76 {"boardrev", 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff}, 77 {"boardflags", 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff}, 78 {"boardflags", 0x00000004, SRFL_PRHEX|SRFL_MORE, SROM_BFL, 0xffff}, 79 {"", 0, 0, SROM_BFL2, 0xffff}, 80 {"boardflags", 0x00000008, SRFL_PRHEX|SRFL_MORE, SROM_BFL, 0xffff}, 81 {"", 0, 0, SROM3_BFL2, 0xffff}, 82 {"boardflags", 0x00000010, SRFL_PRHEX|SRFL_MORE, SROM4_BFL0, 0xffff}, 83 {"", 0, 0, SROM4_BFL1, 0xffff}, 84 {"boardflags", 0x000000e0, SRFL_PRHEX|SRFL_MORE, SROM5_BFL0, 0xffff}, 85 {"", 0, 0, SROM5_BFL1, 0xffff}, 86 {"boardflags", 0xffffff00, SRFL_PRHEX|SRFL_MORE, SROM8_BFL0, 0xffff}, 87 {"", 0, 0, SROM8_BFL1, 0xffff}, 88 {"boardflags2", 0x00000010, SRFL_PRHEX|SRFL_MORE, SROM4_BFL2, 0xffff}, 89 {"", 0, 0, SROM4_BFL3, 0xffff}, 90 {"boardflags2", 0x000000e0, SRFL_PRHEX|SRFL_MORE, SROM5_BFL2, 0xffff}, 91 {"", 0, 0, SROM5_BFL3, 0xffff}, 92 {"boardflags2", 0xffffff00, SRFL_PRHEX|SRFL_MORE, SROM8_BFL2, 0xffff}, 93 {"", 0, 0, SROM8_BFL3, 0xffff}, 94 {"boardtype", 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff}, 95 {"subvid", 0xfffffffc, SRFL_PRHEX, SROM_SVID, 0xffff}, 96 {"boardnum", 0x00000006, 0, SROM_MACLO_IL0, 0xffff}, 97 {"boardnum", 0x00000008, 0, SROM3_MACLO, 0xffff}, 98 {"boardnum", 0x00000010, 0, SROM4_MACLO, 0xffff}, 99 {"boardnum", 0x000000e0, 0, SROM5_MACLO, 0xffff}, 100 {"boardnum", 0x00000700, 0, SROM8_MACLO, 0xffff}, 101 {"cc", 0x00000002, 0, SROM_AABREV, SROM_CC_MASK}, 102 {"regrev", 0x00000008, 0, SROM_OPO, 0xff00}, 103 {"regrev", 0x00000010, 0, SROM4_REGREV, 0xffff}, 104 {"regrev", 0x000000e0, 0, SROM5_REGREV, 0xffff}, 105 {"regrev", 0x00000700, 0, SROM8_REGREV, 0xffff}, 106 {"pa0b0", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff}, 107 {"pa0b1", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff}, 108 {"pa0b2", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff}, 109 {"pa0itssit", 0x0000000e, 0, SROM_ITT, 0x00ff}, 110 {"pa0maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0x00ff}, 111 {"pa0b0", 0x00000700, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff}, 112 {"pa0b1", 0x00000700, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff}, 113 {"pa0b2", 0x00000700, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff}, 114 {"pa0itssit", 0x00000700, 0, SROM8_W0_ITTMAXP, 0xff00}, 115 {"pa0maxpwr", 0x00000700, 0, SROM8_W0_ITTMAXP, 0x00ff}, 116 {"opo", 0x0000000c, 0, SROM_OPO, 0x00ff}, 117 {"opo", 0x00000700, 0, SROM8_2G_OFDMPO, 0x00ff}, 118 {"aa2g", 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK}, 119 {"aa2g", 0x000000f0, 0, SROM4_AA, 0x00ff}, 120 {"aa2g", 0x00000700, 0, SROM8_AA, 0x00ff}, 121 {"aa5g", 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK}, 122 {"aa5g", 0x000000f0, 0, SROM4_AA, 0xff00}, 123 {"aa5g", 0x00000700, 0, SROM8_AA, 0xff00}, 124 {"ag0", 0x0000000e, 0, SROM_AG10, 0x00ff}, 125 {"ag1", 0x0000000e, 0, SROM_AG10, 0xff00}, 126 {"ag0", 0x000000f0, 0, SROM4_AG10, 0x00ff}, 127 {"ag1", 0x000000f0, 0, SROM4_AG10, 0xff00}, 128 {"ag2", 0x000000f0, 0, SROM4_AG32, 0x00ff}, 129 {"ag3", 0x000000f0, 0, SROM4_AG32, 0xff00}, 130 {"ag0", 0x00000700, 0, SROM8_AG10, 0x00ff}, 131 {"ag1", 0x00000700, 0, SROM8_AG10, 0xff00}, 132 {"ag2", 0x00000700, 0, SROM8_AG32, 0x00ff}, 133 {"ag3", 0x00000700, 0, SROM8_AG32, 0xff00}, 134 {"pa1b0", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff}, 135 {"pa1b1", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff}, 136 {"pa1b2", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff}, 137 {"pa1lob0", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff}, 138 {"pa1lob1", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff}, 139 {"pa1lob2", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff}, 140 {"pa1hib0", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff}, 141 {"pa1hib1", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff}, 142 {"pa1hib2", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff}, 143 {"pa1itssit", 0x0000000e, 0, SROM_ITT, 0xff00}, 144 {"pa1maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0xff00}, 145 {"pa1lomaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00}, 146 {"pa1himaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff}, 147 {"pa1b0", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff}, 148 {"pa1b1", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff}, 149 {"pa1b2", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff}, 150 {"pa1lob0", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff}, 151 {"pa1lob1", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff}, 152 {"pa1lob2", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff}, 153 {"pa1hib0", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff}, 154 {"pa1hib1", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff}, 155 {"pa1hib2", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff}, 156 {"pa1itssit", 0x00000700, 0, SROM8_W1_ITTMAXP, 0xff00}, 157 {"pa1maxpwr", 0x00000700, 0, SROM8_W1_ITTMAXP, 0x00ff}, 158 {"pa1lomaxpwr", 0x00000700, 0, SROM8_W1_MAXP_LCHC, 0xff00}, 159 {"pa1himaxpwr", 0x00000700, 0, SROM8_W1_MAXP_LCHC, 0x00ff}, 160 {"bxa2g", 0x00000008, 0, SROM_BXARSSI2G, 0x1800}, 161 {"rssisav2g", 0x00000008, 0, SROM_BXARSSI2G, 0x0700}, 162 {"rssismc2g", 0x00000008, 0, SROM_BXARSSI2G, 0x00f0}, 163 {"rssismf2g", 0x00000008, 0, SROM_BXARSSI2G, 0x000f}, 164 {"bxa2g", 0x00000700, 0, SROM8_BXARSSI2G, 0x1800}, 165 {"rssisav2g", 0x00000700, 0, SROM8_BXARSSI2G, 0x0700}, 166 {"rssismc2g", 0x00000700, 0, SROM8_BXARSSI2G, 0x00f0}, 167 {"rssismf2g", 0x00000700, 0, SROM8_BXARSSI2G, 0x000f}, 168 {"bxa5g", 0x00000008, 0, SROM_BXARSSI5G, 0x1800}, 169 {"rssisav5g", 0x00000008, 0, SROM_BXARSSI5G, 0x0700}, 170 {"rssismc5g", 0x00000008, 0, SROM_BXARSSI5G, 0x00f0}, 171 {"rssismf5g", 0x00000008, 0, SROM_BXARSSI5G, 0x000f}, 172 {"bxa5g", 0x00000700, 0, SROM8_BXARSSI5G, 0x1800}, 173 {"rssisav5g", 0x00000700, 0, SROM8_BXARSSI5G, 0x0700}, 174 {"rssismc5g", 0x00000700, 0, SROM8_BXARSSI5G, 0x00f0}, 175 {"rssismf5g", 0x00000700, 0, SROM8_BXARSSI5G, 0x000f}, 176 {"tri2g", 0x00000008, 0, SROM_TRI52G, 0x00ff}, 177 {"tri5g", 0x00000008, 0, SROM_TRI52G, 0xff00}, 178 {"tri5gl", 0x00000008, 0, SROM_TRI5GHL, 0x00ff}, 179 {"tri5gh", 0x00000008, 0, SROM_TRI5GHL, 0xff00}, 180 {"tri2g", 0x00000700, 0, SROM8_TRI52G, 0x00ff}, 181 {"tri5g", 0x00000700, 0, SROM8_TRI52G, 0xff00}, 182 {"tri5gl", 0x00000700, 0, SROM8_TRI5GHL, 0x00ff}, 183 {"tri5gh", 0x00000700, 0, SROM8_TRI5GHL, 0xff00}, 184 {"rxpo2g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff}, 185 {"rxpo5g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00}, 186 {"rxpo2g", 0x00000700, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff}, 187 {"rxpo5g", 0x00000700, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00}, 188 {"txchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_TXCHAIN_MASK}, 189 {"rxchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_RXCHAIN_MASK}, 190 {"antswitch", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_SWITCH_MASK}, 191 {"txchain", 0x00000700, SRFL_NOFFS, SROM8_TXRXC, SROM4_TXCHAIN_MASK}, 192 {"rxchain", 0x00000700, SRFL_NOFFS, SROM8_TXRXC, SROM4_RXCHAIN_MASK}, 193 {"antswitch", 0x00000700, SRFL_NOFFS, SROM8_TXRXC, SROM4_SWITCH_MASK}, 194 {"tssipos2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_TSSIPOS_MASK}, 195 {"extpagain2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_EXTPA_GAIN_MASK}, 196 {"pdetrange2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_PDET_RANGE_MASK}, 197 {"triso2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK}, 198 {"antswctl2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_ANTSWLUT_MASK}, 199 {"tssipos5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_TSSIPOS_MASK}, 200 {"extpagain5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_EXTPA_GAIN_MASK}, 201 {"pdetrange5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_PDET_RANGE_MASK}, 202 {"triso5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK}, 203 {"antswctl5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_ANTSWLUT_MASK}, 204 {"txpid2ga0", 0x000000f0, 0, SROM4_TXPID2G, 0x00ff}, 205 {"txpid2ga1", 0x000000f0, 0, SROM4_TXPID2G, 0xff00}, 206 {"txpid2ga2", 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff}, 207 {"txpid2ga3", 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00}, 208 {"txpid5ga0", 0x000000f0, 0, SROM4_TXPID5G, 0x00ff}, 209 {"txpid5ga1", 0x000000f0, 0, SROM4_TXPID5G, 0xff00}, 210 {"txpid5ga2", 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff}, 211 {"txpid5ga3", 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00}, 212 {"txpid5gla0", 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff}, 213 {"txpid5gla1", 0x000000f0, 0, SROM4_TXPID5GL, 0xff00}, 214 {"txpid5gla2", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff}, 215 {"txpid5gla3", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00}, 216 {"txpid5gha0", 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff}, 217 {"txpid5gha1", 0x000000f0, 0, SROM4_TXPID5GH, 0xff00}, 218 {"txpid5gha2", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff}, 219 {"txpid5gha3", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00}, 220 221 {"ccode", 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff}, 222 {"ccode", 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff}, 223 {"ccode", 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff}, 224 {"ccode", 0x00000700, SRFL_CCODE, SROM8_CCODE, 0xffff}, 225 {"macaddr", 0x00000700, SRFL_ETHADDR, SROM8_MACHI, 0xffff}, 226 {"macaddr", 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff}, 227 {"macaddr", 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff}, 228 {"macaddr", 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff}, 229 {"il0macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0, 0xffff}, 230 {"et1macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1, 0xffff}, 231 232 {"tempthresh", 0x00000700, 0, SROM8_THERMAL, 0xff00}, 233 {"tempoffset", 0x00000700, 0, SROM8_THERMAL, 0x00ff}, 234 {"rawtempsense", 0x00000700, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0x01ff}, 235 {"measpower", 0x00000700, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0xfe00}, 236 {"tempsense_slope", 0x00000700, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0x00ff}, 237 {"tempcorrx", 0x00000700, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0xfc00}, 238 {"tempsense_option", 0x00000700, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0x0300}, 239 {"freqoffset_corr", 0x00000700, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x000f}, 240 {"iqcal_swp_dis", 0x00000700, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0010}, 241 {"hw_iqcal_en", 0x00000700, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0020}, 242 {"elna2g", 0x00000700, 0, SROM8_EXTLNAGAIN, 0x00ff}, 243 {"elna5g", 0x00000700, 0, SROM8_EXTLNAGAIN, 0xff00}, 244 {"phycal_tempdelta", 0x00000700, 0, SROM8_PHYCAL_TEMPDELTA, 0x00ff}, 245 {"temps_period", 0x00000700, 0, SROM8_PHYCAL_TEMPDELTA, 0x0f00}, 246 {"temps_hysteresis", 0x00000700, 0, SROM8_PHYCAL_TEMPDELTA, 0xf000}, 247 {"measpower1", 0x00000700, SRFL_PRHEX, SROM8_MPWR_1_AND_2, 0x007f}, 248 {"measpower2", 0x00000700, SRFL_PRHEX, SROM8_MPWR_1_AND_2, 0x3f80}, 249 250 {"cck2gpo", 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff}, 251 {"cck2gpo", 0x00000100, 0, SROM8_2G_CCKPO, 0xffff}, 252 {"ofdm2gpo", 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff}, 253 {"", 0, 0, SROM4_2G_OFDMPO + 1, 0xffff}, 254 {"ofdm5gpo", 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff}, 255 {"", 0, 0, SROM4_5G_OFDMPO + 1, 0xffff}, 256 {"ofdm5glpo", 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff}, 257 {"", 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff}, 258 {"ofdm5ghpo", 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff}, 259 {"", 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff}, 260 {"ofdm2gpo", 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff}, 261 {"", 0, 0, SROM8_2G_OFDMPO + 1, 0xffff}, 262 {"ofdm5gpo", 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff}, 263 {"", 0, 0, SROM8_5G_OFDMPO + 1, 0xffff}, 264 {"ofdm5glpo", 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff}, 265 {"", 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff}, 266 {"ofdm5ghpo", 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff}, 267 {"", 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff}, 268 {"mcs2gpo0", 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff}, 269 {"mcs2gpo1", 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff}, 270 {"mcs2gpo2", 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff}, 271 {"mcs2gpo3", 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff}, 272 {"mcs2gpo4", 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff}, 273 {"mcs2gpo5", 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff}, 274 {"mcs2gpo6", 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff}, 275 {"mcs2gpo7", 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff}, 276 {"mcs5gpo0", 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff}, 277 {"mcs5gpo1", 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff}, 278 {"mcs5gpo2", 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff}, 279 {"mcs5gpo3", 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff}, 280 {"mcs5gpo4", 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff}, 281 {"mcs5gpo5", 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff}, 282 {"mcs5gpo6", 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff}, 283 {"mcs5gpo7", 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff}, 284 {"mcs5glpo0", 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff}, 285 {"mcs5glpo1", 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff}, 286 {"mcs5glpo2", 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff}, 287 {"mcs5glpo3", 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff}, 288 {"mcs5glpo4", 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff}, 289 {"mcs5glpo5", 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff}, 290 {"mcs5glpo6", 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff}, 291 {"mcs5glpo7", 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff}, 292 {"mcs5ghpo0", 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff}, 293 {"mcs5ghpo1", 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff}, 294 {"mcs5ghpo2", 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff}, 295 {"mcs5ghpo3", 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff}, 296 {"mcs5ghpo4", 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff}, 297 {"mcs5ghpo5", 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff}, 298 {"mcs5ghpo6", 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff}, 299 {"mcs5ghpo7", 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff}, 300 {"mcs2gpo0", 0x00000100, 0, SROM8_2G_MCSPO, 0xffff}, 301 {"mcs2gpo1", 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff}, 302 {"mcs2gpo2", 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff}, 303 {"mcs2gpo3", 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff}, 304 {"mcs2gpo4", 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff}, 305 {"mcs2gpo5", 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff}, 306 {"mcs2gpo6", 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff}, 307 {"mcs2gpo7", 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff}, 308 {"mcs5gpo0", 0x00000100, 0, SROM8_5G_MCSPO, 0xffff}, 309 {"mcs5gpo1", 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff}, 310 {"mcs5gpo2", 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff}, 311 {"mcs5gpo3", 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff}, 312 {"mcs5gpo4", 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff}, 313 {"mcs5gpo5", 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff}, 314 {"mcs5gpo6", 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff}, 315 {"mcs5gpo7", 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff}, 316 {"mcs5glpo0", 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff}, 317 {"mcs5glpo1", 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff}, 318 {"mcs5glpo2", 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff}, 319 {"mcs5glpo3", 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff}, 320 {"mcs5glpo4", 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff}, 321 {"mcs5glpo5", 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff}, 322 {"mcs5glpo6", 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff}, 323 {"mcs5glpo7", 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff}, 324 {"mcs5ghpo0", 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff}, 325 {"mcs5ghpo1", 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff}, 326 {"mcs5ghpo2", 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff}, 327 {"mcs5ghpo3", 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff}, 328 {"mcs5ghpo4", 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff}, 329 {"mcs5ghpo5", 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff}, 330 {"mcs5ghpo6", 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff}, 331 {"mcs5ghpo7", 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff}, 332 {"cddpo", 0x000000f0, 0, SROM4_CDDPO, 0xffff}, 333 {"stbcpo", 0x000000f0, 0, SROM4_STBCPO, 0xffff}, 334 {"bw40po", 0x000000f0, 0, SROM4_BW40PO, 0xffff}, 335 {"bwduppo", 0x000000f0, 0, SROM4_BWDUPPO, 0xffff}, 336 {"cddpo", 0x00000100, 0, SROM8_CDDPO, 0xffff}, 337 {"stbcpo", 0x00000100, 0, SROM8_STBCPO, 0xffff}, 338 {"bw40po", 0x00000100, 0, SROM8_BW40PO, 0xffff}, 339 {"bwduppo", 0x00000100, 0, SROM8_BWDUPPO, 0xffff}, 340 341 /* power per rate from sromrev 9 */ 342 {"cckbw202gpo", 0x00000600, 0, SROM9_2GPO_CCKBW20, 0xffff}, 343 {"cckbw20ul2gpo", 0x00000600, 0, SROM9_2GPO_CCKBW20UL, 0xffff}, 344 {"legofdmbw202gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_LOFDMBW20, 0xffff}, 345 {"", 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff}, 346 {"legofdmbw20ul2gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_LOFDMBW20UL, 0xffff}, 347 {"", 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff}, 348 {"legofdmbw205glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_LOFDMBW20, 0xffff}, 349 {"", 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff}, 350 {"legofdmbw20ul5glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_LOFDMBW20UL, 0xffff}, 351 {"", 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff}, 352 {"legofdmbw205gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_LOFDMBW20, 0xffff}, 353 {"", 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff}, 354 {"legofdmbw20ul5gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_LOFDMBW20UL, 0xffff}, 355 {"", 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff}, 356 {"legofdmbw205ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_LOFDMBW20, 0xffff}, 357 {"", 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff}, 358 {"legofdmbw20ul5ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_LOFDMBW20UL, 0xffff}, 359 {"", 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff}, 360 {"mcsbw202gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_MCSBW20, 0xffff}, 361 {"", 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff}, 362 {"mcsbw20ul2gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_MCSBW20UL, 0xffff}, 363 {"", 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff}, 364 {"mcsbw402gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_MCSBW40, 0xffff}, 365 {"", 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff}, 366 {"mcsbw205glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_MCSBW20, 0xffff}, 367 {"", 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff}, 368 {"mcsbw20ul5glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_MCSBW20UL, 0xffff}, 369 {"", 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff}, 370 {"mcsbw405glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_MCSBW40, 0xffff}, 371 {"", 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff}, 372 {"mcsbw205gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_MCSBW20, 0xffff}, 373 {"", 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff}, 374 {"mcsbw20ul5gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_MCSBW20UL, 0xffff}, 375 {"", 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff}, 376 {"mcsbw405gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_MCSBW40, 0xffff}, 377 {"", 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff}, 378 {"mcsbw205ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_MCSBW20, 0xffff}, 379 {"", 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff}, 380 {"mcsbw20ul5ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_MCSBW20UL, 0xffff}, 381 {"", 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff}, 382 {"mcsbw405ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_MCSBW40, 0xffff}, 383 {"", 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff}, 384 {"mcs32po", 0x00000600, 0, SROM9_PO_MCS32, 0xffff}, 385 {"legofdm40duppo", 0x00000600, 0, SROM9_PO_LOFDM40DUP, 0xffff}, 386 {"pcieingress_war", 0x00000700, 0, SROM8_PCIEINGRESS_WAR, 0xf}, 387 {"eu_edthresh2g", 0x00000100, 0, SROM8_EU_EDCRSTH, 0x00ff}, 388 {"eu_edthresh5g", 0x00000100, 0, SROM8_EU_EDCRSTH, 0xff00}, 389 {"eu_edthresh2g", 0x00000200, 0, SROM9_EU_EDCRSTH, 0x00ff}, 390 {"eu_edthresh5g", 0x00000200, 0, SROM9_EU_EDCRSTH, 0xff00}, 391 {"rxgainerr2ga0", 0x00000700, 0, SROM8_RXGAINERR_2G, 0x003f}, 392 {"rxgainerr2ga0", 0x00000700, 0, SROM8_RXGAINERR_2G, 0x003f}, 393 {"rxgainerr2ga1", 0x00000700, 0, SROM8_RXGAINERR_2G, 0x07c0}, 394 {"rxgainerr2ga2", 0x00000700, 0, SROM8_RXGAINERR_2G, 0xf800}, 395 {"rxgainerr5gla0", 0x00000700, 0, SROM8_RXGAINERR_5GL, 0x003f}, 396 {"rxgainerr5gla1", 0x00000700, 0, SROM8_RXGAINERR_5GL, 0x07c0}, 397 {"rxgainerr5gla2", 0x00000700, 0, SROM8_RXGAINERR_5GL, 0xf800}, 398 {"rxgainerr5gma0", 0x00000700, 0, SROM8_RXGAINERR_5GM, 0x003f}, 399 {"rxgainerr5gma1", 0x00000700, 0, SROM8_RXGAINERR_5GM, 0x07c0}, 400 {"rxgainerr5gma2", 0x00000700, 0, SROM8_RXGAINERR_5GM, 0xf800}, 401 {"rxgainerr5gha0", 0x00000700, 0, SROM8_RXGAINERR_5GH, 0x003f}, 402 {"rxgainerr5gha1", 0x00000700, 0, SROM8_RXGAINERR_5GH, 0x07c0}, 403 {"rxgainerr5gha2", 0x00000700, 0, SROM8_RXGAINERR_5GH, 0xf800}, 404 {"rxgainerr5gua0", 0x00000700, 0, SROM8_RXGAINERR_5GU, 0x003f}, 405 {"rxgainerr5gua1", 0x00000700, 0, SROM8_RXGAINERR_5GU, 0x07c0}, 406 {"rxgainerr5gua2", 0x00000700, 0, SROM8_RXGAINERR_5GU, 0xf800}, 407 {"sar2g", 0x00000600, 0, SROM9_SAR, 0x00ff}, 408 {"sar5g", 0x00000600, 0, SROM9_SAR, 0xff00}, 409 {"noiselvl2ga0", 0x00000700, 0, SROM8_NOISELVL_2G, 0x001f}, 410 {"noiselvl2ga1", 0x00000700, 0, SROM8_NOISELVL_2G, 0x03e0}, 411 {"noiselvl2ga2", 0x00000700, 0, SROM8_NOISELVL_2G, 0x7c00}, 412 {"noiselvl5gla0", 0x00000700, 0, SROM8_NOISELVL_5GL, 0x001f}, 413 {"noiselvl5gla1", 0x00000700, 0, SROM8_NOISELVL_5GL, 0x03e0}, 414 {"noiselvl5gla2", 0x00000700, 0, SROM8_NOISELVL_5GL, 0x7c00}, 415 {"noiselvl5gma0", 0x00000700, 0, SROM8_NOISELVL_5GM, 0x001f}, 416 {"noiselvl5gma1", 0x00000700, 0, SROM8_NOISELVL_5GM, 0x03e0}, 417 {"noiselvl5gma2", 0x00000700, 0, SROM8_NOISELVL_5GM, 0x7c00}, 418 {"noiselvl5gha0", 0x00000700, 0, SROM8_NOISELVL_5GH, 0x001f}, 419 {"noiselvl5gha1", 0x00000700, 0, SROM8_NOISELVL_5GH, 0x03e0}, 420 {"noiselvl5gha2", 0x00000700, 0, SROM8_NOISELVL_5GH, 0x7c00}, 421 {"noiselvl5gua0", 0x00000700, 0, SROM8_NOISELVL_5GU, 0x001f}, 422 {"noiselvl5gua1", 0x00000700, 0, SROM8_NOISELVL_5GU, 0x03e0}, 423 {"noiselvl5gua2", 0x00000700, 0, SROM8_NOISELVL_5GU, 0x7c00}, 424 {"noisecaloffset", 0x00000300, 0, SROM8_NOISECALOFFSET, 0x00ff}, 425 {"noisecaloffset5g", 0x00000300, 0, SROM8_NOISECALOFFSET, 0xff00}, 426 {"subband5gver", 0x00000700, 0, SROM8_SUBBAND_PPR, 0x7}, 427 428 {"cckPwrOffset", 0x00000400, 0, SROM10_CCKPWROFFSET, 0xffff}, 429 {"eu_edthresh2g", 0x00000400, 0, SROM10_EU_EDCRSTH, 0x00ff}, 430 {"eu_edthresh5g", 0x00000400, 0, SROM10_EU_EDCRSTH, 0xff00}, 431 /* swctrlmap_2g array, note that the last element doesn't have SRFL_ARRAY flag set */ 432 {"swctrlmap_2g", 0x00000400, SRFL_MORE|SRFL_PRHEX|SRFL_ARRAY, SROM10_SWCTRLMAP_2G, 0xffff}, 433 {"", 0x00000400, SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 1, 0xffff}, 434 {"", 0x00000400, SRFL_MORE|SRFL_PRHEX|SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 2, 0xffff}, 435 {"", 0x00000400, SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 3, 0xffff}, 436 {"", 0x00000400, SRFL_MORE|SRFL_PRHEX|SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 4, 0xffff}, 437 {"", 0x00000400, SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 5, 0xffff}, 438 {"", 0x00000400, SRFL_MORE|SRFL_PRHEX|SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 6, 0xffff}, 439 {"", 0x00000400, SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 7, 0xffff}, 440 {"", 0x00000400, SRFL_PRHEX, SROM10_SWCTRLMAP_2G + 8, 0xffff}, 441 442 /* sromrev 11 */ 443 {"boardflags3", 0xfffff800, SRFL_PRHEX|SRFL_MORE, SROM11_BFL4, 0xffff}, 444 {"", 0, 0, SROM11_BFL5, 0xffff}, 445 {"boardnum", 0xfffff800, 0, SROM11_MACLO, 0xffff}, 446 {"macaddr", 0xfffff800, SRFL_ETHADDR, SROM11_MACHI, 0xffff}, 447 {"ccode", 0xfffff800, SRFL_CCODE, SROM11_CCODE, 0xffff}, 448 {"regrev", 0xfffff800, 0, SROM11_REGREV, 0xffff}, 449 {"aa2g", 0xfffff800, 0, SROM11_AA, 0x00ff}, 450 {"aa5g", 0xfffff800, 0, SROM11_AA, 0xff00}, 451 {"agbg0", 0xfffff800, 0, SROM11_AGBG10, 0xff00}, 452 {"agbg1", 0xfffff800, 0, SROM11_AGBG10, 0x00ff}, 453 {"agbg2", 0xfffff800, 0, SROM11_AGBG2A0, 0xff00}, 454 {"aga0", 0xfffff800, 0, SROM11_AGBG2A0, 0x00ff}, 455 {"aga1", 0xfffff800, 0, SROM11_AGA21, 0xff00}, 456 {"aga2", 0xfffff800, 0, SROM11_AGA21, 0x00ff}, 457 {"txchain", 0xfffff800, SRFL_NOFFS, SROM11_TXRXC, SROM4_TXCHAIN_MASK}, 458 {"rxchain", 0xfffff800, SRFL_NOFFS, SROM11_TXRXC, SROM4_RXCHAIN_MASK}, 459 {"antswitch", 0xfffff800, SRFL_NOFFS, SROM11_TXRXC, SROM4_SWITCH_MASK}, 460 461 {"tssiposslope2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x0001}, 462 {"epagain2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x000e}, 463 {"pdgain2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x01f0}, 464 {"tworangetssi2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x0200}, 465 {"papdcap2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x0400}, 466 {"femctrl", 0xfffff800, 0, SROM11_FEM_CFG1, 0xf800}, 467 468 {"tssiposslope5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x0001}, 469 {"epagain5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x000e}, 470 {"pdgain5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x01f0}, 471 {"tworangetssi5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x0200}, 472 {"papdcap5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x0400}, 473 {"gainctrlsph", 0xfffff800, 0, SROM11_FEM_CFG2, 0xf800}, 474 475 {"tempthresh", 0xfffff800, 0, SROM11_THERMAL, 0xff00}, 476 {"tempoffset", 0xfffff800, 0, SROM11_THERMAL, 0x00ff}, 477 {"rawtempsense", 0xfffff800, SRFL_PRHEX, SROM11_MPWR_RAWTS, 0x01ff}, 478 {"measpower", 0xfffff800, SRFL_PRHEX, SROM11_MPWR_RAWTS, 0xfe00}, 479 {"tempsense_slope", 0xfffff800, SRFL_PRHEX, SROM11_TS_SLP_OPT_CORRX, 0x00ff}, 480 {"tempcorrx", 0xfffff800, SRFL_PRHEX, SROM11_TS_SLP_OPT_CORRX, 0xfc00}, 481 {"tempsense_option", 0xfffff800, SRFL_PRHEX, SROM11_TS_SLP_OPT_CORRX, 0x0300}, 482 {"xtalfreq", 0xfffff800, 0, SROM11_XTAL_FREQ, 0xffff}, 483 {"txpwrbckof", 0x00000800, SRFL_PRHEX, SROM11_PATH0 + SROM11_2G_MAXP, 0xff00}, 484 /* Special PA Params for 4350 5G Band, 40/80 MHz BW Ant #1 */ 485 {"pa5gbw4080a1", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_4080_W0_A1, 0xffff}, 486 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_4080_W1_A1, 0xffff}, 487 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_4080_W2_A1, 0xffff}, 488 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_4080_W0_A1, 0xffff}, 489 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_4080_PA, 0xffff}, 490 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_4080_PA + 1, 0xffff}, 491 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_4080_PA, 0xffff}, 492 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_4080_PA + 1, 0xffff}, 493 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_4080_PA + 2, 0xffff}, 494 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_4080_PA, 0xffff}, 495 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_4080_PA + 1, 0xffff}, 496 {"", 0xfffff800, SRFL_PRHEX, SROM11_PATH2 + SROM11_5GB3_4080_PA + 2, 0xffff}, 497 {"phycal_tempdelta", 0xfffff800, 0, SROM11_PHYCAL_TEMPDELTA, 0x00ff}, 498 {"temps_period", 0xfffff800, 0, SROM11_PHYCAL_TEMPDELTA, 0x0f00}, 499 {"temps_hysteresis", 0xfffff800, 0, SROM11_PHYCAL_TEMPDELTA, 0xf000}, 500 {"measpower1", 0xfffff800, SRFL_PRHEX, SROM11_MPWR_1_AND_2, 0x007f}, 501 {"measpower2", 0xfffff800, SRFL_PRHEX, SROM11_MPWR_1_AND_2, 0x3f80}, 502 {"tssifloor2g", 0xfffff800, SRFL_PRHEX, SROM11_TSSIFLOOR_2G, 0x03ff}, 503 {"tssifloor5g", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_TSSIFLOOR_5GL, 0x03ff}, 504 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_TSSIFLOOR_5GM, 0x03ff}, 505 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_TSSIFLOOR_5GH, 0x03ff}, 506 {"", 0xfffff800, SRFL_PRHEX, SROM11_TSSIFLOOR_5GU, 0x03ff}, 507 {"pdoffset2g40ma0", 0xfffff800, 0, SROM11_PDOFF_2G_40M, 0x000f}, 508 {"pdoffset2g40ma1", 0xfffff800, 0, SROM11_PDOFF_2G_40M, 0x00f0}, 509 {"pdoffset2g40ma2", 0xfffff800, 0, SROM11_PDOFF_2G_40M, 0x0f00}, 510 {"pdoffset2g40mvalid", 0xfffff800, 0, SROM11_PDOFF_2G_40M, 0x8000}, 511 {"pdoffset40ma0", 0xfffff800, 0, SROM11_PDOFF_40M_A0, 0xffff}, 512 {"pdoffset40ma1", 0xfffff800, 0, SROM11_PDOFF_40M_A1, 0xffff}, 513 {"pdoffset40ma2", 0xfffff800, 0, SROM11_PDOFF_40M_A2, 0xffff}, 514 {"pdoffset80ma0", 0xfffff800, 0, SROM11_PDOFF_80M_A0, 0xffff}, 515 {"pdoffset80ma1", 0xfffff800, 0, SROM11_PDOFF_80M_A1, 0xffff}, 516 {"pdoffset80ma2", 0xfffff800, 0, SROM11_PDOFF_80M_A2, 0xffff}, 517 518 {"subband5gver", 0xfffff800, SRFL_PRHEX, SROM11_SUBBAND5GVER, 0xffff}, 519 {"paparambwver", 0xfffff800, 0, SROM11_MCSLR5GLPO, 0xf000}, 520 {"rx5ggainwar", 0xfffff800, 0, SROM11_MCSLR5GMPO, 0x2000}, 521 /* Special PA Params for 4350 5G Band, 40/80 MHz BW Ant #0 */ 522 {"pa5gbw4080a0", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 +SROM11_5GB0_PA, 0xffff}, 523 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA + 1, 0xffff}, 524 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA + 2, 0xffff}, 525 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA, 0xffff}, 526 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA + 1, 0xffff}, 527 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA + 2, 0xffff}, 528 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA, 0xffff}, 529 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA + 1, 0xffff}, 530 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA + 2, 0xffff}, 531 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_PA, 0xffff}, 532 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_PA + 1, 0xffff}, 533 {"", 0xfffff800, SRFL_PRHEX, SROM11_PATH2 + SROM11_5GB3_PA + 2, 0xffff}, 534 /* Special PA Params for 4335 5G Band, 40 MHz BW */ 535 {"pa5gbw40a0", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB0_PA, 0xffff}, 536 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB0_PA + 1, 0xffff}, 537 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB0_PA + 2, 0xffff}, 538 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB1_PA, 0xffff}, 539 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB1_PA + 1, 0xffff}, 540 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB1_PA + 2, 0xffff}, 541 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB2_PA, 0xffff}, 542 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB2_PA + 1, 0xffff}, 543 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB2_PA + 2, 0xffff}, 544 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB3_PA, 0xffff}, 545 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB3_PA + 1, 0xffff}, 546 {"", 0xfffff800, SRFL_PRHEX, SROM11_PATH1 + SROM11_5GB3_PA + 2, 0xffff}, 547 /* Special PA Params for 4335 5G Band, 80 MHz BW */ 548 {"pa5gbw80a0", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA, 0xffff}, 549 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA + 1, 0xffff}, 550 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA + 2, 0xffff}, 551 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA, 0xffff}, 552 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA + 1, 0xffff}, 553 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA + 2, 0xffff}, 554 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA, 0xffff}, 555 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA + 1, 0xffff}, 556 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA + 2, 0xffff}, 557 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_PA, 0xffff}, 558 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_PA + 1, 0xffff}, 559 {"", 0xfffff800, SRFL_PRHEX, SROM11_PATH2 + SROM11_5GB3_PA + 2, 0xffff}, 560 /* Special PA Params for 4335 2G Band, CCK */ 561 {"pa2gccka0", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_2G_PA, 0xffff}, 562 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_2G_PA + 1, 0xffff}, 563 {"", 0xfffff800, SRFL_PRHEX, SROM11_PATH1 + SROM11_2G_PA + 2, 0xffff}, 564 565 /* power per rate */ 566 {"cckbw202gpo", 0xfffff800, 0, SROM11_CCKBW202GPO, 0xffff}, 567 {"cckbw20ul2gpo", 0xfffff800, 0, SROM11_CCKBW20UL2GPO, 0xffff}, 568 {"mcsbw202gpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW202GPO, 0xffff}, 569 {"", 0xfffff800, 0, SROM11_MCSBW202GPO_1, 0xffff}, 570 {"mcsbw402gpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW402GPO, 0xffff}, 571 {"", 0xfffff800, 0, SROM11_MCSBW402GPO_1, 0xffff}, 572 {"dot11agofdmhrbw202gpo", 0xfffff800, 0, SROM11_DOT11AGOFDMHRBW202GPO, 0xffff}, 573 {"ofdmlrbw202gpo", 0xfffff800, 0, SROM11_OFDMLRBW202GPO, 0xffff}, 574 {"mcsbw205glpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW205GLPO, 0xffff}, 575 {"", 0xfffff800, 0, SROM11_MCSBW205GLPO_1, 0xffff}, 576 {"mcsbw405glpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW405GLPO, 0xffff}, 577 {"", 0xfffff800, 0, SROM11_MCSBW405GLPO_1, 0xffff}, 578 {"mcsbw805glpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW805GLPO, 0xffff}, 579 {"", 0xfffff800, 0, SROM11_MCSBW805GLPO_1, 0xffff}, 580 {"mcsbw205gmpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW205GMPO, 0xffff}, 581 {"", 0xfffff800, 0, SROM11_MCSBW205GMPO_1, 0xffff}, 582 {"mcsbw405gmpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW405GMPO, 0xffff}, 583 {"", 0xfffff800, 0, SROM11_MCSBW405GMPO_1, 0xffff}, 584 {"mcsbw805gmpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW805GMPO, 0xffff}, 585 {"", 0xfffff800, 0, SROM11_MCSBW805GMPO_1, 0xffff}, 586 {"mcsbw205ghpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW205GHPO, 0xffff}, 587 {"", 0xfffff800, 0, SROM11_MCSBW205GHPO_1, 0xffff}, 588 {"mcsbw405ghpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW405GHPO, 0xffff}, 589 {"", 0xfffff800, 0, SROM11_MCSBW405GHPO_1, 0xffff}, 590 {"mcsbw805ghpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW805GHPO, 0xffff}, 591 {"", 0xfffff800, 0, SROM11_MCSBW805GHPO_1, 0xffff}, 592 {"mcslr5glpo", 0xfffff800, 0, SROM11_MCSLR5GLPO, 0x0fff}, 593 {"mcslr5gmpo", 0xfffff800, 0, SROM11_MCSLR5GMPO, 0xffff}, 594 {"mcslr5ghpo", 0xfffff800, 0, SROM11_MCSLR5GHPO, 0xffff}, 595 {"sb20in40hrpo", 0xfffff800, 0, SROM11_SB20IN40HRPO, 0xffff}, 596 {"sb20in80and160hr5glpo", 0xfffff800, 0, SROM11_SB20IN80AND160HR5GLPO, 0xffff}, 597 {"sb40and80hr5glpo", 0xfffff800, 0, SROM11_SB40AND80HR5GLPO, 0xffff}, 598 {"sb20in80and160hr5gmpo", 0xfffff800, 0, SROM11_SB20IN80AND160HR5GMPO, 0xffff}, 599 {"sb40and80hr5gmpo", 0xfffff800, 0, SROM11_SB40AND80HR5GMPO, 0xffff}, 600 {"sb20in80and160hr5ghpo", 0xfffff800, 0, SROM11_SB20IN80AND160HR5GHPO, 0xffff}, 601 {"sb40and80hr5ghpo", 0xfffff800, 0, SROM11_SB40AND80HR5GHPO, 0xffff}, 602 {"sb20in40lrpo", 0xfffff800, 0, SROM11_SB20IN40LRPO, 0xffff}, 603 {"sb20in80and160lr5glpo", 0xfffff800, 0, SROM11_SB20IN80AND160LR5GLPO, 0xffff}, 604 {"sb40and80lr5glpo", 0xfffff800, 0, SROM11_SB40AND80LR5GLPO, 0xffff}, 605 {"sb20in80and160lr5gmpo", 0xfffff800, 0, SROM11_SB20IN80AND160LR5GMPO, 0xffff}, 606 {"sb40and80lr5gmpo", 0xfffff800, 0, SROM11_SB40AND80LR5GMPO, 0xffff}, 607 {"sb20in80and160lr5ghpo", 0xfffff800, 0, SROM11_SB20IN80AND160LR5GHPO, 0xffff}, 608 {"sb40and80lr5ghpo", 0xfffff800, 0, SROM11_SB40AND80LR5GHPO, 0xffff}, 609 {"dot11agduphrpo", 0xfffff800, 0, SROM11_DOT11AGDUPHRPO, 0xffff}, 610 {"dot11agduplrpo", 0xfffff800, 0, SROM11_DOT11AGDUPLRPO, 0xffff}, 611 612 /* Misc */ 613 {"sar2g", 0xfffff800, 0, SROM11_SAR, 0x00ff}, 614 {"sar5g", 0xfffff800, 0, SROM11_SAR, 0xff00}, 615 616 {"noiselvl2ga0", 0xfffff800, 0, SROM11_NOISELVL_2G, 0x001f}, 617 {"noiselvl2ga1", 0xfffff800, 0, SROM11_NOISELVL_2G, 0x03e0}, 618 {"noiselvl2ga2", 0xfffff800, 0, SROM11_NOISELVL_2G, 0x7c00}, 619 {"noiselvl5ga0", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GL, 0x001f}, 620 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GM, 0x001f}, 621 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GH, 0x001f}, 622 {"", 0xfffff800, 0, SROM11_NOISELVL_5GU, 0x001f}, 623 {"noiselvl5ga1", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GL, 0x03e0}, 624 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GM, 0x03e0}, 625 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GH, 0x03e0}, 626 {"", 0xfffff800, 0, SROM11_NOISELVL_5GU, 0x03e0}, 627 {"noiselvl5ga2", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GL, 0x7c00}, 628 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GM, 0x7c00}, 629 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GH, 0x7c00}, 630 {"", 0xfffff800, 0, SROM11_NOISELVL_5GU, 0x7c00}, 631 {"eu_edthresh2g", 0x00000800, 0, SROM11_EU_EDCRSTH, 0x00ff}, 632 {"eu_edthresh5g", 0x00000800, 0, SROM11_EU_EDCRSTH, 0xff00}, 633 634 {"rxgainerr2ga0", 0xfffff800, 0, SROM11_RXGAINERR_2G, 0x003f}, 635 {"rxgainerr2ga1", 0xfffff800, 0, SROM11_RXGAINERR_2G, 0x07c0}, 636 {"rxgainerr2ga2", 0xfffff800, 0, SROM11_RXGAINERR_2G, 0xf800}, 637 {"rxgainerr5ga0", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GL, 0x003f}, 638 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GM, 0x003f}, 639 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GH, 0x003f}, 640 {"", 0xfffff800, 0, SROM11_RXGAINERR_5GU, 0x003f}, 641 {"rxgainerr5ga1", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GL, 0x07c0}, 642 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GM, 0x07c0}, 643 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GH, 0x07c0}, 644 {"", 0xfffff800, 0, SROM11_RXGAINERR_5GU, 0x07c0}, 645 {"rxgainerr5ga2", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GL, 0xf800}, 646 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GM, 0xf800}, 647 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GH, 0xf800}, 648 {"", 0xfffff800, 0, SROM11_RXGAINERR_5GU, 0xf800}, 649 {"rpcal2g", 0xfffff800, 0, SROM11_RPCAL_2G, 0xffff}, 650 {"rpcal5gb0", 0xfffff800, 0, SROM11_RPCAL_5GL, 0xffff}, 651 {"rpcal5gb1", 0xfffff800, 0, SROM11_RPCAL_5GM, 0xffff}, 652 {"rpcal5gb2", 0xfffff800, 0, SROM11_RPCAL_5GH, 0xffff}, 653 {"rpcal5gb3", 0xfffff800, 0, SROM11_RPCAL_5GU, 0xffff}, 654 {"txidxcap2g", 0xfffff800, 0, SROM11_TXIDXCAP2G, 0x0ff0}, 655 {"txidxcap5g", 0xfffff800, 0, SROM11_TXIDXCAP5G, 0x0ff0}, 656 {"pdoffsetcckma0", 0xfffff800, 0, SROM11_PDOFF_2G_CCK, 0x000f}, 657 {"pdoffsetcckma1", 0xfffff800, 0, SROM11_PDOFF_2G_CCK, 0x00f0}, 658 {"pdoffsetcckma2", 0xfffff800, 0, SROM11_PDOFF_2G_CCK, 0x0f00}, 659 660 /* sromrev 12 */ 661 {"boardflags4", 0xfffff000, SRFL_PRHEX|SRFL_MORE, SROM12_BFL6, 0xffff}, 662 {"", 0, 0, SROM12_BFL7, 0xffff}, 663 {"pdoffsetcck", 0xfffff000, 0, SROM12_PDOFF_2G_CCK, 0xffff}, 664 {"pdoffset20in40m5gb0", 0xfffff000, 0, SROM12_PDOFF_20in40M_5G_B0, 0xffff}, 665 {"pdoffset20in40m5gb1", 0xfffff000, 0, SROM12_PDOFF_20in40M_5G_B1, 0xffff}, 666 {"pdoffset20in40m5gb2", 0xfffff000, 0, SROM12_PDOFF_20in40M_5G_B2, 0xffff}, 667 {"pdoffset20in40m5gb3", 0xfffff000, 0, SROM12_PDOFF_20in40M_5G_B3, 0xffff}, 668 {"pdoffset20in40m5gb4", 0xfffff000, 0, SROM12_PDOFF_20in40M_5G_B4, 0xffff}, 669 {"pdoffset40in80m5gb0", 0xfffff000, 0, SROM12_PDOFF_40in80M_5G_B0, 0xffff}, 670 {"pdoffset40in80m5gb1", 0xfffff000, 0, SROM12_PDOFF_40in80M_5G_B1, 0xffff}, 671 {"pdoffset40in80m5gb2", 0xfffff000, 0, SROM12_PDOFF_40in80M_5G_B2, 0xffff}, 672 {"pdoffset40in80m5gb3", 0xfffff000, 0, SROM12_PDOFF_40in80M_5G_B3, 0xffff}, 673 {"pdoffset40in80m5gb4", 0xfffff000, 0, SROM12_PDOFF_40in80M_5G_B4, 0xffff}, 674 {"pdoffset20in80m5gb0", 0xfffff000, 0, SROM12_PDOFF_20in80M_5G_B0, 0xffff}, 675 {"pdoffset20in80m5gb1", 0xfffff000, 0, SROM12_PDOFF_20in80M_5G_B1, 0xffff}, 676 {"pdoffset20in80m5gb2", 0xfffff000, 0, SROM12_PDOFF_20in80M_5G_B2, 0xffff}, 677 {"pdoffset20in80m5gb3", 0xfffff000, 0, SROM12_PDOFF_20in80M_5G_B3, 0xffff}, 678 {"pdoffset20in80m5gb4", 0xfffff000, 0, SROM12_PDOFF_20in80M_5G_B4, 0xffff}, 679 680 /* power per rate */ 681 {"mcsbw205gx1po", 0xfffff000, SRFL_MORE, SROM12_MCSBW205GX1PO, 0xffff}, 682 {"", 0xfffff000, 0, SROM12_MCSBW205GX1PO_1, 0xffff}, 683 {"mcsbw405gx1po", 0xfffff000, SRFL_MORE, SROM12_MCSBW405GX1PO, 0xffff}, 684 {"", 0xfffff000, 0, SROM12_MCSBW405GX1PO_1, 0xffff}, 685 {"mcsbw805gx1po", 0xfffff000, SRFL_MORE, SROM12_MCSBW805GX1PO, 0xffff}, 686 {"", 0xfffff000, 0, SROM12_MCSBW805GX1PO_1, 0xffff}, 687 {"mcsbw205gx2po", 0xfffff000, SRFL_MORE, SROM12_MCSBW205GX2PO, 0xffff}, 688 {"", 0xfffff000, 0, SROM12_MCSBW205GX2PO_1, 0xffff}, 689 {"mcsbw405gx2po", 0xfffff000, SRFL_MORE, SROM12_MCSBW405GX2PO, 0xffff}, 690 {"", 0xfffff000, 0, SROM12_MCSBW405GX2PO_1, 0xffff}, 691 {"mcsbw805gx2po", 0xfffff000, SRFL_MORE, SROM12_MCSBW805GX2PO, 0xffff}, 692 {"", 0xfffff000, 0, SROM12_MCSBW805GX2PO_1, 0xffff}, 693 694 {"sb20in80and160hr5gx1po", 0xfffff000, 0, SROM12_SB20IN80AND160HR5GX1PO, 0xffff}, 695 {"sb40and80hr5gx1po", 0xfffff000, 0, SROM12_SB40AND80HR5GX1PO, 0xffff}, 696 {"sb20in80and160lr5gx1po", 0xfffff000, 0, SROM12_SB20IN80AND160LR5GX1PO, 0xffff}, 697 {"sb40and80hr5gx1po", 0xfffff000, 0, SROM12_SB40AND80HR5GX1PO, 0xffff}, 698 {"sb20in80and160hr5gx2po", 0xfffff000, 0, SROM12_SB20IN80AND160HR5GX2PO, 0xffff}, 699 {"sb40and80hr5gx2po", 0xfffff000, 0, SROM12_SB40AND80HR5GX2PO, 0xffff}, 700 {"sb20in80and160lr5gx2po", 0xfffff000, 0, SROM12_SB20IN80AND160LR5GX2PO, 0xffff}, 701 {"sb40and80hr5gx2po", 0xfffff000, 0, SROM12_SB40AND80HR5GX2PO, 0xffff}, 702 703 {"rxgains5gmelnagaina0", 0xfffff000, 0, SROM12_RXGAINS10, 0x0007}, 704 {"rxgains5gmelnagaina1", 0xfffff000, 0, SROM12_RXGAINS11, 0x0007}, 705 {"rxgains5gmelnagaina2", 0xfffff000, 0, SROM12_RXGAINS12, 0x0007}, 706 {"rxgains5gmtrisoa0", 0xfffff000, 0, SROM12_RXGAINS10, 0x0078}, 707 {"rxgains5gmtrisoa1", 0xfffff000, 0, SROM12_RXGAINS11, 0x0078}, 708 {"rxgains5gmtrisoa2", 0xfffff000, 0, SROM12_RXGAINS12, 0x0078}, 709 {"rxgains5gmtrelnabypa0", 0xfffff000, 0, SROM12_RXGAINS10, 0x0080}, 710 {"rxgains5gmtrelnabypa1", 0xfffff000, 0, SROM12_RXGAINS11, 0x0080}, 711 {"rxgains5gmtrelnabypa2", 0xfffff000, 0, SROM12_RXGAINS12, 0x0080}, 712 {"rxgains5ghelnagaina0", 0xfffff000, 0, SROM12_RXGAINS10, 0x0700}, 713 {"rxgains5ghelnagaina1", 0xfffff000, 0, SROM12_RXGAINS11, 0x0700}, 714 {"rxgains5ghelnagaina2", 0xfffff000, 0, SROM12_RXGAINS12, 0x0700}, 715 {"rxgains5ghtrisoa0", 0xfffff000, 0, SROM12_RXGAINS10, 0x7800}, 716 {"rxgains5ghtrisoa1", 0xfffff000, 0, SROM12_RXGAINS11, 0x7800}, 717 {"rxgains5ghtrisoa2", 0xfffff000, 0, SROM12_RXGAINS12, 0x7800}, 718 {"rxgains5ghtrelnabypa0", 0xfffff000, 0, SROM12_RXGAINS10, 0x8000}, 719 {"rxgains5ghtrelnabypa1", 0xfffff000, 0, SROM12_RXGAINS11, 0x8000}, 720 {"rxgains5ghtrelnabypa2", 0xfffff000, 0, SROM12_RXGAINS12, 0x8000}, 721 {"eu_edthresh2g", 0x00001000, 0, SROM12_EU_EDCRSTH, 0x00ff}, 722 {"eu_edthresh5g", 0x00001000, 0, SROM12_EU_EDCRSTH, 0xff00}, 723 724 {"gpdn", 0xfffff000, SRFL_PRHEX|SRFL_MORE, SROM12_GPDN_L, 0xffff}, 725 {"", 0, 0, SROM12_GPDN_H, 0xffff}, 726 727 {"rpcal2gcore3", 0xffffe000, 0, SROM13_RPCAL2GCORE3, 0x00ff}, 728 {"rpcal5gb0core3", 0xffffe000, 0, SROM13_RPCAL5GB01CORE3, 0x00ff}, 729 {"rpcal5gb1core3", 0xffffe000, 0, SROM13_RPCAL5GB01CORE3, 0xff00}, 730 {"rpcal5gb2core3", 0xffffe000, 0, SROM13_RPCAL5GB23CORE3, 0x00ff}, 731 {"rpcal5gb3core3", 0xffffe000, 0, SROM13_RPCAL5GB23CORE3, 0xff00}, 732 733 {"sw_txchain_mask", 0xffffe000, 0, SROM13_SW_TXRX_MASK, 0x000f}, 734 {"sw_rxchain_mask", 0xffffe000, 0, SROM13_SW_TXRX_MASK, 0x00f0}, 735 736 {"eu_edthresh2g", 0x00002000, 0, SROM13_EU_EDCRSTH, 0x00ff}, 737 {"eu_edthresh5g", 0x00002000, 0, SROM13_EU_EDCRSTH, 0xff00}, 738 739 {"agbg3", 0xffffe000, 0, SROM13_ANTGAIN_BANDBGA, 0xff00}, 740 {"aga3", 0xffffe000, 0, SROM13_ANTGAIN_BANDBGA, 0x00ff}, 741 {"noiselvl2ga3", 0xffffe000, 0, SROM13_NOISELVLCORE3, 0x001f}, 742 {"noiselvl5ga3", 0xffffe000, SRFL_ARRAY, SROM13_NOISELVLCORE3, 0x03e0}, 743 {"", 0xffffe000, SRFL_ARRAY, SROM13_NOISELVLCORE3, 0x7c00}, 744 {"", 0xffffe000, SRFL_ARRAY, SROM13_NOISELVLCORE3_1, 0x001f}, 745 {"", 0xffffe000, 0, SROM13_NOISELVLCORE3_1, 0x03e0}, 746 {"rxgainerr2ga3", 0xffffe000, 0, SROM13_RXGAINERRCORE3, 0x001f}, 747 {"rxgainerr5ga3", 0xffffe000, SRFL_ARRAY, SROM13_RXGAINERRCORE3, 0x03e0}, 748 {"", 0xffffe000, SRFL_ARRAY, SROM13_RXGAINERRCORE3, 0x7c00}, 749 {"", 0xffffe000, SRFL_ARRAY, SROM13_RXGAINERRCORE3_1, 0x001f}, 750 {"", 0xffffe000, 0, SROM13_RXGAINERRCORE3_1, 0x03e0}, 751 {"rxgains5gmelnagaina3", 0xffffe000, 0, SROM13_RXGAINS1CORE3, 0x0007}, 752 {"rxgains5gmtrisoa3", 0xffffe000, 0, SROM13_RXGAINS1CORE3, 0x0078}, 753 {"rxgains5gmtrelnabypa3", 0xffffe000, 0, SROM13_RXGAINS1CORE3, 0x0080}, 754 {"rxgains5ghelnagaina3", 0xffffe000, 0, SROM13_RXGAINS1CORE3, 0x0700}, 755 {"rxgains5ghtrisoa3", 0xffffe000, 0, SROM13_RXGAINS1CORE3, 0x7800}, 756 {"rxgains5ghtrelnabypa3", 0xffffe000, 0, SROM13_RXGAINS1CORE3, 0x8000}, 757 758 /* pdoffset */ 759 {"pdoffset20in40m5gcore3", 0xffffe000, 0, SROM13_PDOFFSET20IN40M5GCORE3, 0xffff}, 760 {"pdoffset20in40m5gcore3_1", 0xffffe000, 0, SROM13_PDOFFSET20IN40M5GCORE3_1, 0xffff}, 761 {"pdoffset20in80m5gcore3", 0xffffe000, 0, SROM13_PDOFFSET20IN80M5GCORE3, 0xffff}, 762 {"pdoffset20in80m5gcore3_1", 0xffffe000, 0, SROM13_PDOFFSET20IN80M5GCORE3_1, 0xffff}, 763 {"pdoffset40in80m5gcore3", 0xffffe000, 0, SROM13_PDOFFSET40IN80M5GCORE3, 0xffff}, 764 {"pdoffset40in80m5gcore3_1", 0xffffe000, 0, SROM13_PDOFFSET40IN80M5GCORE3_1, 0xffff}, 765 766 {"pdoffset20in40m2g", 0xffffe000, 0, SROM13_PDOFFSET20IN40M2G, 0xffff}, 767 {"pdoffset20in40m2gcore3", 0xffffe000, 0, SROM13_PDOFFSET20IN40M2GCORE3, 0xffff}, 768 {"pdoffsetcck20m", 0xffffe000, 0, SROM13_PDOFF_2G_CCK_20M, 0xffff}, 769 770 /* power per rate */ 771 {"mcs1024qam2gpo", 0xffffe000, 0, SROM13_MCS1024QAM2GPO, 0xffff}, 772 {"mcs1024qam5glpo", 0xffffe000, SRFL_MORE, SROM13_MCS1024QAM5GLPO, 0xffff}, 773 {"", 0xffffe000, 0, SROM13_MCS1024QAM5GLPO_1, 0xffff}, 774 {"mcs1024qam5gmpo", 0xffffe000, SRFL_MORE, SROM13_MCS1024QAM5GMPO, 0xffff}, 775 {"", 0xffffe000, 0, SROM13_MCS1024QAM5GMPO_1, 0xffff}, 776 {"mcs1024qam5ghpo", 0xffffe000, SRFL_MORE, SROM13_MCS1024QAM5GHPO, 0xffff}, 777 {"", 0xffffe000, 0, SROM13_MCS1024QAM5GHPO_1, 0xffff}, 778 {"mcs1024qam5gx1po", 0xffffe000, SRFL_MORE, SROM13_MCS1024QAM5GX1PO, 0xffff}, 779 {"", 0xffffe000, 0, SROM13_MCS1024QAM5GX1PO_1, 0xffff}, 780 {"mcs1024qam5gx2po", 0xffffe000, SRFL_MORE, SROM13_MCS1024QAM5GX2PO, 0xffff}, 781 {"", 0xffffe000, 0, SROM13_MCS1024QAM5GX2PO_1, 0xffff}, 782 783 {"mcsbw1605glpo", 0xffffe000, SRFL_MORE, SROM13_MCSBW1605GLPO, 0xffff}, 784 {"", 0xffffe000, 0, SROM13_MCSBW1605GLPO_1, 0xffff}, 785 {"mcsbw1605gmpo", 0xffffe000, SRFL_MORE, SROM13_MCSBW1605GMPO, 0xffff}, 786 {"", 0xffffe000, 0, SROM13_MCSBW1605GMPO_1, 0xffff}, 787 {"mcsbw1605ghpo", 0xffffe000, SRFL_MORE, SROM13_MCSBW1605GHPO, 0xffff}, 788 {"", 0xffffe000, 0, SROM13_MCSBW1605GHPO_1, 0xffff}, 789 {"mcsbw1605gx1po", 0xffffe000, SRFL_MORE, SROM13_MCSBW1605GX1PO, 0xffff}, 790 {"", 0xffffe000, 0, SROM13_MCSBW1605GX1PO_1, 0xffff}, 791 {"mcsbw1605gx2po", 0xffffe000, SRFL_MORE, SROM13_MCSBW1605GX2PO, 0xffff}, 792 {"", 0xffffe000, 0, SROM13_MCSBW1605GX2PO_1, 0xffff}, 793 794 {"ulbpproffs2g", 0xffffe000, 0, SROM13_ULBPPROFFS2G, 0xffff}, 795 796 {"mcs8poexp", 0xffffe000, SRFL_MORE, SROM13_MCS8POEXP, 0xffff}, 797 {"", 0xffffe000, 0, SROM13_MCS8POEXP_1, 0xffff}, 798 {"mcs9poexp", 0xffffe000, SRFL_MORE, SROM13_MCS9POEXP, 0xffff}, 799 {"", 0xffffe000, 0, SROM13_MCS9POEXP_1, 0xffff}, 800 {"mcs10poexp", 0xffffe000, SRFL_MORE, SROM13_MCS10POEXP, 0xffff}, 801 {"", 0xffffe000, 0, SROM13_MCS10POEXP_1, 0xffff}, 802 {"mcs11poexp", 0xffffe000, SRFL_MORE, SROM13_MCS11POEXP, 0xffff}, 803 {"", 0xffffe000, 0, SROM13_MCS11POEXP_1, 0xffff}, 804 805 {"ulbpdoffs5gb0a0", 0xffffe000, 0, SROM13_ULBPDOFFS5GB0A0, 0xffff}, 806 {"ulbpdoffs5gb0a1", 0xffffe000, 0, SROM13_ULBPDOFFS5GB0A1, 0xffff}, 807 {"ulbpdoffs5gb0a2", 0xffffe000, 0, SROM13_ULBPDOFFS5GB0A2, 0xffff}, 808 {"ulbpdoffs5gb0a3", 0xffffe000, 0, SROM13_ULBPDOFFS5GB0A3, 0xffff}, 809 {"ulbpdoffs5gb1a0", 0xffffe000, 0, SROM13_ULBPDOFFS5GB1A0, 0xffff}, 810 {"ulbpdoffs5gb1a1", 0xffffe000, 0, SROM13_ULBPDOFFS5GB1A1, 0xffff}, 811 {"ulbpdoffs5gb1a2", 0xffffe000, 0, SROM13_ULBPDOFFS5GB1A2, 0xffff}, 812 {"ulbpdoffs5gb1a3", 0xffffe000, 0, SROM13_ULBPDOFFS5GB1A3, 0xffff}, 813 {"ulbpdoffs5gb2a0", 0xffffe000, 0, SROM13_ULBPDOFFS5GB2A0, 0xffff}, 814 {"ulbpdoffs5gb2a1", 0xffffe000, 0, SROM13_ULBPDOFFS5GB2A1, 0xffff}, 815 {"ulbpdoffs5gb2a2", 0xffffe000, 0, SROM13_ULBPDOFFS5GB2A2, 0xffff}, 816 {"ulbpdoffs5gb2a3", 0xffffe000, 0, SROM13_ULBPDOFFS5GB2A3, 0xffff}, 817 {"ulbpdoffs5gb3a0", 0xffffe000, 0, SROM13_ULBPDOFFS5GB3A0, 0xffff}, 818 {"ulbpdoffs5gb3a1", 0xffffe000, 0, SROM13_ULBPDOFFS5GB3A1, 0xffff}, 819 {"ulbpdoffs5gb3a2", 0xffffe000, 0, SROM13_ULBPDOFFS5GB3A2, 0xffff}, 820 {"ulbpdoffs5gb3a3", 0xffffe000, 0, SROM13_ULBPDOFFS5GB3A3, 0xffff}, 821 {"ulbpdoffs5gb4a0", 0xffffe000, 0, SROM13_ULBPDOFFS5GB4A0, 0xffff}, 822 {"ulbpdoffs5gb4a1", 0xffffe000, 0, SROM13_ULBPDOFFS5GB4A1, 0xffff}, 823 {"ulbpdoffs5gb4a2", 0xffffe000, 0, SROM13_ULBPDOFFS5GB4A2, 0xffff}, 824 {"ulbpdoffs5gb4a3", 0xffffe000, 0, SROM13_ULBPDOFFS5GB4A3, 0xffff}, 825 {"ulbpdoffs2ga0", 0xffffe000, 0, SROM13_ULBPDOFFS2GA0, 0xffff}, 826 {"ulbpdoffs2ga1", 0xffffe000, 0, SROM13_ULBPDOFFS2GA1, 0xffff}, 827 {"ulbpdoffs2ga2", 0xffffe000, 0, SROM13_ULBPDOFFS2GA2, 0xffff}, 828 {"ulbpdoffs2ga3", 0xffffe000, 0, SROM13_ULBPDOFFS2GA3, 0xffff}, 829 830 {"rpcal5gb4", 0xffffe000, 0, SROM13_RPCAL5GB4, 0xffff}, 831 832 {"sb20in40hrlrpox", 0xffffe000, 0, SROM13_SB20IN40HRLRPOX, 0xffff}, 833 834 {"swctrlmap4_cfg", 0xffffe000, 0, SROM13_SWCTRLMAP4_CFG, 0xffff}, 835 {"swctrlmap4_TX2g_fem3to0", 0xffffe000, 0, SROM13_SWCTRLMAP4_TX2G_FEM3TO0, 0xffff}, 836 {"swctrlmap4_RX2g_fem3to0", 0xffffe000, 0, SROM13_SWCTRLMAP4_RX2G_FEM3TO0, 0xffff}, 837 {"swctrlmap4_RXByp2g_fem3to0", 0xffffe000, 0, SROM13_SWCTRLMAP4_RXBYP2G_FEM3TO0, 0xffff}, 838 {"swctrlmap4_misc2g_fem3to0", 0xffffe000, 0, SROM13_SWCTRLMAP4_MISC2G_FEM3TO0, 0xffff}, 839 {"swctrlmap4_TX5g_fem3to0", 0xffffe000, 0, SROM13_SWCTRLMAP4_TX5G_FEM3TO0, 0xffff}, 840 {"swctrlmap4_RX5g_fem3to0", 0xffffe000, 0, SROM13_SWCTRLMAP4_RX5G_FEM3TO0, 0xffff}, 841 {"swctrlmap4_RXByp5g_fem3to0", 0xffffe000, 0, SROM13_SWCTRLMAP4_RXBYP5G_FEM3TO0, 0xffff}, 842 {"swctrlmap4_misc5g_fem3to0", 0xffffe000, 0, SROM13_SWCTRLMAP4_MISC5G_FEM3TO0, 0xffff}, 843 {"swctrlmap4_TX2g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_TX2G_FEM7TO4, 0xffff}, 844 {"swctrlmap4_RX2g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_RX2G_FEM7TO4, 0xffff}, 845 {"swctrlmap4_RXByp2g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_RXBYP2G_FEM7TO4, 0xffff}, 846 {"swctrlmap4_misc2g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_MISC2G_FEM7TO4, 0xffff}, 847 {"swctrlmap4_TX5g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_TX5G_FEM7TO4, 0xffff}, 848 {"swctrlmap4_RX5g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_RX5G_FEM7TO4, 0xffff}, 849 {"swctrlmap4_RXByp5g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_RXBYP5G_FEM7TO4, 0xffff}, 850 {"swctrlmap4_misc5g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_MISC5G_FEM7TO4, 0xffff}, 851 {NULL, 0, 0, 0, 0} 852 }; 853 #endif /* !defined(SROM15_MEMOPT) */ 854 855 static const sromvar_t BCMATTACHDATA(pci_srom15vars)[] = { 856 {"macaddr", 0x00008000, SRFL_ETHADDR, SROM15_MACHI, 0xffff}, 857 {"caldata_offset", 0x00008000, 0, SROM15_CAL_OFFSET_LOC, 0xffff}, 858 {"boardrev", 0x00008000, SRFL_PRHEX, SROM15_BRDREV, 0xffff}, 859 {"ccode", 0x00008000, SRFL_CCODE, SROM15_CCODE, 0xffff}, 860 {"regrev", 0x00008000, 0, SROM15_REGREV, 0xffff}, 861 {NULL, 0, 0, 0, 0} 862 }; 863 864 static const sromvar_t BCMATTACHDATA(pci_srom16vars)[] = { 865 {"macaddr", 0x00010000, SRFL_ETHADDR, SROM16_MACHI, 0xffff}, 866 {"caldata_offset", 0x00010000, 0, SROM16_CALDATA_OFFSET_LOC, 0xffff}, 867 {"boardrev", 0x00010000, SRFL_PRHEX, SROM16_BOARDREV, 0xffff}, 868 {"ccode", 0x00010000, SRFL_CCODE, SROM16_CCODE, 0xffff}, 869 {"regrev", 0x00010000, 0, SROM16_REGREV, 0xffff}, 870 {NULL, 0, 0, 0, 0} 871 }; 872 873 static const sromvar_t BCMATTACHDATA(pci_srom17vars)[] = { 874 {"boardrev", 0x00020000, SRFL_PRHEX, SROM17_BRDREV, 0xffff}, 875 {"macaddr", 0x00020000, SRFL_ETHADDR, SROM17_MACADDR, 0xffff}, 876 {"ccode", 0x00020000, SRFL_CCODE, SROM17_CCODE, 0xffff}, 877 {"caldata_offset", 0x00020000, 0, SROM17_CALDATA, 0xffff}, 878 {"gain_cal_temp", 0x00020000, SRFL_PRHEX, SROM17_GCALTMP, 0xffff}, 879 {"rssi_delta_2gb0_c0", 0x00020000, PRHEX_N_MORE, SROM17_C0SRD202G, 0xffff}, 880 {"", 0x00020000, 0, SROM17_C0SRD202G_1, 0xffff}, 881 {"rssi_delta_5gl_c0", 0x00020000, PRHEX_N_MORE, SROM17_C0SRD205GL, 0xffff}, 882 {"", 0x00020000, 0, SROM17_C0SRD205GL_1, 0xffff}, 883 {"rssi_delta_5gml_c0", 0x00020000, PRHEX_N_MORE, SROM17_C0SRD205GML, 0xffff}, 884 {"", 0x00020000, 0, SROM17_C0SRD205GML_1, 0xffff}, 885 {"rssi_delta_5gmu_c0", 0x00020000, PRHEX_N_MORE, SROM17_C0SRD205GMU, 0xffff}, 886 {"", 0x00020000, 0, SROM17_C0SRD205GMU_1, 0xffff}, 887 {"rssi_delta_5gh_c0", 0x00020000, PRHEX_N_MORE, SROM17_C0SRD205GH, 0xffff}, 888 {"", 0x00020000, 0, SROM17_C0SRD205GH_1, 0xffff}, 889 {"rssi_delta_2gb0_c1", 0x00020000, PRHEX_N_MORE, SROM17_C1SRD202G, 0xffff}, 890 {"", 0x00020000, 0, SROM17_C1SRD202G_1, 0xffff}, 891 {"rssi_delta_5gl_c1", 0x00020000, PRHEX_N_MORE, SROM17_C1SRD205GL, 0xffff}, 892 {"", 0x00020000, 0, SROM17_C1SRD205GL_1, 0xffff}, 893 {"rssi_delta_5gml_c1", 0x00020000, PRHEX_N_MORE, SROM17_C1SRD205GML, 0xffff}, 894 {"", 0x00020000, 0, SROM17_C1SRD205GML_1, 0xffff}, 895 {"rssi_delta_5gmu_c1", 0x00020000, PRHEX_N_MORE, SROM17_C1SRD205GMU, 0xffff}, 896 {"", 0x00020000, 0, SROM17_C1SRD205GMU_1, 0xffff}, 897 {"rssi_delta_5gh_c1", 0x00020000, PRHEX_N_MORE, SROM17_C1SRD205GH, 0xffff}, 898 {"", 0x00020000, 0, SROM17_C1SRD205GH_1, 0xffff}, 899 {"txpa_trim_magic", 0x00020000, PRHEX_N_MORE, SROM17_TRAMMAGIC, 0xffff}, 900 {"", 0x00020000, 0, SROM17_TRAMMAGIC_1, 0xffff}, 901 {"txpa_trim_data", 0x00020000, SRFL_PRHEX, SROM17_TRAMDATA, 0xffff}, 902 {NULL, 0, 0, 0, 0x00} 903 }; 904 905 static const sromvar_t BCMATTACHDATA(pci_srom18vars)[] = { 906 {"macaddr", 0x00040000, SRFL_ETHADDR, SROM18_MACHI, 0xffff}, 907 {"caldata_offset", 0x00040000, 0, SROM18_CALDATA_OFFSET_LOC, 0xffff}, 908 {"boardrev", 0x00040000, SRFL_PRHEX, SROM18_BOARDREV, 0xffff}, 909 {"ccode", 0x00040000, SRFL_CCODE, SROM18_CCODE, 0xffff}, 910 {"regrev", 0x00040000, 0, SROM18_REGREV, 0xffff}, 911 {NULL, 0, 0, 0, 0} 912 }; 913 914 static const sromvar_t BCMATTACHDATA(perpath_pci_sromvars)[] = { 915 {"maxp2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff}, 916 {"itt2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00}, 917 {"itt5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00}, 918 {"pa2gw0a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff}, 919 {"pa2gw1a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff}, 920 {"pa2gw2a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff}, 921 {"pa2gw3a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff}, 922 {"maxp5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff}, 923 {"maxp5gha", 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff}, 924 {"maxp5gla", 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00}, 925 {"pa5gw0a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff}, 926 {"pa5gw1a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff}, 927 {"pa5gw2a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff}, 928 {"pa5gw3a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff}, 929 {"pa5glw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff}, 930 {"pa5glw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1, 0xffff}, 931 {"pa5glw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2, 0xffff}, 932 {"pa5glw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3, 0xffff}, 933 {"pa5ghw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff}, 934 {"pa5ghw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1, 0xffff}, 935 {"pa5ghw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2, 0xffff}, 936 {"pa5ghw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3, 0xffff}, 937 {"maxp2ga", 0x00000700, 0, SROM8_2G_ITT_MAXP, 0x00ff}, 938 {"itt2ga", 0x00000700, 0, SROM8_2G_ITT_MAXP, 0xff00}, 939 {"itt5ga", 0x00000700, 0, SROM8_5G_ITT_MAXP, 0xff00}, 940 {"pa2gw0a", 0x00000700, SRFL_PRHEX, SROM8_2G_PA, 0xffff}, 941 {"pa2gw1a", 0x00000700, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff}, 942 {"pa2gw2a", 0x00000700, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff}, 943 {"maxp5ga", 0x00000700, 0, SROM8_5G_ITT_MAXP, 0x00ff}, 944 {"maxp5gha", 0x00000700, 0, SROM8_5GLH_MAXP, 0x00ff}, 945 {"maxp5gla", 0x00000700, 0, SROM8_5GLH_MAXP, 0xff00}, 946 {"pa5gw0a", 0x00000700, SRFL_PRHEX, SROM8_5G_PA, 0xffff}, 947 {"pa5gw1a", 0x00000700, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff}, 948 {"pa5gw2a", 0x00000700, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff}, 949 {"pa5glw0a", 0x00000700, SRFL_PRHEX, SROM8_5GL_PA, 0xffff}, 950 {"pa5glw1a", 0x00000700, SRFL_PRHEX, SROM8_5GL_PA + 1, 0xffff}, 951 {"pa5glw2a", 0x00000700, SRFL_PRHEX, SROM8_5GL_PA + 2, 0xffff}, 952 {"pa5ghw0a", 0x00000700, SRFL_PRHEX, SROM8_5GH_PA, 0xffff}, 953 {"pa5ghw1a", 0x00000700, SRFL_PRHEX, SROM8_5GH_PA + 1, 0xffff}, 954 {"pa5ghw2a", 0x00000700, SRFL_PRHEX, SROM8_5GH_PA + 2, 0xffff}, 955 956 /* sromrev 11 */ 957 {"maxp2ga", 0xfffff800, 0, SROM11_2G_MAXP, 0x00ff}, 958 {"pa2ga", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_2G_PA, 0xffff}, 959 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_2G_PA + 1, 0xffff}, 960 {"", 0x00000800, SRFL_PRHEX, SROM11_2G_PA + 2, 0xffff}, 961 {"rxgains5gmelnagaina", 0x00000800, 0, SROM11_RXGAINS1, 0x0007}, 962 {"rxgains5gmtrisoa", 0x00000800, 0, SROM11_RXGAINS1, 0x0078}, 963 {"rxgains5gmtrelnabypa", 0x00000800, 0, SROM11_RXGAINS1, 0x0080}, 964 {"rxgains5ghelnagaina", 0x00000800, 0, SROM11_RXGAINS1, 0x0700}, 965 {"rxgains5ghtrisoa", 0x00000800, 0, SROM11_RXGAINS1, 0x7800}, 966 {"rxgains5ghtrelnabypa", 0x00000800, 0, SROM11_RXGAINS1, 0x8000}, 967 {"rxgains2gelnagaina", 0x00000800, 0, SROM11_RXGAINS, 0x0007}, 968 {"rxgains2gtrisoa", 0x00000800, 0, SROM11_RXGAINS, 0x0078}, 969 {"rxgains2gtrelnabypa", 0x00000800, 0, SROM11_RXGAINS, 0x0080}, 970 {"rxgains5gelnagaina", 0x00000800, 0, SROM11_RXGAINS, 0x0700}, 971 {"rxgains5gtrisoa", 0x00000800, 0, SROM11_RXGAINS, 0x7800}, 972 {"rxgains5gtrelnabypa", 0x00000800, 0, SROM11_RXGAINS, 0x8000}, 973 {"maxp5ga", 0x00000800, SRFL_ARRAY, SROM11_5GB1B0_MAXP, 0x00ff}, 974 {"", 0x00000800, SRFL_ARRAY, SROM11_5GB1B0_MAXP, 0xff00}, 975 {"", 0x00000800, SRFL_ARRAY, SROM11_5GB3B2_MAXP, 0x00ff}, 976 {"", 0x00000800, 0, SROM11_5GB3B2_MAXP, 0xff00}, 977 {"pa5ga", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_PA, 0xffff}, 978 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_PA + 1, 0xffff}, 979 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_PA + 2, 0xffff}, 980 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_PA, 0xffff}, 981 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_PA + 1, 0xffff}, 982 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_PA + 2, 0xffff}, 983 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB2_PA, 0xffff}, 984 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB2_PA + 1, 0xffff}, 985 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB2_PA + 2, 0xffff}, 986 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB3_PA, 0xffff}, 987 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB3_PA + 1, 0xffff}, 988 {"", 0x00000800, SRFL_PRHEX, SROM11_5GB3_PA + 2, 0xffff}, 989 990 /* sromrev 12 */ 991 {"maxp5gb4a", 0xfffff000, 0, SROM12_5GB42G_MAXP, 0x00ff00}, 992 {"pa2ga", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_2GB0_PA_W0, 0x00ffff}, 993 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_2GB0_PA_W1, 0x00ffff}, 994 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_2GB0_PA_W2, 0x00ffff}, 995 {"", 0xfffff000, SRFL_PRHEX, SROM12_2GB0_PA_W3, 0x00ffff}, 996 997 {"pa2g40a", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_2G40B0_PA_W0, 0x00ffff}, 998 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_2G40B0_PA_W1, 0x00ffff}, 999 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_2G40B0_PA_W2, 0x00ffff}, 1000 {"", 0xfffff000, SRFL_PRHEX, SROM12_2G40B0_PA_W3, 0x00ffff}, 1001 {"maxp5gb0a", 0xfffff000, 0, SROM12_5GB1B0_MAXP, 0x00ff}, 1002 {"maxp5gb1a", 0xfffff000, 0, SROM12_5GB1B0_MAXP, 0x00ff00}, 1003 {"maxp5gb2a", 0xfffff000, 0, SROM12_5GB3B2_MAXP, 0x00ff}, 1004 {"maxp5gb3a", 0xfffff000, 0, SROM12_5GB3B2_MAXP, 0x00ff00}, 1005 1006 {"pa5ga", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB0_PA_W0, 0x00ffff}, 1007 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB0_PA_W1, 0x00ffff}, 1008 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB0_PA_W2, 0x00ffff}, 1009 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB0_PA_W3, 0x00ffff}, 1010 1011 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB1_PA_W0, 0x00ffff}, 1012 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB1_PA_W1, 0x00ffff}, 1013 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB1_PA_W2, 0x00ffff}, 1014 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB1_PA_W3, 0x00ffff}, 1015 1016 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB2_PA_W0, 0x00ffff}, 1017 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB2_PA_W1, 0x00ffff}, 1018 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB2_PA_W2, 0x00ffff}, 1019 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB2_PA_W3, 0x00ffff}, 1020 1021 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB3_PA_W0, 0x00ffff}, 1022 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB3_PA_W1, 0x00ffff}, 1023 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB3_PA_W2, 0x00ffff}, 1024 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB3_PA_W3, 0x00ffff}, 1025 1026 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB4_PA_W0, 0x00ffff}, 1027 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB4_PA_W1, 0x00ffff}, 1028 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB4_PA_W2, 0x00ffff}, 1029 {"", 0xfffff000, SRFL_PRHEX, SROM12_5GB4_PA_W3, 0x00ffff}, 1030 1031 {"pa5g40a", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B0_PA_W0, 0x00ffff}, 1032 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B0_PA_W1, 0x00ffff}, 1033 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B0_PA_W2, 0x00ffff}, 1034 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B0_PA_W3, 0x00ffff}, 1035 1036 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B1_PA_W0, 0x00ffff}, 1037 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B1_PA_W1, 0x00ffff}, 1038 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B1_PA_W2, 0x00ffff}, 1039 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B1_PA_W3, 0x00ffff}, 1040 1041 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B2_PA_W0, 0x00ffff}, 1042 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B2_PA_W1, 0x00ffff}, 1043 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B2_PA_W2, 0x00ffff}, 1044 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B2_PA_W3, 0x00ffff}, 1045 1046 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B3_PA_W0, 0x00ffff}, 1047 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B3_PA_W1, 0x00ffff}, 1048 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B3_PA_W2, 0x00ffff}, 1049 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B3_PA_W3, 0x00ffff}, 1050 1051 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B4_PA_W0, 0x00ffff}, 1052 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B4_PA_W1, 0x00ffff}, 1053 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B4_PA_W2, 0x00ffff}, 1054 {"", 0xfffff000, SRFL_PRHEX, SROM12_5G40B4_PA_W3, 0x00ffff}, 1055 1056 {"pa5g80a", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B0_PA_W0, 0x00ffff}, 1057 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B0_PA_W1, 0x00ffff}, 1058 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B0_PA_W2, 0x00ffff}, 1059 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B0_PA_W3, 0x00ffff}, 1060 1061 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B1_PA_W0, 0x00ffff}, 1062 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B1_PA_W1, 0x00ffff}, 1063 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B1_PA_W2, 0x00ffff}, 1064 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B1_PA_W3, 0x00ffff}, 1065 1066 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B2_PA_W0, 0x00ffff}, 1067 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B2_PA_W1, 0x00ffff}, 1068 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B2_PA_W2, 0x00ffff}, 1069 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B2_PA_W3, 0x00ffff}, 1070 1071 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B3_PA_W0, 0x00ffff}, 1072 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B3_PA_W1, 0x00ffff}, 1073 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B3_PA_W2, 0x00ffff}, 1074 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B3_PA_W3, 0x00ffff}, 1075 1076 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B4_PA_W0, 0x00ffff}, 1077 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B4_PA_W1, 0x00ffff}, 1078 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B4_PA_W2, 0x00ffff}, 1079 {"", 0xfffff000, SRFL_PRHEX, SROM12_5G80B4_PA_W3, 0x00ffff}, 1080 /* sromrev 13 */ 1081 {"rxgains2gelnagaina", 0xffffe000, 0, SROM13_RXGAINS, 0x0007}, 1082 {"rxgains2gtrisoa", 0xffffe000, 0, SROM13_RXGAINS, 0x0078}, 1083 {"rxgains2gtrelnabypa", 0xffffe000, 0, SROM13_RXGAINS, 0x0080}, 1084 {"rxgains5gelnagaina", 0xffffe000, 0, SROM13_RXGAINS, 0x0700}, 1085 {"rxgains5gtrisoa", 0xffffe000, 0, SROM13_RXGAINS, 0x7800}, 1086 {"rxgains5gtrelnabypa", 0xffffe000, 0, SROM13_RXGAINS, 0x8000}, 1087 {NULL, 0, 0, 0, 0} 1088 }; 1089 1090 typedef struct { 1091 uint8 tag; /* Broadcom subtag name */ 1092 uint32 revmask; /* Supported cis_sromrev bitmask. Some of the parameters in 1093 * different tuples have the same name. Therefore, the MFGc tool 1094 * needs to know which tuple to generate when seeing these 1095 * parameters (given that we know sromrev from user input, like the 1096 * nvram file). 1097 */ 1098 uint8 len; /* Length field of the tuple, note that it includes the 1099 * subtag name (1 byte): 1 + tuple content length 1100 */ 1101 const char *params; /* Each param is in this form: length(1 byte ascii) + var name 1102 * Note that the order here has to match the parsing 1103 * order in parsecis() in src/shared/bcmsrom.c 1104 */ 1105 } cis_tuple_t; 1106 1107 #define OTP_RAW (0xff - 1) /* Reserved tuple number for wrvar Raw input */ 1108 /* quick hacks for supporting standard CIS tuples. */ 1109 #define OTP_VERS_1 (0xff - 2) /* CISTPL_VERS_1 */ 1110 #define OTP_MANFID (0xff - 3) /* CISTPL_MANFID */ 1111 #define OTP_RAW1 (0xff - 4) /* Like RAW, but comes first */ 1112 1113 /** this array is used by CIS creating/writing applications */ 1114 static const cis_tuple_t cis_hnbuvars[] = { 1115 /* tag revmask len params */ 1116 {OTP_RAW1, 0xffffffff, 0, ""}, /* special case */ 1117 {OTP_VERS_1, 0xffffffff, 0, "smanf sproductname"}, /* special case (non BRCM tuple) */ 1118 {OTP_MANFID, 0xffffffff, 4, "2manfid 2prodid"}, /* special case (non BRCM tuple) */ 1119 /* Unified OTP: tupple to embed USB manfid inside SDIO CIS */ 1120 {HNBU_UMANFID, 0xffffffff, 8, "8usbmanfid"}, 1121 {HNBU_SROMREV, 0xffffffff, 2, "1sromrev"}, 1122 /* NOTE: subdevid is also written to boardtype. 1123 * Need to write HNBU_BOARDTYPE to change it if it is different. 1124 */ 1125 {HNBU_CHIPID, 0xffffffff, 11, "2vendid 2devid 2chiprev 2subvendid 2subdevid"}, 1126 {HNBU_BOARDREV, 0xffffffff, 3, "2boardrev"}, 1127 {HNBU_PAPARMS, 0xffffffff, 10, "2pa0b0 2pa0b1 2pa0b2 1pa0itssit 1pa0maxpwr 1opo"}, 1128 {HNBU_AA, 0xffffffff, 3, "1aa2g 1aa5g"}, 1129 {HNBU_AA, 0xffffffff, 3, "1aa0 1aa1"}, /* backward compatibility */ 1130 {HNBU_AG, 0xffffffff, 5, "1ag0 1ag1 1ag2 1ag3"}, 1131 {HNBU_BOARDFLAGS, 0xffffffff, 21, "4boardflags 4boardflags2 4boardflags3 " 1132 "4boardflags4 4boardflags5 "}, 1133 {HNBU_CCODE, 0xffffffff, 4, "2ccode 1cctl"}, 1134 {HNBU_CCKPO, 0xffffffff, 3, "2cckpo"}, 1135 {HNBU_OFDMPO, 0xffffffff, 5, "4ofdmpo"}, 1136 {HNBU_PAPARMS5G, 0xffffffff, 23, "2pa1b0 2pa1b1 2pa1b2 2pa1lob0 2pa1lob1 2pa1lob2 " 1137 "2pa1hib0 2pa1hib1 2pa1hib2 1pa1itssit " 1138 "1pa1maxpwr 1pa1lomaxpwr 1pa1himaxpwr"}, 1139 {HNBU_RDLID, 0xffffffff, 3, "2rdlid"}, 1140 {HNBU_RSSISMBXA2G, 0xffffffff, 3, "0rssismf2g 0rssismc2g " 1141 "0rssisav2g 0bxa2g"}, /* special case */ 1142 {HNBU_RSSISMBXA5G, 0xffffffff, 3, "0rssismf5g 0rssismc5g " 1143 "0rssisav5g 0bxa5g"}, /* special case */ 1144 {HNBU_XTALFREQ, 0xffffffff, 5, "4xtalfreq"}, 1145 {HNBU_TRI2G, 0xffffffff, 2, "1tri2g"}, 1146 {HNBU_TRI5G, 0xffffffff, 4, "1tri5gl 1tri5g 1tri5gh"}, 1147 {HNBU_RXPO2G, 0xffffffff, 2, "1rxpo2g"}, 1148 {HNBU_RXPO5G, 0xffffffff, 2, "1rxpo5g"}, 1149 {HNBU_BOARDNUM, 0xffffffff, 3, "2boardnum"}, 1150 {HNBU_MACADDR, 0xffffffff, 7, "6macaddr"}, /* special case */ 1151 {HNBU_RDLSN, 0xffffffff, 3, "2rdlsn"}, 1152 {HNBU_BOARDTYPE, 0xffffffff, 3, "2boardtype"}, 1153 {HNBU_RDLRNDIS, 0xffffffff, 2, "1rdlndis"}, 1154 {HNBU_CHAINSWITCH, 0xffffffff, 5, "1txchain 1rxchain 2antswitch"}, 1155 {HNBU_REGREV, 0xffffffff, 3, "2regrev"}, 1156 {HNBU_FEM, 0x000007fe, 5, "0antswctl2g 0triso2g 0pdetrange2g 0extpagain2g " 1157 "0tssipos2g 0antswctl5g 0triso5g 0pdetrange5g 0extpagain5g 0tssipos5g"}, /* special case */ 1158 {HNBU_PAPARMS_C0, 0x000007fe, 31, "1maxp2ga0 1itt2ga0 2pa2gw0a0 2pa2gw1a0 " 1159 "2pa2gw2a0 1maxp5ga0 1itt5ga0 1maxp5gha0 1maxp5gla0 2pa5gw0a0 2pa5gw1a0 2pa5gw2a0 " 1160 "2pa5glw0a0 2pa5glw1a0 2pa5glw2a0 2pa5ghw0a0 2pa5ghw1a0 2pa5ghw2a0"}, 1161 {HNBU_PAPARMS_C1, 0x000007fe, 31, "1maxp2ga1 1itt2ga1 2pa2gw0a1 2pa2gw1a1 " 1162 "2pa2gw2a1 1maxp5ga1 1itt5ga1 1maxp5gha1 1maxp5gla1 2pa5gw0a1 2pa5gw1a1 2pa5gw2a1 " 1163 "2pa5glw0a1 2pa5glw1a1 2pa5glw2a1 2pa5ghw0a1 2pa5ghw1a1 2pa5ghw2a1"}, 1164 {HNBU_PO_CCKOFDM, 0xffffffff, 19, "2cck2gpo 4ofdm2gpo 4ofdm5gpo 4ofdm5glpo " 1165 "4ofdm5ghpo"}, 1166 {HNBU_PO_MCS2G, 0xffffffff, 17, "2mcs2gpo0 2mcs2gpo1 2mcs2gpo2 2mcs2gpo3 " 1167 "2mcs2gpo4 2mcs2gpo5 2mcs2gpo6 2mcs2gpo7"}, 1168 {HNBU_PO_MCS5GM, 0xffffffff, 17, "2mcs5gpo0 2mcs5gpo1 2mcs5gpo2 2mcs5gpo3 " 1169 "2mcs5gpo4 2mcs5gpo5 2mcs5gpo6 2mcs5gpo7"}, 1170 {HNBU_PO_MCS5GLH, 0xffffffff, 33, "2mcs5glpo0 2mcs5glpo1 2mcs5glpo2 2mcs5glpo3 " 1171 "2mcs5glpo4 2mcs5glpo5 2mcs5glpo6 2mcs5glpo7 " 1172 "2mcs5ghpo0 2mcs5ghpo1 2mcs5ghpo2 2mcs5ghpo3 " 1173 "2mcs5ghpo4 2mcs5ghpo5 2mcs5ghpo6 2mcs5ghpo7"}, 1174 {HNBU_CCKFILTTYPE, 0xffffffff, 2, "1cckdigfilttype"}, 1175 {HNBU_PO_CDD, 0xffffffff, 3, "2cddpo"}, 1176 {HNBU_PO_STBC, 0xffffffff, 3, "2stbcpo"}, 1177 {HNBU_PO_40M, 0xffffffff, 3, "2bw40po"}, 1178 {HNBU_PO_40MDUP, 0xffffffff, 3, "2bwduppo"}, 1179 {HNBU_RDLRWU, 0xffffffff, 2, "1rdlrwu"}, 1180 {HNBU_WPS, 0xffffffff, 3, "1wpsgpio 1wpsled"}, 1181 {HNBU_USBFS, 0xffffffff, 2, "1usbfs"}, 1182 {HNBU_ELNA2G, 0xffffffff, 2, "1elna2g"}, 1183 {HNBU_ELNA5G, 0xffffffff, 2, "1elna5g"}, 1184 {HNBU_CUSTOM1, 0xffffffff, 5, "4customvar1"}, 1185 {OTP_RAW, 0xffffffff, 0, ""}, /* special case */ 1186 {HNBU_OFDMPO5G, 0xffffffff, 13, "4ofdm5gpo 4ofdm5glpo 4ofdm5ghpo"}, 1187 {HNBU_USBEPNUM, 0xffffffff, 3, "2usbepnum"}, 1188 {HNBU_CCKBW202GPO, 0xffffffff, 7, "2cckbw202gpo 2cckbw20ul2gpo 2cckbw20in802gpo"}, 1189 {HNBU_LEGOFDMBW202GPO, 0xffffffff, 9, "4legofdmbw202gpo 4legofdmbw20ul2gpo"}, 1190 {HNBU_LEGOFDMBW205GPO, 0xffffffff, 25, "4legofdmbw205glpo 4legofdmbw20ul5glpo " 1191 "4legofdmbw205gmpo 4legofdmbw20ul5gmpo 4legofdmbw205ghpo 4legofdmbw20ul5ghpo"}, 1192 {HNBU_MCS2GPO, 0xffffffff, 17, "4mcsbw202gpo 4mcsbw20ul2gpo 4mcsbw402gpo 4mcsbw802gpo"}, 1193 {HNBU_MCS5GLPO, 0xffffffff, 13, "4mcsbw205glpo 4mcsbw20ul5glpo 4mcsbw405glpo"}, 1194 {HNBU_MCS5GMPO, 0xffffffff, 13, "4mcsbw205gmpo 4mcsbw20ul5gmpo 4mcsbw405gmpo"}, 1195 {HNBU_MCS5GHPO, 0xffffffff, 13, "4mcsbw205ghpo 4mcsbw20ul5ghpo 4mcsbw405ghpo"}, 1196 {HNBU_MCS32PO, 0xffffffff, 3, "2mcs32po"}, 1197 {HNBU_LEG40DUPPO, 0xffffffff, 3, "2legofdm40duppo"}, 1198 {HNBU_TEMPTHRESH, 0xffffffff, 7, "1tempthresh 0temps_period 0temps_hysteresis " 1199 "1tempoffset 1tempsense_slope 0tempcorrx 0tempsense_option " 1200 "1phycal_tempdelta"}, /* special case */ 1201 {HNBU_MUXENAB, 0xffffffff, 2, "1muxenab"}, 1202 {HNBU_FEM_CFG, 0xfffff800, 5, "0femctrl 0papdcap2g 0tworangetssi2g 0pdgain2g " 1203 "0epagain2g 0tssiposslope2g 0gainctrlsph 0papdcap5g 0tworangetssi5g 0pdgain5g 0epagain5g " 1204 "0tssiposslope5g"}, /* special case */ 1205 {HNBU_ACPA_C0, 0x00001800, 39, "2subband5gver 2maxp2ga0 2*3pa2ga0 " 1206 "1*4maxp5ga0 2*12pa5ga0"}, 1207 {HNBU_ACPA_C1, 0x00001800, 37, "2maxp2ga1 2*3pa2ga1 1*4maxp5ga1 2*12pa5ga1"}, 1208 {HNBU_ACPA_C2, 0x00001800, 37, "2maxp2ga2 2*3pa2ga2 1*4maxp5ga2 2*12pa5ga2"}, 1209 {HNBU_MEAS_PWR, 0xfffff800, 5, "1measpower 1measpower1 1measpower2 2rawtempsense"}, 1210 {HNBU_PDOFF, 0xfffff800, 13, "2pdoffset40ma0 2pdoffset40ma1 2pdoffset40ma2 " 1211 "2pdoffset80ma0 2pdoffset80ma1 2pdoffset80ma2"}, 1212 {HNBU_ACPPR_2GPO, 0xfffff800, 13, "2dot11agofdmhrbw202gpo 2ofdmlrbw202gpo " 1213 "2sb20in40dot11agofdm2gpo 2sb20in80dot11agofdm2gpo 2sb20in40ofdmlrbw202gpo " 1214 "2sb20in80ofdmlrbw202gpo"}, 1215 {HNBU_ACPPR_5GPO, 0xfffff800, 59, "4mcsbw805glpo 4mcsbw1605glpo 4mcsbw805gmpo " 1216 "4mcsbw1605gmpo 4mcsbw805ghpo 4mcsbw1605ghpo 2mcslr5glpo 2mcslr5gmpo 2mcslr5ghpo " 1217 "4mcsbw80p805glpo 4mcsbw80p805gmpo 4mcsbw80p805ghpo 4mcsbw80p805gx1po 2mcslr5gx1po " 1218 "2mcslr5g80p80po 4mcsbw805gx1po 4mcsbw1605gx1po"}, 1219 {HNBU_MCS5Gx1PO, 0xfffff800, 9, "4mcsbw205gx1po 4mcsbw405gx1po"}, 1220 {HNBU_ACPPR_SBPO, 0xfffff800, 49, "2sb20in40hrpo 2sb20in80and160hr5glpo " 1221 "2sb40and80hr5glpo 2sb20in80and160hr5gmpo 2sb40and80hr5gmpo 2sb20in80and160hr5ghpo " 1222 "2sb40and80hr5ghpo 2sb20in40lrpo 2sb20in80and160lr5glpo 2sb40and80lr5glpo " 1223 "2sb20in80and160lr5gmpo 2sb40and80lr5gmpo 2sb20in80and160lr5ghpo 2sb40and80lr5ghpo " 1224 "4dot11agduphrpo 4dot11agduplrpo 2sb20in40and80hrpo 2sb20in40and80lrpo " 1225 "2sb20in80and160hr5gx1po 2sb20in80and160lr5gx1po 2sb40and80hr5gx1po 2sb40and80lr5gx1po " 1226 }, 1227 {HNBU_ACPPR_SB8080_PO, 0xfffff800, 23, "2sb2040and80in80p80hr5glpo " 1228 "2sb2040and80in80p80lr5glpo 2sb2040and80in80p80hr5gmpo " 1229 "2sb2040and80in80p80lr5gmpo 2sb2040and80in80p80hr5ghpo 2sb2040and80in80p80lr5ghpo " 1230 "2sb2040and80in80p80hr5gx1po 2sb2040and80in80p80lr5gx1po 2sb20in80p80hr5gpo " 1231 "2sb20in80p80lr5gpo 2dot11agduppo"}, 1232 {HNBU_NOISELVL, 0xfffff800, 16, "1noiselvl2ga0 1noiselvl2ga1 1noiselvl2ga2 " 1233 "1*4noiselvl5ga0 1*4noiselvl5ga1 1*4noiselvl5ga2"}, 1234 {HNBU_RXGAIN_ERR, 0xfffff800, 16, "1rxgainerr2ga0 1rxgainerr2ga1 1rxgainerr2ga2 " 1235 "1*4rxgainerr5ga0 1*4rxgainerr5ga1 1*4rxgainerr5ga2"}, 1236 {HNBU_AGBGA, 0xfffff800, 7, "1agbg0 1agbg1 1agbg2 1aga0 1aga1 1aga2"}, 1237 {HNBU_USBDESC_COMPOSITE, 0xffffffff, 3, "2usbdesc_composite"}, 1238 {HNBU_UUID, 0xffffffff, 17, "16uuid"}, 1239 {HNBU_WOWLGPIO, 0xffffffff, 2, "1wowl_gpio"}, 1240 {HNBU_ACRXGAINS_C0, 0xfffff800, 5, "0rxgains5gtrelnabypa0 0rxgains5gtrisoa0 " 1241 "0rxgains5gelnagaina0 0rxgains2gtrelnabypa0 0rxgains2gtrisoa0 0rxgains2gelnagaina0 " 1242 "0rxgains5ghtrelnabypa0 0rxgains5ghtrisoa0 0rxgains5ghelnagaina0 0rxgains5gmtrelnabypa0 " 1243 "0rxgains5gmtrisoa0 0rxgains5gmelnagaina0"}, /* special case */ 1244 {HNBU_ACRXGAINS_C1, 0xfffff800, 5, "0rxgains5gtrelnabypa1 0rxgains5gtrisoa1 " 1245 "0rxgains5gelnagaina1 0rxgains2gtrelnabypa1 0rxgains2gtrisoa1 0rxgains2gelnagaina1 " 1246 "0rxgains5ghtrelnabypa1 0rxgains5ghtrisoa1 0rxgains5ghelnagaina1 0rxgains5gmtrelnabypa1 " 1247 "0rxgains5gmtrisoa1 0rxgains5gmelnagaina1"}, /* special case */ 1248 {HNBU_ACRXGAINS_C2, 0xfffff800, 5, "0rxgains5gtrelnabypa2 0rxgains5gtrisoa2 " 1249 "0rxgains5gelnagaina2 0rxgains2gtrelnabypa2 0rxgains2gtrisoa2 0rxgains2gelnagaina2 " 1250 "0rxgains5ghtrelnabypa2 0rxgains5ghtrisoa2 0rxgains5ghelnagaina2 0rxgains5gmtrelnabypa2 " 1251 "0rxgains5gmtrisoa2 0rxgains5gmelnagaina2"}, /* special case */ 1252 {HNBU_TXDUTY, 0xfffff800, 9, "2tx_duty_cycle_ofdm_40_5g " 1253 "2tx_duty_cycle_thresh_40_5g 2tx_duty_cycle_ofdm_80_5g 2tx_duty_cycle_thresh_80_5g"}, 1254 {HNBU_PDOFF_2G, 0xfffff800, 3, "0pdoffset2g40ma0 0pdoffset2g40ma1 " 1255 "0pdoffset2g40ma2 0pdoffset2g40mvalid"}, 1256 {HNBU_ACPA_CCK_C0, 0xfffff800, 7, "2*3pa2gccka0"}, 1257 {HNBU_ACPA_CCK_C1, 0xfffff800, 7, "2*3pa2gccka1"}, 1258 {HNBU_ACPA_40, 0xfffff800, 25, "2*12pa5gbw40a0"}, 1259 {HNBU_ACPA_80, 0xfffff800, 25, "2*12pa5gbw80a0"}, 1260 {HNBU_ACPA_4080, 0xfffff800, 49, "2*12pa5gbw4080a0 2*12pa5gbw4080a1"}, 1261 {HNBU_ACPA_4X4C0, 0xffffe000, 23, "1maxp2ga0 2*4pa2ga0 2*4pa2g40a0 " 1262 "1maxp5gb0a0 1maxp5gb1a0 1maxp5gb2a0 1maxp5gb3a0 1maxp5gb4a0"}, 1263 {HNBU_ACPA_4X4C1, 0xffffe000, 23, "1maxp2ga1 2*4pa2ga1 2*4pa2g40a1 " 1264 "1maxp5gb0a1 1maxp5gb1a1 1maxp5gb2a1 1maxp5gb3a1 1maxp5gb4a1"}, 1265 {HNBU_ACPA_4X4C2, 0xffffe000, 23, "1maxp2ga2 2*4pa2ga2 2*4pa2g40a2 " 1266 "1maxp5gb0a2 1maxp5gb1a2 1maxp5gb2a2 1maxp5gb3a2 1maxp5gb4a2"}, 1267 {HNBU_ACPA_4X4C3, 0xffffe000, 23, "1maxp2ga3 2*4pa2ga3 2*4pa2g40a3 " 1268 "1maxp5gb0a3 1maxp5gb1a3 1maxp5gb2a3 1maxp5gb3a3 1maxp5gb4a3"}, 1269 {HNBU_ACPA_BW20_4X4C0, 0xffffe000, 41, "2*20pa5ga0"}, 1270 {HNBU_ACPA_BW40_4X4C0, 0xffffe000, 41, "2*20pa5g40a0"}, 1271 {HNBU_ACPA_BW80_4X4C0, 0xffffe000, 41, "2*20pa5g80a0"}, 1272 {HNBU_ACPA_BW20_4X4C1, 0xffffe000, 41, "2*20pa5ga1"}, 1273 {HNBU_ACPA_BW40_4X4C1, 0xffffe000, 41, "2*20pa5g40a1"}, 1274 {HNBU_ACPA_BW80_4X4C1, 0xffffe000, 41, "2*20pa5g80a1"}, 1275 {HNBU_ACPA_BW20_4X4C2, 0xffffe000, 41, "2*20pa5ga2"}, 1276 {HNBU_ACPA_BW40_4X4C2, 0xffffe000, 41, "2*20pa5g40a2"}, 1277 {HNBU_ACPA_BW80_4X4C2, 0xffffe000, 41, "2*20pa5g80a2"}, 1278 {HNBU_ACPA_BW20_4X4C3, 0xffffe000, 41, "2*20pa5ga3"}, 1279 {HNBU_ACPA_BW40_4X4C3, 0xffffe000, 41, "2*20pa5g40a3"}, 1280 {HNBU_ACPA_BW80_4X4C3, 0xffffe000, 41, "2*20pa5g80a3"}, 1281 {HNBU_SUBBAND5GVER, 0xfffff800, 3, "2subband5gver"}, 1282 {HNBU_PAPARAMBWVER, 0xfffff800, 2, "1paparambwver"}, 1283 {HNBU_TXBFRPCALS, 0xfffff800, 11, 1284 "2rpcal2g 2rpcal5gb0 2rpcal5gb1 2rpcal5gb2 2rpcal5gb3"}, /* txbf rpcalvars */ 1285 {HNBU_GPIO_PULL_DOWN, 0xffffffff, 5, "4gpdn"}, 1286 {HNBU_MACADDR2, 0xffffffff, 7, "6macaddr2"}, /* special case */ 1287 {HNBU_RSSI_DELTA_2G_B0, 0xffffffff, 17, "1*16rssi_delta_2gb0"}, 1288 {HNBU_RSSI_DELTA_2G_B1, 0xffffffff, 17, "1*16rssi_delta_2gb1"}, 1289 {HNBU_RSSI_DELTA_2G_B2, 0xffffffff, 17, "1*16rssi_delta_2gb2"}, 1290 {HNBU_RSSI_DELTA_2G_B3, 0xffffffff, 17, "1*16rssi_delta_2gb3"}, 1291 {HNBU_RSSI_DELTA_2G_B4, 0xffffffff, 17, "1*16rssi_delta_2gb4"}, 1292 {HNBU_RSSI_CAL_FREQ_GRP_2G, 0xffffffff, 8, "1*7rssi_cal_freq_grp"}, 1293 {HNBU_RSSI_DELTA_5GL, 0xffffffff, 25, "1*24rssi_delta_5gl"}, 1294 {HNBU_RSSI_DELTA_5GML, 0xffffffff, 25, "1*24rssi_delta_5gml"}, 1295 {HNBU_RSSI_DELTA_5GMU, 0xffffffff, 25, "1*24rssi_delta_5gmu"}, 1296 {HNBU_RSSI_DELTA_5GH, 0xffffffff, 25, "1*24rssi_delta_5gh"}, 1297 {HNBU_ACPA_6G_C0, 0x00000800, 45, "2subband6gver 1*6maxp6ga0 2*18pa6ga0 "}, 1298 {HNBU_ACPA_6G_C1, 0x00000800, 43, "1*6maxp6ga1 2*18pa6ga1 "}, 1299 {HNBU_ACPA_6G_C2, 0x00000800, 43, "1*6maxp6ga2 2*18pa6ga2 "}, 1300 {0xFF, 0xffffffff, 0, ""} 1301 }; 1302 1303 #endif /* _bcmsrom_tbl_h_ */ 1304