1 /* 2 * SROM format definition. 3 * 4 * Copyright (C) 2020, Broadcom. 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * 21 * <<Broadcom-WL-IPTag/Dual:>> 22 */ 23 24 #ifndef _bcmsrom_fmt_h_ 25 #define _bcmsrom_fmt_h_ 26 27 #define SROM_MAXREV 18 /* max revision supported by driver */ 28 29 /* Maximum srom: 16 Kilobits == 2048 bytes */ 30 31 #define SROM_MAX 2048 32 #define SROM_MAXW 1024 33 34 #ifdef LARGE_NVRAM_MAXSZ 35 #define VARS_MAX LARGE_NVRAM_MAXSZ 36 #else 37 #if defined(BCMROMBUILD) || defined(DONGLEBUILD) 38 #define VARS_MAX 4096 39 #else 40 #define LARGE_NVRAM_MAXSZ 8192 41 #define VARS_MAX LARGE_NVRAM_MAXSZ 42 #endif /* BCMROMBUILD || DONGLEBUILD */ 43 #endif /* LARGE_NVRAM_MAXSZ */ 44 45 /* PCI fields */ 46 #define PCI_F0DEVID 48 47 48 /* SROM Rev 2: 1 Kilobit map for 11a/b/g devices. 49 * SROM Rev 3: Upward compatible modification for lpphy and PCIe 50 * hardware workaround. 51 */ 52 53 #define SROM_WORDS 64 54 #define SROM_SIGN_MINWORDS 128 55 #define SROM3_SWRGN_OFF 28 /* s/w region offset in words */ 56 57 #define SROM_SSID 2 58 #define SROM_SVID 3 59 60 #define SROM_WL1LHMAXP 29 61 62 #define SROM_WL1LPAB0 30 63 #define SROM_WL1LPAB1 31 64 #define SROM_WL1LPAB2 32 65 66 #define SROM_WL1HPAB0 33 67 #define SROM_WL1HPAB1 34 68 #define SROM_WL1HPAB2 35 69 70 #define SROM_MACHI_IL0 36 71 #define SROM_MACMID_IL0 37 72 #define SROM_MACLO_IL0 38 73 #define SROM_MACHI_ET0 39 74 #define SROM_MACMID_ET0 40 75 #define SROM_MACLO_ET0 41 76 #define SROM_MACHI_ET1 42 77 #define SROM_MACMID_ET1 43 78 #define SROM_MACLO_ET1 44 79 #define SROM3_MACHI 37 80 #define SROM3_MACMID 38 81 #define SROM3_MACLO 39 82 83 #define SROM_BXARSSI2G 40 84 #define SROM_BXARSSI5G 41 85 86 #define SROM_TRI52G 42 87 #define SROM_TRI5GHL 43 88 89 #define SROM_RXPO52G 45 90 91 #define SROM2_ENETPHY 45 92 93 #define SROM_AABREV 46 94 /* Fields in AABREV */ 95 #define SROM_BR_MASK 0x00ff 96 #define SROM_CC_MASK 0x0f00 97 #define SROM_CC_SHIFT 8 98 #define SROM_AA0_MASK 0x3000 99 #define SROM_AA0_SHIFT 12 100 #define SROM_AA1_MASK 0xc000 101 #define SROM_AA1_SHIFT 14 102 103 #define SROM_WL0PAB0 47 104 #define SROM_WL0PAB1 48 105 #define SROM_WL0PAB2 49 106 107 #define SROM_LEDBH10 50 108 #define SROM_LEDBH32 51 109 110 #define SROM_WL10MAXP 52 111 112 #define SROM_WL1PAB0 53 113 #define SROM_WL1PAB1 54 114 #define SROM_WL1PAB2 55 115 116 #define SROM_ITT 56 117 118 #define SROM_BFL 57 119 #define SROM_BFL2 28 120 #define SROM3_BFL2 61 121 122 #define SROM_AG10 58 123 124 #define SROM_CCODE 59 125 126 #define SROM_OPO 60 127 128 #define SROM3_LEDDC 62 129 130 #define SROM_CRCREV 63 131 132 /* SROM Rev 4: Reallocate the software part of the srom to accomodate 133 * MIMO features. It assumes up to two PCIE functions and 440 bytes 134 * of useable srom i.e. the useable storage in chips with OTP that 135 * implements hardware redundancy. 136 */ 137 138 #define SROM4_WORDS 220 139 140 #define SROM4_SIGN 32 141 #define SROM4_SIGNATURE 0x5372 142 143 #define SROM4_BREV 33 144 145 #define SROM4_BFL0 34 146 #define SROM4_BFL1 35 147 #define SROM4_BFL2 36 148 #define SROM4_BFL3 37 149 #define SROM5_BFL0 37 150 #define SROM5_BFL1 38 151 #define SROM5_BFL2 39 152 #define SROM5_BFL3 40 153 154 #define SROM4_MACHI 38 155 #define SROM4_MACMID 39 156 #define SROM4_MACLO 40 157 #define SROM5_MACHI 41 158 #define SROM5_MACMID 42 159 #define SROM5_MACLO 43 160 161 #define SROM4_CCODE 41 162 #define SROM4_REGREV 42 163 #define SROM5_CCODE 34 164 #define SROM5_REGREV 35 165 166 #define SROM4_LEDBH10 43 167 #define SROM4_LEDBH32 44 168 #define SROM5_LEDBH10 59 169 #define SROM5_LEDBH32 60 170 171 #define SROM4_LEDDC 45 172 #define SROM5_LEDDC 45 173 174 #define SROM4_AA 46 175 #define SROM4_AA2G_MASK 0x00ff 176 #define SROM4_AA2G_SHIFT 0 177 #define SROM4_AA5G_MASK 0xff00 178 #define SROM4_AA5G_SHIFT 8 179 180 #define SROM4_AG10 47 181 #define SROM4_AG32 48 182 183 #define SROM4_TXPID2G 49 184 #define SROM4_TXPID5G 51 185 #define SROM4_TXPID5GL 53 186 #define SROM4_TXPID5GH 55 187 188 #define SROM4_TXRXC 61 189 #define SROM4_TXCHAIN_MASK 0x000f 190 #define SROM4_TXCHAIN_SHIFT 0 191 #define SROM4_RXCHAIN_MASK 0x00f0 192 #define SROM4_RXCHAIN_SHIFT 4 193 #define SROM4_SWITCH_MASK 0xff00 194 #define SROM4_SWITCH_SHIFT 8 195 196 /* Per-path fields */ 197 #define MAX_PATH_SROM 4 198 #define SROM4_PATH0 64 199 #define SROM4_PATH1 87 200 #define SROM4_PATH2 110 201 #define SROM4_PATH3 133 202 203 #define SROM4_2G_ITT_MAXP 0 204 #define SROM4_2G_PA 1 205 #define SROM4_5G_ITT_MAXP 5 206 #define SROM4_5GLH_MAXP 6 207 #define SROM4_5G_PA 7 208 #define SROM4_5GL_PA 11 209 #define SROM4_5GH_PA 15 210 211 /* Fields in the ITT_MAXP and 5GLH_MAXP words */ 212 #define B2G_MAXP_MASK 0xff 213 #define B2G_ITT_SHIFT 8 214 #define B5G_MAXP_MASK 0xff 215 #define B5G_ITT_SHIFT 8 216 #define B5GH_MAXP_MASK 0xff 217 #define B5GL_MAXP_SHIFT 8 218 219 /* All the miriad power offsets */ 220 #define SROM4_2G_CCKPO 156 221 #define SROM4_2G_OFDMPO 157 222 #define SROM4_5G_OFDMPO 159 223 #define SROM4_5GL_OFDMPO 161 224 #define SROM4_5GH_OFDMPO 163 225 #define SROM4_2G_MCSPO 165 226 #define SROM4_5G_MCSPO 173 227 #define SROM4_5GL_MCSPO 181 228 #define SROM4_5GH_MCSPO 189 229 #define SROM4_CDDPO 197 230 #define SROM4_STBCPO 198 231 #define SROM4_BW40PO 199 232 #define SROM4_BWDUPPO 200 233 234 #define SROM4_CRCREV 219 235 236 /* SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6. 237 * This is acombined srom for both MIMO and SISO boards, usable in 238 * the .130 4Kilobit OTP with hardware redundancy. 239 */ 240 241 #define SROM8_SIGN 64 242 243 #define SROM8_BREV 65 244 245 #define SROM8_BFL0 66 246 #define SROM8_BFL1 67 247 #define SROM8_BFL2 68 248 #define SROM8_BFL3 69 249 250 #define SROM8_MACHI 70 251 #define SROM8_MACMID 71 252 #define SROM8_MACLO 72 253 254 #define SROM8_CCODE 73 255 #define SROM8_REGREV 74 256 257 #define SROM8_LEDBH10 75 258 #define SROM8_LEDBH32 76 259 260 #define SROM8_LEDDC 77 261 262 #define SROM8_AA 78 263 264 #define SROM8_AG10 79 265 #define SROM8_AG32 80 266 267 #define SROM8_TXRXC 81 268 269 #define SROM8_BXARSSI2G 82 270 #define SROM8_BXARSSI5G 83 271 #define SROM8_TRI52G 84 272 #define SROM8_TRI5GHL 85 273 #define SROM8_RXPO52G 86 274 275 #define SROM8_FEM2G 87 276 #define SROM8_FEM5G 88 277 #define SROM8_FEM_ANTSWLUT_MASK 0xf800 278 #define SROM8_FEM_ANTSWLUT_SHIFT 11 279 #define SROM8_FEM_TR_ISO_MASK 0x0700 280 #define SROM8_FEM_TR_ISO_SHIFT 8 281 #define SROM8_FEM_PDET_RANGE_MASK 0x00f8 282 #define SROM8_FEM_PDET_RANGE_SHIFT 3 283 #define SROM8_FEM_EXTPA_GAIN_MASK 0x0006 284 #define SROM8_FEM_EXTPA_GAIN_SHIFT 1 285 #define SROM8_FEM_TSSIPOS_MASK 0x0001 286 #define SROM8_FEM_TSSIPOS_SHIFT 0 287 288 #define SROM8_THERMAL 89 289 290 /* Temp sense related entries */ 291 #define SROM8_MPWR_RAWTS 90 292 #define SROM8_TS_SLP_OPT_CORRX 91 293 /* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */ 294 #define SROM8_FOC_HWIQ_IQSWP 92 295 296 #define SROM8_EXTLNAGAIN 93 297 298 /* Temperature delta for PHY calibration */ 299 #define SROM8_PHYCAL_TEMPDELTA 94 300 301 /* Measured power 1 & 2, 0-13 bits at offset 95, MSB 2 bits are unused for now. */ 302 #define SROM8_MPWR_1_AND_2 95 303 304 /* Per-path offsets & fields */ 305 #define SROM8_PATH0 96 306 #define SROM8_PATH1 112 307 #define SROM8_PATH2 128 308 #define SROM8_PATH3 144 309 310 #define SROM8_2G_ITT_MAXP 0 311 #define SROM8_2G_PA 1 312 #define SROM8_5G_ITT_MAXP 4 313 #define SROM8_5GLH_MAXP 5 314 #define SROM8_5G_PA 6 315 #define SROM8_5GL_PA 9 316 #define SROM8_5GH_PA 12 317 318 /* All the miriad power offsets */ 319 #define SROM8_2G_CCKPO 160 320 321 #define SROM8_2G_OFDMPO 161 322 #define SROM8_5G_OFDMPO 163 323 #define SROM8_5GL_OFDMPO 165 324 #define SROM8_5GH_OFDMPO 167 325 326 #define SROM8_2G_MCSPO 169 327 #define SROM8_5G_MCSPO 177 328 #define SROM8_5GL_MCSPO 185 329 #define SROM8_5GH_MCSPO 193 330 331 #define SROM8_CDDPO 201 332 #define SROM8_STBCPO 202 333 #define SROM8_BW40PO 203 334 #define SROM8_BWDUPPO 204 335 336 /* SISO PA parameters are in the path0 spaces */ 337 #define SROM8_SISO 96 338 339 /* Legacy names for SISO PA paramters */ 340 #define SROM8_W0_ITTMAXP (SROM8_SISO + SROM8_2G_ITT_MAXP) 341 #define SROM8_W0_PAB0 (SROM8_SISO + SROM8_2G_PA) 342 #define SROM8_W0_PAB1 (SROM8_SISO + SROM8_2G_PA + 1) 343 #define SROM8_W0_PAB2 (SROM8_SISO + SROM8_2G_PA + 2) 344 #define SROM8_W1_ITTMAXP (SROM8_SISO + SROM8_5G_ITT_MAXP) 345 #define SROM8_W1_MAXP_LCHC (SROM8_SISO + SROM8_5GLH_MAXP) 346 #define SROM8_W1_PAB0 (SROM8_SISO + SROM8_5G_PA) 347 #define SROM8_W1_PAB1 (SROM8_SISO + SROM8_5G_PA + 1) 348 #define SROM8_W1_PAB2 (SROM8_SISO + SROM8_5G_PA + 2) 349 #define SROM8_W1_PAB0_LC (SROM8_SISO + SROM8_5GL_PA) 350 #define SROM8_W1_PAB1_LC (SROM8_SISO + SROM8_5GL_PA + 1) 351 #define SROM8_W1_PAB2_LC (SROM8_SISO + SROM8_5GL_PA + 2) 352 #define SROM8_W1_PAB0_HC (SROM8_SISO + SROM8_5GH_PA) 353 #define SROM8_W1_PAB1_HC (SROM8_SISO + SROM8_5GH_PA + 1) 354 #define SROM8_W1_PAB2_HC (SROM8_SISO + SROM8_5GH_PA + 2) 355 356 #define SROM8_CRCREV 219 357 358 /* SROM REV 9 */ 359 #define SROM9_2GPO_CCKBW20 160 360 #define SROM9_2GPO_CCKBW20UL 161 361 #define SROM9_2GPO_LOFDMBW20 162 362 #define SROM9_2GPO_LOFDMBW20UL 164 363 364 #define SROM9_5GLPO_LOFDMBW20 166 365 #define SROM9_5GLPO_LOFDMBW20UL 168 366 #define SROM9_5GMPO_LOFDMBW20 170 367 #define SROM9_5GMPO_LOFDMBW20UL 172 368 #define SROM9_5GHPO_LOFDMBW20 174 369 #define SROM9_5GHPO_LOFDMBW20UL 176 370 371 #define SROM9_2GPO_MCSBW20 178 372 #define SROM9_2GPO_MCSBW20UL 180 373 #define SROM9_2GPO_MCSBW40 182 374 375 #define SROM9_5GLPO_MCSBW20 184 376 #define SROM9_5GLPO_MCSBW20UL 186 377 #define SROM9_5GLPO_MCSBW40 188 378 #define SROM9_5GMPO_MCSBW20 190 379 #define SROM9_5GMPO_MCSBW20UL 192 380 #define SROM9_5GMPO_MCSBW40 194 381 #define SROM9_5GHPO_MCSBW20 196 382 #define SROM9_5GHPO_MCSBW20UL 198 383 #define SROM9_5GHPO_MCSBW40 200 384 385 #define SROM9_PO_MCS32 202 386 #define SROM9_PO_LOFDM40DUP 203 387 #define SROM9_EU_EDCRSTH 204 388 #define SROM10_EU_EDCRSTH 204 389 #define SROM8_RXGAINERR_2G 205 390 #define SROM8_RXGAINERR_5GL 206 391 #define SROM8_RXGAINERR_5GM 207 392 #define SROM8_RXGAINERR_5GH 208 393 #define SROM8_RXGAINERR_5GU 209 394 #define SROM8_SUBBAND_PPR 210 395 #define SROM8_PCIEINGRESS_WAR 211 396 #define SROM8_EU_EDCRSTH 212 397 #define SROM9_SAR 212 398 399 #define SROM8_NOISELVL_2G 213 400 #define SROM8_NOISELVL_5GL 214 401 #define SROM8_NOISELVL_5GM 215 402 #define SROM8_NOISELVL_5GH 216 403 #define SROM8_NOISELVL_5GU 217 404 #define SROM8_NOISECALOFFSET 218 405 406 #define SROM9_REV_CRC 219 407 408 #define SROM10_CCKPWROFFSET 218 409 #define SROM10_SIGN 219 410 #define SROM10_SWCTRLMAP_2G 220 411 #define SROM10_CRCREV 229 412 413 #define SROM10_WORDS 230 414 #define SROM10_SIGNATURE SROM4_SIGNATURE 415 416 /* SROM REV 11 */ 417 #define SROM11_BREV 65 418 419 #define SROM11_BFL0 66 420 #define SROM11_BFL1 67 421 #define SROM11_BFL2 68 422 #define SROM11_BFL3 69 423 #define SROM11_BFL4 70 424 #define SROM11_BFL5 71 425 426 #define SROM11_MACHI 72 427 #define SROM11_MACMID 73 428 #define SROM11_MACLO 74 429 430 #define SROM11_CCODE 75 431 #define SROM11_REGREV 76 432 433 #define SROM11_LEDBH10 77 434 #define SROM11_LEDBH32 78 435 436 #define SROM11_LEDDC 79 437 438 #define SROM11_AA 80 439 440 #define SROM11_AGBG10 81 441 #define SROM11_AGBG2A0 82 442 #define SROM11_AGA21 83 443 444 #define SROM11_TXRXC 84 445 446 #define SROM11_FEM_CFG1 85 447 #define SROM11_FEM_CFG2 86 448 449 /* Masks and offsets for FEM_CFG */ 450 #define SROM11_FEMCTRL_MASK 0xf800 451 #define SROM11_FEMCTRL_SHIFT 11 452 #define SROM11_PAPDCAP_MASK 0x0400 453 #define SROM11_PAPDCAP_SHIFT 10 454 #define SROM11_TWORANGETSSI_MASK 0x0200 455 #define SROM11_TWORANGETSSI_SHIFT 9 456 #define SROM11_PDGAIN_MASK 0x01f0 457 #define SROM11_PDGAIN_SHIFT 4 458 #define SROM11_EPAGAIN_MASK 0x000e 459 #define SROM11_EPAGAIN_SHIFT 1 460 #define SROM11_TSSIPOSSLOPE_MASK 0x0001 461 #define SROM11_TSSIPOSSLOPE_SHIFT 0 462 #define SROM11_GAINCTRLSPH_MASK 0xf800 463 #define SROM11_GAINCTRLSPH_SHIFT 11 464 465 #define SROM11_THERMAL 87 466 #define SROM11_MPWR_RAWTS 88 467 #define SROM11_TS_SLP_OPT_CORRX 89 468 #define SROM11_XTAL_FREQ 90 469 #define SROM11_5GB0_4080_W0_A1 91 470 #define SROM11_PHYCAL_TEMPDELTA 92 471 #define SROM11_MPWR_1_AND_2 93 472 #define SROM11_5GB0_4080_W1_A1 94 473 #define SROM11_TSSIFLOOR_2G 95 474 #define SROM11_TSSIFLOOR_5GL 96 475 #define SROM11_TSSIFLOOR_5GM 97 476 #define SROM11_TSSIFLOOR_5GH 98 477 #define SROM11_TSSIFLOOR_5GU 99 478 479 /* Masks and offsets for Thermal parameters */ 480 #define SROM11_TEMPS_PERIOD_MASK 0xf0 481 #define SROM11_TEMPS_PERIOD_SHIFT 4 482 #define SROM11_TEMPS_HYSTERESIS_MASK 0x0f 483 #define SROM11_TEMPS_HYSTERESIS_SHIFT 0 484 #define SROM11_TEMPCORRX_MASK 0xfc 485 #define SROM11_TEMPCORRX_SHIFT 2 486 #define SROM11_TEMPSENSE_OPTION_MASK 0x3 487 #define SROM11_TEMPSENSE_OPTION_SHIFT 0 488 489 #define SROM11_PDOFF_2G_40M_A0_MASK 0x000f 490 #define SROM11_PDOFF_2G_40M_A0_SHIFT 0 491 #define SROM11_PDOFF_2G_40M_A1_MASK 0x00f0 492 #define SROM11_PDOFF_2G_40M_A1_SHIFT 4 493 #define SROM11_PDOFF_2G_40M_A2_MASK 0x0f00 494 #define SROM11_PDOFF_2G_40M_A2_SHIFT 8 495 #define SROM11_PDOFF_2G_40M_VALID_MASK 0x8000 496 #define SROM11_PDOFF_2G_40M_VALID_SHIFT 15 497 498 #define SROM11_PDOFF_2G_40M 100 499 #define SROM11_PDOFF_40M_A0 101 500 #define SROM11_PDOFF_40M_A1 102 501 #define SROM11_PDOFF_40M_A2 103 502 #define SROM11_5GB0_4080_W2_A1 103 503 #define SROM11_PDOFF_80M_A0 104 504 #define SROM11_PDOFF_80M_A1 105 505 #define SROM11_PDOFF_80M_A2 106 506 #define SROM11_5GB1_4080_W0_A1 106 507 508 #define SROM11_SUBBAND5GVER 107 509 510 /* Per-path fields and offset */ 511 #define MAX_PATH_SROM_11 3 512 #define SROM11_PATH0 108 513 #define SROM11_PATH1 128 514 #define SROM11_PATH2 148 515 516 #define SROM11_2G_MAXP 0 517 #define SROM11_5GB1_4080_PA 0 518 #define SROM11_2G_PA 1 519 #define SROM11_5GB2_4080_PA 2 520 #define SROM11_RXGAINS1 4 521 #define SROM11_RXGAINS 5 522 #define SROM11_5GB3_4080_PA 5 523 #define SROM11_5GB1B0_MAXP 6 524 #define SROM11_5GB3B2_MAXP 7 525 #define SROM11_5GB0_PA 8 526 #define SROM11_5GB1_PA 11 527 #define SROM11_5GB2_PA 14 528 #define SROM11_5GB3_PA 17 529 530 /* Masks and offsets for rxgains */ 531 #define SROM11_RXGAINS5GTRELNABYPA_MASK 0x8000 532 #define SROM11_RXGAINS5GTRELNABYPA_SHIFT 15 533 #define SROM11_RXGAINS5GTRISOA_MASK 0x7800 534 #define SROM11_RXGAINS5GTRISOA_SHIFT 11 535 #define SROM11_RXGAINS5GELNAGAINA_MASK 0x0700 536 #define SROM11_RXGAINS5GELNAGAINA_SHIFT 8 537 #define SROM11_RXGAINS2GTRELNABYPA_MASK 0x0080 538 #define SROM11_RXGAINS2GTRELNABYPA_SHIFT 7 539 #define SROM11_RXGAINS2GTRISOA_MASK 0x0078 540 #define SROM11_RXGAINS2GTRISOA_SHIFT 3 541 #define SROM11_RXGAINS2GELNAGAINA_MASK 0x0007 542 #define SROM11_RXGAINS2GELNAGAINA_SHIFT 0 543 #define SROM11_RXGAINS5GHTRELNABYPA_MASK 0x8000 544 #define SROM11_RXGAINS5GHTRELNABYPA_SHIFT 15 545 #define SROM11_RXGAINS5GHTRISOA_MASK 0x7800 546 #define SROM11_RXGAINS5GHTRISOA_SHIFT 11 547 #define SROM11_RXGAINS5GHELNAGAINA_MASK 0x0700 548 #define SROM11_RXGAINS5GHELNAGAINA_SHIFT 8 549 #define SROM11_RXGAINS5GMTRELNABYPA_MASK 0x0080 550 #define SROM11_RXGAINS5GMTRELNABYPA_SHIFT 7 551 #define SROM11_RXGAINS5GMTRISOA_MASK 0x0078 552 #define SROM11_RXGAINS5GMTRISOA_SHIFT 3 553 #define SROM11_RXGAINS5GMELNAGAINA_MASK 0x0007 554 #define SROM11_RXGAINS5GMELNAGAINA_SHIFT 0 555 556 /* Power per rate */ 557 #define SROM11_CCKBW202GPO 168 558 #define SROM11_CCKBW20UL2GPO 169 559 #define SROM11_MCSBW202GPO 170 560 #define SROM11_MCSBW202GPO_1 171 561 #define SROM11_MCSBW402GPO 172 562 #define SROM11_MCSBW402GPO_1 173 563 #define SROM11_DOT11AGOFDMHRBW202GPO 174 564 #define SROM11_OFDMLRBW202GPO 175 565 566 #define SROM11_MCSBW205GLPO 176 567 #define SROM11_MCSBW205GLPO_1 177 568 #define SROM11_MCSBW405GLPO 178 569 #define SROM11_MCSBW405GLPO_1 179 570 #define SROM11_MCSBW805GLPO 180 571 #define SROM11_MCSBW805GLPO_1 181 572 #define SROM11_RPCAL_2G 182 573 #define SROM11_RPCAL_5GL 183 574 #define SROM11_MCSBW205GMPO 184 575 #define SROM11_MCSBW205GMPO_1 185 576 #define SROM11_MCSBW405GMPO 186 577 #define SROM11_MCSBW405GMPO_1 187 578 #define SROM11_MCSBW805GMPO 188 579 #define SROM11_MCSBW805GMPO_1 189 580 #define SROM11_RPCAL_5GM 190 581 #define SROM11_RPCAL_5GH 191 582 #define SROM11_MCSBW205GHPO 192 583 #define SROM11_MCSBW205GHPO_1 193 584 #define SROM11_MCSBW405GHPO 194 585 #define SROM11_MCSBW405GHPO_1 195 586 #define SROM11_MCSBW805GHPO 196 587 #define SROM11_MCSBW805GHPO_1 197 588 #define SROM11_RPCAL_5GU 198 589 #define SROM11_PDOFF_2G_CCK 199 590 #define SROM11_MCSLR5GLPO 200 591 #define SROM11_MCSLR5GMPO 201 592 #define SROM11_MCSLR5GHPO 202 593 594 #define SROM11_SB20IN40HRPO 203 595 #define SROM11_SB20IN80AND160HR5GLPO 204 596 #define SROM11_SB40AND80HR5GLPO 205 597 #define SROM11_SB20IN80AND160HR5GMPO 206 598 #define SROM11_SB40AND80HR5GMPO 207 599 #define SROM11_SB20IN80AND160HR5GHPO 208 600 #define SROM11_SB40AND80HR5GHPO 209 601 #define SROM11_SB20IN40LRPO 210 602 #define SROM11_SB20IN80AND160LR5GLPO 211 603 #define SROM11_SB40AND80LR5GLPO 212 604 #define SROM11_TXIDXCAP2G 212 605 #define SROM11_SB20IN80AND160LR5GMPO 213 606 #define SROM11_SB40AND80LR5GMPO 214 607 #define SROM11_TXIDXCAP5G 214 608 #define SROM11_SB20IN80AND160LR5GHPO 215 609 #define SROM11_SB40AND80LR5GHPO 216 610 611 #define SROM11_DOT11AGDUPHRPO 217 612 #define SROM11_DOT11AGDUPLRPO 218 613 614 /* MISC */ 615 #define SROM11_PCIEINGRESS_WAR 220 616 #define SROM11_SAR 221 617 618 #define SROM11_NOISELVL_2G 222 619 #define SROM11_NOISELVL_5GL 223 620 #define SROM11_NOISELVL_5GM 224 621 #define SROM11_NOISELVL_5GH 225 622 #define SROM11_NOISELVL_5GU 226 623 624 #define SROM11_RXGAINERR_2G 227 625 #define SROM11_RXGAINERR_5GL 228 626 #define SROM11_RXGAINERR_5GM 229 627 #define SROM11_RXGAINERR_5GH 230 628 #define SROM11_RXGAINERR_5GU 231 629 630 #define SROM11_EU_EDCRSTH 232 631 #define SROM12_EU_EDCRSTH 232 632 633 #define SROM11_SIGN 64 634 #define SROM11_CRCREV 233 635 636 #define SROM11_WORDS 234 637 #define SROM11_SIGNATURE 0x0634 638 639 /* SROM REV 12 */ 640 #define SROM12_SIGN 64 641 #define SROM12_WORDS 512 642 #define SROM12_SIGNATURE 0x8888 643 #define SROM12_CRCREV 511 644 645 #define SROM12_BFL6 486 646 #define SROM12_BFL7 487 647 648 #define SROM12_MCSBW205GX1PO 234 649 #define SROM12_MCSBW205GX1PO_1 235 650 #define SROM12_MCSBW405GX1PO 236 651 #define SROM12_MCSBW405GX1PO_1 237 652 #define SROM12_MCSBW805GX1PO 238 653 #define SROM12_MCSBW805GX1PO_1 239 654 #define SROM12_MCSLR5GX1PO 240 655 #define SROM12_SB40AND80LR5GX1PO 241 656 #define SROM12_SB20IN80AND160LR5GX1PO 242 657 #define SROM12_SB20IN80AND160HR5GX1PO 243 658 #define SROM12_SB40AND80HR5GX1PO 244 659 660 #define SROM12_MCSBW205GX2PO 245 661 #define SROM12_MCSBW205GX2PO_1 246 662 #define SROM12_MCSBW405GX2PO 247 663 #define SROM12_MCSBW405GX2PO_1 248 664 #define SROM12_MCSBW805GX2PO 249 665 #define SROM12_MCSBW805GX2PO_1 250 666 #define SROM12_MCSLR5GX2PO 251 667 #define SROM12_SB40AND80LR5GX2PO 252 668 #define SROM12_SB20IN80AND160LR5GX2PO 253 669 #define SROM12_SB20IN80AND160HR5GX2PO 254 670 #define SROM12_SB40AND80HR5GX2PO 255 671 672 /* MISC */ 673 #define SROM12_RXGAINS10 483 674 #define SROM12_RXGAINS11 484 675 #define SROM12_RXGAINS12 485 676 677 /* Per-path fields and offset */ 678 #define MAX_PATH_SROM_12 3 679 #define SROM12_PATH0 256 680 #define SROM12_PATH1 328 681 #define SROM12_PATH2 400 682 683 #define SROM12_5GB42G_MAXP 0 684 #define SROM12_2GB0_PA 1 685 #define SROM12_2GB0_PA_W0 1 686 #define SROM12_2GB0_PA_W1 2 687 #define SROM12_2GB0_PA_W2 3 688 #define SROM12_2GB0_PA_W3 4 689 690 #define SROM12_RXGAINS 5 691 #define SROM12_5GB1B0_MAXP 6 692 #define SROM12_5GB3B2_MAXP 7 693 694 #define SROM12_5GB0_PA 8 695 #define SROM12_5GB0_PA_W0 8 696 #define SROM12_5GB0_PA_W1 9 697 #define SROM12_5GB0_PA_W2 10 698 #define SROM12_5GB0_PA_W3 11 699 700 #define SROM12_5GB1_PA 12 701 #define SROM12_5GB1_PA_W0 12 702 #define SROM12_5GB1_PA_W1 13 703 #define SROM12_5GB1_PA_W2 14 704 #define SROM12_5GB1_PA_W3 15 705 706 #define SROM12_5GB2_PA 16 707 #define SROM12_5GB2_PA_W0 16 708 #define SROM12_5GB2_PA_W1 17 709 #define SROM12_5GB2_PA_W2 18 710 #define SROM12_5GB2_PA_W3 19 711 712 #define SROM12_5GB3_PA 20 713 #define SROM12_5GB3_PA_W0 20 714 #define SROM12_5GB3_PA_W1 21 715 #define SROM12_5GB3_PA_W2 22 716 #define SROM12_5GB3_PA_W3 23 717 718 #define SROM12_5GB4_PA 24 719 #define SROM12_5GB4_PA_W0 24 720 #define SROM12_5GB4_PA_W1 25 721 #define SROM12_5GB4_PA_W2 26 722 #define SROM12_5GB4_PA_W3 27 723 724 #define SROM12_2G40B0_PA 28 725 #define SROM12_2G40B0_PA_W0 28 726 #define SROM12_2G40B0_PA_W1 29 727 #define SROM12_2G40B0_PA_W2 30 728 #define SROM12_2G40B0_PA_W3 31 729 730 #define SROM12_5G40B0_PA 32 731 #define SROM12_5G40B0_PA_W0 32 732 #define SROM12_5G40B0_PA_W1 33 733 #define SROM12_5G40B0_PA_W2 34 734 #define SROM12_5G40B0_PA_W3 35 735 736 #define SROM12_5G40B1_PA 36 737 #define SROM12_5G40B1_PA_W0 36 738 #define SROM12_5G40B1_PA_W1 37 739 #define SROM12_5G40B1_PA_W2 38 740 #define SROM12_5G40B1_PA_W3 39 741 742 #define SROM12_5G40B2_PA 40 743 #define SROM12_5G40B2_PA_W0 40 744 #define SROM12_5G40B2_PA_W1 41 745 #define SROM12_5G40B2_PA_W2 42 746 #define SROM12_5G40B2_PA_W3 43 747 748 #define SROM12_5G40B3_PA 44 749 #define SROM12_5G40B3_PA_W0 44 750 #define SROM12_5G40B3_PA_W1 45 751 #define SROM12_5G40B3_PA_W2 46 752 #define SROM12_5G40B3_PA_W3 47 753 754 #define SROM12_5G40B4_PA 48 755 #define SROM12_5G40B4_PA_W0 48 756 #define SROM12_5G40B4_PA_W1 49 757 #define SROM12_5G40B4_PA_W2 50 758 #define SROM12_5G40B4_PA_W3 51 759 760 #define SROM12_5G80B0_PA 52 761 #define SROM12_5G80B0_PA_W0 52 762 #define SROM12_5G80B0_PA_W1 53 763 #define SROM12_5G80B0_PA_W2 54 764 #define SROM12_5G80B0_PA_W3 55 765 766 #define SROM12_5G80B1_PA 56 767 #define SROM12_5G80B1_PA_W0 56 768 #define SROM12_5G80B1_PA_W1 57 769 #define SROM12_5G80B1_PA_W2 58 770 #define SROM12_5G80B1_PA_W3 59 771 772 #define SROM12_5G80B2_PA 60 773 #define SROM12_5G80B2_PA_W0 60 774 #define SROM12_5G80B2_PA_W1 61 775 #define SROM12_5G80B2_PA_W2 62 776 #define SROM12_5G80B2_PA_W3 63 777 778 #define SROM12_5G80B3_PA 64 779 #define SROM12_5G80B3_PA_W0 64 780 #define SROM12_5G80B3_PA_W1 65 781 #define SROM12_5G80B3_PA_W2 66 782 #define SROM12_5G80B3_PA_W3 67 783 784 #define SROM12_5G80B4_PA 68 785 #define SROM12_5G80B4_PA_W0 68 786 #define SROM12_5G80B4_PA_W1 69 787 #define SROM12_5G80B4_PA_W2 70 788 #define SROM12_5G80B4_PA_W3 71 789 790 /* PD offset */ 791 #define SROM12_PDOFF_2G_CCK 472 792 793 #define SROM12_PDOFF_20in40M_5G_B0 473 794 #define SROM12_PDOFF_20in40M_5G_B1 474 795 #define SROM12_PDOFF_20in40M_5G_B2 475 796 #define SROM12_PDOFF_20in40M_5G_B3 476 797 #define SROM12_PDOFF_20in40M_5G_B4 477 798 799 #define SROM12_PDOFF_40in80M_5G_B0 478 800 #define SROM12_PDOFF_40in80M_5G_B1 479 801 #define SROM12_PDOFF_40in80M_5G_B2 480 802 #define SROM12_PDOFF_40in80M_5G_B3 481 803 #define SROM12_PDOFF_40in80M_5G_B4 482 804 805 #define SROM12_PDOFF_20in80M_5G_B0 488 806 #define SROM12_PDOFF_20in80M_5G_B1 489 807 #define SROM12_PDOFF_20in80M_5G_B2 490 808 #define SROM12_PDOFF_20in80M_5G_B3 491 809 #define SROM12_PDOFF_20in80M_5G_B4 492 810 811 #define SROM12_GPDN_L 91 /* GPIO pull down bits [15:0] */ 812 #define SROM12_GPDN_H 233 /* GPIO pull down bits [31:16] */ 813 814 #define SROM13_SIGN 64 815 #define SROM13_WORDS 590 816 #define SROM13_SIGNATURE 0x4d55 817 #define SROM13_CRCREV 589 818 819 /* Per-path fields and offset */ 820 #define MAX_PATH_SROM_13 4 821 #define SROM13_PATH0 256 822 #define SROM13_PATH1 328 823 #define SROM13_PATH2 400 824 #define SROM13_PATH3 512 825 #define SROM13_RXGAINS 5 826 827 #define SROM13_XTALFREQ 90 828 829 #define SROM13_PDOFFSET20IN40M2G 94 830 #define SROM13_PDOFFSET20IN40M2GCORE3 95 831 #define SROM13_SB20IN40HRLRPOX 96 832 833 #define SROM13_RXGAINS1CORE3 97 834 835 #define SROM13_PDOFFSET20IN40M5GCORE3 98 836 #define SROM13_PDOFFSET20IN40M5GCORE3_1 99 837 838 #define SROM13_ANTGAIN_BANDBGA 100 839 840 #define SROM13_PDOFFSET40IN80M5GCORE3 105 841 #define SROM13_PDOFFSET40IN80M5GCORE3_1 106 842 843 /* power per rate */ 844 #define SROM13_MCS1024QAM2GPO 108 845 #define SROM13_MCS1024QAM5GLPO 109 846 #define SROM13_MCS1024QAM5GLPO_1 110 847 #define SROM13_MCS1024QAM5GMPO 111 848 #define SROM13_MCS1024QAM5GMPO_1 112 849 #define SROM13_MCS1024QAM5GHPO 113 850 #define SROM13_MCS1024QAM5GHPO_1 114 851 #define SROM13_MCS1024QAM5GX1PO 115 852 #define SROM13_MCS1024QAM5GX1PO_1 116 853 #define SROM13_MCS1024QAM5GX2PO 117 854 #define SROM13_MCS1024QAM5GX2PO_1 118 855 856 #define SROM13_MCSBW1605GLPO 119 857 #define SROM13_MCSBW1605GLPO_1 120 858 #define SROM13_MCSBW1605GMPO 121 859 #define SROM13_MCSBW1605GMPO_1 122 860 #define SROM13_MCSBW1605GHPO 123 861 #define SROM13_MCSBW1605GHPO_1 124 862 863 #define SROM13_MCSBW1605GX1PO 125 864 #define SROM13_MCSBW1605GX1PO_1 126 865 #define SROM13_MCSBW1605GX2PO 127 866 #define SROM13_MCSBW1605GX2PO_1 128 867 868 #define SROM13_ULBPPROFFS5GB0 129 869 #define SROM13_ULBPPROFFS5GB1 130 870 #define SROM13_ULBPPROFFS5GB2 131 871 #define SROM13_ULBPPROFFS5GB3 132 872 #define SROM13_ULBPPROFFS5GB4 133 873 #define SROM13_ULBPPROFFS2G 134 874 875 #define SROM13_MCS8POEXP 135 876 #define SROM13_MCS8POEXP_1 136 877 #define SROM13_MCS9POEXP 137 878 #define SROM13_MCS9POEXP_1 138 879 #define SROM13_MCS10POEXP 139 880 #define SROM13_MCS10POEXP_1 140 881 #define SROM13_MCS11POEXP 141 882 #define SROM13_MCS11POEXP_1 142 883 #define SROM13_ULBPDOFFS5GB0A0 143 884 #define SROM13_ULBPDOFFS5GB0A1 144 885 #define SROM13_ULBPDOFFS5GB0A2 145 886 #define SROM13_ULBPDOFFS5GB0A3 146 887 #define SROM13_ULBPDOFFS5GB1A0 147 888 #define SROM13_ULBPDOFFS5GB1A1 148 889 #define SROM13_ULBPDOFFS5GB1A2 149 890 #define SROM13_ULBPDOFFS5GB1A3 150 891 #define SROM13_ULBPDOFFS5GB2A0 151 892 #define SROM13_ULBPDOFFS5GB2A1 152 893 #define SROM13_ULBPDOFFS5GB2A2 153 894 #define SROM13_ULBPDOFFS5GB2A3 154 895 #define SROM13_ULBPDOFFS5GB3A0 155 896 #define SROM13_ULBPDOFFS5GB3A1 156 897 #define SROM13_ULBPDOFFS5GB3A2 157 898 #define SROM13_ULBPDOFFS5GB3A3 158 899 #define SROM13_ULBPDOFFS5GB4A0 159 900 #define SROM13_ULBPDOFFS5GB4A1 160 901 #define SROM13_ULBPDOFFS5GB4A2 161 902 #define SROM13_ULBPDOFFS5GB4A3 162 903 #define SROM13_ULBPDOFFS2GA0 163 904 #define SROM13_ULBPDOFFS2GA1 164 905 #define SROM13_ULBPDOFFS2GA2 165 906 #define SROM13_ULBPDOFFS2GA3 166 907 908 #define SROM13_RPCAL5GB4 199 909 #define SROM13_RPCAL2GCORE3 101 910 #define SROM13_RPCAL5GB01CORE3 102 911 #define SROM13_RPCAL5GB23CORE3 103 912 913 #define SROM13_SW_TXRX_MASK 104 914 915 #define SROM13_EU_EDCRSTH 232 916 917 #define SROM13_SWCTRLMAP4_CFG 493 918 #define SROM13_SWCTRLMAP4_TX2G_FEM3TO0 494 919 #define SROM13_SWCTRLMAP4_RX2G_FEM3TO0 495 920 #define SROM13_SWCTRLMAP4_RXBYP2G_FEM3TO0 496 921 #define SROM13_SWCTRLMAP4_MISC2G_FEM3TO0 497 922 #define SROM13_SWCTRLMAP4_TX5G_FEM3TO0 498 923 #define SROM13_SWCTRLMAP4_RX5G_FEM3TO0 499 924 #define SROM13_SWCTRLMAP4_RXBYP5G_FEM3TO0 500 925 #define SROM13_SWCTRLMAP4_MISC5G_FEM3TO0 501 926 #define SROM13_SWCTRLMAP4_TX2G_FEM7TO4 502 927 #define SROM13_SWCTRLMAP4_RX2G_FEM7TO4 503 928 #define SROM13_SWCTRLMAP4_RXBYP2G_FEM7TO4 504 929 #define SROM13_SWCTRLMAP4_MISC2G_FEM7TO4 505 930 #define SROM13_SWCTRLMAP4_TX5G_FEM7TO4 506 931 #define SROM13_SWCTRLMAP4_RX5G_FEM7TO4 507 932 #define SROM13_SWCTRLMAP4_RXBYP5G_FEM7TO4 508 933 #define SROM13_SWCTRLMAP4_MISC5G_FEM7TO4 509 934 935 #define SROM13_PDOFFSET20IN80M5GCORE3 510 936 #define SROM13_PDOFFSET20IN80M5GCORE3_1 511 937 938 #define SROM13_NOISELVLCORE3 584 939 #define SROM13_NOISELVLCORE3_1 585 940 #define SROM13_RXGAINERRCORE3 586 941 #define SROM13_RXGAINERRCORE3_1 587 942 943 #define SROM13_PDOFF_2G_CCK_20M 167 944 945 #define SROM15_CALDATA_WORDS 943 946 #define SROM15_CAL_OFFSET_LOC 68 947 #define MAX_IOCTL_TXCHUNK_SIZE 1500 948 #define SROM15_MAX_CAL_SIZE 1886 949 #define SROM15_SIGNATURE 0x110c 950 #define SROM15_WORDS 1024 951 #define SROM15_MACHI 65 952 #define SROM15_CRCREV 1023 953 #define SROM15_BRDREV 69 954 #define SROM15_CCODE 70 955 #define SROM15_REGREV 71 956 #define SROM15_SIGN 64 957 958 #define SROM16_SIGN 128 959 #define SROM16_WORDS 1024 960 #define SROM16_SFLASH_WORDS 2048U 961 #define SROM16_SIGNATURE 0x4357 962 #define SROM16_CRCREV 1023 963 #define SROM16_MACHI (SROM16_SIGN + 1) 964 #define SROM16_CALDATA_OFFSET_LOC (SROM16_SIGN + 4) 965 #define SROM16_BOARDREV (SROM16_SIGN + 5) 966 #define SROM16_CCODE (SROM16_SIGN + 6) 967 #define SROM16_REGREV (SROM16_SIGN + 7) 968 969 #define SROM_CALDATA_WORDS 832 970 971 #define SROM17_SIGN 64 972 #define SROM17_BRDREV 65 973 #define SROM17_MACADDR 66 974 #define SROM17_CCODE 69 975 #define SROM17_CALDATA 70 976 #define SROM17_GCALTMP 71 977 978 #define SROM17_C0SRD202G 72 979 #define SROM17_C0SRD202G_1 73 980 #define SROM17_C0SRD205GL 74 981 #define SROM17_C0SRD205GL_1 75 982 #define SROM17_C0SRD205GML 76 983 #define SROM17_C0SRD205GML_1 77 984 #define SROM17_C0SRD205GMU 78 985 #define SROM17_C0SRD205GMU_1 79 986 #define SROM17_C0SRD205GH 80 987 #define SROM17_C0SRD205GH_1 81 988 989 #define SROM17_C1SRD202G 82 990 #define SROM17_C1SRD202G_1 83 991 #define SROM17_C1SRD205GL 84 992 #define SROM17_C1SRD205GL_1 85 993 #define SROM17_C1SRD205GML 86 994 #define SROM17_C1SRD205GML_1 87 995 #define SROM17_C1SRD205GMU 88 996 #define SROM17_C1SRD205GMU_1 89 997 #define SROM17_C1SRD205GH 90 998 #define SROM17_C1SRD205GH_1 91 999 1000 #define SROM17_TRAMMAGIC 92 1001 #define SROM17_TRAMMAGIC_1 93 1002 #define SROM17_TRAMDATA 94 1003 1004 #define SROM17_WORDS 256 1005 #define SROM17_CRCREV 255 1006 #define SROM17_CALDATA_WORDS 161 1007 #define SROM17_SIGNATURE 0x1103 /* 4355 in hex format */ 1008 1009 #define SROM18_SIGN 112 1010 #define SROM18_WORDS 1024 1011 #define SROM18_SIGNATURE 0x4377 1012 #define SROM18_CRCREV 1023 1013 #define SROM18_MACHI (SROM18_SIGN + 1) 1014 #define SROM18_CALDATA_OFFSET_LOC (SROM18_SIGN + 4) 1015 #define SROM18_BOARDREV (SROM18_SIGN + 5) 1016 #define SROM18_CCODE (SROM18_SIGN + 6) 1017 #define SROM18_REGREV (SROM18_SIGN + 7) 1018 #define SROM18_CALDATA_WORDS (SROM18_WORDS - SROM18_CALDATA_OFFSET_LOC) 1019 1020 typedef struct { 1021 uint8 tssipos; /* TSSI positive slope, 1: positive, 0: negative */ 1022 uint8 extpagain; /* Ext PA gain-type: full-gain: 0, pa-lite: 1, no_pa: 2 */ 1023 uint8 pdetrange; /* support 32 combinations of different Pdet dynamic ranges */ 1024 uint8 triso; /* TR switch isolation */ 1025 uint8 antswctrllut; /* antswctrl lookup table configuration: 32 possible choices */ 1026 } srom_fem_t; 1027 1028 #endif /* _bcmsrom_fmt_h_ */ 1029