1 /* 2 * Broadcom SDIO/PCMCIA 3 * Software-specific definitions shared between device and host side 4 * 5 * Copyright (C) 2020, Broadcom. 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions of 17 * the license of that module. An independent module is a module which is not 18 * derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * 22 * <<Broadcom-WL-IPTag/Dual:>> 23 */ 24 25 #ifndef _bcmsdpcm_h_ 26 #define _bcmsdpcm_h_ 27 28 /* 29 * Software allocation of To SB Mailbox resources 30 */ 31 32 /* intstatus bits */ 33 #define I_SMB_NAK I_SMB_SW0 /* To SB Mailbox Frame NAK */ 34 #define I_SMB_INT_ACK I_SMB_SW1 /* To SB Mailbox Host Interrupt ACK */ 35 #define I_SMB_USE_OOB I_SMB_SW2 /* To SB Mailbox Use OOB Wakeup */ 36 #define I_SMB_DEV_INT I_SMB_SW3 /* To SB Mailbox Miscellaneous Interrupt */ 37 38 #define I_TOSBMAIL (I_SMB_NAK | I_SMB_INT_ACK | I_SMB_USE_OOB | I_SMB_DEV_INT) 39 40 /* tosbmailbox bits corresponding to intstatus bits */ 41 #define SMB_NAK (1 << 0) /* To SB Mailbox Frame NAK */ 42 #define SMB_INT_ACK (1 << 1) /* To SB Mailbox Host Interrupt ACK */ 43 #define SMB_USE_OOB (1 << 2) /* To SB Mailbox Use OOB Wakeup */ 44 #define SMB_DEV_INT (1 << 3) /* To SB Mailbox Miscellaneous Interrupt */ 45 #define SMB_MASK 0x0000000f /* To SB Mailbox Mask */ 46 47 /* tosbmailboxdata */ 48 49 #ifdef DS_PROT 50 /* Bit msgs for custom deep sleep protocol */ 51 #define SMB_DATA_D3INFORM 0x100 /* host announcing D3 entry */ 52 #define SMB_DATA_DSACK 0x200 /* host acking a deepsleep request */ 53 #define SMB_DATA_DSNACK 0x400 /* host nacking a deepsleep request */ 54 #endif /* DS_PROT */ 55 /* force a trap */ 56 #define SMB_DATA_TRAP 0x800 /* host forcing trap */ 57 58 #define SMB_DATA_VERSION_MASK 0x00ff0000 /* host protocol version (sent with F2 enable) */ 59 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version (sent with F2 enable) */ 60 61 /* 62 * Software allocation of To Host Mailbox resources 63 */ 64 65 /* intstatus bits */ 66 #define I_HMB_INT_ACK I_HMB_SW0 /* To Host Mailbox Dev Interrupt ACK */ 67 #define I_HMB_FC_STATE I_HMB_SW0 /* To Host Mailbox Flow Control State */ 68 #define I_HMB_FC_CHANGE I_HMB_SW1 /* To Host Mailbox Flow Control State Changed */ 69 #define I_HMB_FRAME_IND I_HMB_SW2 /* To Host Mailbox Frame Indication */ 70 #define I_HMB_HOST_INT I_HMB_SW3 /* To Host Mailbox Miscellaneous Interrupt */ 71 72 #define I_TOHOSTMAIL (I_HMB_INT_ACK | I_HMB_FRAME_IND | I_HMB_HOST_INT) 73 74 /* tohostmailbox bits corresponding to intstatus bits */ 75 #define HMB_INT_ACK (1 << 0) /* To Host Mailbox Dev Interrupt ACK */ 76 #define HMB_FRAME_IND (1 << 2) /* To Host Mailbox Frame Indication */ 77 #define HMB_HOST_INT (1 << 3) /* To Host Mailbox Miscellaneous Interrupt */ 78 #define HMB_MASK 0x0000000f /* To Host Mailbox Mask */ 79 80 /* tohostmailboxdata */ 81 #define HMB_DATA_NAKHANDLED 0x01 /* we're ready to retransmit NAK'd frame to host */ 82 #define HMB_DATA_DEVREADY 0x02 /* we're ready to to talk to host after enable */ 83 #define HMB_DATA_FC 0x04 /* per prio flowcontrol update flag to host */ 84 #define HMB_DATA_FWREADY 0x08 /* firmware is ready for protocol activity */ 85 #define HMB_DATA_FWHALT 0x10 /* firmware has halted operation */ 86 87 #ifdef DS_PROT 88 /* Bit msgs for custom deep sleep protocol */ 89 #define HMB_DATA_DSREQ 0x100 /* firmware requesting deepsleep entry */ 90 #define HMB_DATA_DSEXIT 0x200 /* firmware announcing deepsleep exit */ 91 #define HMB_DATA_D3ACK 0x400 /* firmware acking a D3 notice from host */ 92 #define HMB_DATA_D3EXIT 0x800 /* firmware announcing D3 exit */ 93 #define HMB_DATA_DSPROT_MASK 0xf00 94 #endif /* DS_PROT */ 95 96 #define HMB_DATA_FCDATA_MASK 0xff000000 /* per prio flowcontrol data */ 97 #define HMB_DATA_FCDATA_SHIFT 24 /* per prio flowcontrol data */ 98 99 #define HMB_DATA_VERSION_MASK 0x00ff0000 /* device protocol version (with devready) */ 100 #define HMB_DATA_VERSION_SHIFT 16 /* device protocol version (with devready) */ 101 102 /* 103 * Software-defined protocol header 104 */ 105 /* Replace all this with packed struct */ 106 107 /* Current protocol version */ 108 #define SDPCM_PROT_VERSION 4 109 110 /* SW frame header */ 111 #define SDPCM_SEQUENCE_MASK 0x000000ff /* Sequence Number Mask */ 112 #define SDPCM_PACKET_SEQUENCE(p) (((uint8 *)p)[0] & 0xff) /* p starts w/SW Header */ 113 114 #define SDPCM_CHANNEL_MASK 0x00000f00 /* Channel Number Mask */ 115 #define SDPCM_CHANNEL_SHIFT 8 /* Channel Number Shift */ 116 #define SDPCM_PACKET_CHANNEL(p) (((uint8 *)p)[1] & 0x0f) /* p starts w/SW Header */ 117 118 #define SDPCM_FLAGS_MASK 0x0000f000 /* Mask of flag bits */ 119 #define SDPCM_FLAGS_SHIFT 12 /* Flag bits shift */ 120 #define SDPCM_PACKET_FLAGS(p) ((((uint8 *)p)[1] & 0xf0) >> 4) /* p starts w/SW Header */ 121 122 /* Next Read Len: lookahead length of next frame, in 16-byte units (rounded up) */ 123 #define SDPCM_NEXTLEN_MASK 0x00ff0000 /* Next Read Len Mask */ 124 #define SDPCM_NEXTLEN_SHIFT 16 /* Next Read Len Shift */ 125 #define SDPCM_NEXTLEN_VALUE(p) ((((uint8 *)p)[2] & 0xff) << 4) /* p starts w/SW Header */ 126 #define SDPCM_NEXTLEN_OFFSET 2 127 128 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */ 129 #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */ 130 #define SDPCM_DOFFSET_VALUE(p) (((uint8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff) 131 #define SDPCM_DOFFSET_MASK 0xff000000 132 #define SDPCM_DOFFSET_SHIFT 24 133 134 #define SDPCM_FCMASK_OFFSET 4 /* Flow control */ 135 #define SDPCM_FCMASK_VALUE(p) (((uint8 *)p)[SDPCM_FCMASK_OFFSET ] & 0xff) 136 #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */ 137 #define SDPCM_WINDOW_VALUE(p) (((uint8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff) 138 #define SDPCM_VERSION_OFFSET 6 /* Version # */ 139 #define SDPCM_VERSION_VALUE(p) (((uint8 *)p)[SDPCM_VERSION_OFFSET] & 0xff) 140 #define SDPCM_UNUSED_OFFSET 7 /* Spare */ 141 #define SDPCM_UNUSED_VALUE(p) (((uint8 *)p)[SDPCM_UNUSED_OFFSET] & 0xff) 142 143 #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */ 144 145 /* logical channel numbers */ 146 #define SDPCM_CONTROL_CHANNEL 0 /* Control Request/Response Channel Id */ 147 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */ 148 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */ 149 #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets (superframes) */ 150 #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */ 151 #define SDPCM_MAX_CHANNEL 15 152 153 #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for eight-bit frame seq number */ 154 155 #define SDPCM_FLAG_RESVD0 0x01 156 #define SDPCM_FLAG_RESVD1 0x02 157 #define SDPCM_FLAG_GSPI_TXENAB 0x04 /* GSPI Tx enable (PR55150 only) */ 158 #define SDPCM_FLAG_GLOMDESC 0x08 /* Superframe descriptor mask */ 159 160 /* For GLOM_CHANNEL frames, use a flag to indicate descriptor frame */ 161 #define SDPCM_GLOMDESC_FLAG (SDPCM_FLAG_GLOMDESC << SDPCM_FLAGS_SHIFT) 162 163 #define SDPCM_GLOMDESC(p) (((uint8 *)p)[1] & 0x80) 164 165 /* For TEST_CHANNEL packets, define another 4-byte header */ 166 #define SDPCM_TEST_HDRLEN 4 /* Generally: Cmd(1), Ext(1), Len(2); 167 * Semantics of Ext byte depend on command. 168 * Len is current or requested frame length, not 169 * including test header; sent little-endian. 170 */ 171 #define SDPCM_TEST_PKT_CNT_FLD_LEN 4 /* Packet count filed legth */ 172 #define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext is a pattern id. */ 173 #define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext is a pattern id. */ 174 #define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext is a pattern id. */ 175 #define SDPCM_TEST_BURST 0x04 /* Receiver to send a burst. Ext is a frame count 176 * (Backward compatabilty) Set frame count in a 177 * 4 byte filed adjacent to the HDR 178 */ 179 #define SDPCM_TEST_SEND 0x05 /* Receiver sets send mode. Ext is boolean on/off 180 * Set frame count in a 4 byte filed adjacent to 181 * the HDR 182 */ 183 184 /* Handy macro for filling in datagen packets with a pattern */ 185 #define SDPCM_TEST_FILL(byteno, id) ((uint8)(id + byteno)) 186 187 /* 188 * Software counters (first part matches hardware counters) 189 */ 190 191 typedef volatile struct { 192 uint32 cmd52rd; /* Cmd52RdCount, SDIO: cmd52 reads */ 193 uint32 cmd52wr; /* Cmd52WrCount, SDIO: cmd52 writes */ 194 uint32 cmd53rd; /* Cmd53RdCount, SDIO: cmd53 reads */ 195 uint32 cmd53wr; /* Cmd53WrCount, SDIO: cmd53 writes */ 196 uint32 abort; /* AbortCount, SDIO: aborts */ 197 uint32 datacrcerror; /* DataCrcErrorCount, SDIO: frames w/CRC error */ 198 uint32 rdoutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Rd Frm out of sync */ 199 uint32 wroutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Wr Frm out of sync */ 200 uint32 writebusy; /* WriteBusyCount, SDIO: device asserted "busy" */ 201 uint32 readwait; /* ReadWaitCount, SDIO: no data ready for a read cmd */ 202 uint32 readterm; /* ReadTermCount, SDIO: read frame termination cmds */ 203 uint32 writeterm; /* WriteTermCount, SDIO: write frames termination cmds */ 204 uint32 rxdescuflo; /* receive descriptor underflows */ 205 uint32 rxfifooflo; /* receive fifo overflows */ 206 uint32 txfifouflo; /* transmit fifo underflows */ 207 uint32 runt; /* runt (too short) frames recv'd from bus */ 208 uint32 badlen; /* frame's rxh len does not match its hw tag len */ 209 uint32 badcksum; /* frame's hw tag chksum doesn't agree with len value */ 210 uint32 seqbreak; /* break in sequence # space from one rx frame to the next */ 211 uint32 rxfcrc; /* frame rx header indicates crc error */ 212 uint32 rxfwoos; /* frame rx header indicates write out of sync */ 213 uint32 rxfwft; /* frame rx header indicates write frame termination */ 214 uint32 rxfabort; /* frame rx header indicates frame aborted */ 215 uint32 woosint; /* write out of sync interrupt */ 216 uint32 roosint; /* read out of sync interrupt */ 217 uint32 rftermint; /* read frame terminate interrupt */ 218 uint32 wftermint; /* write frame terminate interrupt */ 219 } sdpcmd_cnt_t; 220 221 /* 222 * Register Access Macros 223 */ 224 225 #define SDIODREV_IS(var, val) ((var) == (val)) 226 #define SDIODREV_GE(var, val) ((var) >= (val)) 227 #define SDIODREV_GT(var, val) ((var) > (val)) 228 #define SDIODREV_LT(var, val) ((var) < (val)) 229 #define SDIODREV_LE(var, val) ((var) <= (val)) 230 231 #define SDIODDMAREG32(h, dir, chnl) \ 232 ((dir) == DMA_TX ? \ 233 (void *)(uintptr)&((h)->regs->dma.sdiod32.dma32regs[chnl].xmt) : \ 234 (void *)(uintptr)&((h)->regs->dma.sdiod32.dma32regs[chnl].rcv)) 235 236 #define SDIODDMAREG64(h, dir, chnl) \ 237 ((dir) == DMA_TX ? \ 238 (void *)(uintptr)&((h)->regs->dma.sdiod64.dma64regs[chnl].xmt) : \ 239 (void *)(uintptr)&((h)->regs->dma.sdiod64.dma64regs[chnl].rcv)) 240 241 #define SDIODDMAREG(h, dir, chnl) \ 242 (SDIODREV_LT((h)->corerev, 1) ? \ 243 SDIODDMAREG32((h), (dir), (chnl)) : \ 244 SDIODDMAREG64((h), (dir), (chnl))) 245 246 #define PCMDDMAREG(h, dir, chnl) \ 247 ((dir) == DMA_TX ? \ 248 (void *)(uintptr)&((h)->regs->dma.pcm32.dmaregs.xmt) : \ 249 (void *)(uintptr)&((h)->regs->dma.pcm32.dmaregs.rcv)) 250 251 #define SDPCMDMAREG(h, dir, chnl, coreid) \ 252 ((coreid) == SDIOD_CORE_ID ? \ 253 SDIODDMAREG(h, dir, chnl) : \ 254 PCMDDMAREG(h, dir, chnl)) 255 256 #define SDIODFIFOREG(h, corerev) \ 257 (SDIODREV_LT((corerev), 1) ? \ 258 ((dma32diag_t *)(uintptr)&((h)->regs->dma.sdiod32.dmafifo)) : \ 259 ((dma32diag_t *)(uintptr)&((h)->regs->dma.sdiod64.dmafifo))) 260 261 #define PCMDFIFOREG(h) \ 262 ((dma32diag_t *)(uintptr)&((h)->regs->dma.pcm32.dmafifo)) 263 264 #define SDPCMFIFOREG(h, coreid, corerev) \ 265 ((coreid) == SDIOD_CORE_ID ? \ 266 SDIODFIFOREG(h, corerev) : \ 267 PCMDFIFOREG(h)) 268 269 /* 270 * Shared structure between dongle and the host. 271 * The structure contains pointers to trap or assert information. 272 */ 273 #define SDPCM_SHARED_VERSION 0x0001 274 #define SDPCM_SHARED_VERSION_MASK 0x00FF 275 #define SDPCM_SHARED_ASSERT_BUILT 0x0100 276 #define SDPCM_SHARED_ASSERT 0x0200 277 #define SDPCM_SHARED_TRAP 0x0400 278 #define SDPCM_SHARED_IN_BRPT 0x0800 279 #define SDPCM_SHARED_SET_BRPT 0x1000 280 #define SDPCM_SHARED_PENDING_BRPT 0x2000 281 #define SDPCM_SHARED_FATAL_LOGBUF_VALID 0x100000 282 #define SDPCM_SHARED_RXLIM_POST 0x4000 283 #define SDPCM_SHARED_TXSEQ_SYNC 0x4000 284 285 typedef struct { 286 uint32 flags; 287 uint32 trap_addr; 288 uint32 assert_exp_addr; 289 uint32 assert_file_addr; 290 uint32 assert_line; 291 uint32 console_addr; /* Address of hnd_cons_t */ 292 uint32 msgtrace_addr; 293 uint32 fwid; 294 uint32 device_fatal_logbuf_start; 295 #ifdef BCMSDIO_TXSEQ_SYNC 296 uint32 txseq_sync_addr; 297 #endif /* BCMSDIO_TXSEQ_SYNC */ 298 } sdpcm_shared_t; 299 300 /* Device F/W provides the following access function: 301 * sdpcm_shared_t *hnd_get_sdpcm_shared(void); 302 */ 303 304 #endif /* _bcmsdpcm_h_ */ 305