1 /* 2 * Broadcom PCIE 3 * Software-specific definitions shared between device and host side 4 * Explains the shared area between host and dongle 5 * 6 * Copyright (C) 2020, Broadcom. 7 * 8 * Unless you and Broadcom execute a separate written software license 9 * agreement governing use of this software, this software is licensed to you 10 * under the terms of the GNU General Public License version 2 (the "GPL"), 11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12 * following added to such license: 13 * 14 * As a special exception, the copyright holders of this software give you 15 * permission to link this software with independent modules, and to copy and 16 * distribute the resulting executable under terms of your choice, provided that 17 * you also meet, for each linked independent module, the terms and conditions of 18 * the license of that module. An independent module is a module which is not 19 * derived from this software. The special exception does not apply to any 20 * modifications of the software. 21 * 22 * 23 * <<Broadcom-WL-IPTag/Dual:>> 24 */ 25 26 #ifndef _bcmpcie_h_ 27 #define _bcmpcie_h_ 28 29 #include <typedefs.h> 30 31 #define ADDR_64(x) (x.addr) 32 #define HIGH_ADDR_32(x) ((uint32) (((sh_addr_t) x).high_addr)) 33 #define LOW_ADDR_32(x) ((uint32) (((sh_addr_t) x).low_addr)) 34 35 typedef struct { 36 uint32 low_addr; 37 uint32 high_addr; 38 } sh_addr_t; 39 40 /* May be overridden by 43xxxxx-roml.mk */ 41 #if !defined(BCMPCIE_MAX_TX_FLOWS) 42 #define BCMPCIE_MAX_TX_FLOWS 40 43 #endif /* ! BCMPCIE_MAX_TX_FLOWS */ 44 45 #define PCIE_SHARED_VERSION_9 0x00009 46 #define PCIE_SHARED_VERSION_8 0x00008 47 #define PCIE_SHARED_VERSION_7 0x00007 48 #define PCIE_SHARED_VERSION_6 0x00006 /* rev6 is compatible with rev 5 */ 49 #define PCIE_SHARED_VERSION_5 0x00005 /* rev6 is compatible with rev 5 */ 50 /** 51 * Feature flags enabled in dongle. Advertised by dongle to DHD via the PCIe Shared structure that 52 * is located in device memory. 53 */ 54 #define PCIE_SHARED_VERSION_MASK 0x000FF 55 #define PCIE_SHARED_ASSERT_BUILT 0x00100 56 #define PCIE_SHARED_ASSERT 0x00200 57 #define PCIE_SHARED_TRAP 0x00400 58 #define PCIE_SHARED_IN_BRPT 0x00800 59 #define PCIE_SHARED_SET_BRPT 0x01000 60 #define PCIE_SHARED_PENDING_BRPT 0x02000 61 /* BCMPCIE_SUPPORT_TX_PUSH_RING 0x04000 obsolete */ 62 #define PCIE_SHARED_EVT_SEQNUM 0x08000 63 #define PCIE_SHARED_DMA_INDEX 0x10000 64 65 /** 66 * There are host types where a device interrupt can 'race ahead' of data written by the device into 67 * host memory. The dongle can avoid this condition using a variety of techniques (read barrier, 68 * using PCIe Message Signalled Interrupts, or by using the PCIE_DMA_INDEX feature). Unfortunately 69 * these techniques have drawbacks on router platforms. For these platforms, it was decided to not 70 * avoid the condition, but to detect the condition instead and act on it. 71 * D2H M2M DMA Complete Sync mechanism: Modulo-253-SeqNum or XORCSUM 72 */ 73 #define PCIE_SHARED_D2H_SYNC_SEQNUM 0x20000 74 #define PCIE_SHARED_D2H_SYNC_XORCSUM 0x40000 75 #define PCIE_SHARED_D2H_SYNC_MODE_MASK \ 76 (PCIE_SHARED_D2H_SYNC_SEQNUM | PCIE_SHARED_D2H_SYNC_XORCSUM) 77 #define PCIE_SHARED_IDLE_FLOW_RING 0x80000 78 #define PCIE_SHARED_2BYTE_INDICES 0x100000 79 80 #define PCIE_SHARED_FAST_DELETE_RING 0x00000020 /* Fast Delete Ring */ 81 #define PCIE_SHARED_EVENT_BUF_POOL_MAX 0x000000c0 /* event buffer pool max bits */ 82 #define PCIE_SHARED_EVENT_BUF_POOL_MAX_POS 6 /* event buffer pool max bit position */ 83 84 /* dongle supports fatal buf log collection */ 85 #define PCIE_SHARED_FATAL_LOGBUG_VALID 0x200000 86 87 /* Implicit DMA with corerev 19 and after */ 88 #define PCIE_SHARED_IDMA 0x400000 89 90 /* MSI support */ 91 #define PCIE_SHARED_D2H_MSI_MULTI_MSG 0x800000 92 93 /* IFRM with corerev 19 and after */ 94 #define PCIE_SHARED_IFRM 0x1000000 95 96 /** 97 * From Rev6 and above, suspend/resume can be done using two handshake methods. 98 * 1. Using ctrl post/ctrl cmpl messages (Default rev6) 99 * 2. Using Mailbox data (old method as used in rev5) 100 * This shared flag indicates whether to overide rev6 default method and use mailbox for 101 * suspend/resume. 102 */ 103 #define PCIE_SHARED_USE_MAILBOX 0x2000000 104 105 /* Firmware compiled for mfgbuild purposes */ 106 #define PCIE_SHARED_MFGBUILD_FW 0x4000000 107 108 /* Firmware could use DB0 value as host timestamp */ 109 #define PCIE_SHARED_TIMESTAMP_DB0 0x8000000 110 /* Firmware could use Hostready (IPC rev7) */ 111 #define PCIE_SHARED_HOSTRDY_SUPPORT 0x10000000 112 113 /* When set, Firmwar does not support OOB Device Wake based DS protocol */ 114 #define PCIE_SHARED_NO_OOB_DW 0x20000000 115 116 /* When set, Firmwar supports Inband DS protocol */ 117 #define PCIE_SHARED_INBAND_DS 0x40000000 118 119 /* use DAR registers */ 120 #define PCIE_SHARED_DAR 0x80000000 121 122 /** 123 * Following are the shared2 flags. All bits in flags have been used. A flags2 124 * field got added and the definition for these flags come here: 125 */ 126 /* WAR: D11 txstatus through unused status field of PCIe completion header */ 127 #define PCIE_SHARED2_EXTENDED_TRAP_DATA 0x00000001 /* using flags2 in shared area */ 128 #define PCIE_SHARED2_TXSTATUS_METADATA 0x00000002 129 #define PCIE_SHARED2_BT_LOGGING 0x00000004 /* BT logging support */ 130 #define PCIE_SHARED2_SNAPSHOT_UPLOAD 0x00000008 /* BT/WLAN snapshot upload support */ 131 #define PCIE_SHARED2_SUBMIT_COUNT_WAR 0x00000010 /* submission count WAR */ 132 #define PCIE_SHARED2_FAST_DELETE_RING 0x00000020 /* Fast Delete ring support */ 133 #define PCIE_SHARED2_EVTBUF_MAX_MASK 0x000000C0 /* 0:32, 1:64, 2:128, 3: 256 */ 134 135 /* using flags2 to indicate firmware support added to reuse timesync to update PKT txstatus */ 136 #define PCIE_SHARED2_PKT_TX_STATUS 0x00000100 137 #define PCIE_SHARED2_FW_SMALL_MEMDUMP 0x00000200 /* FW small memdump */ 138 #define PCIE_SHARED2_FW_HC_ON_TRAP 0x00000400 139 #define PCIE_SHARED2_HSCB 0x00000800 /* Host SCB support */ 140 141 #define PCIE_SHARED2_EDL_RING 0x00001000 /* Support Enhanced Debug Lane */ 142 #define PCIE_SHARED2_DEBUG_BUF_DEST 0x00002000 /* debug buf dest support */ 143 #define PCIE_SHARED2_PCIE_ENUM_RESET_FLR 0x00004000 /* BT producer index reset WAR */ 144 #define PCIE_SHARED2_PKT_TIMESTAMP 0x00008000 /* Timestamp in packet */ 145 146 #define PCIE_SHARED2_HP2P 0x00010000u /* HP2P feature */ 147 #define PCIE_SHARED2_HWA 0x00020000u /* HWA feature */ 148 #define PCIE_SHARED2_TRAP_ON_HOST_DB7 0x00040000u /* can take a trap on DB7 from host */ 149 150 #define PCIE_SHARED2_DURATION_SCALE 0x00100000u 151 #define PCIE_SHARED2_ETD_ADDR_SUPPORT 0x00800000u 152 153 #define PCIE_SHARED2_TXCSO 0x00200000u /* Tx Checksum offload support */ 154 #define PCIE_SHARED2_TXPOST_EXT 0x00400000u /* extended txpost work item support */ 155 156 #define PCIE_SHARED2_D2H_D11_TX_STATUS 0x40000000 157 #define PCIE_SHARED2_H2D_D11_TX_STATUS 0x80000000 158 159 #define PCIE_SHARED_D2H_MAGIC 0xFEDCBA09 160 #define PCIE_SHARED_H2D_MAGIC 0x12345678 161 162 typedef uint16 pcie_hwa_db_index_t; /* 16 bit HWA index (IPC Rev 7) */ 163 #define PCIE_HWA_DB_INDEX_SZ (2u) /* 2 bytes sizeof(pcie_hwa_db_index_t) */ 164 165 /** 166 * Message rings convey messages between host and device. They are unidirectional, and are located 167 * in host memory. 168 * 169 * This is the minimal set of message rings, known as 'common message rings': 170 */ 171 #define BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT 0 172 #define BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT 1 173 #define BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE 2 174 #define BCMPCIE_D2H_MSGRING_TX_COMPLETE 3 175 #define BCMPCIE_D2H_MSGRING_RX_COMPLETE 4 176 #define BCMPCIE_COMMON_MSGRING_MAX_ID 4 177 178 #define BCMPCIE_H2D_COMMON_MSGRINGS 2 179 #define BCMPCIE_D2H_COMMON_MSGRINGS 3 180 #define BCMPCIE_COMMON_MSGRINGS 5 181 182 #define BCMPCIE_H2D_MSGRINGS(max_tx_flows) \ 183 (BCMPCIE_H2D_COMMON_MSGRINGS + (max_tx_flows)) 184 185 /* different ring types */ 186 #define BCMPCIE_H2D_RING_TYPE_CTRL_SUBMIT 0x1 187 #define BCMPCIE_H2D_RING_TYPE_TXFLOW_RING 0x2 188 #define BCMPCIE_H2D_RING_TYPE_RXBUFPOST 0x3 189 #define BCMPCIE_H2D_RING_TYPE_TXSUBMIT 0x4 190 #define BCMPCIE_H2D_RING_TYPE_DBGBUF_SUBMIT 0x5 191 #define BCMPCIE_H2D_RING_TYPE_BTLOG_SUBMIT 0x6 192 193 #define BCMPCIE_D2H_RING_TYPE_CTRL_CPL 0x1 194 #define BCMPCIE_D2H_RING_TYPE_TX_CPL 0x2 195 #define BCMPCIE_D2H_RING_TYPE_RX_CPL 0x3 196 #define BCMPCIE_D2H_RING_TYPE_DBGBUF_CPL 0x4 197 #define BCMPCIE_D2H_RING_TYPE_AC_RX_COMPLETE 0x5 198 #define BCMPCIE_D2H_RING_TYPE_BTLOG_CPL 0x6 199 #define BCMPCIE_D2H_RING_TYPE_EDL 0x7 200 #define BCMPCIE_D2H_RING_TYPE_HPP_TX_CPL 0x8 201 #define BCMPCIE_D2H_RING_TYPE_HPP_RX_CPL 0x9 202 203 /** 204 * H2D and D2H, WR and RD index, are maintained in the following arrays: 205 * - Array of all H2D WR Indices 206 * - Array of all H2D RD Indices 207 * - Array of all D2H WR Indices 208 * - Array of all D2H RD Indices 209 * 210 * The offset of the WR or RD indexes (for common rings) in these arrays are 211 * listed below. Arrays ARE NOT indexed by a ring's id. 212 * 213 * D2H common rings WR and RD index start from 0, even though their ringids 214 * start from BCMPCIE_H2D_COMMON_MSGRINGS 215 */ 216 217 #define BCMPCIE_H2D_RING_IDX(h2d_ring_id) (h2d_ring_id) 218 219 enum h2dring_idx { 220 /* H2D common rings */ 221 BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT_IDX = 222 BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT), 223 BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT_IDX = 224 BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT), 225 226 /* First TxPost's WR or RD index starts after all H2D common rings */ 227 BCMPCIE_H2D_MSGRING_TXFLOW_IDX_START = 228 BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_COMMON_MSGRINGS) 229 }; 230 231 #define BCMPCIE_D2H_RING_IDX(d2h_ring_id) \ 232 ((d2h_ring_id) - BCMPCIE_H2D_COMMON_MSGRINGS) 233 234 enum d2hring_idx { 235 /* D2H Common Rings */ 236 BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE_IDX = 237 BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE), 238 BCMPCIE_D2H_MSGRING_TX_COMPLETE_IDX = 239 BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_TX_COMPLETE), 240 BCMPCIE_D2H_MSGRING_RX_COMPLETE_IDX = 241 BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_RX_COMPLETE) 242 }; 243 244 /** 245 * Macros for managing arrays of RD WR indices: 246 * rw_index_sz: 247 * - in dongle, rw_index_sz is known at compile time 248 * - in host/DHD, rw_index_sz is derived from advertized pci_shared flags 249 * 250 * ring_idx: See h2dring_idx and d2hring_idx 251 */ 252 253 /** Offset of a RD or WR index in H2D or D2H indices array */ 254 #define BCMPCIE_RW_INDEX_OFFSET(rw_index_sz, ring_idx) \ 255 ((rw_index_sz) * (ring_idx)) 256 257 /** Fetch the address of RD or WR index in H2D or D2H indices array */ 258 #define BCMPCIE_RW_INDEX_ADDR(indices_array_base, rw_index_sz, ring_idx) \ 259 (void *)((uint32)(indices_array_base) + \ 260 BCMPCIE_RW_INDEX_OFFSET((rw_index_sz), (ring_idx))) 261 262 /** H2D DMA Indices array size: given max flow rings */ 263 #define BCMPCIE_H2D_RW_INDEX_ARRAY_SZ(rw_index_sz, max_tx_flows) \ 264 ((rw_index_sz) * BCMPCIE_H2D_MSGRINGS(max_tx_flows)) 265 266 /** D2H DMA Indices array size */ 267 #define BCMPCIE_D2H_RW_INDEX_ARRAY_SZ(rw_index_sz) \ 268 ((rw_index_sz) * BCMPCIE_D2H_COMMON_MSGRINGS) 269 270 /* Backwards compatibility for legacy branches. */ 271 #if !defined(PHYS_ADDR_N) 272 #define PHYS_ADDR_N(name) name 273 #endif 274 275 /** 276 * This type is used by a 'message buffer' (which is a FIFO for messages). Message buffers are used 277 * for host<->device communication and are instantiated on both sides. ring_mem_t is instantiated 278 * both in host as well as device memory. 279 */ 280 typedef struct ring_mem { 281 uint16 idx; /* ring id */ 282 uint8 type; 283 uint8 rsvd; 284 uint16 max_item; /* Max number of items in flow ring */ 285 uint16 len_items; /* Items are fixed size. Length in bytes of one item */ 286 sh_addr_t base_addr; /* 64 bits address, either in host or device memory */ 287 } ring_mem_t; 288 289 /** 290 * Per flow ring, information is maintained in device memory, eg at what address the ringmem and 291 * ringstate are located. The flow ring itself can be instantiated in either host or device memory. 292 * 293 * Perhaps this type should be renamed to make clear that it resides in device memory only. 294 */ 295 typedef struct ring_info { 296 uint32 PHYS_ADDR_N(ringmem_ptr); /* ring mem location in dongle memory */ 297 298 /* Following arrays are indexed using h2dring_idx and d2hring_idx, and not 299 * by a ringid. 300 */ 301 302 /* 32bit ptr to arrays of WR or RD indices for all rings in dongle memory */ 303 uint32 PHYS_ADDR_N(h2d_w_idx_ptr); /* Array of all H2D ring's WR indices */ 304 uint32 PHYS_ADDR_N(h2d_r_idx_ptr); /* Array of all H2D ring's RD indices */ 305 uint32 PHYS_ADDR_N(d2h_w_idx_ptr); /* Array of all D2H ring's WR indices */ 306 uint32 PHYS_ADDR_N(d2h_r_idx_ptr); /* Array of all D2H ring's RD indices */ 307 308 /* PCIE_DMA_INDEX feature: Dongle uses mem2mem DMA to sync arrays in host. 309 * Host may directly fetch WR and RD indices from these host-side arrays. 310 * 311 * 64bit ptr to arrays of WR or RD indices for all rings in host memory. 312 */ 313 sh_addr_t h2d_w_idx_hostaddr; /* Array of all H2D ring's WR indices */ 314 sh_addr_t h2d_r_idx_hostaddr; /* Array of all H2D ring's RD indices */ 315 sh_addr_t d2h_w_idx_hostaddr; /* Array of all D2H ring's WR indices */ 316 sh_addr_t d2h_r_idx_hostaddr; /* Array of all D2H ring's RD indices */ 317 318 uint16 max_tx_flowrings; /* maximum number of H2D rings: common + flow */ 319 uint16 max_submission_queues; /* maximum number of H2D rings: common + flow */ 320 uint16 max_completion_rings; /* maximum number of H2D rings: common + flow */ 321 uint16 max_vdevs; /* max number of virtual interfaces supported */ 322 323 sh_addr_t ifrm_w_idx_hostaddr; /* Array of all H2D ring's WR indices for IFRM */ 324 325 /* 32bit ptr to arrays of HWA DB indices for all rings in dongle memory */ 326 uint32 PHYS_ADDR_N(h2d_hwa_db_idx_ptr); /* Array of all H2D rings HWA DB indices */ 327 uint32 PHYS_ADDR_N(d2h_hwa_db_idx_ptr); /* Array of all D2H rings HWA DB indices */ 328 329 } ring_info_t; 330 331 /** 332 * A structure located in TCM that is shared between host and device, primarily used during 333 * initialization. 334 */ 335 typedef struct { 336 /** shared area version captured at flags 7:0 */ 337 uint32 flags; 338 339 uint32 PHYS_ADDR_N(trap_addr); 340 uint32 PHYS_ADDR_N(assert_exp_addr); 341 uint32 PHYS_ADDR_N(assert_file_addr); 342 uint32 assert_line; 343 uint32 PHYS_ADDR_N(console_addr); /**< Address of hnd_cons_t */ 344 345 uint32 PHYS_ADDR_N(msgtrace_addr); 346 347 uint32 fwid; 348 349 /* Used for debug/flow control */ 350 uint16 total_lfrag_pkt_cnt; 351 uint16 max_host_rxbufs; /* rsvd in spec */ 352 353 uint32 dma_rxoffset; /* rsvd in spec */ 354 355 /** these will be used for sleep request/ack, d3 req/ack */ 356 uint32 PHYS_ADDR_N(h2d_mb_data_ptr); 357 uint32 PHYS_ADDR_N(d2h_mb_data_ptr); 358 359 /* information pertinent to host IPC/msgbuf channels */ 360 /** location in the TCM memory which has the ring_info */ 361 uint32 PHYS_ADDR_N(rings_info_ptr); 362 363 /** block of host memory for the scratch buffer */ 364 uint32 host_dma_scratch_buffer_len; 365 sh_addr_t host_dma_scratch_buffer; 366 367 /* location in host memory for scb host offload structures */ 368 sh_addr_t host_scb_addr; 369 uint32 host_scb_size; 370 371 /* anonymous union for overloading fields in structure */ 372 union { 373 uint32 buzz_dbg_ptr; /* BUZZZ state format strings and trace buffer */ 374 struct { 375 /* Host provided trap buffer length in words */ 376 uint16 device_trap_debug_buffer_len; 377 uint16 rsvd2; 378 }; 379 }; 380 381 /* rev6 compatible changes */ 382 uint32 flags2; 383 uint32 host_cap; 384 385 /* location in the host address space to write trap indication. 386 * At this point for the current rev of the spec, firmware will 387 * support only indications to 32 bit host addresses. 388 * This essentially is device_trap_debug_buffer_addr 389 */ 390 sh_addr_t host_trap_addr; 391 392 /* location for host fatal error log buffer start address */ 393 uint32 PHYS_ADDR_N(device_fatal_logbuf_start); 394 395 /* location in host memory for offloaded modules */ 396 sh_addr_t hoffload_addr; 397 uint32 flags3; 398 uint32 host_cap2; 399 uint32 host_cap3; /* host indicates its txpost ext tag capabilities */ 400 uint32 PHYS_ADDR_N(etd_addr); 401 402 /* Device advertises the txpost extended tag capabilities */ 403 uint32 device_txpost_ext_tags_bitmask; 404 405 } pciedev_shared_t; 406 407 /* Device F/W provides the following access function: 408 * pciedev_shared_t *hnd_get_pciedev_shared(void); 409 */ 410 411 /* host capabilities */ 412 #define HOSTCAP_PCIEAPI_VERSION_MASK 0x000000FF 413 #define HOSTCAP_H2D_VALID_PHASE 0x00000100 414 #define HOSTCAP_H2D_ENABLE_TRAP_ON_BADPHASE 0x00000200 415 #define HOSTCAP_H2D_ENABLE_HOSTRDY 0x00000400 416 #define HOSTCAP_DB0_TIMESTAMP 0x00000800 417 #define HOSTCAP_DS_NO_OOB_DW 0x00001000 418 #define HOSTCAP_DS_INBAND_DW 0x00002000 419 #define HOSTCAP_H2D_IDMA 0x00004000 420 #define HOSTCAP_H2D_IFRM 0x00008000 421 #define HOSTCAP_H2D_DAR 0x00010000 422 #define HOSTCAP_EXTENDED_TRAP_DATA 0x00020000 423 #define HOSTCAP_TXSTATUS_METADATA 0x00040000 424 #define HOSTCAP_BT_LOGGING 0x00080000 425 #define HOSTCAP_SNAPSHOT_UPLOAD 0x00100000 426 #define HOSTCAP_FAST_DELETE_RING 0x00200000 427 #define HOSTCAP_PKT_TXSTATUS 0x00400000 428 #define HOSTCAP_UR_FW_NO_TRAP 0x00800000 /* Don't trap on UR */ 429 #define HOSTCAP_TX_CSO 0x01000000 430 #define HOSTCAP_HSCB 0x02000000 431 /* Host support for extended device trap debug buffer */ 432 #define HOSTCAP_EXT_TRAP_DBGBUF 0x04000000 433 #define HOSTCAP_TXPOST_EXT 0x08000000 434 /* Host support for enhanced debug lane */ 435 #define HOSTCAP_EDL_RING 0x10000000 436 #define HOSTCAP_PKT_TIMESTAMP 0x20000000 437 #define HOSTCAP_PKT_HP2P 0x40000000 438 #define HOSTCAP_HWA 0x80000000 439 440 #define HOSTCAP2_DURATION_SCALE_MASK 0x0000003Fu 441 442 /* extended trap debug buffer allocation sizes. Note that this buffer can be used for 443 * other trap related purposes also. 444 */ 445 #define BCMPCIE_HOST_EXT_TRAP_DBGBUF_LEN_MIN (64u * 1024u) 446 #define BCMPCIE_HOST_EXT_TRAP_DBGBUF_LEN (96u * 1024u) 447 #define BCMPCIE_HOST_EXT_TRAP_DBGBUF_LEN_MAX (256u * 1024u) 448 449 /** 450 * Mailboxes notify a remote party that an event took place, using interrupts. They use hardware 451 * support. 452 */ 453 454 /* H2D mail box Data */ 455 #define H2D_HOST_D3_INFORM 0x00000001 456 #define H2D_HOST_DS_ACK 0x00000002 457 #define H2D_HOST_DS_NAK 0x00000004 458 #define H2D_HOST_D0_INFORM_IN_USE 0x00000008 459 #define H2D_HOST_D0_INFORM 0x00000010 460 #define H2DMB_DS_ACTIVE 0x00000020 461 #define H2DMB_DS_DEVICE_WAKE 0x00000040 462 #define H2D_HOST_IDMA_INITED 0x00000080 463 #define H2D_HOST_ACK_NOINT 0x00010000 /* d2h_ack interrupt ignore */ 464 #define H2D_HOST_CONS_INT 0x80000000 /**< h2d int for console cmds */ 465 #define H2D_FW_TRAP 0x20000000 /**< h2d force TRAP */ 466 #define H2DMB_DS_HOST_SLEEP_INFORM H2D_HOST_D3_INFORM 467 #define H2DMB_DS_DEVICE_SLEEP_ACK H2D_HOST_DS_ACK 468 #define H2DMB_DS_DEVICE_SLEEP_NAK H2D_HOST_DS_NAK 469 #define H2DMB_D0_INFORM_IN_USE H2D_HOST_D0_INFORM_IN_USE 470 #define H2DMB_D0_INFORM H2D_HOST_D0_INFORM 471 #define H2DMB_FW_TRAP H2D_FW_TRAP 472 #define H2DMB_HOST_CONS_INT H2D_HOST_CONS_INT 473 #define H2DMB_DS_DEVICE_WAKE_ASSERT H2DMB_DS_DEVICE_WAKE 474 #define H2DMB_DS_DEVICE_WAKE_DEASSERT H2DMB_DS_ACTIVE 475 476 /* D2H mail box Data */ 477 #define D2H_DEV_D3_ACK 0x00000001 478 #define D2H_DEV_DS_ENTER_REQ 0x00000002 479 #define D2H_DEV_DS_EXIT_NOTE 0x00000004 480 #define D2HMB_DS_HOST_SLEEP_EXIT_ACK 0x00000008 481 #define D2H_DEV_IDMA_INITED 0x00000010 482 #define D2HMB_DS_HOST_SLEEP_ACK D2H_DEV_D3_ACK 483 #define D2HMB_DS_DEVICE_SLEEP_ENTER_REQ D2H_DEV_DS_ENTER_REQ 484 #define D2HMB_DS_DEVICE_SLEEP_EXIT D2H_DEV_DS_EXIT_NOTE 485 486 #define D2H_DEV_MB_MASK (D2H_DEV_D3_ACK | D2H_DEV_DS_ENTER_REQ | \ 487 D2H_DEV_DS_EXIT_NOTE | D2H_DEV_IDMA_INITED) 488 #define D2H_DEV_MB_INVALIDATED(x) ((!x) || (x & ~D2H_DEV_MB_MASK)) 489 490 /* trap data codes */ 491 #define D2H_DEV_FWHALT 0x10000000 492 #define D2H_DEV_EXT_TRAP_DATA 0x20000000 493 #define D2H_DEV_TRAP_IN_TRAP 0x40000000 494 #define D2H_DEV_TRAP_HOSTDB 0x80000000 /* trap as set by host DB */ 495 #define D2H_DEV_TRAP_DUE_TO_BT 0x01000000 496 /* Indicates trap due to HMAP violation */ 497 #define D2H_DEV_TRAP_DUE_TO_HMAP 0x02000000 498 /* Indicates whether HMAP violation was Write */ 499 #define D2H_DEV_TRAP_HMAP_WRITE 0x04000000 500 #define D2H_DEV_TRAP_PING_HOST_FAILURE 0x08000000 501 #define D2H_FWTRAP_MASK 0x0000001F /* Adding maskbits for TRAP information */ 502 503 #define D2HMB_FWHALT D2H_DEV_FWHALT 504 #define D2HMB_TRAP_IN_TRAP D2H_DEV_TRAP_IN_TRAP 505 #define D2HMB_EXT_TRAP_DATA D2H_DEV_EXT_TRAP_DATA 506 #define D2H_FWTRAP_MAC_SSSR_RDY 0x00010000u /* MAC SSSR prepped */ 507 508 /* Size of Extended Trap data Buffer */ 509 #define BCMPCIE_EXT_TRAP_DATA_MAXLEN 4096 510 511 /** These macro's operate on type 'inuse_lclbuf_pool_t' and are used by firmware only */ 512 #define PREVTXP(i, d) (((i) == 0) ? ((d) - 1) : ((i) - 1)) 513 #define NEXTTXP(i, d) ((((i)+1) >= (d)) ? 0 : ((i)+1)) 514 #define NEXTNTXP(i, n, d) ((((i)+(n)) >= (d)) ? 0 : ((i)+(n))) 515 #define NTXPACTIVE(r, w, d) (((r) <= (w)) ? ((w)-(r)) : ((d)-(r)+(w))) 516 #define NTXPAVAIL(r, w, d) (((d) - NTXPACTIVE((r), (w), (d))) > 1) 517 518 /* Function can be used to notify host of FW halt */ 519 #define READ_AVAIL_SPACE(w, r, d) ((w >= r) ? (uint32)(w - r) : (uint32)(d - r)) 520 #define WRITE_SPACE_AVAIL_CONTINUOUS(r, w, d) ((w >= r) ? (d - w) : (r - w)) 521 #define WRITE_SPACE_AVAIL(r, w, d) (d - (NTXPACTIVE(r, w, d)) - 1) 522 #define CHECK_WRITE_SPACE(r, w, d) ((r) > (w)) ? \ 523 (uint32)((r) - (w) - 1) : ((r) == 0 || (w) == 0) ? \ 524 (uint32)((d) - (w) - 1) : (uint32)((d) - (w)) 525 526 #define CHECK_NOWRITE_SPACE(r, w, d) \ 527 (((uint32)(r) == (uint32)((w) + 1)) || (((r) == 0) && ((w) == ((d) - 1)))) 528 529 /* These should be moved into pciedev.h --- */ 530 #define WRT_PEND(x) ((x)->wr_pending) 531 #define DNGL_RING_WPTR(msgbuf) (*((msgbuf)->tcm_rs_w_ptr)) /**< advanced by producer */ 532 #define BCMMSGBUF_RING_SET_W_PTR(msgbuf, a) (DNGL_RING_WPTR(msgbuf) = (a)) 533 534 #define DNGL_RING_RPTR(msgbuf) (*((msgbuf)->tcm_rs_r_ptr)) /**< advanced by consumer */ 535 #define BCMMSGBUF_RING_SET_R_PTR(msgbuf, a) (DNGL_RING_RPTR(msgbuf) = (a)) 536 537 #define MODULO_RING_IDX(x, y) ((x) % (y)->bitmap_size) 538 539 #define RING_READ_PTR(x) ((x)->ringstate->r_offset) 540 #define RING_WRITE_PTR(x) ((x)->ringstate->w_offset) 541 #define RING_START_PTR(x) ((x)->ringmem->base_addr.low_addr) 542 #define RING_MAX_ITEM(x) ((x)->ringmem->max_item) 543 #define RING_LEN_ITEMS(x) ((x)->ringmem->len_items) 544 #define HOST_RING_BASE(x) ((x)->dma_buf.va) 545 #define HOST_RING_END(x) ((uint8 *)HOST_RING_BASE((x)) + \ 546 ((RING_MAX_ITEM((x))-1)*RING_LEN_ITEMS((x)))) 547 548 /* Trap types copied in the pciedev_shared.trap_addr */ 549 #define FW_INITIATED_TRAP_TYPE (0x1 << 7) 550 #define HEALTHCHECK_NODS_TRAP_TYPE (0x1 << 6) 551 552 /* Device supported txpost extended tag capabilities */ 553 #define PCIE_SHARED2_DEV_TXPOST_EXT_TAG_CAP_RSVD (1u << 0u) /* Reserved */ 554 #define PCIE_SHARED2_DEV_TXPOST_EXT_TAG_CAP_CSO (1u << 1u) /* CSO */ 555 #define PCIE_SHARED2_DEV_TXPOST_EXT_TAG_CAP_MESH (1u << 2u) /* MESH */ 556 557 #define RING_MESH(x) (((x)->txpost_ext_cap_flags) & PCIE_SHARED2_DEV_TXPOST_EXT_TAG_CAP_MESH) 558 559 #endif /* _bcmpcie_h_ */ 560