1 /* 2 * MSGBUF network driver ioctl/indication encoding 3 * Broadcom 802.11abg Networking Device Driver 4 * 5 * Definitions subject to change without notice. 6 * 7 * Copyright (C) 2020, Broadcom. 8 * 9 * Unless you and Broadcom execute a separate written software license 10 * agreement governing use of this software, this software is licensed to you 11 * under the terms of the GNU General Public License version 2 (the "GPL"), 12 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 13 * following added to such license: 14 * 15 * As a special exception, the copyright holders of this software give you 16 * permission to link this software with independent modules, and to copy and 17 * distribute the resulting executable under terms of your choice, provided that 18 * you also meet, for each linked independent module, the terms and conditions of 19 * the license of that module. An independent module is a module which is not 20 * derived from this software. The special exception does not apply to any 21 * modifications of the software. 22 * 23 * 24 * <<Broadcom-WL-IPTag/Dual:>> 25 */ 26 #ifndef _bcmmsgbuf_h_ 27 #define _bcmmsgbuf_h_ 28 29 #include <ethernet.h> 30 #include <wlioctl.h> 31 #include <bcmpcie.h> 32 33 #define MSGBUF_MAX_MSG_SIZE ETHER_MAX_LEN 34 35 #define D2H_EPOCH_MODULO 253 /* sequence number wrap */ 36 #define D2H_EPOCH_INIT_VAL (D2H_EPOCH_MODULO + 1) 37 38 #define H2D_EPOCH_MODULO 253 /* sequence number wrap */ 39 #define H2D_EPOCH_INIT_VAL (H2D_EPOCH_MODULO + 1) 40 41 /* Txpost base workitem size w/o any extended tags */ 42 #define H2DRING_TXPOST_BASE_ITEMSIZE 48u 43 44 /* 45 * The workitem size - H2DRING_TXPOST_ITEMSIZE is fixed at compile time 46 * only for FW, depending on the BCMPCIE_EXT_TXPOST_SUPPORT flag. 47 * For DHD the work item size is decided dynamically based on 48 * the dongle capability announced in the PCIE_SHARED2 flags which 49 * is read by DHD during dhdpcie_readshared(). Because this 50 * happens before DHD allocs memory for the flowrings, the workitem 51 * size can be dynamic for DHD. 52 */ 53 #define H2DRING_TXPOST_EXT_ITEMSIZE 56 54 #if defined(BCMPCIE_EXT_TXPOST_SUPPORT) 55 #define H2DRING_TXPOST_ITEMSIZE H2DRING_TXPOST_EXT_ITEMSIZE 56 #else 57 #define H2DRING_TXPOST_ITEMSIZE H2DRING_TXPOST_BASE_ITEMSIZE 58 #endif 59 #define H2DRING_RXPOST_ITEMSIZE 32 60 #define H2DRING_CTRL_SUB_ITEMSIZE 40 61 62 #define D2HRING_TXCMPLT_ITEMSIZE 24 63 #define D2HRING_RXCMPLT_ITEMSIZE 40 64 65 #define D2HRING_TXCMPLT_ITEMSIZE_PREREV7 16 66 #define D2HRING_RXCMPLT_ITEMSIZE_PREREV7 32 67 68 #define D2HRING_CTRL_CMPLT_ITEMSIZE 24 69 #define H2DRING_INFO_BUFPOST_ITEMSIZE H2DRING_CTRL_SUB_ITEMSIZE 70 #define D2HRING_INFO_BUFCMPLT_ITEMSIZE D2HRING_CTRL_CMPLT_ITEMSIZE 71 72 #define D2HRING_SNAPSHOT_CMPLT_ITEMSIZE 20 73 74 #define H2DRING_DYNAMIC_INFO_MAX_ITEM 32 75 #define D2HRING_DYNAMIC_INFO_MAX_ITEM 32 76 77 #define H2DRING_TXPOST_MAX_ITEM 512 78 79 #if defined(DHD_HTPUT_TUNABLES) 80 #define H2DRING_RXPOST_MAX_ITEM 2048 81 #define D2HRING_RXCMPLT_MAX_ITEM 1024 82 #define D2HRING_TXCMPLT_MAX_ITEM 2048 83 /* Only few htput flowrings use htput max items, other use normal max items */ 84 #define H2DRING_HTPUT_TXPOST_MAX_ITEM 2048 85 #define H2DRING_CTRL_SUB_MAX_ITEM 128 86 #else 87 #define H2DRING_RXPOST_MAX_ITEM 512 88 #define D2HRING_TXCMPLT_MAX_ITEM 1024 89 #define D2HRING_RXCMPLT_MAX_ITEM 512 90 #define H2DRING_CTRL_SUB_MAX_ITEM 64 91 #endif /* DHD_HTPUT_TUNABLES */ 92 93 #define D2HRING_EDL_HDR_SIZE 48u 94 #define D2HRING_EDL_ITEMSIZE 2048u 95 #define D2HRING_EDL_MAX_ITEM 256u 96 #define D2HRING_EDL_WATERMARK (D2HRING_EDL_MAX_ITEM >> 5u) 97 98 #ifdef BCM_ROUTER_DHD 99 #define D2HRING_CTRL_CMPLT_MAX_ITEM 256 100 #else 101 #define D2HRING_CTRL_CMPLT_MAX_ITEM 64 102 #endif 103 104 /* Max pktids for each type of pkt, shared between host and dongle */ 105 #define MAX_PKTID_CTRL (1024) 106 #define MAX_PKTID_RX (4 * 1024) 107 #define MAX_PKTID_TX (36 * 1024) 108 109 enum { 110 DNGL_TO_HOST_MSGBUF, 111 HOST_TO_DNGL_MSGBUF 112 }; 113 114 enum { 115 HOST_TO_DNGL_TXP_DATA, 116 HOST_TO_DNGL_RXP_DATA, 117 HOST_TO_DNGL_CTRL, 118 DNGL_TO_HOST_DATA, 119 DNGL_TO_HOST_CTRL 120 }; 121 122 #define MESSAGE_PAYLOAD(a) (a & MSG_TYPE_INTERNAL_USE_START) ? TRUE : FALSE 123 #define PCIEDEV_FIRMWARE_TSINFO 0x1 124 #define PCIEDEV_FIRMWARE_TSINFO_FIRST 0x1 125 #define PCIEDEV_FIRMWARE_TSINFO_MIDDLE 0x2 126 #define PCIEDEV_BTLOG_POST 0x3 127 #define PCIEDEV_BT_SNAPSHOT_POST 0x4 128 129 #ifdef PCIE_API_REV1 130 131 #define BCMMSGBUF_DUMMY_REF(a, b) do {BCM_REFERENCE((a));BCM_REFERENCE((b));} while (0) 132 133 #define BCMMSGBUF_API_IFIDX(a) 0 134 #define BCMMSGBUF_API_SEQNUM(a) 0 135 #define BCMMSGBUF_IOCTL_XTID(a) 0 136 #define BCMMSGBUF_IOCTL_PKTID(a) ((a)->cmd_id) 137 138 #define BCMMSGBUF_SET_API_IFIDX(a, b) BCMMSGBUF_DUMMY_REF(a, b) 139 #define BCMMSGBUF_SET_API_SEQNUM(a, b) BCMMSGBUF_DUMMY_REF(a, b) 140 #define BCMMSGBUF_IOCTL_SET_PKTID(a, b) (BCMMSGBUF_IOCTL_PKTID(a) = (b)) 141 #define BCMMSGBUF_IOCTL_SET_XTID(a, b) BCMMSGBUF_DUMMY_REF(a, b) 142 143 #else /* PCIE_API_REV1 */ 144 145 #define BCMMSGBUF_API_IFIDX(a) ((a)->if_id) 146 #define BCMMSGBUF_IOCTL_PKTID(a) ((a)->pkt_id) 147 #define BCMMSGBUF_API_SEQNUM(a) ((a)->u.seq.seq_no) 148 #define BCMMSGBUF_IOCTL_XTID(a) ((a)->xt_id) 149 150 #define BCMMSGBUF_SET_API_IFIDX(a, b) (BCMMSGBUF_API_IFIDX((a)) = (b)) 151 #define BCMMSGBUF_SET_API_SEQNUM(a, b) (BCMMSGBUF_API_SEQNUM((a)) = (b)) 152 #define BCMMSGBUF_IOCTL_SET_PKTID(a, b) (BCMMSGBUF_IOCTL_PKTID((a)) = (b)) 153 #define BCMMSGBUF_IOCTL_SET_XTID(a, b) (BCMMSGBUF_IOCTL_XTID((a)) = (b)) 154 155 #endif /* PCIE_API_REV1 */ 156 157 /* utility data structures */ 158 159 union addr64 { 160 struct { 161 uint32 low; 162 uint32 high; 163 }; 164 struct { 165 uint32 low_addr; 166 uint32 high_addr; 167 }; 168 uint64 u64; 169 } DECLSPEC_ALIGN(8); 170 171 typedef union addr64 bcm_addr64_t; 172 173 /* IOCTL req Hdr */ 174 /* cmn Msg Hdr */ 175 typedef struct cmn_msg_hdr { 176 /** message type */ 177 uint8 msg_type; 178 /** interface index this is valid for */ 179 uint8 if_id; 180 /* flags */ 181 uint8 flags; 182 /** sequence number */ 183 uint8 epoch; 184 /** packet Identifier for the associated host buffer */ 185 uint32 request_id; 186 } cmn_msg_hdr_t; 187 188 /* cmn aggregated work item msg hdr */ 189 typedef struct cmn_aggr_msg_hdr { 190 /** aggregate message type */ 191 uint8 msg_type; 192 /** aggregation count */ 193 uint8 aggr_cnt; 194 /* current phase */ 195 uint8 phase; 196 /* flags or sequence number */ 197 union { 198 uint8 flags; /* H2D direction */ 199 uint8 epoch; /* D2H direction */ 200 }; 201 } cmn_aggr_msg_hdr_t; 202 203 /** cmn aggregated completion work item msg hdr */ 204 typedef struct compl_aggr_msg_hdr { 205 /** interface index this is valid for */ 206 uint8 if_id; 207 /** status for the completion */ 208 int8 status; 209 /** submisison flow ring id which generated this status */ 210 uint16 ring_id; 211 } compl_aggr_msg_hdr_t; 212 213 /** message type */ 214 typedef enum bcmpcie_msgtype { 215 MSG_TYPE_GEN_STATUS = 0x1, 216 MSG_TYPE_RING_STATUS = 0x2, 217 MSG_TYPE_FLOW_RING_CREATE = 0x3, 218 MSG_TYPE_FLOW_RING_CREATE_CMPLT = 0x4, 219 /* Enum value as copied from BISON 7.15: new generic message */ 220 MSG_TYPE_RING_CREATE_CMPLT = 0x4, 221 MSG_TYPE_FLOW_RING_DELETE = 0x5, 222 MSG_TYPE_FLOW_RING_DELETE_CMPLT = 0x6, 223 /* Enum value as copied from BISON 7.15: new generic message */ 224 MSG_TYPE_RING_DELETE_CMPLT = 0x6, 225 MSG_TYPE_FLOW_RING_FLUSH = 0x7, 226 MSG_TYPE_FLOW_RING_FLUSH_CMPLT = 0x8, 227 MSG_TYPE_IOCTLPTR_REQ = 0x9, 228 MSG_TYPE_IOCTLPTR_REQ_ACK = 0xA, 229 MSG_TYPE_IOCTLRESP_BUF_POST = 0xB, 230 MSG_TYPE_IOCTL_CMPLT = 0xC, 231 MSG_TYPE_EVENT_BUF_POST = 0xD, 232 MSG_TYPE_WL_EVENT = 0xE, 233 MSG_TYPE_TX_POST = 0xF, 234 MSG_TYPE_TX_STATUS = 0x10, 235 MSG_TYPE_RXBUF_POST = 0x11, 236 MSG_TYPE_RX_CMPLT = 0x12, 237 MSG_TYPE_LPBK_DMAXFER = 0x13, 238 MSG_TYPE_LPBK_DMAXFER_CMPLT = 0x14, 239 MSG_TYPE_FLOW_RING_RESUME = 0x15, 240 MSG_TYPE_FLOW_RING_RESUME_CMPLT = 0x16, 241 MSG_TYPE_FLOW_RING_SUSPEND = 0x17, 242 MSG_TYPE_FLOW_RING_SUSPEND_CMPLT = 0x18, 243 MSG_TYPE_INFO_BUF_POST = 0x19, 244 MSG_TYPE_INFO_BUF_CMPLT = 0x1A, 245 MSG_TYPE_H2D_RING_CREATE = 0x1B, 246 MSG_TYPE_D2H_RING_CREATE = 0x1C, 247 MSG_TYPE_H2D_RING_CREATE_CMPLT = 0x1D, 248 MSG_TYPE_D2H_RING_CREATE_CMPLT = 0x1E, 249 MSG_TYPE_H2D_RING_CONFIG = 0x1F, 250 MSG_TYPE_D2H_RING_CONFIG = 0x20, 251 MSG_TYPE_H2D_RING_CONFIG_CMPLT = 0x21, 252 MSG_TYPE_D2H_RING_CONFIG_CMPLT = 0x22, 253 MSG_TYPE_H2D_MAILBOX_DATA = 0x23, 254 MSG_TYPE_D2H_MAILBOX_DATA = 0x24, 255 MSG_TYPE_TIMSTAMP_BUFPOST = 0x25, 256 MSG_TYPE_HOSTTIMSTAMP = 0x26, 257 MSG_TYPE_HOSTTIMSTAMP_CMPLT = 0x27, 258 MSG_TYPE_FIRMWARE_TIMESTAMP = 0x28, 259 MSG_TYPE_SNAPSHOT_UPLOAD = 0x29, 260 MSG_TYPE_SNAPSHOT_CMPLT = 0x2A, 261 MSG_TYPE_H2D_RING_DELETE = 0x2B, 262 MSG_TYPE_D2H_RING_DELETE = 0x2C, 263 MSG_TYPE_H2D_RING_DELETE_CMPLT = 0x2D, 264 MSG_TYPE_D2H_RING_DELETE_CMPLT = 0x2E, 265 MSG_TYPE_TX_POST_AGGR = 0x2F, 266 MSG_TYPE_TX_STATUS_AGGR = 0x30, 267 MSG_TYPE_RXBUF_POST_AGGR = 0x31, 268 MSG_TYPE_RX_CMPLT_AGGR = 0x32, 269 MSG_TYPE_API_MAX_RSVD = 0x3F 270 } bcmpcie_msg_type_t; 271 272 /* message type used in internal queue */ 273 typedef enum bcmpcie_msgtype_int { 274 MSG_TYPE_INTERNAL_USE_START = 0x40, /* internal pkt */ 275 MSG_TYPE_EVENT_PYLD = 0x41, /* wl event pkt */ 276 MSG_TYPE_IOCT_PYLD = 0x42, /* ioctl compl pkt */ 277 MSG_TYPE_RX_PYLD = 0x43, 278 MSG_TYPE_HOST_FETCH = 0x44, 279 MSG_TYPE_LPBK_DMAXFER_PYLD = 0x45, /* loopback pkt */ 280 MSG_TYPE_TXMETADATA_PYLD = 0x46, /* transmit status pkt */ 281 MSG_TYPE_INDX_UPDATE = 0x47, /* write indx updated */ 282 MSG_TYPE_INFO_PYLD = 0x48, 283 MSG_TYPE_TS_EVENT_PYLD = 0x49, 284 MSG_TYPE_PVT_BTLOG_CMPLT = 0x4A, 285 MSG_TYPE_BTLOG_PYLD = 0x4B, 286 MSG_TYPE_HMAPTEST_PYLD = 0x4C, 287 MSG_TYPE_PVT_BT_SNAPSHOT_CMPLT = 0x4D, 288 MSG_TYPE_BT_SNAPSHOT_PYLD = 0x4E, 289 MSG_TYPE_LPBK_DMAXFER_PYLD_ADDR = 0x4F /* loopback from addr pkt */ 290 } bcmpcie_msgtype_int_t; 291 292 typedef enum bcmpcie_msgtype_u { 293 MSG_TYPE_TX_BATCH_POST = 0x80, 294 MSG_TYPE_IOCTL_REQ = 0x81, 295 MSG_TYPE_HOST_EVNT = 0x82, /* console related */ 296 MSG_TYPE_LOOPBACK = 0x83 297 } bcmpcie_msgtype_u_t; 298 299 /** 300 * D2H ring host wakeup soft doorbell, override the PCIE doorbell. 301 * Host configures an <32bit address,value> tuple, and dongle uses SBTOPCIE 302 * Transl0 to write specified value to host address. 303 * 304 * Use case: 32bit Address mapped to HW Accelerator Core/Thread Wakeup Register 305 * and value is Core/Thread context. Host will ensure routing the 32bit address 306 * offerred to PCIE to the mapped register. 307 * 308 * D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL 309 */ 310 typedef struct bcmpcie_soft_doorbell { 311 uint32 value; /* host defined value to be written, eg HW threadid */ 312 bcm_addr64_t haddr; /* host address, eg thread wakeup register address */ 313 uint16 items; /* interrupt coalescing: item count before wakeup */ 314 uint16 msecs; /* interrupt coalescing: timeout in millisecs */ 315 } bcmpcie_soft_doorbell_t; 316 317 /** 318 * D2H interrupt using MSI instead of INTX 319 * Host configures MSI vector offset for each D2H interrupt 320 * 321 * D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL 322 */ 323 typedef enum bcmpcie_msi_intr_idx { 324 MSI_INTR_IDX_CTRL_CMPL_RING = 0, 325 MSI_INTR_IDX_TXP_CMPL_RING = 1, 326 MSI_INTR_IDX_RXP_CMPL_RING = 2, 327 MSI_INTR_IDX_INFO_CMPL_RING = 3, 328 MSI_INTR_IDX_MAILBOX = 4, 329 MSI_INTR_IDX_MAX = 5 330 } bcmpcie_msi_intr_idx_t; 331 332 #define BCMPCIE_D2H_MSI_OFFSET_SINGLE 0 333 typedef enum bcmpcie_msi_offset_type { 334 BCMPCIE_D2H_MSI_OFFSET_MB0 = 2, 335 BCMPCIE_D2H_MSI_OFFSET_MB1 = 3, 336 BCMPCIE_D2H_MSI_OFFSET_DB0 = 4, 337 BCMPCIE_D2H_MSI_OFFSET_DB1 = 5, 338 BCMPCIE_D2H_MSI_OFFSET_H1_DB0 = 6, 339 BCMPCIE_D2H_MSI_OFFSET_MAX = 7 340 } bcmpcie_msi_offset_type_t; 341 342 typedef struct bcmpcie_msi_offset { 343 uint16 intr_idx; /* interrupt index */ 344 uint16 msi_offset; /* msi vector offset */ 345 } bcmpcie_msi_offset_t; 346 347 typedef struct bcmpcie_msi_offset_config { 348 uint32 len; 349 bcmpcie_msi_offset_t bcmpcie_msi_offset[MSI_INTR_IDX_MAX]; 350 } bcmpcie_msi_offset_config_t; 351 352 #define BCMPCIE_D2H_MSI_OFFSET_DEFAULT BCMPCIE_D2H_MSI_OFFSET_DB1 353 354 #define BCMPCIE_D2H_MSI_SINGLE 0xFFFE 355 356 /* if_id */ 357 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT 5 358 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX 0x7 359 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_MASK \ 360 (BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX << BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT) 361 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_SHFT 0 362 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_MAX 0x1F 363 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_MASK \ 364 (BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX << BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT) 365 366 /* flags */ 367 #define BCMPCIE_CMNHDR_FLAGS_DMA_R_IDX 0x1 368 #define BCMPCIE_CMNHDR_FLAGS_DMA_R_IDX_INTR 0x2 369 #define BCMPCIE_CMNHDR_FLAGS_TS_SEQNUM_INIT 0x4 370 #define BCMPCIE_CMNHDR_FLAGS_PHASE_BIT 0x80 371 #define BCMPCIE_CMNHDR_PHASE_BIT_INIT 0x80 372 373 /* IOCTL request message */ 374 typedef struct ioctl_req_msg { 375 /** common message header */ 376 cmn_msg_hdr_t cmn_hdr; 377 /** ioctl command type */ 378 uint32 cmd; 379 /** ioctl transaction ID, to pair with a ioctl response */ 380 uint16 trans_id; 381 /** input arguments buffer len */ 382 uint16 input_buf_len; 383 /** expected output len */ 384 uint16 output_buf_len; 385 /** to align the host address on 8 byte boundary */ 386 uint16 rsvd[3]; 387 /** always align on 8 byte boundary */ 388 bcm_addr64_t host_input_buf_addr; 389 /* rsvd */ 390 uint32 rsvd1[2]; 391 } ioctl_req_msg_t; 392 393 /** buffer post messages for device to use to return IOCTL responses, Events */ 394 typedef struct ioctl_resp_evt_buf_post_msg { 395 /** common message header */ 396 cmn_msg_hdr_t cmn_hdr; 397 /** length of the host buffer supplied */ 398 uint16 host_buf_len; 399 /** to align the host address on 8 byte boundary */ 400 uint16 reserved[3]; 401 /** always align on 8 byte boundary */ 402 bcm_addr64_t host_buf_addr; 403 uint32 rsvd[4]; 404 } ioctl_resp_evt_buf_post_msg_t; 405 406 /* buffer post messages for device to use to return dbg buffers */ 407 typedef ioctl_resp_evt_buf_post_msg_t info_buf_post_msg_t; 408 409 #ifdef DHD_EFI 410 #define DHD_INFOBUF_RX_BUFPOST_PKTSZ 1800 411 #else 412 #define DHD_INFOBUF_RX_BUFPOST_PKTSZ (2 * 1024) 413 #endif 414 415 #define DHD_BTLOG_RX_BUFPOST_PKTSZ (2 * 1024) 416 417 /* An infobuf host buffer starts with a 32 bit (LE) version. */ 418 #define PCIE_INFOBUF_V1 1 419 /* Infobuf v1 type MSGTRACE's data is exactly the same as the MSGTRACE data that 420 * is wrapped previously/also in a WLC_E_TRACE event. See structure 421 * msgrace_hdr_t in msgtrace.h. 422 */ 423 #define PCIE_INFOBUF_V1_TYPE_MSGTRACE 1 424 425 /* Infobuf v1 type LOGTRACE data is exactly the same as the LOGTRACE data that 426 * is wrapped previously/also in a WLC_E_TRACE event. See structure 427 * msgrace_hdr_t in msgtrace.h. (The only difference between a MSGTRACE 428 * and a LOGTRACE is the "trace type" field.) 429 */ 430 #define PCIE_INFOBUF_V1_TYPE_LOGTRACE 2 431 432 /* An infobuf version 1 host buffer has a single TLV. The information on the 433 * version 1 types follow this structure definition. (int's LE) 434 */ 435 typedef struct info_buf_payload_hdr_s { 436 uint16 type; 437 uint16 length; 438 } info_buf_payload_hdr_t; 439 440 /* BT logs/memory to DMA directly from BT memory to host */ 441 typedef struct info_buf_btlog_s { 442 void (*status_cb)(void *ctx, void *p, int error); /* obsolete - to be removed */ 443 void *ctx; 444 dma64addr_t src_addr; 445 uint32 length; 446 bool (*pcie_status_cb)(osl_t *osh, void *p, int error); 447 uint32 bt_intstatus; 448 int error; 449 } info_buf_btlog_t; 450 451 /** snapshot upload request message */ 452 typedef struct snapshot_upload_request_msg { 453 /** common message header */ 454 cmn_msg_hdr_t cmn_hdr; 455 /** length of the snaphost buffer supplied */ 456 uint32 snapshot_buf_len; 457 /** type of snapshot */ 458 uint8 snapshot_type; 459 /** snapshot param */ 460 uint8 snapshot_param; 461 /** to align the host address on 8 byte boundary */ 462 uint8 reserved[2]; 463 /** always align on 8 byte boundary */ 464 bcm_addr64_t host_buf_addr; 465 uint32 rsvd[4]; 466 } snapshot_upload_request_msg_t; 467 468 /** snapshot types */ 469 typedef enum bcmpcie_snapshot_type { 470 SNAPSHOT_TYPE_BT = 0, /* Bluetooth SRAM and patch RAM */ 471 SNAPSHOT_TYPE_WLAN_SOCRAM = 1, /* WLAN SOCRAM */ 472 SNAPSHOT_TYPE_WLAN_HEAP = 2, /* WLAN HEAP */ 473 SNAPSHOT_TYPE_WLAN_REGISTER = 3 /* WLAN registers */ 474 } bcmpcie_snapshot_type_t; 475 476 #define PCIE_DMA_XFER_FLG_D11_LPBK_MASK 0xF 477 #define PCIE_DMA_XFER_FLG_D11_LPBK_SHIFT 2 478 #define PCIE_DMA_XFER_FLG_CORE_NUMBER_MASK 3 479 #define PCIE_DMA_XFER_FLG_CORE_NUMBER_SHIFT 0 480 481 typedef struct pcie_dma_xfer_params { 482 /** common message header */ 483 cmn_msg_hdr_t cmn_hdr; 484 485 /** always align on 8 byte boundary */ 486 bcm_addr64_t host_input_buf_addr; 487 488 /** always align on 8 byte boundary */ 489 bcm_addr64_t host_ouput_buf_addr; 490 491 /** length of transfer */ 492 uint32 xfer_len; 493 /** delay before doing the src txfer */ 494 uint32 srcdelay; 495 /** delay before doing the dest txfer */ 496 uint32 destdelay; 497 uint8 rsvd[3]; 498 /* bit0: D11 DMA loopback flag */ 499 uint8 flags; 500 } pcie_dma_xfer_params_t; 501 502 #define BCMPCIE_FLOW_RING_INTF_HP2P 0x01u /* bit0 */ 503 #define BCMPCIE_FLOW_RING_OPT_EXT_TXSTATUS 0x02u /* bit1 */ 504 #define BCMPCIE_FLOW_RING_INTF_MESH 0x04u /* bit2, identifies the mesh flow ring */ 505 506 /** Complete msgbuf hdr for flow ring update from host to dongle */ 507 typedef struct tx_flowring_create_request { 508 cmn_msg_hdr_t msg; 509 uint8 da[ETHER_ADDR_LEN]; 510 uint8 sa[ETHER_ADDR_LEN]; 511 uint8 tid; 512 uint8 if_flags; 513 uint16 flow_ring_id; 514 uint8 tc; 515 /* priority_ifrmmask is to define core mask in ifrm mode. 516 * currently it is not used for priority. so uses solely for ifrm mask 517 */ 518 uint8 priority_ifrmmask; 519 uint16 int_vector; 520 uint16 max_items; 521 uint16 len_item; 522 bcm_addr64_t flow_ring_ptr; 523 } tx_flowring_create_request_t; 524 525 typedef struct tx_flowring_delete_request { 526 cmn_msg_hdr_t msg; 527 uint16 flow_ring_id; 528 uint16 reason; 529 uint32 rsvd[7]; 530 } tx_flowring_delete_request_t; 531 532 typedef tx_flowring_delete_request_t d2h_ring_delete_req_t; 533 typedef tx_flowring_delete_request_t h2d_ring_delete_req_t; 534 535 typedef struct tx_flowring_flush_request { 536 cmn_msg_hdr_t msg; 537 uint16 flow_ring_id; 538 uint16 reason; 539 uint32 rsvd[7]; 540 } tx_flowring_flush_request_t; 541 542 /** Subtypes for ring_config_req control message */ 543 typedef enum ring_config_subtype { 544 /** Default D2H PCIE doorbell override using ring_config_req msg */ 545 D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL = 1, /* Software doorbell */ 546 D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL = 2 /* MSI configuration */ 547 } ring_config_subtype_t; 548 549 typedef struct ring_config_req { /* pulled from upcoming rev6 ... */ 550 cmn_msg_hdr_t msg; 551 uint16 subtype; 552 uint16 ring_id; 553 uint32 rsvd; 554 union { 555 uint32 data[6]; 556 /** D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL */ 557 bcmpcie_soft_doorbell_t soft_doorbell; 558 /** D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL */ 559 bcmpcie_msi_offset_config_t msi_offset; 560 }; 561 } ring_config_req_t; 562 563 /* data structure to use to create on the fly d2h rings */ 564 typedef struct d2h_ring_create_req { 565 cmn_msg_hdr_t msg; 566 uint16 ring_id; 567 uint16 ring_type; 568 uint32 flags; 569 bcm_addr64_t ring_ptr; 570 uint16 max_items; 571 uint16 len_item; 572 uint32 rsvd[3]; 573 } d2h_ring_create_req_t; 574 575 /* data structure to use to create on the fly h2d rings */ 576 #define MAX_COMPLETION_RING_IDS_ASSOCIATED 4 577 typedef struct h2d_ring_create_req { 578 cmn_msg_hdr_t msg; 579 uint16 ring_id; 580 uint8 ring_type; 581 uint8 n_completion_ids; 582 uint32 flags; 583 bcm_addr64_t ring_ptr; 584 uint16 max_items; 585 uint16 len_item; 586 uint16 completion_ring_ids[MAX_COMPLETION_RING_IDS_ASSOCIATED]; 587 uint32 rsvd; 588 } h2d_ring_create_req_t; 589 590 typedef struct d2h_ring_config_req { 591 cmn_msg_hdr_t msg; 592 uint16 d2h_ring_config_subtype; 593 uint16 d2h_ring_id; 594 uint32 d2h_ring_config_data[4]; 595 uint32 rsvd[3]; 596 } d2h_ring_config_req_t; 597 598 typedef struct h2d_ring_config_req { 599 cmn_msg_hdr_t msg; 600 uint16 h2d_ring_config_subtype; 601 uint16 h2d_ring_id; 602 uint32 h2d_ring_config_data; 603 uint32 rsvd[6]; 604 } h2d_ring_config_req_t; 605 606 typedef struct h2d_mailbox_data { 607 cmn_msg_hdr_t msg; 608 uint32 mail_box_data; 609 uint32 rsvd[7]; 610 } h2d_mailbox_data_t; 611 typedef struct host_timestamp_msg { 612 cmn_msg_hdr_t msg; 613 uint16 xt_id; /* transaction ID */ 614 uint16 input_data_len; /* data len at the host_buf_addr, data in TLVs */ 615 uint16 seqnum; /* number of times host captured the timestamp */ 616 uint16 rsvd; 617 /* always align on 8 byte boundary */ 618 bcm_addr64_t host_buf_addr; 619 /* rsvd */ 620 uint32 rsvd1[4]; 621 } host_timestamp_msg_t; 622 623 /* buffer post message for timestamp events MSG_TYPE_TIMSTAMP_BUFPOST */ 624 typedef ioctl_resp_evt_buf_post_msg_t ts_buf_post_msg_t; 625 626 typedef union ctrl_submit_item { 627 ioctl_req_msg_t ioctl_req; 628 ioctl_resp_evt_buf_post_msg_t resp_buf_post; 629 pcie_dma_xfer_params_t dma_xfer; 630 tx_flowring_create_request_t flow_create; 631 tx_flowring_delete_request_t flow_delete; 632 tx_flowring_flush_request_t flow_flush; 633 ring_config_req_t ring_config_req; 634 d2h_ring_create_req_t d2h_create; 635 h2d_ring_create_req_t h2d_create; 636 d2h_ring_config_req_t d2h_config; 637 h2d_ring_config_req_t h2d_config; 638 h2d_mailbox_data_t h2d_mailbox_data; 639 host_timestamp_msg_t host_ts; 640 ts_buf_post_msg_t ts_buf_post; 641 d2h_ring_delete_req_t d2h_delete; 642 h2d_ring_delete_req_t h2d_delete; 643 unsigned char check[H2DRING_CTRL_SUB_ITEMSIZE]; 644 } ctrl_submit_item_t; 645 646 typedef struct info_ring_submit_item { 647 info_buf_post_msg_t info_buf_post; 648 unsigned char check[H2DRING_INFO_BUFPOST_ITEMSIZE]; 649 } info_sumbit_item_t; 650 651 /** Control Completion messages (20 bytes) */ 652 typedef struct compl_msg_hdr { 653 union { 654 /** status for the completion */ 655 int16 status; 656 657 /* mutually exclusive with pkt fate debug feature */ 658 struct pktts_compl_hdr { 659 uint16 d_t4; /* Delta TimeStamp 3: T4-tref */ 660 } tx_pktts; 661 }; 662 /** submisison flow ring id which generated this status */ 663 union { 664 uint16 ring_id; 665 uint16 flow_ring_id; 666 }; 667 } compl_msg_hdr_t; 668 669 /** XOR checksum or a magic number to audit DMA done */ 670 typedef uint32 dma_done_t; 671 672 #define MAX_CLKSRC_ID 0xF 673 #define TX_PKT_RETRY_CNT_0_MASK 0x000000FF 674 #define TX_PKT_RETRY_CNT_0_SHIFT 0 675 #define TX_PKT_RETRY_CNT_1_MASK 0x0000FF00 676 #define TX_PKT_RETRY_CNT_1_SHIFT 8 677 #define TX_PKT_RETRY_CNT_2_MASK 0x00FF0000 678 #define TX_PKT_RETRY_CNT_2_SHIFT 16 679 #define TX_PKT_BAND_INFO 0x0F000000 680 #define TX_PKT_BAND_INFO_SHIFT 24 681 #define TX_PKT_VALID_INFO 0xF0000000 682 #define TX_PKT_VALID_INFO_SHIFT 28 683 684 typedef struct ts_timestamp_srcid { 685 union { 686 uint32 ts_low; /* time stamp low 32 bits */ 687 uint32 rate_spec; /* use ratespec */ 688 }; 689 union { 690 uint32 ts_high; /* time stamp high 28 bits */ 691 union { 692 uint32 ts_high_ext :28; /* time stamp high 28 bits */ 693 uint32 clk_id_ext :3; /* clock ID source */ 694 uint32 phase :1; /* Phase bit */ 695 dma_done_t marker_ext; 696 }; 697 uint32 tx_pkt_band_retry_info; 698 }; 699 } ts_timestamp_srcid_t; 700 701 typedef ts_timestamp_srcid_t ipc_timestamp_t; 702 703 typedef struct ts_timestamp { 704 uint32 low; 705 uint32 high; 706 } ts_timestamp_t; 707 708 typedef ts_timestamp_t tick_count_64_t; 709 typedef ts_timestamp_t ts_timestamp_ns_64_t; 710 typedef ts_timestamp_t ts_correction_m_t; 711 typedef ts_timestamp_t ts_correction_b_t; 712 713 typedef struct _pktts { 714 uint32 tref; /* Ref Clk in uSec (currently, tsf) */ 715 uint16 d_t2; /* Delta TimeStamp 1: T2-tref */ 716 uint16 d_t3; /* Delta TimeStamp 2: T3-tref */ 717 } pktts_t; 718 719 /* completion header status codes */ 720 #define BCMPCIE_SUCCESS 0 721 #define BCMPCIE_NOTFOUND 1 722 #define BCMPCIE_NOMEM 2 723 #define BCMPCIE_BADOPTION 3 724 #define BCMPCIE_RING_IN_USE 4 725 #define BCMPCIE_RING_ID_INVALID 5 726 #define BCMPCIE_PKT_FLUSH 6 727 #define BCMPCIE_NO_EVENT_BUF 7 728 #define BCMPCIE_NO_RX_BUF 8 729 #define BCMPCIE_NO_IOCTLRESP_BUF 9 730 #define BCMPCIE_MAX_IOCTLRESP_BUF 10 731 #define BCMPCIE_MAX_EVENT_BUF 11 732 #define BCMPCIE_BAD_PHASE 12 733 #define BCMPCIE_INVALID_CPL_RINGID 13 734 #define BCMPCIE_RING_TYPE_INVALID 14 735 #define BCMPCIE_NO_TS_EVENT_BUF 15 736 #define BCMPCIE_MAX_TS_EVENT_BUF 16 737 #define BCMPCIE_PCIE_NO_BTLOG_BUF 17 738 #define BCMPCIE_BT_DMA_ERR 18 739 #define BCMPCIE_BT_DMA_DESCR_FETCH_ERR 19 740 #define BCMPCIE_SNAPSHOT_ERR 20 741 #define BCMPCIE_NOT_READY 21 742 #define BCMPCIE_INVALID_DATA 22 743 #define BCMPCIE_NO_RESPONSE 23 744 #define BCMPCIE_NO_CLOCK 24 745 746 /** IOCTL completion response */ 747 typedef struct ioctl_compl_resp_msg { 748 /** common message header */ 749 cmn_msg_hdr_t cmn_hdr; 750 /** completion message header */ 751 compl_msg_hdr_t compl_hdr; 752 /** response buffer len where a host buffer is involved */ 753 uint16 resp_len; 754 /** transaction id to pair with a request */ 755 uint16 trans_id; 756 /** cmd id */ 757 uint32 cmd; 758 /** XOR checksum or a magic number to audit DMA done */ 759 dma_done_t marker; 760 } ioctl_comp_resp_msg_t; 761 762 /** IOCTL request acknowledgement */ 763 typedef struct ioctl_req_ack_msg { 764 /** common message header */ 765 cmn_msg_hdr_t cmn_hdr; 766 /** completion message header */ 767 compl_msg_hdr_t compl_hdr; 768 /** cmd id */ 769 uint32 cmd; 770 uint32 rsvd; 771 /** XOR checksum or a magic number to audit DMA done */ 772 dma_done_t marker; 773 } ioctl_req_ack_msg_t; 774 775 /** WL event message: send from device to host */ 776 typedef struct wlevent_req_msg { 777 /** common message header */ 778 cmn_msg_hdr_t cmn_hdr; 779 /** completion message header */ 780 compl_msg_hdr_t compl_hdr; 781 /** event data len valid with the event buffer */ 782 uint16 event_data_len; 783 /** sequence number */ 784 uint16 seqnum; 785 /** rsvd */ 786 uint32 rsvd; 787 /** XOR checksum or a magic number to audit DMA done */ 788 dma_done_t marker; 789 } wlevent_req_msg_t; 790 791 /** dma xfer complete message */ 792 typedef struct pcie_dmaxfer_cmplt { 793 /** common message header */ 794 cmn_msg_hdr_t cmn_hdr; 795 /** completion message header */ 796 compl_msg_hdr_t compl_hdr; 797 uint32 rsvd[2]; 798 /** XOR checksum or a magic number to audit DMA done */ 799 dma_done_t marker; 800 } pcie_dmaxfer_cmplt_t; 801 802 /** general status message */ 803 typedef struct pcie_gen_status { 804 /** common message header */ 805 cmn_msg_hdr_t cmn_hdr; 806 /** completion message header */ 807 compl_msg_hdr_t compl_hdr; 808 uint32 rsvd[2]; 809 /** XOR checksum or a magic number to audit DMA done */ 810 dma_done_t marker; 811 } pcie_gen_status_t; 812 813 /** ring status message */ 814 typedef struct pcie_ring_status { 815 /** common message header */ 816 cmn_msg_hdr_t cmn_hdr; 817 /** completion message header */ 818 compl_msg_hdr_t compl_hdr; 819 /** message which firmware couldn't decode */ 820 uint16 write_idx; 821 uint16 rsvd[3]; 822 /** XOR checksum or a magic number to audit DMA done */ 823 dma_done_t marker; 824 } pcie_ring_status_t; 825 826 typedef struct ring_create_response { 827 cmn_msg_hdr_t cmn_hdr; 828 compl_msg_hdr_t cmplt; 829 uint32 rsvd[2]; 830 /** XOR checksum or a magic number to audit DMA done */ 831 dma_done_t marker; 832 } ring_create_response_t; 833 834 typedef ring_create_response_t tx_flowring_create_response_t; 835 typedef ring_create_response_t h2d_ring_create_response_t; 836 typedef ring_create_response_t d2h_ring_create_response_t; 837 838 typedef struct tx_flowring_delete_response { 839 cmn_msg_hdr_t msg; 840 compl_msg_hdr_t cmplt; 841 uint16 read_idx; 842 uint16 rsvd[3]; 843 /** XOR checksum or a magic number to audit DMA done */ 844 dma_done_t marker; 845 } tx_flowring_delete_response_t; 846 847 typedef tx_flowring_delete_response_t h2d_ring_delete_response_t; 848 typedef tx_flowring_delete_response_t d2h_ring_delete_response_t; 849 850 typedef struct tx_flowring_flush_response { 851 cmn_msg_hdr_t msg; 852 compl_msg_hdr_t cmplt; 853 uint32 rsvd[2]; 854 /** XOR checksum or a magic number to audit DMA done */ 855 dma_done_t marker; 856 } tx_flowring_flush_response_t; 857 858 /** Common layout of all d2h control messages */ 859 typedef struct ctrl_compl_msg { 860 /** common message header */ 861 cmn_msg_hdr_t cmn_hdr; 862 /** completion message header */ 863 compl_msg_hdr_t compl_hdr; 864 uint32 rsvd[2]; 865 /** XOR checksum or a magic number to audit DMA done */ 866 dma_done_t marker; 867 } ctrl_compl_msg_t; 868 869 typedef struct ring_config_resp { 870 /** common message header */ 871 cmn_msg_hdr_t cmn_hdr; 872 /** completion message header */ 873 compl_msg_hdr_t compl_hdr; 874 uint16 subtype; 875 uint16 rsvd[3]; 876 /** XOR checksum or a magic number to audit DMA done */ 877 dma_done_t marker; 878 } ring_config_resp_t; 879 880 typedef struct d2h_mailbox_data { 881 cmn_msg_hdr_t msg; 882 compl_msg_hdr_t cmplt; 883 uint32 d2h_mailbox_data; 884 uint32 rsvd[1]; 885 /* XOR checksum or a magic number to audit DMA done */ 886 dma_done_t marker; 887 } d2h_mailbox_data_t; 888 889 /* dbg buf completion msg: send from device to host */ 890 typedef struct info_buf_resp { 891 /* common message header */ 892 cmn_msg_hdr_t cmn_hdr; 893 /* completion message header */ 894 compl_msg_hdr_t compl_hdr; 895 /* event data len valid with the event buffer */ 896 uint16 info_data_len; 897 /* sequence number */ 898 uint16 seqnum; 899 /* destination */ 900 uint8 dest; 901 /* rsvd */ 902 uint8 rsvd[3]; 903 /* XOR checksum or a magic number to audit DMA done */ 904 dma_done_t marker; 905 } info_buf_resp_t; 906 907 /* snapshot completion msg: send from device to host */ 908 typedef struct snapshot_resp { 909 /* common message header */ 910 cmn_msg_hdr_t cmn_hdr; 911 /* completion message header */ 912 compl_msg_hdr_t compl_hdr; 913 /* snapshot length uploaded */ 914 uint32 resp_len; 915 /* snapshot type */ 916 uint8 type; 917 /* rsvd */ 918 uint8 rsvd[3]; 919 /* XOR checksum or a magic number to audit DMA done */ 920 dma_done_t marker; 921 } snapshot_resp_t; 922 923 typedef struct info_ring_cpl_item { 924 info_buf_resp_t info_buf_post; 925 unsigned char check[D2HRING_INFO_BUFCMPLT_ITEMSIZE]; 926 } info_cpl_item_t; 927 928 typedef struct host_timestamp_msg_cpl { 929 cmn_msg_hdr_t msg; 930 compl_msg_hdr_t cmplt; 931 uint16 xt_id; /* transaction ID */ 932 uint16 rsvd; 933 uint32 rsvd1; 934 /* XOR checksum or a magic number to audit DMA done */ 935 dma_done_t marker; 936 } host_timestamp_msg_cpl_t; 937 938 typedef struct fw_timestamp_event_msg { 939 cmn_msg_hdr_t msg; 940 compl_msg_hdr_t cmplt; 941 /* fw captures time stamp info and passed that to host in TLVs */ 942 uint16 buf_len; /* length of the time stamp data copied in host buf */ 943 uint16 seqnum; /* number of times fw captured time stamp */ 944 uint32 rsvd; 945 /* XOR checksum or a magic number to audit DMA done */ 946 dma_done_t marker; 947 } fw_timestamp_event_msg_t; 948 949 typedef union ctrl_completion_item { 950 ioctl_comp_resp_msg_t ioctl_resp; 951 wlevent_req_msg_t event; 952 ioctl_req_ack_msg_t ioct_ack; 953 pcie_dmaxfer_cmplt_t pcie_xfer_cmplt; 954 pcie_gen_status_t pcie_gen_status; 955 pcie_ring_status_t pcie_ring_status; 956 tx_flowring_create_response_t txfl_create_resp; 957 tx_flowring_delete_response_t txfl_delete_resp; 958 tx_flowring_flush_response_t txfl_flush_resp; 959 ctrl_compl_msg_t ctrl_compl; 960 ring_config_resp_t ring_config_resp; 961 d2h_mailbox_data_t d2h_mailbox_data; 962 info_buf_resp_t dbg_resp; 963 h2d_ring_create_response_t h2d_ring_create_resp; 964 d2h_ring_create_response_t d2h_ring_create_resp; 965 host_timestamp_msg_cpl_t host_ts_cpl; 966 fw_timestamp_event_msg_t fw_ts_event; 967 h2d_ring_delete_response_t h2d_ring_delete_resp; 968 d2h_ring_delete_response_t d2h_ring_delete_resp; 969 unsigned char ctrl_response[D2HRING_CTRL_CMPLT_ITEMSIZE]; 970 } ctrl_completion_item_t; 971 972 /** H2D Rxpost ring work items */ 973 typedef struct host_rxbuf_post { 974 /** common message header */ 975 cmn_msg_hdr_t cmn_hdr; 976 /** provided meta data buffer len */ 977 uint16 metadata_buf_len; 978 /** provided data buffer len to receive data */ 979 uint16 data_buf_len; 980 /** alignment to make the host buffers start on 8 byte boundary */ 981 uint32 rsvd; 982 /** provided meta data buffer */ 983 bcm_addr64_t metadata_buf_addr; 984 /** provided data buffer to receive data */ 985 bcm_addr64_t data_buf_addr; 986 } host_rxbuf_post_t; 987 988 typedef union rxbuf_submit_item { 989 host_rxbuf_post_t rxpost; 990 unsigned char check[H2DRING_RXPOST_ITEMSIZE]; 991 } rxbuf_submit_item_t; 992 993 /* D2H Rxcompletion ring work items for IPC rev7 */ 994 typedef struct host_rxbuf_cmpl { 995 /** common message header */ 996 cmn_msg_hdr_t cmn_hdr; 997 /** completion message header */ 998 compl_msg_hdr_t compl_hdr; 999 /** filled up meta data len */ 1000 uint16 metadata_len; 1001 /** filled up buffer len to receive data */ 1002 uint16 data_len; 1003 /** offset in the host rx buffer where the data starts */ 1004 uint16 data_offset; 1005 /** offset in the host rx buffer where the data starts */ 1006 uint16 flags; 1007 /** rx status */ 1008 uint32 rx_status_0; 1009 uint32 rx_status_1; 1010 1011 union { /* size per IPC = (3 x uint32) bytes */ 1012 struct { 1013 /* used by Monitor mode */ 1014 uint32 marker; 1015 /* timestamp */ 1016 ipc_timestamp_t ts; 1017 }; 1018 1019 /* LatTS_With_XORCSUM */ 1020 struct { 1021 /* latency timestamp */ 1022 pktts_t rx_pktts; 1023 /* XOR checksum or a magic number to audit DMA done */ 1024 dma_done_t marker_ext; 1025 }; 1026 }; 1027 } host_rxbuf_cmpl_t; 1028 1029 typedef union rxbuf_complete_item { 1030 host_rxbuf_cmpl_t rxcmpl; 1031 unsigned char check[D2HRING_RXCMPLT_ITEMSIZE]; 1032 } rxbuf_complete_item_t; 1033 1034 typedef struct host_txbuf_post_v1 { 1035 /** common message header */ 1036 cmn_msg_hdr_t cmn_hdr; 1037 /** eth header */ 1038 uint8 txhdr[ETHER_HDR_LEN]; 1039 /** flags */ 1040 uint8 flags; 1041 /** number of segments */ 1042 uint8 seg_cnt; 1043 1044 /** provided meta data buffer for txstatus */ 1045 bcm_addr64_t metadata_buf_addr; 1046 /** provided data buffer containing Tx payload */ 1047 bcm_addr64_t data_buf_addr; 1048 /** provided meta data buffer len */ 1049 uint16 metadata_buf_len; 1050 /** provided data buffer len */ 1051 uint16 data_len; 1052 union { 1053 struct { 1054 /** extended transmit flags */ 1055 uint8 ext_flags; 1056 uint8 scale_factor; 1057 1058 /** user defined rate */ 1059 uint8 rate; 1060 uint8 exp_time; 1061 }; 1062 /** XOR checksum or a magic number to audit DMA done */ 1063 dma_done_t marker; 1064 }; 1065 } host_txbuf_post_v1_t; 1066 1067 typedef enum pkt_csum_type_shift { 1068 PKT_CSUM_TYPE_IPV4_SHIFT = 0, /* pkt has IPv4 hdr */ 1069 PKT_CSUM_TYPE_IPV6_SHIFT = 1, /* pkt has IPv6 hdr */ 1070 PKT_CSUM_TYPE_TCP_SHIFT = 2, /* pkt has TCP hdr */ 1071 PKT_CSUM_TYPE_UDP_SHIFT = 3, /* pkt has UDP hdr */ 1072 PKT_CSUM_TYPE_NWK_CSUM_SHIFT = 4, /* pkt requires IP csum offload */ 1073 PKT_CSUM_TYPE_TRANS_CSUM_SHIFT = 5, /* pkt requires TCP/UDP csum offload */ 1074 PKT_CSUM_TYPE_PSEUDOHDR_CSUM_SHIFT = 6, /* pkt requires pseudo header csum offload */ 1075 } pkt_type_shift_t; 1076 1077 typedef struct pkt_info_cso { 1078 /* packet csum type = ipv4/v6|udp|tcp|nwk_csum|trans_csum|ph_csum */ 1079 uint8 ver; 1080 uint8 pkt_csum_type; 1081 uint8 nwk_hdr_len; /* IP header length */ 1082 uint8 trans_hdr_len; /* TCP header length */ 1083 } pkt_info_cso_t; 1084 1085 typedef struct host_txbuf_post_v2 { 1086 /** common message header */ 1087 cmn_msg_hdr_t cmn_hdr; 1088 /** eth header */ 1089 uint8 txhdr[ETHER_HDR_LEN]; 1090 /** flags */ 1091 uint8 flags; 1092 /** number of segments */ 1093 uint8 seg_cnt; 1094 1095 /** provided meta data buffer for txstatus */ 1096 bcm_addr64_t metadata_buf_addr; 1097 /** provided data buffer containing Tx payload */ 1098 bcm_addr64_t data_buf_addr; 1099 /** provided meta data buffer len */ 1100 uint16 metadata_buf_len; 1101 /** provided data buffer len */ 1102 uint16 data_len; 1103 struct { 1104 /** extended transmit flags */ 1105 uint8 ext_flags; 1106 uint8 scale_factor; 1107 1108 /** user defined rate */ 1109 uint8 rate; 1110 uint8 exp_time; 1111 }; 1112 /** additional information on the packet required for CSO */ 1113 pkt_info_cso_t pktinfo; 1114 uint32 PAD; 1115 } host_txbuf_post_v2_t; 1116 1117 #if defined(BCMPCIE_EXT_TXPOST_SUPPORT) || defined(TX_CSO) 1118 typedef host_txbuf_post_v2_t host_txbuf_post_t; 1119 #else 1120 typedef host_txbuf_post_v1_t host_txbuf_post_t; 1121 #endif 1122 1123 #define BCMPCIE_PKT_FLAGS_FRAME_802_3 0x01 1124 #define BCMPCIE_PKT_FLAGS_FRAME_802_11 0x02 1125 1126 #define BCMPCIE_PKT_FLAGS_FRAME_NORETRY 0x01 /* Disable retry on this frame */ 1127 #define BCMPCIE_PKT_FLAGS_FRAME_NOAGGR 0x02 /* Disable aggregation for this frame */ 1128 #define BCMPCIE_PKT_FLAGS_FRAME_UDR 0x04 /* User defined rate for this frame */ 1129 #define BCMPCIE_PKT_FLAGS_FRAME_ATTR_MASK 0x07 /* Attribute mask */ 1130 1131 #define BCMPCIE_PKT_FLAGS_FRAME_EXEMPT_MASK 0x03 /* Exempt uses 2 bits */ 1132 #define BCMPCIE_PKT_FLAGS_FRAME_EXEMPT_SHIFT 0x02 /* needs to be shifted past other bits */ 1133 1134 #define BCMPCIE_PKT_FLAGS_EPOCH_SHIFT 3u 1135 #define BCMPCIE_PKT_FLAGS_EPOCH_MASK (1u << BCMPCIE_PKT_FLAGS_EPOCH_SHIFT) 1136 1137 #define BCMPCIE_PKT_FLAGS_PRIO_SHIFT 5 1138 #define BCMPCIE_PKT_FLAGS_PRIO_MASK (7 << BCMPCIE_PKT_FLAGS_PRIO_SHIFT) 1139 #define BCMPCIE_PKT_FLAGS_MONITOR_NO_AMSDU 0x00 1140 #define BCMPCIE_PKT_FLAGS_MONITOR_FIRST_PKT 0x01 1141 #define BCMPCIE_PKT_FLAGS_MONITOR_INTER_PKT 0x02 1142 #define BCMPCIE_PKT_FLAGS_MONITOR_LAST_PKT 0x03 1143 #define BCMPCIE_PKT_FLAGS_MONITOR_SHIFT 8 1144 #define BCMPCIE_PKT_FLAGS_MONITOR_MASK (3 << BCMPCIE_PKT_FLAGS_MONITOR_SHIFT) 1145 1146 #define BCMPCIE_PKT_FLAGS_FRAME_MESH 0x400u 1147 /* Indicate RX checksum verified and passed */ 1148 #define BCMPCIE_PKT_FLAGS_RCSUM_VALID 0x800u 1149 1150 /* These are added to fix up compile issues */ 1151 #define BCMPCIE_TXPOST_FLAGS_FRAME_802_3 BCMPCIE_PKT_FLAGS_FRAME_802_3 1152 #define BCMPCIE_TXPOST_FLAGS_FRAME_802_11 BCMPCIE_PKT_FLAGS_FRAME_802_11 1153 #define BCMPCIE_TXPOST_FLAGS_PRIO_SHIFT BCMPCIE_PKT_FLAGS_PRIO_SHIFT 1154 #define BCMPCIE_TXPOST_FLAGS_PRIO_MASK BCMPCIE_PKT_FLAGS_PRIO_MASK 1155 1156 #define BCMPCIE_TXPOST_FLAGS_HOST_SFH_LLC 0x10u 1157 #define BCMPCIE_TXPOST_RATE_EXT_USAGE 0x80 /* The rate field has extended usage */ 1158 #define BCMPCIE_TXPOST_RATE_PROFILE_IDX_MASK 0x07 /* The Tx profile index in the rate field */ 1159 1160 /* H2D Txpost ring work items */ 1161 typedef union txbuf_submit_item { 1162 host_txbuf_post_t txpost; 1163 unsigned char check[H2DRING_TXPOST_ITEMSIZE]; 1164 } txbuf_submit_item_t; 1165 1166 /* D2H Txcompletion ring work items - extended for IOC rev7 */ 1167 typedef struct host_txbuf_cmpl { 1168 /** common message header */ 1169 cmn_msg_hdr_t cmn_hdr; 1170 /** completion message header */ 1171 compl_msg_hdr_t compl_hdr; 1172 1173 union { /* size per IPC = (3 x uint32) bytes */ 1174 /* Usage 1: TxS_With_TimeSync */ 1175 struct { 1176 struct { 1177 union { 1178 /** provided meta data len */ 1179 uint16 metadata_len; 1180 /** provided extended TX status */ 1181 uint16 tx_status_ext; 1182 }; /*Ext_TxStatus */ 1183 1184 /** WLAN side txstatus */ 1185 uint16 tx_status; 1186 }; /* TxS */ 1187 /* timestamp */ 1188 ipc_timestamp_t ts; 1189 }; /* TxS_with_TS */ 1190 1191 /* Usage 2: LatTS_With_XORCSUM */ 1192 struct { 1193 /* latency timestamp */ 1194 pktts_t tx_pktts; 1195 /* XOR checksum or a magic number to audit DMA done */ 1196 dma_done_t marker_ext; 1197 }; 1198 }; 1199 1200 } host_txbuf_cmpl_t; 1201 1202 typedef union txbuf_complete_item { 1203 host_txbuf_cmpl_t txcmpl; 1204 unsigned char check[D2HRING_TXCMPLT_ITEMSIZE]; 1205 } txbuf_complete_item_t; 1206 1207 #define METADATA_VER_1 1u 1208 #define METADATA_VER_2 2u 1209 #define PCIE_METADATA_VER METADATA_VER_2 1210 1211 /* version and length are not part of this structure. 1212 * dhd queries version and length through bus iovar "bus:metadata_info". 1213 */ 1214 struct metadata_txcmpl_v1 { 1215 uint32 tref; /* TSF or Ref Clock in uSecs */ 1216 uint16 d_t2; /* T2-fwt1 delta */ 1217 uint16 d_t3; /* T3-fwt1 delta */ 1218 uint16 d_t4; /* T4-fwt1 delta */ 1219 uint16 rsvd; /* reserved */ 1220 }; 1221 1222 struct metadata_txcmpl_v2 { 1223 uint32 tref; /* TSF or Ref Clock in uSecs */ 1224 uint16 d_t2; /* T2-fwt1 delta */ 1225 uint16 d_t3; /* T3-fwt1 delta */ 1226 uint16 d_t4; /* T4-fwt1 delta */ 1227 1228 uint16 u_t1; /* PSM Packet Fetch Time in 32us */ 1229 uint16 u_t2; /* Medium Access Delay delta */ 1230 uint16 u_t3; /* Rx duration delta */ 1231 uint16 u_t4; /* Mac Suspend Duration delta */ 1232 uint16 u_t5; /* TxStatus Time in 32us */ 1233 1234 uint16 u_c1; /* Number of times Tx was enabled */ 1235 uint16 u_c2; /* Other AC TxStatus count */ 1236 uint16 u_c3; /* DataRetry count */ 1237 uint16 u_c4; /* RTS */ 1238 uint16 u_c5; /* CTS */ 1239 uint16 u_c6; /* debug 1 */ 1240 uint16 u_c7; /* debug 2 */ 1241 uint16 u_c8; /* debug 3 */ 1242 }; 1243 typedef struct metadata_txcmpl_v2 metadata_txcmpl_t; 1244 1245 #define BCMPCIE_D2H_METADATA_HDRLEN 4 1246 #define BCMPCIE_D2H_METADATA_MINLEN (BCMPCIE_D2H_METADATA_HDRLEN + 4) 1247 1248 /** ret buf struct */ 1249 typedef struct ret_buf_ptr { 1250 uint32 low_addr; 1251 uint32 high_addr; 1252 } ret_buf_t; 1253 1254 #ifdef PCIE_API_REV1 1255 1256 /* ioctl specific hdr */ 1257 typedef struct ioctl_hdr { 1258 uint16 cmd; 1259 uint16 retbuf_len; 1260 uint32 cmd_id; 1261 } ioctl_hdr_t; 1262 1263 typedef struct ioctlptr_hdr { 1264 uint16 cmd; 1265 uint16 retbuf_len; 1266 uint16 buflen; 1267 uint16 rsvd; 1268 uint32 cmd_id; 1269 } ioctlptr_hdr_t; 1270 1271 #else /* PCIE_API_REV1 */ 1272 1273 typedef struct ioctl_req_hdr { 1274 uint32 pkt_id; /**< Packet ID */ 1275 uint32 cmd; /**< IOCTL ID */ 1276 uint16 retbuf_len; 1277 uint16 buflen; 1278 uint16 xt_id; /**< transaction ID */ 1279 uint16 rsvd[1]; 1280 } ioctl_req_hdr_t; 1281 1282 #endif /* PCIE_API_REV1 */ 1283 1284 /** Complete msgbuf hdr for ioctl from host to dongle */ 1285 typedef struct ioct_reqst_hdr { 1286 cmn_msg_hdr_t msg; 1287 #ifdef PCIE_API_REV1 1288 ioctl_hdr_t ioct_hdr; 1289 #else 1290 ioctl_req_hdr_t ioct_hdr; 1291 #endif 1292 ret_buf_t ret_buf; 1293 } ioct_reqst_hdr_t; 1294 1295 typedef struct ioctptr_reqst_hdr { 1296 cmn_msg_hdr_t msg; 1297 #ifdef PCIE_API_REV1 1298 ioctlptr_hdr_t ioct_hdr; 1299 #else 1300 ioctl_req_hdr_t ioct_hdr; 1301 #endif 1302 ret_buf_t ret_buf; 1303 ret_buf_t ioct_buf; 1304 } ioctptr_reqst_hdr_t; 1305 1306 /** ioctl response header */ 1307 typedef struct ioct_resp_hdr { 1308 cmn_msg_hdr_t msg; 1309 #ifdef PCIE_API_REV1 1310 uint32 cmd_id; 1311 #else 1312 uint32 pkt_id; 1313 #endif 1314 uint32 status; 1315 uint32 ret_len; 1316 uint32 inline_data; 1317 #ifdef PCIE_API_REV1 1318 #else 1319 uint16 xt_id; /**< transaction ID */ 1320 uint16 rsvd[1]; 1321 #endif 1322 } ioct_resp_hdr_t; 1323 1324 /* ioct resp header used in dongle */ 1325 /* ret buf hdr will be stripped off inside dongle itself */ 1326 typedef struct msgbuf_ioctl_resp { 1327 ioct_resp_hdr_t ioct_hdr; 1328 ret_buf_t ret_buf; /**< ret buf pointers */ 1329 } msgbuf_ioct_resp_t; 1330 1331 /** WL event hdr info */ 1332 typedef struct wl_event_hdr { 1333 cmn_msg_hdr_t msg; 1334 uint16 event; 1335 uint8 flags; 1336 uint8 rsvd; 1337 uint16 retbuf_len; 1338 uint16 rsvd1; 1339 uint32 rxbufid; 1340 } wl_event_hdr_t; 1341 1342 #define TXDESCR_FLOWID_PCIELPBK_1 0xFF 1343 #define TXDESCR_FLOWID_PCIELPBK_2 0xFE 1344 1345 typedef struct txbatch_lenptr_tup { 1346 uint32 pktid; 1347 uint16 pktlen; 1348 uint16 rsvd; 1349 ret_buf_t ret_buf; /**< ret buf pointers */ 1350 } txbatch_lenptr_tup_t; 1351 1352 typedef struct txbatch_cmn_msghdr { 1353 cmn_msg_hdr_t msg; 1354 uint8 priority; 1355 uint8 hdrlen; 1356 uint8 pktcnt; 1357 uint8 flowid; 1358 uint8 txhdr[ETHER_HDR_LEN]; 1359 uint16 rsvd; 1360 } txbatch_cmn_msghdr_t; 1361 1362 typedef struct txbatch_msghdr { 1363 txbatch_cmn_msghdr_t txcmn; 1364 txbatch_lenptr_tup_t tx_tup[0]; /**< Based on packet count */ 1365 } txbatch_msghdr_t; 1366 1367 /* TX desc posting header */ 1368 typedef struct tx_lenptr_tup { 1369 uint16 pktlen; 1370 uint16 rsvd; 1371 ret_buf_t ret_buf; /**< ret buf pointers */ 1372 } tx_lenptr_tup_t; 1373 1374 typedef struct txdescr_cmn_msghdr { 1375 cmn_msg_hdr_t msg; 1376 uint8 priority; 1377 uint8 hdrlen; 1378 uint8 descrcnt; 1379 uint8 flowid; 1380 uint32 pktid; 1381 } txdescr_cmn_msghdr_t; 1382 1383 typedef struct txdescr_msghdr { 1384 txdescr_cmn_msghdr_t txcmn; 1385 uint8 txhdr[ETHER_HDR_LEN]; 1386 uint16 rsvd; 1387 tx_lenptr_tup_t tx_tup[0]; /**< Based on descriptor count */ 1388 } txdescr_msghdr_t; 1389 1390 /** Tx status header info */ 1391 typedef struct txstatus_hdr { 1392 cmn_msg_hdr_t msg; 1393 uint32 pktid; 1394 } txstatus_hdr_t; 1395 1396 /** RX bufid-len-ptr tuple */ 1397 typedef struct rx_lenptr_tup { 1398 uint32 rxbufid; 1399 uint16 len; 1400 uint16 rsvd2; 1401 ret_buf_t ret_buf; /**< ret buf pointers */ 1402 } rx_lenptr_tup_t; 1403 1404 /** Rx descr Post hdr info */ 1405 typedef struct rxdesc_msghdr { 1406 cmn_msg_hdr_t msg; 1407 uint16 rsvd0; 1408 uint8 rsvd1; 1409 uint8 descnt; 1410 rx_lenptr_tup_t rx_tup[0]; 1411 } rxdesc_msghdr_t; 1412 1413 /** RX complete tuples */ 1414 typedef struct rxcmplt_tup { 1415 uint16 retbuf_len; 1416 uint16 data_offset; 1417 uint32 rxstatus0; 1418 uint32 rxstatus1; 1419 uint32 rxbufid; 1420 } rxcmplt_tup_t; 1421 1422 /** RX complete messge hdr */ 1423 typedef struct rxcmplt_hdr { 1424 cmn_msg_hdr_t msg; 1425 uint16 rsvd0; 1426 uint16 rxcmpltcnt; 1427 rxcmplt_tup_t rx_tup[0]; 1428 } rxcmplt_hdr_t; 1429 1430 typedef struct hostevent_hdr { 1431 cmn_msg_hdr_t msg; 1432 uint32 evnt_pyld; 1433 } hostevent_hdr_t; 1434 1435 typedef struct dma_xfer_params { 1436 uint32 src_physaddr_hi; 1437 uint32 src_physaddr_lo; 1438 uint32 dest_physaddr_hi; 1439 uint32 dest_physaddr_lo; 1440 uint32 len; 1441 uint32 srcdelay; 1442 uint32 destdelay; 1443 } dma_xfer_params_t; 1444 1445 enum { 1446 HOST_EVENT_CONS_CMD = 1 1447 }; 1448 1449 /* defines for flags */ 1450 #define MSGBUF_IOC_ACTION_MASK 0x1 1451 1452 #define MAX_SUSPEND_REQ 15 1453 1454 typedef struct tx_idle_flowring_suspend_request { 1455 cmn_msg_hdr_t msg; 1456 uint16 ring_id[MAX_SUSPEND_REQ]; /* ring Id's */ 1457 uint16 num; /* number of flowid's to suspend */ 1458 } tx_idle_flowring_suspend_request_t; 1459 1460 typedef struct tx_idle_flowring_suspend_response { 1461 cmn_msg_hdr_t msg; 1462 compl_msg_hdr_t cmplt; 1463 uint32 rsvd[2]; 1464 dma_done_t marker; 1465 } tx_idle_flowring_suspend_response_t; 1466 1467 typedef struct tx_idle_flowring_resume_request { 1468 cmn_msg_hdr_t msg; 1469 uint16 flow_ring_id; 1470 uint16 reason; 1471 uint32 rsvd[7]; 1472 } tx_idle_flowring_resume_request_t; 1473 1474 typedef struct tx_idle_flowring_resume_response { 1475 cmn_msg_hdr_t msg; 1476 compl_msg_hdr_t cmplt; 1477 uint32 rsvd[2]; 1478 dma_done_t marker; 1479 } tx_idle_flowring_resume_response_t; 1480 1481 /* timesync related additions */ 1482 1483 /* defined similar to bcm_xtlv_t */ 1484 typedef struct _bcm_xtlv { 1485 uint16 id; /* TLV idenitifier */ 1486 uint16 len; /* TLV length in bytes */ 1487 } _bcm_xtlv_t; 1488 1489 #define BCMMSGBUF_FW_CLOCK_INFO_TAG 0 1490 #define BCMMSGBUF_HOST_CLOCK_INFO_TAG 1 1491 #define BCMMSGBUF_HOST_CLOCK_SELECT_TAG 2 1492 #define BCMMSGBUF_D2H_CLOCK_CORRECTION_TAG 3 1493 #define BCMMSGBUF_HOST_TIMESTAMPING_CONFIG_TAG 4 1494 #define BCMMSGBUF_MAX_TSYNC_TAG 5 1495 1496 /* Flags in fw clock info TLV */ 1497 #define CAP_DEVICE_TS (1 << 0) 1498 #define CAP_CORRECTED_TS (1 << 1) 1499 #define TS_CLK_ACTIVE (1 << 2) 1500 1501 typedef struct ts_fw_clock_info { 1502 _bcm_xtlv_t xtlv; /* BCMMSGBUF_FW_CLOCK_INFO_TAG */ 1503 ts_timestamp_srcid_t ts; /* tick count */ 1504 uchar clk_src[4]; /* clock source acronym ILP/AVB/TSF */ 1505 uint32 nominal_clock_freq; 1506 uint32 reset_cnt; 1507 uint8 flags; 1508 uint8 rsvd[3]; 1509 } ts_fw_clock_info_t; 1510 1511 typedef struct ts_host_clock_info { 1512 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_CLOCK_INFO_TAG */ 1513 tick_count_64_t ticks; /* 64 bit host tick counter */ 1514 ts_timestamp_ns_64_t ns; /* 64 bit host time in nano seconds */ 1515 } ts_host_clock_info_t; 1516 1517 typedef struct ts_host_clock_sel { 1518 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_CLOCK_SELECT_TAG */ 1519 uint32 seqnum; /* number of times GPIO time sync toggled */ 1520 uint8 min_clk_idx; /* clock idenitifer configured for packet tiem stamping */ 1521 uint8 max_clk_idx; /* clock idenitifer configured for packet tiem stamping */ 1522 uint16 rsvd[1]; 1523 } ts_host_clock_sel_t; 1524 1525 typedef struct ts_d2h_clock_correction { 1526 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_CLOCK_INFO_TAG */ 1527 uint8 clk_id; /* clock source in the device */ 1528 uint8 rsvd[3]; 1529 ts_correction_m_t m; /* y = 'm' x + b */ 1530 ts_correction_b_t b; /* y = 'm' x + 'c' */ 1531 } ts_d2h_clock_correction_t; 1532 1533 typedef struct ts_host_timestamping_config { 1534 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_TIMESTAMPING_CONFIG_TAG */ 1535 /* time period to capture the device time stamp and toggle WLAN_TIME_SYNC_GPIO */ 1536 uint16 period_ms; 1537 uint8 flags; 1538 uint8 post_delay; 1539 uint32 reset_cnt; 1540 } ts_host_timestamping_config_t; 1541 1542 /* Flags in host timestamping config TLV */ 1543 #define FLAG_HOST_RESET (1 << 0) 1544 #define IS_HOST_RESET(x) ((x) & FLAG_HOST_RESET) 1545 #define CLEAR_HOST_RESET(x) ((x) & ~FLAG_HOST_RESET) 1546 1547 #define FLAG_CONFIG_NODROP (1 << 1) 1548 #define IS_CONFIG_NODROP(x) ((x) & FLAG_CONFIG_NODROP) 1549 #define CLEAR_CONFIG_NODROP(x) ((x) & ~FLAG_CONFIG_NODROP) 1550 1551 /* HP2P RLLW Extended TxStatus info when host enables the same */ 1552 #define D2H_TXSTATUS_EXT_PKT_WITH_OVRRD 0x8000 /**< set when pkt had override bit on */ 1553 #define D2H_TXSTATUS_EXT_PKT_XMIT_ON5G 0x4000 /**< set when pkt xmitted on 5G */ 1554 #define D2H_TXSTATUS_EXT_PKT_BT_DENY 0x2000 /**< set when WLAN is given prio over BT */ 1555 #define D2H_TXSTATUS_EXT_PKT_NAV_SWITCH 0x1000 /**< set when band switched due to NAV intr */ 1556 #define D2H_TXSTATUS_EXT_PKT_HOF_SWITCH 0x0800 /**< set when band switched due to HOF intr */ 1557 1558 /* H2D Txpost aggregated work item */ 1559 #define TXBUF_AGGR_CNT (2u) 1560 1561 /* aggregated work item of txpost v2 */ 1562 typedef struct host_txbuf_post_aggr_v2 { 1563 /** common aggregated message header */ 1564 cmn_aggr_msg_hdr_t cmn_aggr_hdr; 1565 1566 /** data buffer len to transmit */ 1567 uint16 data_buf_len[TXBUF_AGGR_CNT]; 1568 1569 /** address of data buffer to transmit */ 1570 bcm_addr64_t data_buf_addr[TXBUF_AGGR_CNT]; 1571 1572 /** packet Identifier for the associated host buffer */ 1573 uint32 request_id[TXBUF_AGGR_CNT]; 1574 1575 /** eth header */ 1576 uint8 txhdr[ETHER_HDR_LEN]; 1577 1578 /* reserved bytes */ 1579 uint16 reserved; 1580 1581 /** additional information on the packet required for CSO */ 1582 pkt_info_cso_t pktinfo[TXBUF_AGGR_CNT]; 1583 } host_txbuf_post_aggr_v2_t; 1584 1585 /* aggregated work item of txpost v1 */ 1586 typedef struct host_txbuf_post_aggr_v1 { 1587 /** common aggregated message header */ 1588 cmn_aggr_msg_hdr_t cmn_aggr_hdr; 1589 1590 /** data buffer len to transmit */ 1591 uint16 data_buf_len[TXBUF_AGGR_CNT]; 1592 1593 /** address of data buffer to transmit */ 1594 bcm_addr64_t data_buf_addr[TXBUF_AGGR_CNT]; 1595 1596 /** packet Identifier for the associated host buffer */ 1597 uint32 request_id[TXBUF_AGGR_CNT]; 1598 1599 /** eth header */ 1600 uint8 txhdr[ETHER_HDR_LEN]; 1601 1602 /* pad bytes */ 1603 uint16 PAD; 1604 } host_txbuf_post_aggr_v1_t; 1605 1606 #if defined(BCMPCIE_EXT_TXPOST_SUPPORT) || defined(TX_CSO) 1607 typedef host_txbuf_post_aggr_v2_t host_txbuf_post_aggr_t; 1608 #else 1609 typedef host_txbuf_post_aggr_v1_t host_txbuf_post_aggr_t; 1610 #endif 1611 1612 /* D2H Txcompletion ring aggregated work item */ 1613 #define TXCPL_AGGR_CNT (4u) 1614 1615 /* head aggregated work item of txcpl */ 1616 typedef struct host_txbuf_cmpl_aggr { 1617 /** common aggregated message header */ 1618 cmn_aggr_msg_hdr_t cmn_aggr_hdr; 1619 1620 /** completion aggregated message header */ 1621 compl_aggr_msg_hdr_t compl_aggr_hdr; 1622 1623 /** packet Identifier for the associated host buffer */ 1624 uint32 request_id[TXCPL_AGGR_CNT]; 1625 } host_txbuf_cmpl_aggr_t; 1626 1627 #define TXCPL_AGGR_CNT_EXT (6u) 1628 /* non-head aggregated work item of txcpl */ 1629 typedef struct host_txbuf_cmpl_aggr_ext { 1630 /** packet Identifier for the associated host buffer */ 1631 uint32 request_id[TXCPL_AGGR_CNT_EXT]; 1632 } host_txbuf_cmpl_aggr_ext_t; 1633 1634 /* H2D Rxpost ring aggregated work items */ 1635 #define RXBUF_AGGR_CNT (2u) 1636 1637 /* aggregated work item of rxpost */ 1638 typedef struct host_rxbuf_post_aggr { 1639 /** common aggregated message header */ 1640 cmn_aggr_msg_hdr_t cmn_aggr_hdr; 1641 1642 /** data buffer len to transmit */ 1643 uint16 data_buf_len[RXBUF_AGGR_CNT]; 1644 1645 /** packet Identifier for the associated host buffer */ 1646 uint32 request_id[RXBUF_AGGR_CNT]; 1647 1648 /** address of data buffer to transmit */ 1649 bcm_addr64_t data_buf_addr[RXBUF_AGGR_CNT]; 1650 } host_rxbuf_post_aggr_t; 1651 1652 /* D2H Rxcompletion ring for aggregated work items */ 1653 #define RXCPL_AGGR_CNT (2u) 1654 1655 /* each rx buffer work item */ 1656 typedef struct host_rxbuf_cmpl_pkt { 1657 /** offset in the host rx buffer where the data starts */ 1658 uint16 data_offset; 1659 /** filled up buffer len to receive data */ 1660 uint16 data_len; 1661 /** packet Identifier for the associated host buffer */ 1662 uint32 request_id; 1663 } host_rxbuf_cmpl_item_t; 1664 1665 /* head aggregated work item of rxcpl */ 1666 typedef struct host_rxbuf_cmpl_aggr { 1667 /** common aggregated message header */ 1668 cmn_aggr_msg_hdr_t cmn_aggr_hdr; 1669 1670 /** completion aggregated message header */ 1671 compl_aggr_msg_hdr_t compl_aggr_hdr; 1672 1673 /** rxbuffer work item */ 1674 host_rxbuf_cmpl_item_t item[RXCPL_AGGR_CNT]; 1675 } host_rxbuf_cmpl_aggr_t; 1676 1677 #define RXCPL_AGGR_CNT_EXT (5u) 1678 /* non-head aggregated work item of rxcpl */ 1679 typedef struct host_rxbuf_cmpl_aggr_ext { 1680 /** rxbuffer work item */ 1681 host_rxbuf_cmpl_item_t item[RXCPL_AGGR_CNT_EXT]; 1682 } host_rxbuf_cmpl_aggr_ext_t; 1683 1684 /* txpost extended tag types */ 1685 typedef uint8 txpost_ext_tag_type_t; 1686 enum { 1687 TXPOST_EXT_TAG_TYPE_RSVD = 0u, /* Reserved */ 1688 TXPOST_EXT_TAG_TYPE_CSO = 1u, 1689 TXPOST_EXT_TAG_TYPE_MESH = 2u, 1690 TXPOST_EXT_TAG_TYPE_MAX = 3u /* NOTE: increment this as you add reasons above */ 1691 }; 1692 1693 /* Fixed lengths for each extended tag */ 1694 typedef uint8 txpost_ext_tag_len_t; 1695 enum { 1696 TXPOST_EXT_TAG_LEN_RSVD = 0u, /* Reserved */ 1697 TXPOST_EXT_TAG_LEN_CSO = 4u, 1698 TXPOST_EXT_TAG_LEN_MESH = 20u 1699 }; 1700 1701 /* 1702 * Note: The only requirement is that the overall size of the workitem be multiple of 8. 1703 * However, each individual ext tag not necessarily 8x. 1704 */ 1705 1706 #endif /* _bcmmsgbuf_h_ */ 1707