1 /*
2 * Misc utility routines for accessing lhl specific features
3 * of the SiliconBackplane-based Broadcom chips.
4 *
5 * Copyright (C) 2020, Broadcom.
6 *
7 * Unless you and Broadcom execute a separate written software license
8 * agreement governing use of this software, this software is licensed to you
9 * under the terms of the GNU General Public License version 2 (the "GPL"),
10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
11 * following added to such license:
12 *
13 * As a special exception, the copyright holders of this software give you
14 * permission to link this software with independent modules, and to copy and
15 * distribute the resulting executable under terms of your choice, provided that
16 * you also meet, for each linked independent module, the terms and conditions of
17 * the license of that module. An independent module is a module which is not
18 * derived from this software. The special exception does not apply to any
19 * modifications of the software.
20 *
21 *
22 * <<Broadcom-WL-IPTag/Dual:>>
23 */
24
25 #include <hndpmu.h>
26 #include <hndlhl.h>
27 #include <sbchipc.h>
28 #include <hndsoc.h>
29 #include <bcmdevs.h>
30 #include <osl.h>
31 #include <sbgci.h>
32 #include <siutils.h>
33 #include <bcmutils.h>
34
35 #define SI_LHL_EXT_WAKE_REQ_MASK_MAGIC 0x7FBBF7FF /* magic number for LHL EXT */
36
37 /* PmuRev1 has a 24-bit PMU RsrcReq timer. However it pushes all other bits
38 * upward. To make the code to run for all revs we use a variable to tell how
39 * many bits we need to shift.
40 */
41 #define FLAGS_SHIFT 14
42 #define LHL_ERROR(args) printf args
43 static const char BCMATTACHDATA(rstr_rfldo3p3_cap_war)[] = "rfldo3p3_cap_war";
44 static const char BCMATTACHDATA(rstr_abuck_volt_sleep)[] = "abuck_volt_sleep";
45 static const char BCMATTACHDATA(rstr_cbuck_volt_sleep)[] = "cbuck_volt_sleep";
46
47 void
si_lhl_setup(si_t * sih,osl_t * osh)48 si_lhl_setup(si_t *sih, osl_t *osh)
49 {
50 if ((CHIPID(sih->chip) == BCM43012_CHIP_ID) ||
51 (CHIPID(sih->chip) == BCM43013_CHIP_ID) ||
52 (CHIPID(sih->chip) == BCM43014_CHIP_ID)) {
53 /* Enable PMU sleep mode0 */
54 #ifdef BCMQT
55 LHL_REG(sih, lhl_top_pwrseq_ctl_adr, LHL_PWRSEQ_CTL, PMU_SLEEP_MODE_0);
56 #else
57 LHL_REG(sih, lhl_top_pwrseq_ctl_adr, LHL_PWRSEQ_CTL, PMU_SLEEP_MODE_2);
58 #endif
59 /* Modify as per the
60 BCM43012/LHL#LHL-RecommendedsettingforvariousPMUSleepModes:
61 */
62 LHL_REG(sih, lhl_top_pwrup_ctl_adr, LHL_PWRUP_CTL_MASK, LHL_PWRUP_CTL);
63 LHL_REG(sih, lhl_top_pwrup2_ctl_adr, LHL_PWRUP2_CTL_MASK, LHL_PWRUP2_CTL);
64 LHL_REG(sih, lhl_top_pwrdn_ctl_adr, LHL_PWRDN_CTL_MASK, LHL_PWRDN_SLEEP_CNT);
65 LHL_REG(sih, lhl_top_pwrdn2_ctl_adr, LHL_PWRDN2_CTL_MASK, LHL_PWRDN2_CTL);
66 }
67
68 if (!FWSIGN_ENAB() && si_hib_ext_wakeup_isenab(sih)) {
69 /*
70 * Enable wakeup on GPIO1, PCIE clkreq and perst signal,
71 * GPIO[0] is mapped to GPIO1
72 * GPIO[1] is mapped to PCIE perst
73 * GPIO[2] is mapped to PCIE clkreq
74 */
75
76 /* GPIO1 */
77 /* Clear any old interrupt status */
78 LHL_REG(sih, gpio_int_st_port_adr[0],
79 1 << PCIE_GPIO1_GPIO_PIN, 1 << PCIE_GPIO1_GPIO_PIN);
80 /* active high level trigger */
81 LHL_REG(sih, gpio_ctrl_iocfg_p_adr[PCIE_GPIO1_GPIO_PIN], ~0,
82 1 << GCI_GPIO_STS_WL_DIN_SELECT);
83 LHL_REG(sih, gpio_int_en_port_adr[0],
84 1 << PCIE_GPIO1_GPIO_PIN, 1 << PCIE_GPIO1_GPIO_PIN);
85 LHL_REG(sih, gpio_int_st_port_adr[0],
86 1 << PCIE_GPIO1_GPIO_PIN, 1 << PCIE_GPIO1_GPIO_PIN);
87 si_gci_set_functionsel(sih, 1, CC_FNSEL_SAMEASPIN);
88
89 /* PCIE perst */
90 LHL_REG(sih, gpio_int_st_port_adr[0],
91 1 << PCIE_PERST_GPIO_PIN, 1 << PCIE_PERST_GPIO_PIN);
92 LHL_REG(sih, gpio_ctrl_iocfg_p_adr[PCIE_PERST_GPIO_PIN], ~0,
93 (1 << GCI_GPIO_STS_EDGE_TRIG_BIT |
94 1 << GCI_GPIO_STS_WL_DIN_SELECT));
95 LHL_REG(sih, gpio_int_en_port_adr[0],
96 1 << PCIE_PERST_GPIO_PIN, 1 << PCIE_PERST_GPIO_PIN);
97 LHL_REG(sih, gpio_int_st_port_adr[0],
98 1 << PCIE_PERST_GPIO_PIN, 1 << PCIE_PERST_GPIO_PIN);
99
100 /* PCIE clkreq */
101 LHL_REG(sih, gpio_int_st_port_adr[0],
102 1 << PCIE_CLKREQ_GPIO_PIN, 1 << PCIE_CLKREQ_GPIO_PIN);
103 LHL_REG(sih, gpio_ctrl_iocfg_p_adr[PCIE_CLKREQ_GPIO_PIN], ~0,
104 (1 << GCI_GPIO_STS_NEG_EDGE_TRIG_BIT) |
105 (1 << GCI_GPIO_STS_WL_DIN_SELECT));
106 LHL_REG(sih, gpio_int_en_port_adr[0],
107 1 << PCIE_CLKREQ_GPIO_PIN, 1 << PCIE_CLKREQ_GPIO_PIN);
108 LHL_REG(sih, gpio_int_st_port_adr[0],
109 1 << PCIE_CLKREQ_GPIO_PIN, 1 << PCIE_CLKREQ_GPIO_PIN);
110 }
111 }
112
113 static const uint32 lpo_opt_tab[4][2] = {
114 { LPO1_PD_EN, LHL_LPO1_SEL },
115 { LPO2_PD_EN, LHL_LPO2_SEL },
116 { OSC_32k_PD, LHL_32k_SEL},
117 { EXTLPO_BUF_PD, LHL_EXT_SEL }
118 };
119
120 #define LPO_EN_OFFSET 0u
121 #define LPO_SEL_OFFSET 1u
122
123 static int
si_lhl_get_lpo_sel(si_t * sih,uint32 lpo)124 si_lhl_get_lpo_sel(si_t *sih, uint32 lpo)
125 {
126 int sel;
127 if (lpo <= LHL_EXT_SEL) {
128 LHL_REG(sih, lhl_main_ctl_adr, lpo_opt_tab[lpo - 1u][LPO_EN_OFFSET], 0u);
129 sel = lpo_opt_tab[lpo - 1u][LPO_SEL_OFFSET];
130 } else {
131 sel = BCME_NOTFOUND;
132 }
133 return sel;
134 }
135
136 static void
si_lhl_detect_lpo(si_t * sih,osl_t * osh)137 si_lhl_detect_lpo(si_t *sih, osl_t *osh)
138 {
139 uint clk_det_cnt;
140 int timeout = 0;
141 gciregs_t *gciregs;
142 gciregs = si_setcore(sih, GCI_CORE_ID, 0);
143 ASSERT(gciregs != NULL);
144
145 LHL_REG(sih, lhl_clk_det_ctl_adr, LHL_CLK_DET_CTL_ADR_LHL_CNTR_EN, 0);
146 LHL_REG(sih, lhl_clk_det_ctl_adr,
147 LHL_CLK_DET_CTL_ADR_LHL_CNTR_CLR, LHL_CLK_DET_CTL_ADR_LHL_CNTR_CLR);
148 timeout = 0;
149 clk_det_cnt =
150 ((R_REG(osh, &gciregs->lhl_clk_det_ctl_adr) & LHL_CLK_DET_CNT) >>
151 LHL_CLK_DET_CNT_SHIFT);
152 while (clk_det_cnt != 0 && timeout <= LPO_SEL_TIMEOUT) {
153 OSL_DELAY(10);
154 clk_det_cnt =
155 ((R_REG(osh, &gciregs->lhl_clk_det_ctl_adr) & LHL_CLK_DET_CNT) >>
156 LHL_CLK_DET_CNT_SHIFT);
157 timeout++;
158 }
159
160 if (clk_det_cnt != 0) {
161 LHL_ERROR(("Clock not present as clear did not work timeout = %d\n", timeout));
162 ROMMABLE_ASSERT(0);
163 }
164 LHL_REG(sih, lhl_clk_det_ctl_adr, LHL_CLK_DET_CTL_ADR_LHL_CNTR_CLR, 0);
165 LHL_REG(sih, lhl_clk_det_ctl_adr, LHL_CLK_DET_CTL_ADR_LHL_CNTR_EN,
166 LHL_CLK_DET_CTL_ADR_LHL_CNTR_EN);
167 clk_det_cnt =
168 ((R_REG(osh, &gciregs->lhl_clk_det_ctl_adr) & LHL_CLK_DET_CNT) >>
169 LHL_CLK_DET_CNT_SHIFT);
170 timeout = 0;
171
172 while (clk_det_cnt <= CLK_DET_CNT_THRESH && timeout <= LPO_SEL_TIMEOUT) {
173 OSL_DELAY(10);
174 clk_det_cnt =
175 ((R_REG(osh, &gciregs->lhl_clk_det_ctl_adr) & LHL_CLK_DET_CNT) >>
176 LHL_CLK_DET_CNT_SHIFT);
177 timeout++;
178 }
179
180 if (timeout >= LPO_SEL_TIMEOUT) {
181 LHL_ERROR(("LPO is not available timeout = %u\n, timeout", timeout));
182 ROMMABLE_ASSERT(0);
183 }
184 }
185
186 static void
si_lhl_select_lpo(si_t * sih,osl_t * osh,int sel,uint32 lpo)187 si_lhl_select_lpo(si_t *sih, osl_t *osh, int sel, uint32 lpo)
188 {
189 uint status;
190 int timeout = 0u;
191 gciregs_t *gciregs;
192 uint32 final_clk_sel;
193 uint32 final_lpo_sel;
194 gciregs = si_setcore(sih, GCI_CORE_ID, 0);
195 ASSERT(gciregs != NULL);
196
197 LHL_REG(sih, lhl_main_ctl_adr,
198 LHL_MAIN_CTL_ADR_LHL_WLCLK_SEL, (sel) << LPO_SEL_SHIFT);
199 final_clk_sel = (R_REG(osh, &gciregs->lhl_clk_status_adr)
200 & LHL_MAIN_CTL_ADR_FINAL_CLK_SEL);
201 final_lpo_sel = (unsigned)(((1u << sel) << LPO_FINAL_SEL_SHIFT));
202
203 status = (final_clk_sel == final_lpo_sel) ? 1u : 0u;
204 timeout = 0;
205 while (!status && timeout <= LPO_SEL_TIMEOUT) {
206 OSL_DELAY(10);
207 final_clk_sel = (R_REG(osh, &gciregs->lhl_clk_status_adr)
208 & LHL_MAIN_CTL_ADR_FINAL_CLK_SEL);
209 status = (final_clk_sel == final_lpo_sel) ? 1u : 0u;
210 timeout++;
211 }
212
213 if (timeout >= LPO_SEL_TIMEOUT) {
214 LHL_ERROR(("LPO is not available timeout = %u\n, timeout", timeout));
215 ROMMABLE_ASSERT(0);
216 }
217
218 /* for 4377 and chiprev B0 and greater do not power-off other LPOs */
219 if (BCM4389_CHIP(sih->chip) || BCM4378_CHIP(sih->chip) || BCM4397_CHIP(sih->chip) ||
220 BCM4388_CHIP(sih->chip) || BCM4387_CHIP(sih->chip) ||
221 (CHIPID(sih->chip) == BCM4377_CHIP_ID)) {
222 LHL_ERROR(("NOT Power Down other LPO\n"));
223 } else {
224 /* Power down the rest of the LPOs */
225
226 if (lpo != LHL_EXT_LPO_ENAB) {
227 LHL_REG(sih, lhl_main_ctl_adr, EXTLPO_BUF_PD, EXTLPO_BUF_PD);
228 }
229
230 if (lpo != LHL_LPO1_ENAB) {
231 LHL_REG(sih, lhl_main_ctl_adr, LPO1_PD_EN, LPO1_PD_EN);
232 LHL_REG(sih, lhl_main_ctl_adr, LPO1_PD_SEL, LPO1_PD_SEL_VAL);
233 }
234 if (lpo != LHL_LPO2_ENAB) {
235 LHL_REG(sih, lhl_main_ctl_adr, LPO2_PD_EN, LPO2_PD_EN);
236 LHL_REG(sih, lhl_main_ctl_adr, LPO2_PD_SEL, LPO2_PD_SEL_VAL);
237 }
238 if (lpo != LHL_OSC_32k_ENAB) {
239 LHL_REG(sih, lhl_main_ctl_adr, OSC_32k_PD, OSC_32k_PD);
240 }
241 if (lpo != RADIO_LPO_ENAB) {
242 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_06, LPO_SEL, 0);
243 }
244 }
245
246 }
247
248 /* To skip this function, specify a invalid "lpo_select" value in nvram */
249 int
BCMATTACHFN(si_lhl_set_lpoclk)250 BCMATTACHFN(si_lhl_set_lpoclk)(si_t *sih, osl_t *osh, uint32 lpo_force)
251 {
252 int lhl_wlclk_sel;
253 uint32 lpo = 0;
254
255 /* Apply nvram override to lpo */
256 if (!FWSIGN_ENAB()) {
257 if ((lpo = (uint32)getintvar(NULL, "lpo_select")) == 0) {
258 if (lpo_force == LHL_LPO_AUTO) {
259 lpo = LHL_OSC_32k_ENAB;
260 } else {
261 lpo = lpo_force;
262 }
263 }
264 } else {
265 lpo = lpo_force;
266 }
267
268 lhl_wlclk_sel = si_lhl_get_lpo_sel(sih, lpo);
269
270 if (lhl_wlclk_sel < 0) {
271 return BCME_OK;
272 }
273
274 LHL_REG(sih, lhl_clk_det_ctl_adr,
275 LHL_CLK_DET_CTL_AD_CNTR_CLK_SEL, lhl_wlclk_sel);
276
277 /* Detect the desired LPO */
278 si_lhl_detect_lpo(sih, osh);
279
280 /* Select the desired LPO */
281 si_lhl_select_lpo(sih, osh, lhl_wlclk_sel, lpo);
282
283 return BCME_OK;
284 }
285
286 void
BCMATTACHFN(si_lhl_timer_config)287 BCMATTACHFN(si_lhl_timer_config)(si_t *sih, osl_t *osh, int timer_type)
288 {
289 uint origidx;
290 pmuregs_t *pmu = NULL;
291
292 /* Remember original core before switch to chipc/pmu */
293 origidx = si_coreidx(sih);
294 if (AOB_ENAB(sih)) {
295 pmu = si_setcore(sih, PMU_CORE_ID, 0);
296 } else {
297 pmu = si_setcoreidx(sih, SI_CC_IDX);
298 }
299
300 ASSERT(pmu != NULL);
301
302 switch (timer_type) {
303 case LHL_MAC_TIMER:
304 /* Enable MAC Timer interrupt */
305 LHL_REG(sih, lhl_wl_mactim0_intrp_adr,
306 (LHL_WL_MACTIM_INTRP_EN | LHL_WL_MACTIM_INTRP_EDGE_TRIGGER),
307 (LHL_WL_MACTIM_INTRP_EN | LHL_WL_MACTIM_INTRP_EDGE_TRIGGER));
308
309 /* Programs bits for MACPHY_CLK_AVAIL and all its dependent bits in
310 * MacResourceReqMask0.
311 */
312 PMU_REG(sih, mac_res_req_mask, ~0, si_pmu_rsrc_macphy_clk_deps(sih, osh, 0));
313
314 /* One time init of mac_res_req_timer to enable interrupt and clock request */
315 HND_PMU_SYNC_WR(sih, pmu, pmu, osh,
316 PMUREGADDR(sih, pmu, pmu, mac_res_req_timer),
317 ((PRRT_ALP_REQ | PRRT_HQ_REQ | PRRT_INTEN) << FLAGS_SHIFT));
318
319 /*
320 * Reset MAC Main Timer if in case it is running due to previous instance
321 * This also resets the interrupt status
322 */
323 LHL_REG(sih, lhl_wl_mactim_int0_adr, LHL_WL_MACTIMER_MASK, 0x0);
324
325 if (si_pmu_get_mac_rsrc_req_tmr_cnt(sih) > 1) {
326 LHL_REG(sih, lhl_wl_mactim1_intrp_adr,
327 (LHL_WL_MACTIM_INTRP_EN | LHL_WL_MACTIM_INTRP_EDGE_TRIGGER),
328 (LHL_WL_MACTIM_INTRP_EN | LHL_WL_MACTIM_INTRP_EDGE_TRIGGER));
329
330 PMU_REG(sih, mac_res_req_mask1, ~0,
331 si_pmu_rsrc_macphy_clk_deps(sih, osh, 1));
332
333 HND_PMU_SYNC_WR(sih, pmu, pmu, osh,
334 PMUREGADDR(sih, pmu, pmu, mac_res_req_timer1),
335 ((PRRT_ALP_REQ | PRRT_HQ_REQ | PRRT_INTEN) << FLAGS_SHIFT));
336
337 /*
338 * Reset MAC Aux Timer if in case it is running due to previous instance
339 * This also resets the interrupt status
340 */
341 LHL_REG(sih, lhl_wl_mactim_int1_adr, LHL_WL_MACTIMER_MASK, 0x0);
342 }
343
344 if (si_pmu_get_mac_rsrc_req_tmr_cnt(sih) > 2) {
345 LHL_REG(sih, lhl_wl_mactim2_intrp_adr,
346 (LHL_WL_MACTIM_INTRP_EN | LHL_WL_MACTIM_INTRP_EDGE_TRIGGER),
347 (LHL_WL_MACTIM_INTRP_EN | LHL_WL_MACTIM_INTRP_EDGE_TRIGGER));
348
349 PMU_REG_NEW(sih, mac_res_req_mask2, ~0,
350 si_pmu_rsrc_macphy_clk_deps(sih, osh, 2));
351
352 HND_PMU_SYNC_WR(sih, pmu, pmu, osh,
353 PMUREGADDR(sih, pmu, pmu, mac_res_req_timer2),
354 ((PRRT_ALP_REQ | PRRT_HQ_REQ | PRRT_INTEN) << FLAGS_SHIFT));
355
356 /*
357 * Reset Scan MAC Timer if in case it is running due to previous instance
358 * This also resets the interrupt status
359 */
360 LHL_REG(sih, lhl_wl_mactim_int2_adr, LHL_WL_MACTIMER_MASK, 0x0);
361 }
362
363 break;
364
365 case LHL_ARM_TIMER:
366 /* Enable ARM Timer interrupt */
367 LHL_REG(sih, lhl_wl_armtim0_intrp_adr,
368 (LHL_WL_ARMTIM0_INTRP_EN | LHL_WL_ARMTIM0_INTRP_EDGE_TRIGGER),
369 (LHL_WL_ARMTIM0_INTRP_EN | LHL_WL_ARMTIM0_INTRP_EDGE_TRIGGER));
370
371 /* Programs bits for HT_AVAIL and all its dependent bits in ResourceReqMask0 */
372 /* Programs bits for CORE_RDY_CB and all its dependent bits in ResourceReqMask0 */
373 PMU_REG(sih, res_req_mask, ~0, (si_pmu_rsrc_ht_avail_clk_deps(sih, osh) |
374 si_pmu_rsrc_cb_ready_deps(sih, osh)));
375
376 /* One time init of res_req_timer to enable interrupt and clock request
377 * For low power request only ALP (HT_AVAIL is anyway requested by res_req_mask)
378 */
379 HND_PMU_SYNC_WR(sih, pmu, pmu, osh,
380 PMUREGADDR(sih, pmu, pmu, res_req_timer),
381 ((PRRT_ALP_REQ | PRRT_HQ_REQ | PRRT_INTEN) << FLAGS_SHIFT));
382 break;
383 }
384
385 /* Return to original core */
386 si_setcoreidx(sih, origidx);
387 }
388
389 void
BCMATTACHFN(si_lhl_timer_enable)390 BCMATTACHFN(si_lhl_timer_enable)(si_t *sih)
391 {
392 /* Enable clks for pmu int propagation */
393 PMU_REG(sih, pmuintctrl0, PMU_INTC_ALP_REQ, PMU_INTC_ALP_REQ);
394
395 PMU_REG(sih, pmuintmask0, RSRC_INTR_MASK_TIMER_INT_0, RSRC_INTR_MASK_TIMER_INT_0);
396 #ifndef BCMQT
397 LHL_REG(sih, lhl_main_ctl_adr, LHL_FAST_WRITE_EN, LHL_FAST_WRITE_EN);
398 #endif /* BCMQT */
399 PMU_REG(sih, pmucontrol_ext, PCTL_EXT_USE_LHL_TIMER, PCTL_EXT_USE_LHL_TIMER);
400 }
401
402 void
BCMPOSTTRAPFN(si_lhl_timer_reset)403 BCMPOSTTRAPFN(si_lhl_timer_reset)(si_t *sih, uint coreid, uint coreunit)
404 {
405 switch (coreid) {
406 case D11_CORE_ID:
407 switch (coreunit) {
408 case 0: /* MAC_CORE_UNIT_0 */
409 LHL_REG(sih, lhl_wl_mactim_int0_adr, LHL_WL_MACTIMER_MASK, 0x0);
410 LHL_REG(sih, lhl_wl_mactim0_st_adr,
411 LHL_WL_MACTIMER_INT_ST_MASK, LHL_WL_MACTIMER_INT_ST_MASK);
412 break;
413 case 1: /* MAC_CORE_UNIT_1 */
414 LHL_REG(sih, lhl_wl_mactim_int1_adr, LHL_WL_MACTIMER_MASK, 0x0);
415 LHL_REG(sih, lhl_wl_mactim1_st_adr,
416 LHL_WL_MACTIMER_INT_ST_MASK, LHL_WL_MACTIMER_INT_ST_MASK);
417 break;
418 case 2: /* SCAN_CORE_UNIT */
419 LHL_REG(sih, lhl_wl_mactim_int2_adr, LHL_WL_MACTIMER_MASK, 0x0);
420 LHL_REG(sih, lhl_wl_mactim2_st_adr,
421 LHL_WL_MACTIMER_INT_ST_MASK, LHL_WL_MACTIMER_INT_ST_MASK);
422 break;
423 default:
424 LHL_ERROR(("Cannot reset lhl timer, wrong coreunit = %d\n", coreunit));
425 }
426 break;
427 case ARMCR4_CORE_ID: /* intentional fallthrough */
428 case ARMCA7_CORE_ID:
429 LHL_REG(sih, lhl_wl_armtim0_adr, LHL_WL_MACTIMER_MASK, 0x0);
430 LHL_REG(sih, lhl_wl_armtim0_st_adr,
431 LHL_WL_MACTIMER_INT_ST_MASK, LHL_WL_MACTIMER_INT_ST_MASK);
432 break;
433 default:
434 LHL_ERROR(("Cannot reset lhl timer, wrong coreid = 0x%x\n", coreid));
435 }
436 }
437
438 void
si_lhl_ilp_config(si_t * sih,osl_t * osh,uint32 ilp_period)439 si_lhl_ilp_config(si_t *sih, osl_t *osh, uint32 ilp_period)
440 {
441 gciregs_t *gciregs;
442 if ((CHIPID(sih->chip) == BCM43012_CHIP_ID) ||
443 (CHIPID(sih->chip) == BCM43013_CHIP_ID) ||
444 (CHIPID(sih->chip) == BCM43014_CHIP_ID)) {
445 gciregs = si_setcore(sih, GCI_CORE_ID, 0);
446 ASSERT(gciregs != NULL);
447 W_REG(osh, &gciregs->lhl_wl_ilp_val_adr, ilp_period);
448 }
449 }
450
451 lhl_reg_set_t BCMATTACHDATA(lv_sleep_mode_4369_lhl_reg_set)[] =
452 {
453 /* set wl_sleep_en */
454 {LHL_REG_OFF(lhl_top_pwrseq_ctl_adr), (1 << 0), (1 << 0)},
455
456 /* set top_pwrsw_en, top_slb_en, top_iso_en */
457 {LHL_REG_OFF(lhl_top_pwrseq_ctl_adr), BCM_MASK32(5, 3), (0x0 << 3)},
458
459 /* set VMUX_asr_sel_en */
460 {LHL_REG_OFF(lhl_top_pwrseq_ctl_adr), (1 << 8), (1 << 8)},
461
462 /* lhl_lp_main_ctl_adr, disable lp_mode_en, set CSR and ASR field enables for LV mode */
463 {LHL_REG_OFF(lhl_lp_main_ctl_adr), BCM_MASK32(21, 0), 0x3F89FF},
464
465 /* lhl_lp_main_ctl1_adr, set CSR field values - CSR_adj - 0.64V and trim_adj -5mV */
466 {LHL_REG_OFF(lhl_lp_main_ctl1_adr), BCM_MASK32(23, 0), 0x9E9F97},
467
468 /* lhl_lp_main_ctl2_adr, set ASR field values - ASR_adj - 0.76V and trim_adj +5mV */
469 {LHL_REG_OFF(lhl_lp_main_ctl2_adr), BCM_MASK32(13, 0), 0x07EE},
470
471 /* lhl_lp_dn_ctl_adr, set down count for CSR fields- adj, mode, overi_dis */
472 {LHL_REG_OFF(lhl_lp_dn_ctl_adr), ~0, ((LHL4369_CSR_OVERI_DIS_DWN_CNT << 16) |
473 (LHL4369_CSR_MODE_DWN_CNT << 8) | (LHL4369_CSR_ADJ_DWN_CNT << 0))},
474
475 /* lhl_lp_up_ctl_adr, set up count for CSR fields- adj, mode, overi_dis */
476 {LHL_REG_OFF(lhl_lp_up_ctl_adr), ~0, ((LHL4369_CSR_OVERI_DIS_UP_CNT << 16) |
477 (LHL4369_CSR_MODE_UP_CNT << 8) | (LHL4369_CSR_ADJ_UP_CNT << 0))},
478
479 /* lhl_lp_dn_ctl1_adr, set down count for hpbg_chop_dis, ASR_adj, vddc_sw_dis */
480 {LHL_REG_OFF(lhl_lp_dn_ctl1_adr), ~0, ((LHL4369_VDDC_SW_DIS_DWN_CNT << 24) |
481 (LHL4369_ASR_ADJ_DWN_CNT << 16) | (LHL4369_HPBG_CHOP_DIS_DWN_CNT << 0))},
482
483 /* lhl_lp_up_ctl1_adr, set up count for hpbg_chop_dis, ASR_adj, vddc_sw_dis */
484 {LHL_REG_OFF(lhl_lp_up_ctl1_adr), ~0, ((LHL4369_VDDC_SW_DIS_UP_CNT << 24) |
485 (LHL4369_ASR_ADJ_UP_CNT << 16) | (LHL4369_HPBG_CHOP_DIS_UP_CNT << 0))},
486
487 /* lhl_lp_dn_ctl4_adr, set down count for ASR fields -
488 * clk4m_dis, lppfm_mode, mode_sel, manual_mode
489 */
490 {LHL_REG_OFF(lhl_lp_dn_ctl4_adr), ~0, ((LHL4369_ASR_MANUAL_MODE_DWN_CNT << 24) |
491 (LHL4369_ASR_MODE_SEL_DWN_CNT << 16) | (LHL4369_ASR_LPPFM_MODE_DWN_CNT << 8) |
492 (LHL4369_ASR_CLK4M_DIS_DWN_CNT << 0))},
493
494 /* lhl_lp_up_ctl4_adr, set up count for ASR fields -
495 * clk4m_dis, lppfm_mode, mode_sel, manual_mode
496 */
497 {LHL_REG_OFF(lhl_lp_up_ctl4_adr), ~0, ((LHL4369_ASR_MANUAL_MODE_UP_CNT << 24) |
498 (LHL4369_ASR_MODE_SEL_UP_CNT << 16)| (LHL4369_ASR_LPPFM_MODE_UP_CNT << 8) |
499 (LHL4369_ASR_CLK4M_DIS_UP_CNT << 0))},
500
501 /* lhl_lp_dn_ctl3_adr, set down count for hpbg_pu, srbg_ref, ASR_overi_dis,
502 * CSR_pfm_pwr_slice_en
503 */
504 {LHL_REG_OFF(lhl_lp_dn_ctl3_adr), ~0, ((LHL4369_PFM_PWR_SLICE_DWN_CNT << 24) |
505 (LHL4369_ASR_OVERI_DIS_DWN_CNT << 16) | (LHL4369_SRBG_REF_SEL_DWN_CNT << 8) |
506 (LHL4369_HPBG_PU_EN_DWN_CNT << 0))},
507
508 /* lhl_lp_up_ctl3_adr, set up count for hpbg_pu, srbg_ref, ASR_overi_dis,
509 * CSR_pfm_pwr_slice_en
510 */
511 {LHL_REG_OFF(lhl_lp_up_ctl3_adr), ~0, ((LHL4369_PFM_PWR_SLICE_UP_CNT << 24) |
512 (LHL4369_ASR_OVERI_DIS_UP_CNT << 16) | (LHL4369_SRBG_REF_SEL_UP_CNT << 8) |
513 (LHL4369_HPBG_PU_EN_UP_CNT << 0))},
514
515 /* lhl_lp_dn_ctl2_adr, set down count for CSR_trim_adj */
516 {LHL_REG_OFF(lhl_lp_dn_ctl2_adr), ~0, (LHL4369_CSR_TRIM_ADJ_DWN_CNT << 16)},
517
518 /* lhl_lp_up_ctl2_adr, set up count for CSR_trim_adj */
519 {LHL_REG_OFF(lhl_lp_up_ctl2_adr), ~0, (LHL4369_CSR_TRIM_ADJ_UP_CNT << 16)},
520
521 /* lhl_lp_dn_ctl5_adr, set down count for ASR_trim_adj */
522 {LHL_REG_OFF(lhl_lp_dn_ctl5_adr), ~0, (LHL4369_ASR_TRIM_ADJ_DWN_CNT << 0)},
523
524 /* lhl_lp_up_ctl5_adr, set down count for ASR_trim_adj */
525 {LHL_REG_OFF(lhl_lp_up_ctl5_adr), ~0, (LHL4369_ASR_TRIM_ADJ_UP_CNT << 0)},
526
527 /* Change the default down count values for the resources */
528 /* lhl_top_pwrdn_ctl_adr, set down count for top_level_sleep, iso, slb and pwrsw */
529 {LHL_REG_OFF(lhl_top_pwrdn_ctl_adr), ~0, ((LHL4369_PWRSW_EN_DWN_CNT << 24) |
530 (LHL4369_SLB_EN_DWN_CNT << 16) | (LHL4369_ISO_EN_DWN_CNT << 8))},
531
532 /* lhl_top_pwrdn2_ctl_adr, set down count for VMUX_asr_sel */
533 {LHL_REG_OFF(lhl_top_pwrdn2_ctl_adr), ~0, (LHL4369_VMUX_ASR_SEL_DWN_CNT << 16)},
534
535 /* Change the default up count values for the resources */
536 /* lhl_top_pwrup_ctl_adr, set up count for top_level_sleep, iso, slb and pwrsw */
537 {LHL_REG_OFF(lhl_top_pwrup_ctl_adr), ~0, ((LHL4369_PWRSW_EN_UP_CNT << 24) |
538 (LHL4369_SLB_EN_UP_CNT << 16) | (LHL4369_ISO_EN_UP_CNT << 8))},
539
540 /* lhl_top_pwrdn2_ctl_adr, set down count for VMUX_asr_sel */
541 {LHL_REG_OFF(lhl_top_pwrup2_ctl_adr), ~0, ((LHL4369_VMUX_ASR_SEL_UP_CNT << 16))},
542
543 /* Enable lhl interrupt */
544 {LHL_REG_OFF(gci_intmask), (1 << 30), (1 << 30)},
545
546 /* Enable LHL Wake up */
547 {LHL_REG_OFF(gci_wakemask), (1 << 30), (1 << 30)},
548
549 /* Making forceOTPpwrOn 1 */
550 {LHL_REG_OFF(otpcontrol), (1 << 16), (1 << 16)}
551 };
552
553 lhl_reg_set_t BCMATTACHDATA(lv_sleep_mode_4378_lhl_reg_set)[] =
554 {
555 /* set wl_sleep_en */
556 {LHL_REG_OFF(lhl_top_pwrseq_ctl_adr), (1 << 0), (1 << 0)},
557
558 /* set top_pwrsw_en, top_slb_en, top_iso_en */
559 {LHL_REG_OFF(lhl_top_pwrseq_ctl_adr), BCM_MASK32(5, 3), (0x0 << 3)},
560
561 /* set VMUX_asr_sel_en */
562 {LHL_REG_OFF(lhl_top_pwrseq_ctl_adr), (1 << 8), (1 << 8)},
563
564 /* lhl_lp_main_ctl_adr, disable lp_mode_en, set CSR and ASR field enables for LV mode */
565 {LHL_REG_OFF(lhl_lp_main_ctl_adr), BCM_MASK32(21, 0), 0x3F89FF},
566
567 /* lhl_lp_main_ctl1_adr, set CSR field values - CSR_adj - 0.66V and trim_adj -5mV */
568 {LHL_REG_OFF(lhl_lp_main_ctl1_adr), BCM_MASK32(23, 0), 0x9E9F97},
569
570 /* lhl_lp_main_ctl2_adr, set ASR field values - ASR_adj - 0.76V and trim_adj +5mV */
571 {LHL_REG_OFF(lhl_lp_main_ctl2_adr), BCM_MASK32(13, 0), 0x07EE},
572
573 /* lhl_lp_dn_ctl_adr, set down count for CSR fields- adj, mode, overi_dis */
574 {LHL_REG_OFF(lhl_lp_dn_ctl_adr), ~0, ((LHL4378_CSR_OVERI_DIS_DWN_CNT << 16) |
575 (LHL4378_CSR_MODE_DWN_CNT << 8) | (LHL4378_CSR_ADJ_DWN_CNT << 0))},
576
577 /* lhl_lp_up_ctl_adr, set up count for CSR fields- adj, mode, overi_dis */
578 {LHL_REG_OFF(lhl_lp_up_ctl_adr), ~0, ((LHL4378_CSR_OVERI_DIS_UP_CNT << 16) |
579 (LHL4378_CSR_MODE_UP_CNT << 8) | (LHL4378_CSR_ADJ_UP_CNT << 0))},
580
581 /* lhl_lp_dn_ctl1_adr, set down count for hpbg_chop_dis, ASR_adj, vddc_sw_dis */
582 {LHL_REG_OFF(lhl_lp_dn_ctl1_adr), ~0, ((LHL4378_VDDC_SW_DIS_DWN_CNT << 24) |
583 (LHL4378_ASR_ADJ_DWN_CNT << 16) | (LHL4378_HPBG_CHOP_DIS_DWN_CNT << 0))},
584
585 /* lhl_lp_up_ctl1_adr, set up count for hpbg_chop_dis, ASR_adj, vddc_sw_dis */
586 {LHL_REG_OFF(lhl_lp_up_ctl1_adr), ~0, ((LHL4378_VDDC_SW_DIS_UP_CNT << 24) |
587 (LHL4378_ASR_ADJ_UP_CNT << 16) | (LHL4378_HPBG_CHOP_DIS_UP_CNT << 0))},
588
589 /* lhl_lp_dn_ctl4_adr, set down count for ASR fields -
590 * clk4m_dis, lppfm_mode, mode_sel, manual_mode
591 */
592 {LHL_REG_OFF(lhl_lp_dn_ctl4_adr), ~0, ((LHL4378_ASR_MANUAL_MODE_DWN_CNT << 24) |
593 (LHL4378_ASR_MODE_SEL_DWN_CNT << 16) | (LHL4378_ASR_LPPFM_MODE_DWN_CNT << 8) |
594 (LHL4378_ASR_CLK4M_DIS_DWN_CNT << 0))},
595
596 /* lhl_lp_up_ctl4_adr, set up count for ASR fields -
597 * clk4m_dis, lppfm_mode, mode_sel, manual_mode
598 */
599 {LHL_REG_OFF(lhl_lp_up_ctl4_adr), ~0, ((LHL4378_ASR_MANUAL_MODE_UP_CNT << 24) |
600 (LHL4378_ASR_MODE_SEL_UP_CNT << 16)| (LHL4378_ASR_LPPFM_MODE_UP_CNT << 8) |
601 (LHL4378_ASR_CLK4M_DIS_UP_CNT << 0))},
602
603 /* lhl_lp_dn_ctl3_adr, set down count for hpbg_pu, srbg_ref, ASR_overi_dis,
604 * CSR_pfm_pwr_slice_en
605 */
606 {LHL_REG_OFF(lhl_lp_dn_ctl3_adr), ~0, ((LHL4378_PFM_PWR_SLICE_DWN_CNT << 24) |
607 (LHL4378_ASR_OVERI_DIS_DWN_CNT << 16) | (LHL4378_SRBG_REF_SEL_DWN_CNT << 8) |
608 (LHL4378_HPBG_PU_EN_DWN_CNT << 0))},
609
610 /* lhl_lp_up_ctl3_adr, set up count for hpbg_pu, srbg_ref, ASR_overi_dis,
611 * CSR_pfm_pwr_slice_en
612 */
613 {LHL_REG_OFF(lhl_lp_up_ctl3_adr), ~0, ((LHL4378_PFM_PWR_SLICE_UP_CNT << 24) |
614 (LHL4378_ASR_OVERI_DIS_UP_CNT << 16) | (LHL4378_SRBG_REF_SEL_UP_CNT << 8) |
615 (LHL4378_HPBG_PU_EN_UP_CNT << 0))},
616
617 /* lhl_lp_dn_ctl2_adr, set down count for CSR_trim_adj */
618 {LHL_REG_OFF(lhl_lp_dn_ctl2_adr), LHL4378_CSR_TRIM_ADJ_CNT_MASK,
619 (LHL4378_CSR_TRIM_ADJ_DWN_CNT << LHL4378_CSR_TRIM_ADJ_CNT_SHIFT)},
620
621 /* lhl_lp_up_ctl2_adr, set up count for CSR_trim_adj */
622 {LHL_REG_OFF(lhl_lp_up_ctl2_adr), LHL4378_CSR_TRIM_ADJ_CNT_MASK,
623 (LHL4378_CSR_TRIM_ADJ_UP_CNT << LHL4378_CSR_TRIM_ADJ_CNT_SHIFT)},
624
625 /* lhl_lp_dn_ctl5_adr, set down count for ASR_trim_adj */
626 {LHL_REG_OFF(lhl_lp_dn_ctl5_adr), ~0, (LHL4378_ASR_TRIM_ADJ_DWN_CNT << 0)},
627
628 /* lhl_lp_up_ctl5_adr, set down count for ASR_trim_adj */
629 {LHL_REG_OFF(lhl_lp_up_ctl5_adr), LHL4378_ASR_TRIM_ADJ_CNT_MASK,
630 (LHL4378_ASR_TRIM_ADJ_UP_CNT << LHL4378_ASR_TRIM_ADJ_CNT_SHIFT)},
631
632 /* Change the default down count values for the resources */
633 /* lhl_top_pwrdn_ctl_adr, set down count for top_level_sleep, iso, slb and pwrsw */
634 {LHL_REG_OFF(lhl_top_pwrdn_ctl_adr), ~0, ((LHL4378_PWRSW_EN_DWN_CNT << 24) |
635 (LHL4378_SLB_EN_DWN_CNT << 16) | (LHL4378_ISO_EN_DWN_CNT << 8))},
636
637 /* lhl_top_pwrdn2_ctl_adr, set down count for VMUX_asr_sel */
638 {LHL_REG_OFF(lhl_top_pwrdn2_ctl_adr), ~0, (LHL4378_VMUX_ASR_SEL_DWN_CNT << 16)},
639
640 /* Change the default up count values for the resources */
641 /* lhl_top_pwrup_ctl_adr, set up count for top_level_sleep, iso, slb and pwrsw */
642 {LHL_REG_OFF(lhl_top_pwrup_ctl_adr), ~0, ((LHL4378_PWRSW_EN_UP_CNT << 24) |
643 (LHL4378_SLB_EN_UP_CNT << 16) | (LHL4378_ISO_EN_UP_CNT << 8))},
644
645 /* lhl_top_pwrdn2_ctl_adr, set down count for VMUX_asr_sel */
646 {LHL_REG_OFF(lhl_top_pwrup2_ctl_adr), ~0, ((LHL4378_VMUX_ASR_SEL_UP_CNT << 16))},
647
648 /* Enable lhl interrupt */
649 {LHL_REG_OFF(gci_intmask), (1 << 30), (1 << 30)},
650
651 /* Enable LHL Wake up */
652 {LHL_REG_OFF(gci_wakemask), (1 << 30), (1 << 30)},
653
654 /* Making forceOTPpwrOn 1 */
655 {LHL_REG_OFF(otpcontrol), (1 << 16), (1 << 16)}
656 };
657
658 lhl_reg_set_t BCMATTACHDATA(lv_sleep_mode_4387_lhl_reg_set)[] =
659 {
660 {LHL_REG_OFF(lhl_top_pwrseq_ctl_adr),
661 LHL_TOP_PWRSEQ_SLEEP_ENAB_MASK |
662 LHL_TOP_PWRSEQ_MISCLDO_PU_EN_MASK |
663 LHL_TOP_PWRSEQ_SERDES_SLB_EN_MASK |
664 LHL_TOP_PWRSEQ_SERDES_CLK_DIS_EN_MASK,
665 LHL_TOP_PWRSEQ_SLEEP_ENAB_MASK |
666 LHL_TOP_PWRSEQ_MISCLDO_PU_EN_MASK |
667 LHL_TOP_PWRSEQ_SERDES_SLB_EN_MASK |
668 LHL_TOP_PWRSEQ_SERDES_CLK_DIS_EN_MASK},
669
670 /* lhl_lp_main_ctl_adr, disable lp_mode_en, set CSR and ASR field enables for LV mode */
671 {LHL_REG_OFF(lhl_lp_main_ctl_adr), BCM_MASK32(21, 0), 0x3F89FF},
672
673 /* lhl_lp_main_ctl1_adr, set CSR field values - CSR_adj - 0.64V and trim_adj -5mV */
674 {LHL_REG_OFF(lhl_lp_main_ctl1_adr), BCM_MASK32(23, 0), 0x9ED797},
675
676 /* lhl_lp_main_ctl2_adr, set ASR field values - ASR_adj - 0.64V and trim_adj +5mV */
677 {LHL_REG_OFF(lhl_lp_main_ctl2_adr), BCM_MASK32(13, 0), 0x076D},
678
679 /* lhl_lp_dn_ctl_adr, set down count for CSR fields- adj, mode, overi_dis */
680 {LHL_REG_OFF(lhl_lp_dn_ctl_adr), ~0, ((LHL4378_CSR_OVERI_DIS_DWN_CNT << 16) |
681 (LHL4378_CSR_MODE_DWN_CNT << 8) | (LHL4378_CSR_ADJ_DWN_CNT << 0))},
682
683 /* lhl_lp_up_ctl_adr, set up count for CSR fields- adj, mode, overi_dis */
684 {LHL_REG_OFF(lhl_lp_up_ctl_adr), ~0, ((LHL4378_CSR_OVERI_DIS_UP_CNT << 16) |
685 (LHL4378_CSR_MODE_UP_CNT << 8) | (LHL4378_CSR_ADJ_UP_CNT << 0))},
686
687 /* lhl_lp_dn_ctl1_adr, set down count for hpbg_chop_dis, ASR_adj, vddc_sw_dis */
688 {LHL_REG_OFF(lhl_lp_dn_ctl1_adr), ~0, ((LHL4378_VDDC_SW_DIS_DWN_CNT << 24) |
689 (LHL4378_ASR_ADJ_DWN_CNT << 16) | (LHL4378_HPBG_CHOP_DIS_DWN_CNT << 0))},
690
691 /* lhl_lp_up_ctl1_adr, set up count for hpbg_chop_dis, ASR_adj, vddc_sw_dis */
692 {LHL_REG_OFF(lhl_lp_up_ctl1_adr), ~0, ((LHL4378_VDDC_SW_DIS_UP_CNT << 24) |
693 (LHL4378_ASR_ADJ_UP_CNT << 16) | (LHL4378_HPBG_CHOP_DIS_UP_CNT << 0))},
694
695 /* lhl_lp_dn_ctl4_adr, set down count for ASR fields -
696 * clk4m_dis, lppfm_mode, mode_sel, manual_mode
697 */
698 {LHL_REG_OFF(lhl_lp_dn_ctl4_adr), ~0, ((LHL4378_ASR_MANUAL_MODE_DWN_CNT << 24) |
699 (LHL4378_ASR_MODE_SEL_DWN_CNT << 16) | (LHL4378_ASR_LPPFM_MODE_DWN_CNT << 8) |
700 (LHL4378_ASR_CLK4M_DIS_DWN_CNT << 0))},
701
702 /* lhl_lp_up_ctl4_adr, set up count for ASR fields -
703 * clk4m_dis, lppfm_mode, mode_sel, manual_mode
704 */
705 {LHL_REG_OFF(lhl_lp_up_ctl4_adr), ~0, ((LHL4378_ASR_MANUAL_MODE_UP_CNT << 24) |
706 (LHL4378_ASR_MODE_SEL_UP_CNT << 16)| (LHL4378_ASR_LPPFM_MODE_UP_CNT << 8) |
707 (LHL4378_ASR_CLK4M_DIS_UP_CNT << 0))},
708
709 /* lhl_lp_dn_ctl3_adr, set down count for hpbg_pu, srbg_ref, ASR_overi_dis,
710 * CSR_pfm_pwr_slice_en
711 */
712 {LHL_REG_OFF(lhl_lp_dn_ctl3_adr), ~0, ((LHL4378_PFM_PWR_SLICE_DWN_CNT << 24) |
713 (LHL4378_ASR_OVERI_DIS_DWN_CNT << 16) | (LHL4378_SRBG_REF_SEL_DWN_CNT << 8) |
714 (LHL4378_HPBG_PU_EN_DWN_CNT << 0))},
715
716 /* lhl_lp_up_ctl3_adr, set up count for hpbg_pu, srbg_ref, ASR_overi_dis,
717 * CSR_pfm_pwr_slice_en
718 */
719 {LHL_REG_OFF(lhl_lp_up_ctl3_adr), ~0, ((LHL4378_PFM_PWR_SLICE_UP_CNT << 24) |
720 (LHL4378_ASR_OVERI_DIS_UP_CNT << 16) | (LHL4378_SRBG_REF_SEL_UP_CNT << 8) |
721 (LHL4378_HPBG_PU_EN_UP_CNT << 0))},
722
723 /* lhl_lp_dn_ctl2_adr, set down count for CSR_trim_adj */
724 {LHL_REG_OFF(lhl_lp_dn_ctl2_adr), LHL4378_CSR_TRIM_ADJ_CNT_MASK,
725 (LHL4378_CSR_TRIM_ADJ_DWN_CNT << LHL4378_CSR_TRIM_ADJ_CNT_SHIFT)},
726
727 /* lhl_lp_up_ctl2_adr, set up count for CSR_trim_adj */
728 {LHL_REG_OFF(lhl_lp_up_ctl2_adr), LHL4378_CSR_TRIM_ADJ_CNT_MASK,
729 (LHL4378_CSR_TRIM_ADJ_UP_CNT << LHL4378_CSR_TRIM_ADJ_CNT_SHIFT)},
730
731 /* lhl_lp_dn_ctl5_adr, set down count for ASR_trim_adj */
732 {LHL_REG_OFF(lhl_lp_dn_ctl5_adr), LHL4378_ASR_TRIM_ADJ_CNT_MASK,
733 (LHL4378_ASR_TRIM_ADJ_DWN_CNT << LHL4378_ASR_TRIM_ADJ_CNT_SHIFT)},
734
735 /* lhl_lp_up_ctl5_adr, set down count for ASR_trim_adj */
736 {LHL_REG_OFF(lhl_lp_up_ctl5_adr), LHL4378_ASR_TRIM_ADJ_CNT_MASK,
737 (LHL4378_ASR_TRIM_ADJ_UP_CNT << LHL4378_ASR_TRIM_ADJ_CNT_SHIFT)},
738
739 /* Change the default down count values for the resources */
740 /* lhl_top_pwrdn_ctl_adr, set down count for top_level_sleep, iso, slb and pwrsw */
741 {LHL_REG_OFF(lhl_top_pwrdn_ctl_adr), ~0, ((LHL4378_PWRSW_EN_DWN_CNT << 24) |
742 (LHL4378_SLB_EN_DWN_CNT << 16) | (LHL4378_ISO_EN_DWN_CNT << 8))},
743
744 /* lhl_top_pwrdn2_ctl_adr, set down count for VMUX_asr_sel */
745 {LHL_REG_OFF(lhl_top_pwrdn2_ctl_adr), ~0, (LHL4387_VMUX_ASR_SEL_DWN_CNT << 16)},
746
747 /* Change the default up count values for the resources */
748 /* lhl_top_pwrup_ctl_adr, set up count for top_level_sleep, iso, slb and pwrsw */
749 {LHL_REG_OFF(lhl_top_pwrup_ctl_adr), ~0, ((LHL4378_PWRSW_EN_UP_CNT << 24) |
750 (LHL4378_SLB_EN_UP_CNT << 16) | (LHL4378_ISO_EN_UP_CNT << 8))},
751
752 /* lhl_top_pwrdn2_ctl_adr, set down count for VMUX_asr_sel */
753 {LHL_REG_OFF(lhl_top_pwrup2_ctl_adr), ~0, ((LHL4387_VMUX_ASR_SEL_UP_CNT << 16))},
754
755 /* Enable lhl interrupt */
756 {LHL_REG_OFF(gci_intmask), (1 << 30), (1 << 30)},
757
758 /* Enable LHL Wake up */
759 {LHL_REG_OFF(gci_wakemask), (1 << 30), (1 << 30)},
760
761 /* Making forceOTPpwrOn 1 */
762 {LHL_REG_OFF(otpcontrol), (1 << 16), (1 << 16)},
763
764 /* serdes_clk_dis dn=2, miscldo_pu dn=6; Also include CRWLLHL-48 WAR set bit31 */
765 {LHL_REG_OFF(lhl_top_pwrdn3_ctl_adr), ~0, 0x80040c02},
766
767 /* serdes_clk_dis dn=11, miscldo_pu dn=0 */
768 {LHL_REG_OFF(lhl_top_pwrup3_ctl_adr), ~0, 0x00160010}
769 };
770
771 lhl_reg_set_t BCMATTACHDATA(lv_sleep_mode_4387_lhl_reg_set_top_off)[] =
772 {
773 {LHL_REG_OFF(lhl_top_pwrseq_ctl_adr),
774 LHL_TOP_PWRSEQ_SLEEP_ENAB_MASK |
775 LHL_TOP_PWRSEQ_TOP_ISO_EN_MASK |
776 LHL_TOP_PWRSEQ_TOP_SLB_EN_MASK |
777 LHL_TOP_PWRSEQ_TOP_PWRSW_EN_MASK |
778 LHL_TOP_PWRSEQ_MISCLDO_PU_EN_MASK,
779 LHL_TOP_PWRSEQ_SLEEP_ENAB_MASK |
780 LHL_TOP_PWRSEQ_TOP_ISO_EN_MASK |
781 LHL_TOP_PWRSEQ_TOP_SLB_EN_MASK |
782 LHL_TOP_PWRSEQ_TOP_PWRSW_EN_MASK |
783 LHL_TOP_PWRSEQ_MISCLDO_PU_EN_MASK},
784
785 /* lhl_lp_main_ctl_adr, disable lp_mode_en, set CSR and ASR field enables for LV mode */
786 {LHL_REG_OFF(lhl_lp_main_ctl_adr), BCM_MASK32(21, 0), 0x3F87DB},
787
788 /* lhl_lp_main_ctl1_adr, set CSR field values - CSR_adj - 0.64V and trim_adj -5mV */
789 {LHL_REG_OFF(lhl_lp_main_ctl1_adr), BCM_MASK32(23, 0), 0x9ED7B7},
790
791 /* lhl_lp_main_ctl2_adr, set ASR field values - ASR_adj - 0.64V and trim_adj +5mV */
792 {LHL_REG_OFF(lhl_lp_main_ctl2_adr), BCM_MASK32(13, 0), 0x076D},
793
794 /* lhl_lp_dn_ctl_adr, set down count for CSR fields- adj, mode, overi_dis */
795 {LHL_REG_OFF(lhl_lp_dn_ctl_adr), ~0, ((LHL4387_TO_CSR_OVERI_DIS_DWN_CNT << 16) |
796 (LHL4387_TO_CSR_MODE_DWN_CNT << 8) | (LHL4387_TO_CSR_ADJ_DWN_CNT << 0))},
797
798 /* lhl_lp_up_ctl_adr, set up count for CSR fields- adj, mode, overi_dis */
799 {LHL_REG_OFF(lhl_lp_up_ctl_adr), ~0, ((LHL4387_TO_CSR_OVERI_DIS_UP_CNT << 16) |
800 (LHL4387_TO_CSR_MODE_UP_CNT << 8) | (LHL4387_TO_CSR_ADJ_UP_CNT << 0))},
801
802 /* lhl_lp_dn_ctl1_adr, set down count for hpbg_chop_dis, lp_mode_dn_cnt,
803 * ASR_adj, vddc_sw_dis
804 */
805 {LHL_REG_OFF(lhl_lp_dn_ctl1_adr), ~0, ((LHL4387_TO_VDDC_SW_DIS_DWN_CNT << 24) |
806 (LHL4387_TO_ASR_ADJ_DWN_CNT << 16) | (LHL4387_TO_LP_MODE_DWN_CNT << 8) |
807 (LHL4387_TO_HPBG_CHOP_DIS_DWN_CNT << 0))},
808
809 /* lhl_lp_up_ctl1_adr, set up count for hpbg_chop_dis, lp_mode_dn_cnt,
810 * ASR_adj, vddc_sw_dis
811 */
812 {LHL_REG_OFF(lhl_lp_up_ctl1_adr), ~0, ((LHL4387_TO_VDDC_SW_DIS_UP_CNT << 24) |
813 (LHL4387_TO_ASR_ADJ_UP_CNT << 16) | (LHL4387_TO_LP_MODE_UP_CNT << 8) |
814 (LHL4387_TO_HPBG_CHOP_DIS_UP_CNT << 0))},
815
816 /* lhl_lp_dn_ctl4_adr, set down count for ASR fields -
817 * clk4m_dis, lppfm_mode, mode_sel, manual_mode
818 */
819 {LHL_REG_OFF(lhl_lp_dn_ctl4_adr), ~0, ((LHL4387_TO_ASR_MANUAL_MODE_DWN_CNT << 24) |
820 (LHL4387_TO_ASR_MODE_SEL_DWN_CNT << 16) | (LHL4387_TO_ASR_LPPFM_MODE_DWN_CNT << 8) |
821 (LHL4387_TO_ASR_CLK4M_DIS_DWN_CNT << 0))},
822
823 /* lhl_lp_up_ctl4_adr, set up count for ASR fields -
824 * clk4m_dis, lppfm_mode, mode_sel, manual_mode
825 */
826 {LHL_REG_OFF(lhl_lp_up_ctl4_adr), ~0, ((LHL4387_TO_ASR_MANUAL_MODE_UP_CNT << 24) |
827 (LHL4387_TO_ASR_MODE_SEL_UP_CNT << 16)| (LHL4387_TO_ASR_LPPFM_MODE_UP_CNT << 8) |
828 (LHL4387_TO_ASR_CLK4M_DIS_UP_CNT << 0))},
829
830 /* lhl_lp_dn_ctl3_adr, set down count for hpbg_pu, srbg_ref, ASR_overi_dis,
831 * CSR_pfm_pwr_slice_en
832 */
833 {LHL_REG_OFF(lhl_lp_dn_ctl3_adr), ~0, ((LHL4387_TO_PFM_PWR_SLICE_DWN_CNT << 24) |
834 (LHL4387_TO_ASR_OVERI_DIS_DWN_CNT << 16) | (LHL4387_TO_SRBG_REF_SEL_DWN_CNT << 8) |
835 (LHL4387_TO_HPBG_PU_EN_DWN_CNT << 0))},
836
837 /* lhl_lp_up_ctl3_adr, set up count for hpbg_pu, srbg_ref, ASR_overi_dis,
838 * CSR_pfm_pwr_slice_en
839 */
840 {LHL_REG_OFF(lhl_lp_up_ctl3_adr), ~0, ((LHL4387_TO_PFM_PWR_SLICE_UP_CNT << 24) |
841 (LHL4387_TO_ASR_OVERI_DIS_UP_CNT << 16) | (LHL4387_TO_SRBG_REF_SEL_UP_CNT << 8) |
842 (LHL4387_TO_HPBG_PU_EN_UP_CNT << 0))},
843
844 /* ASR_trim_adj downcount=0x3, [30:24] is default value for spmi_*io_sel */
845 {LHL_REG_OFF(lhl_lp_dn_ctl5_adr), LHL4378_ASR_TRIM_ADJ_CNT_MASK, 0x3},
846
847 /* ASR_trim_adj upcount=0x1, [30:24] is default value for spmi_*io_sel */
848 {LHL_REG_OFF(lhl_lp_up_ctl5_adr), LHL4378_ASR_TRIM_ADJ_CNT_MASK, 0x1},
849
850 /* Change the default down count values for the resources */
851 /* lhl_top_pwrdn_ctl_adr, set down count for top_level_sleep, iso, slb and pwrsw */
852 {LHL_REG_OFF(lhl_top_pwrdn_ctl_adr), ~0, ((LHL4387_TO_PWRSW_EN_DWN_CNT << 24) |
853 (LHL4387_TO_SLB_EN_DWN_CNT << 16) | (LHL4387_TO_ISO_EN_DWN_CNT << 8) |
854 (LHL4387_TO_TOP_SLP_EN_DWN_CNT))},
855
856 /* Change the default up count values for the resources */
857 /* lhl_top_pwrup_ctl_adr, set up count for top_level_sleep, iso, slb and pwrsw */
858 {LHL_REG_OFF(lhl_top_pwrup_ctl_adr), ~0, ((LHL4387_TO_PWRSW_EN_UP_CNT << 24) |
859 (LHL4387_TO_SLB_EN_UP_CNT << 16) | (LHL4387_TO_ISO_EN_UP_CNT << 8) |
860 (LHL4387_TO_TOP_SLP_EN_UP_CNT))},
861
862 /* lhl_top_pwrup2_ctl, serdes_slb_en_up_cnt=0x7 */
863 {LHL_REG_OFF(lhl_top_pwrup2_ctl_adr), LHL4378_CSR_TRIM_ADJ_CNT_MASK, 0xe0000},
864
865 /* lhl_top_pwrdn2_ctl, serdes_slb_en_dn_cnt=0x2 */
866 {LHL_REG_OFF(lhl_top_pwrdn2_ctl_adr), LHL4378_CSR_TRIM_ADJ_CNT_MASK, 0x40000},
867
868 /* Enable lhl interrupt */
869 {LHL_REG_OFF(gci_intmask), (1 << 30), (1 << 30)},
870
871 /* Enable LHL Wake up */
872 {LHL_REG_OFF(gci_wakemask), (1 << 30), (1 << 30)},
873
874 /* Making forceOTPpwrOn 1 */
875 {LHL_REG_OFF(otpcontrol), (1 << 16), (1 << 16)},
876
877 /* lhl_top_pwrup3_ctl, FLL pu power up count=0x8, miscldo pu power up count=0x0,
878 * serdes_clk_dis up count=0x7
879 */
880 {LHL_REG_OFF(lhl_top_pwrup3_ctl_adr), ~0, 0xe0010},
881
882 /* lhl_top_pwrdn3_ctl, FLL pu power up count=0x1,miscldo pu power up count=0x3,
883 * serdes_clk_dis up count=0x1
884 */
885 {LHL_REG_OFF(lhl_top_pwrdn3_ctl_adr), ~0, 0x20602}
886 };
887
888 lhl_reg_set_t BCMATTACHDATA(lv_sleep_mode_4389_lhl_reg_set)[] =
889 {
890 /* set wl_sleep_en */
891 {LHL_REG_OFF(lhl_top_pwrseq_ctl_adr), (1 << 0), (1 << 0)},
892
893 /* set top_pwrsw_en, top_slb_en, top_iso_en */
894 {LHL_REG_OFF(lhl_top_pwrseq_ctl_adr), BCM_MASK32(5, 3), (0x0 << 3)},
895
896 /* set VMUX_asr_sel_en */
897 {LHL_REG_OFF(lhl_top_pwrseq_ctl_adr), (1 << 8), (1 << 8)},
898
899 /* lhl_lp_main_ctl_adr, disable lp_mode_en, set CSR and ASR field enables for LV mode */
900 {LHL_REG_OFF(lhl_lp_main_ctl_adr), BCM_MASK32(21, 0), 0x3F89FF},
901
902 /* lhl_lp_main_ctl1_adr, set CSR field values - CSR_adj - 0.64V and trim_adj -5mV */
903 {LHL_REG_OFF(lhl_lp_main_ctl1_adr), BCM_MASK32(23, 0), 0x9EDF97},
904
905 /* lhl_lp_main_ctl2_adr, set ASR field values - ASR_adj - 0.64V and trim_adj +5mV */
906 {LHL_REG_OFF(lhl_lp_main_ctl2_adr), BCM_MASK32(13, 0), 0x07ED},
907
908 /* lhl_lp_dn_ctl_adr, set down count for CSR fields- adj, mode, overi_dis */
909 {LHL_REG_OFF(lhl_lp_dn_ctl_adr), ~0, ((LHL4378_CSR_OVERI_DIS_DWN_CNT << 16) |
910 (LHL4378_CSR_MODE_DWN_CNT << 8) | (LHL4378_CSR_ADJ_DWN_CNT << 0))},
911
912 /* lhl_lp_up_ctl_adr, set up count for CSR fields- adj, mode, overi_dis */
913 {LHL_REG_OFF(lhl_lp_up_ctl_adr), ~0, ((LHL4378_CSR_OVERI_DIS_UP_CNT << 16) |
914 (LHL4378_CSR_MODE_UP_CNT << 8) | (LHL4378_CSR_ADJ_UP_CNT << 0))},
915
916 /* lhl_lp_dn_ctl1_adr, set down count for hpbg_chop_dis, ASR_adj, vddc_sw_dis */
917 {LHL_REG_OFF(lhl_lp_dn_ctl1_adr), ~0, ((LHL4378_VDDC_SW_DIS_DWN_CNT << 24) |
918 (LHL4378_ASR_ADJ_DWN_CNT << 16) | (LHL4378_HPBG_CHOP_DIS_DWN_CNT << 0))},
919
920 /* lhl_lp_up_ctl1_adr, set up count for hpbg_chop_dis, ASR_adj, vddc_sw_dis */
921 {LHL_REG_OFF(lhl_lp_up_ctl1_adr), ~0, ((LHL4378_VDDC_SW_DIS_UP_CNT << 24) |
922 (LHL4378_ASR_ADJ_UP_CNT << 16) | (LHL4378_HPBG_CHOP_DIS_UP_CNT << 0))},
923
924 /* lhl_lp_dn_ctl4_adr, set down count for ASR fields -
925 * clk4m_dis, lppfm_mode, mode_sel, manual_mode
926 */
927 {LHL_REG_OFF(lhl_lp_dn_ctl4_adr), ~0, ((LHL4378_ASR_MANUAL_MODE_DWN_CNT << 24) |
928 (LHL4378_ASR_MODE_SEL_DWN_CNT << 16) | (LHL4378_ASR_LPPFM_MODE_DWN_CNT << 8) |
929 (LHL4378_ASR_CLK4M_DIS_DWN_CNT << 0))},
930
931 /* lhl_lp_up_ctl4_adr, set up count for ASR fields -
932 * clk4m_dis, lppfm_mode, mode_sel, manual_mode
933 */
934 {LHL_REG_OFF(lhl_lp_up_ctl4_adr), ~0, ((LHL4378_ASR_MANUAL_MODE_UP_CNT << 24) |
935 (LHL4378_ASR_MODE_SEL_UP_CNT << 16)| (LHL4378_ASR_LPPFM_MODE_UP_CNT << 8) |
936 (LHL4378_ASR_CLK4M_DIS_UP_CNT << 0))},
937
938 /* lhl_lp_dn_ctl3_adr, set down count for hpbg_pu, srbg_ref, ASR_overi_dis,
939 * CSR_pfm_pwr_slice_en
940 */
941 {LHL_REG_OFF(lhl_lp_dn_ctl3_adr), ~0, ((LHL4378_PFM_PWR_SLICE_DWN_CNT << 24) |
942 (LHL4378_ASR_OVERI_DIS_DWN_CNT << 16) | (LHL4378_SRBG_REF_SEL_DWN_CNT << 8) |
943 (LHL4378_HPBG_PU_EN_DWN_CNT << 0))},
944
945 /* lhl_lp_up_ctl3_adr, set up count for hpbg_pu, srbg_ref, ASR_overi_dis,
946 * CSR_pfm_pwr_slice_en
947 */
948 {LHL_REG_OFF(lhl_lp_up_ctl3_adr), ~0, ((LHL4378_PFM_PWR_SLICE_UP_CNT << 24) |
949 (LHL4378_ASR_OVERI_DIS_UP_CNT << 16) | (LHL4378_SRBG_REF_SEL_UP_CNT << 8) |
950 (LHL4378_HPBG_PU_EN_UP_CNT << 0))},
951
952 /* lhl_lp_dn_ctl2_adr, set down count for CSR_trim_adj */
953 {LHL_REG_OFF(lhl_lp_dn_ctl2_adr), ~0, (LHL4378_CSR_TRIM_ADJ_DWN_CNT << 16)},
954
955 /* lhl_lp_up_ctl2_adr, set up count for CSR_trim_adj */
956 {LHL_REG_OFF(lhl_lp_up_ctl2_adr), ~0, (LHL4378_CSR_TRIM_ADJ_UP_CNT << 16)},
957
958 /* lhl_lp_dn_ctl5_adr, set down count for ASR_trim_adj */
959 {LHL_REG_OFF(lhl_lp_dn_ctl5_adr), LHL4378_ASR_TRIM_ADJ_CNT_MASK,
960 (LHL4378_ASR_TRIM_ADJ_DWN_CNT << LHL4378_ASR_TRIM_ADJ_CNT_SHIFT)},
961
962 /* lhl_lp_up_ctl5_adr, set down count for ASR_trim_adj */
963 {LHL_REG_OFF(lhl_lp_up_ctl5_adr), LHL4378_ASR_TRIM_ADJ_CNT_MASK,
964 (LHL4378_ASR_TRIM_ADJ_UP_CNT << LHL4378_ASR_TRIM_ADJ_CNT_SHIFT)},
965
966 /* Change the default down count values for the resources */
967 /* lhl_top_pwrdn_ctl_adr, set down count for top_level_sleep, iso, slb and pwrsw */
968 {LHL_REG_OFF(lhl_top_pwrdn_ctl_adr), ~0, ((LHL4378_PWRSW_EN_DWN_CNT << 24) |
969 (LHL4378_SLB_EN_DWN_CNT << 16) | (LHL4378_ISO_EN_DWN_CNT << 8))},
970
971 /* lhl_top_pwrdn2_ctl_adr, set down count for VMUX_asr_sel */
972 {LHL_REG_OFF(lhl_top_pwrdn2_ctl_adr), ~0, (LHL4387_VMUX_ASR_SEL_DWN_CNT << 16)},
973
974 /* Change the default up count values for the resources */
975 /* lhl_top_pwrup_ctl_adr, set up count for top_level_sleep, iso, slb and pwrsw */
976 {LHL_REG_OFF(lhl_top_pwrup_ctl_adr), ~0, ((LHL4378_PWRSW_EN_UP_CNT << 24) |
977 (LHL4378_SLB_EN_UP_CNT << 16) | (LHL4378_ISO_EN_UP_CNT << 8))},
978
979 /* lhl_top_pwrdn2_ctl_adr, set down count for VMUX_asr_sel */
980 {LHL_REG_OFF(lhl_top_pwrup2_ctl_adr), ~0, ((LHL4387_VMUX_ASR_SEL_UP_CNT << 16))},
981
982 /* Enable lhl interrupt */
983 {LHL_REG_OFF(gci_intmask), (1 << 30), (1 << 30)},
984
985 /* Enable LHL Wake up */
986 {LHL_REG_OFF(gci_wakemask), (1 << 30), (1 << 30)},
987
988 /* Making forceOTPpwrOn 1 */
989 {LHL_REG_OFF(otpcontrol), (1 << 16), (1 << 16)},
990
991 /* serdes_clk_dis dn=2, miscldo_pu dn=6; Also include CRWLLHL-48 WAR set bit31 */
992 {LHL_REG_OFF(lhl_top_pwrdn3_ctl_adr), ~0, 0x80040c02},
993
994 /* serdes_clk_dis dn=11, miscldo_pu dn=0 */
995 {LHL_REG_OFF(lhl_top_pwrup3_ctl_adr), ~0, 0x00160010}
996 };
997
998 /* LV sleep mode summary:
999 * LV mode is where both ABUCK and CBUCK are programmed to low voltages during
1000 * sleep, and VMUX selects ABUCK as VDDOUT_AON. LPLDO needs to power off.
1001 * With ASR ON, LPLDO OFF
1002 */
1003 void
BCMATTACHFN(si_set_lv_sleep_mode_lhl_config_4369)1004 BCMATTACHFN(si_set_lv_sleep_mode_lhl_config_4369)(si_t *sih)
1005 {
1006 uint i;
1007 uint coreidx = si_findcoreidx(sih, GCI_CORE_ID, 0);
1008 lhl_reg_set_t *regs = lv_sleep_mode_4369_lhl_reg_set;
1009
1010 /* Enable LHL LV mode:
1011 * lhl_top_pwrseq_ctl_adr, set wl_sleep_en, iso_en, slb_en, pwrsw_en,VMUX_asr_sel_en
1012 */
1013 for (i = 0; i < ARRAYSIZE(lv_sleep_mode_4369_lhl_reg_set); i++) {
1014 si_corereg(sih, coreidx, regs[i].offset, regs[i].mask, regs[i].val);
1015 }
1016 if (getintvar(NULL, rstr_rfldo3p3_cap_war)) {
1017 si_corereg(sih, coreidx, LHL_REG_OFF(lhl_lp_main_ctl1_adr),
1018 BCM_MASK32(23, 0), 0x9E9F9F);
1019 }
1020 }
1021
1022 void
BCMATTACHFN(si_set_lv_sleep_mode_lhl_config_4378)1023 BCMATTACHFN(si_set_lv_sleep_mode_lhl_config_4378)(si_t *sih)
1024 {
1025 uint i;
1026 uint coreidx = si_findcoreidx(sih, GCI_CORE_ID, 0);
1027 lhl_reg_set_t *regs = lv_sleep_mode_4378_lhl_reg_set;
1028
1029 /* Enable LHL LV mode:
1030 * lhl_top_pwrseq_ctl_adr, set wl_sleep_en, iso_en, slb_en, pwrsw_en,VMUX_asr_sel_en
1031 */
1032 for (i = 0; i < ARRAYSIZE(lv_sleep_mode_4378_lhl_reg_set); i++) {
1033 si_corereg(sih, coreidx, regs[i].offset, regs[i].mask, regs[i].val);
1034 }
1035 }
1036
1037 void
BCMATTACHFN(si_set_lv_sleep_mode_lhl_config_4387)1038 BCMATTACHFN(si_set_lv_sleep_mode_lhl_config_4387)(si_t *sih)
1039 {
1040 uint i;
1041 uint coreidx = si_findcoreidx(sih, GCI_CORE_ID, 0);
1042 lhl_reg_set_t *regs;
1043 uint32 abuck_volt_sleep, cbuck_volt_sleep;
1044 uint regs_size;
1045
1046 if (BCMSRTOPOFF_ENAB()) {
1047 regs = lv_sleep_mode_4387_lhl_reg_set_top_off;
1048 regs_size = ARRAYSIZE(lv_sleep_mode_4387_lhl_reg_set_top_off);
1049 } else {
1050 /* Enable LHL LV mode:
1051 * lhl_top_pwrseq_ctl_adr, set wl_sleep_en, iso_en, slb_en, pwrsw_en,VMUX_asr_sel_en
1052 */
1053 regs = lv_sleep_mode_4387_lhl_reg_set;
1054 regs_size = ARRAYSIZE(lv_sleep_mode_4387_lhl_reg_set);
1055 }
1056
1057 for (i = 0; i < regs_size; i++) {
1058 si_corereg(sih, coreidx, regs[i].offset, regs[i].mask, regs[i].val);
1059 }
1060
1061 if (getvar(NULL, rstr_cbuck_volt_sleep) != NULL) {
1062 cbuck_volt_sleep = getintvar(NULL, rstr_cbuck_volt_sleep);
1063 LHL_REG(sih, lhl_lp_main_ctl1_adr, LHL_CBUCK_VOLT_SLEEP_MASK,
1064 (cbuck_volt_sleep << LHL_CBUCK_VOLT_SLEEP_SHIFT));
1065 }
1066
1067 if (getvar(NULL, rstr_abuck_volt_sleep) != NULL) {
1068 abuck_volt_sleep = getintvar(NULL, rstr_abuck_volt_sleep);
1069 LHL_REG(sih, lhl_lp_main_ctl2_adr, LHL_ABUCK_VOLT_SLEEP_MASK,
1070 (abuck_volt_sleep << LHL_ABUCK_VOLT_SLEEP_SHIFT));
1071 }
1072
1073 if (BCMSRTOPOFF_ENAB()) {
1074 /* Serdes AFE retention control enable */
1075 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_05,
1076 CC_GCI_05_4387C0_AFE_RET_ENB_MASK,
1077 CC_GCI_05_4387C0_AFE_RET_ENB_MASK);
1078 }
1079 }
1080
1081 void
BCMATTACHFN(si_set_lv_sleep_mode_lhl_config_4389)1082 BCMATTACHFN(si_set_lv_sleep_mode_lhl_config_4389)(si_t *sih)
1083 {
1084 uint i;
1085 uint coreidx = si_findcoreidx(sih, GCI_CORE_ID, 0);
1086 lhl_reg_set_t *regs = lv_sleep_mode_4389_lhl_reg_set;
1087 uint32 abuck_volt_sleep, cbuck_volt_sleep;
1088
1089 /* Enable LHL LV mode:
1090 * lhl_top_pwrseq_ctl_adr, set wl_sleep_en, iso_en, slb_en, pwrsw_en,VMUX_asr_sel_en
1091 */
1092 for (i = 0; i < ARRAYSIZE(lv_sleep_mode_4389_lhl_reg_set); i++) {
1093 si_corereg(sih, coreidx, regs[i].offset, regs[i].mask, regs[i].val);
1094 }
1095
1096 if (getvar(NULL, rstr_cbuck_volt_sleep) != NULL) {
1097 cbuck_volt_sleep = getintvar(NULL, rstr_cbuck_volt_sleep);
1098 LHL_REG(sih, lhl_lp_main_ctl1_adr, LHL_CBUCK_VOLT_SLEEP_MASK,
1099 (cbuck_volt_sleep << LHL_CBUCK_VOLT_SLEEP_SHIFT));
1100 }
1101
1102 if (getvar(NULL, rstr_abuck_volt_sleep) != NULL) {
1103 abuck_volt_sleep = getintvar(NULL, rstr_abuck_volt_sleep);
1104 LHL_REG(sih, lhl_lp_main_ctl2_adr, LHL_ABUCK_VOLT_SLEEP_MASK,
1105 (abuck_volt_sleep << LHL_ABUCK_VOLT_SLEEP_SHIFT));
1106 }
1107
1108 OSL_DELAY(100);
1109 LHL_REG(sih, lhl_top_pwrseq_ctl_adr, ~0, 0x00000101);
1110
1111 /* Clear Misc_LDO override */
1112 si_pmu_vreg_control(sih, PMU_VREG_5, VREG5_4387_MISCLDO_PU_MASK, 0);
1113 }
1114
1115 lhl_reg_set_t BCMATTACHDATA(lv_sleep_mode_4362_lhl_reg_set)[] =
1116 {
1117 /* set wl_sleep_en */
1118 {LHL_REG_OFF(lhl_top_pwrseq_ctl_adr), (1 << 0), (1 << 0)},
1119
1120 /* set top_pwrsw_en, top_slb_en, top_iso_en */
1121 {LHL_REG_OFF(lhl_top_pwrseq_ctl_adr), BCM_MASK32(5, 3), (0x0 << 3)},
1122
1123 /* set VMUX_asr_sel_en */
1124 {LHL_REG_OFF(lhl_top_pwrseq_ctl_adr), (1 << 8), (1 << 8)},
1125
1126 /* lhl_lp_main_ctl_adr, disable lp_mode_en, set CSR and ASR field enables for LV mode */
1127 {LHL_REG_OFF(lhl_lp_main_ctl_adr), BCM_MASK32(21, 0), 0x3F89FF},
1128
1129 /* lhl_lp_main_ctl1_adr, set CSR field values - CSR_adj - 0.66V and trim_adj -5mV */
1130 {LHL_REG_OFF(lhl_lp_main_ctl1_adr), BCM_MASK32(23, 0), 0x9E9F97},
1131
1132 /* lhl_lp_main_ctl2_adr, set ASR field values - ASR_adj - 0.76V and trim_adj +5mV */
1133 {LHL_REG_OFF(lhl_lp_main_ctl2_adr), BCM_MASK32(13, 0), 0x07EE},
1134
1135 /* lhl_lp_dn_ctl_adr, set down count for CSR fields- adj, mode, overi_dis */
1136 {LHL_REG_OFF(lhl_lp_dn_ctl_adr), ~0, ((LHL4362_CSR_OVERI_DIS_DWN_CNT << 16) |
1137 (LHL4362_CSR_MODE_DWN_CNT << 8) | (LHL4362_CSR_ADJ_DWN_CNT << 0))},
1138
1139 /* lhl_lp_up_ctl_adr, set up count for CSR fields- adj, mode, overi_dis */
1140 {LHL_REG_OFF(lhl_lp_up_ctl_adr), ~0, ((LHL4362_CSR_OVERI_DIS_UP_CNT << 16) |
1141 (LHL4362_CSR_MODE_UP_CNT << 8) | (LHL4362_CSR_ADJ_UP_CNT << 0))},
1142
1143 /* lhl_lp_dn_ctl1_adr, set down count for hpbg_chop_dis, ASR_adj, vddc_sw_dis */
1144 {LHL_REG_OFF(lhl_lp_dn_ctl1_adr), ~0, ((LHL4362_VDDC_SW_DIS_DWN_CNT << 24) |
1145 (LHL4362_ASR_ADJ_DWN_CNT << 16) | (LHL4362_HPBG_CHOP_DIS_DWN_CNT << 0))},
1146
1147 /* lhl_lp_up_ctl1_adr, set up count for hpbg_chop_dis, ASR_adj, vddc_sw_dis */
1148 {LHL_REG_OFF(lhl_lp_up_ctl1_adr), ~0, ((LHL4362_VDDC_SW_DIS_UP_CNT << 24) |
1149 (LHL4362_ASR_ADJ_UP_CNT << 16) | (LHL4362_HPBG_CHOP_DIS_UP_CNT << 0))},
1150
1151 /* lhl_lp_dn_ctl4_adr, set down count for ASR fields -
1152 * clk4m_dis, lppfm_mode, mode_sel, manual_mode
1153 */
1154 {LHL_REG_OFF(lhl_lp_dn_ctl4_adr), ~0, ((LHL4362_ASR_MANUAL_MODE_DWN_CNT << 24) |
1155 (LHL4362_ASR_MODE_SEL_DWN_CNT << 16) | (LHL4362_ASR_LPPFM_MODE_DWN_CNT << 8) |
1156 (LHL4362_ASR_CLK4M_DIS_DWN_CNT << 0))},
1157
1158 /* lhl_lp_up_ctl4_adr, set up count for ASR fields -
1159 * clk4m_dis, lppfm_mode, mode_sel, manual_mode
1160 */
1161 {LHL_REG_OFF(lhl_lp_up_ctl4_adr), ~0, ((LHL4362_ASR_MANUAL_MODE_UP_CNT << 24) |
1162 (LHL4362_ASR_MODE_SEL_UP_CNT << 16)| (LHL4362_ASR_LPPFM_MODE_UP_CNT << 8) |
1163 (LHL4362_ASR_CLK4M_DIS_UP_CNT << 0))},
1164
1165 /* lhl_lp_dn_ctl3_adr, set down count for hpbg_pu, srbg_ref, ASR_overi_dis,
1166 * CSR_pfm_pwr_slice_en
1167 */
1168 {LHL_REG_OFF(lhl_lp_dn_ctl3_adr), ~0, ((LHL4362_PFM_PWR_SLICE_DWN_CNT << 24) |
1169 (LHL4362_ASR_OVERI_DIS_DWN_CNT << 16) | (LHL4362_SRBG_REF_SEL_DWN_CNT << 8) |
1170 (LHL4362_HPBG_PU_EN_DWN_CNT << 0))},
1171
1172 /* lhl_lp_up_ctl3_adr, set up count for hpbg_pu, srbg_ref, ASR_overi_dis,
1173 * CSR_pfm_pwr_slice_en
1174 */
1175 {LHL_REG_OFF(lhl_lp_up_ctl3_adr), ~0, ((LHL4362_PFM_PWR_SLICE_UP_CNT << 24) |
1176 (LHL4362_ASR_OVERI_DIS_UP_CNT << 16) | (LHL4362_SRBG_REF_SEL_UP_CNT << 8) |
1177 (LHL4362_HPBG_PU_EN_UP_CNT << 0))},
1178
1179 /* lhl_lp_dn_ctl2_adr, set down count for CSR_trim_adj */
1180 {LHL_REG_OFF(lhl_lp_dn_ctl2_adr), ~0, (LHL4362_CSR_TRIM_ADJ_DWN_CNT << 16)},
1181
1182 /* lhl_lp_up_ctl2_adr, set up count for CSR_trim_adj */
1183 {LHL_REG_OFF(lhl_lp_up_ctl2_adr), ~0, (LHL4362_CSR_TRIM_ADJ_UP_CNT << 16)},
1184
1185 /* lhl_lp_dn_ctl5_adr, set down count for ASR_trim_adj */
1186 {LHL_REG_OFF(lhl_lp_dn_ctl5_adr), ~0, (LHL4362_ASR_TRIM_ADJ_DWN_CNT << 0)},
1187
1188 /* lhl_lp_up_ctl5_adr, set down count for ASR_trim_adj */
1189 {LHL_REG_OFF(lhl_lp_up_ctl5_adr), ~0, (LHL4362_ASR_TRIM_ADJ_UP_CNT << 0)},
1190
1191 /* Change the default down count values for the resources */
1192 /* lhl_top_pwrdn_ctl_adr, set down count for top_level_sleep, iso, slb and pwrsw */
1193 {LHL_REG_OFF(lhl_top_pwrdn_ctl_adr), ~0, ((LHL4362_PWRSW_EN_DWN_CNT << 24) |
1194 (LHL4362_SLB_EN_DWN_CNT << 16) | (LHL4362_ISO_EN_DWN_CNT << 8))},
1195
1196 /* lhl_top_pwrdn2_ctl_adr, set down count for VMUX_asr_sel */
1197 {LHL_REG_OFF(lhl_top_pwrdn2_ctl_adr), ~0, (LHL4362_VMUX_ASR_SEL_DWN_CNT << 16)},
1198
1199 /* Change the default up count values for the resources */
1200 /* lhl_top_pwrup_ctl_adr, set up count for top_level_sleep, iso, slb and pwrsw */
1201 {LHL_REG_OFF(lhl_top_pwrup_ctl_adr), ~0, ((LHL4362_PWRSW_EN_UP_CNT << 24) |
1202 (LHL4362_SLB_EN_UP_CNT << 16) | (LHL4362_ISO_EN_UP_CNT << 8))},
1203
1204 /* lhl_top_pwrdn2_ctl_adr, set down count for VMUX_asr_sel */
1205 {LHL_REG_OFF(lhl_top_pwrup2_ctl_adr), ~0, ((LHL4362_VMUX_ASR_SEL_UP_CNT << 16))},
1206
1207 /* Enable lhl interrupt */
1208 {LHL_REG_OFF(gci_intmask), (1 << 30), (1 << 30)},
1209
1210 /* Enable LHL Wake up */
1211 {LHL_REG_OFF(gci_wakemask), (1 << 30), (1 << 30)},
1212
1213 /* Making forceOTPpwrOn 1 */
1214 {LHL_REG_OFF(otpcontrol), (1 << 16), (1 << 16)}
1215 };
1216
1217 /* LV sleep mode summary:
1218 * LV mode is where both ABUCK and CBUCK are programmed to low voltages during
1219 * sleep, and VMUX selects ABUCK as VDDOUT_AON. LPLDO needs to power off.
1220 * With ASR ON, LPLDO OFF
1221 */
1222 void
BCMATTACHFN(si_set_lv_sleep_mode_lhl_config_4362)1223 BCMATTACHFN(si_set_lv_sleep_mode_lhl_config_4362)(si_t *sih)
1224 {
1225 uint i;
1226 uint coreidx = si_findcoreidx(sih, GCI_CORE_ID, 0);
1227 lhl_reg_set_t *regs = lv_sleep_mode_4362_lhl_reg_set;
1228
1229 /* Enable LHL LV mode:
1230 * lhl_top_pwrseq_ctl_adr, set wl_sleep_en, iso_en, slb_en, pwrsw_en,VMUX_asr_sel_en
1231 */
1232 for (i = 0; i < ARRAYSIZE(lv_sleep_mode_4362_lhl_reg_set); i++) {
1233 si_corereg(sih, coreidx, regs[i].offset, regs[i].mask, regs[i].val);
1234 }
1235 }
1236
1237 void
si_lhl_mactim0_set(si_t * sih,uint32 val)1238 si_lhl_mactim0_set(si_t *sih, uint32 val)
1239 {
1240 LHL_REG(sih, lhl_wl_mactim_int0_adr, LHL_WL_MACTIMER_MASK, val);
1241 }
1242