1 /* 2 * Copyright (C) 2016 Rockchip Electronics Co., Ltd. 3 * Authors: 4 * Zhiqin Wei <wzq@rock-chips.com> 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 */ 18 19 #ifndef _RGA_DRIVER_H_ 20 #define _RGA_DRIVER_H_ 21 22 23 #ifndef ENABLE 24 #define ENABLE 1 25 #endif 26 27 #ifndef DISABLE 28 #define DISABLE 0 29 #endif 30 31 #ifdef __cplusplus 32 extern "C" 33 { 34 #endif 35 36 /* In order to be compatible with RK_FORMAT_XX and HAL_PIXEL_FORMAT_XX, 37 * RK_FORMAT_XX is shifted to the left by 8 bits to distinguish. */ 38 typedef enum _Rga_SURF_FORMAT { 39 RK_FORMAT_RGBA_8888 = 0x0 << 8, 40 RK_FORMAT_RGBX_8888 = 0x1 << 8, 41 RK_FORMAT_RGB_888 = 0x2 << 8, 42 RK_FORMAT_BGRA_8888 = 0x3 << 8, 43 RK_FORMAT_RGB_565 = 0x4 << 8, 44 RK_FORMAT_RGBA_5551 = 0x5 << 8, 45 RK_FORMAT_RGBA_4444 = 0x6 << 8, 46 RK_FORMAT_BGR_888 = 0x7 << 8, 47 48 RK_FORMAT_YCbCr_422_SP = 0x8 << 8, 49 RK_FORMAT_YCbCr_422_P = 0x9 << 8, 50 RK_FORMAT_YCbCr_420_SP = 0xa << 8, 51 RK_FORMAT_YCbCr_420_P = 0xb << 8, 52 53 RK_FORMAT_YCrCb_422_SP = 0xc << 8, 54 RK_FORMAT_YCrCb_422_P = 0xd << 8, 55 RK_FORMAT_YCrCb_420_SP = 0xe << 8, 56 RK_FORMAT_YCrCb_420_P = 0xf << 8, 57 58 RK_FORMAT_BPP1 = 0x10 << 8, 59 RK_FORMAT_BPP2 = 0x11 << 8, 60 RK_FORMAT_BPP4 = 0x12 << 8, 61 RK_FORMAT_BPP8 = 0x13 << 8, 62 63 RK_FORMAT_Y4 = 0x14 << 8, 64 RK_FORMAT_YCbCr_400 = 0x15 << 8, 65 66 RK_FORMAT_BGRX_8888 = 0x16 << 8, 67 68 RK_FORMAT_YVYU_422 = 0x18 << 8, 69 RK_FORMAT_YVYU_420 = 0x19 << 8, 70 RK_FORMAT_VYUY_422 = 0x1a << 8, 71 RK_FORMAT_VYUY_420 = 0x1b << 8, 72 RK_FORMAT_YUYV_422 = 0x1c << 8, 73 RK_FORMAT_YUYV_420 = 0x1d << 8, 74 RK_FORMAT_UYVY_422 = 0x1e << 8, 75 RK_FORMAT_UYVY_420 = 0x1f << 8, 76 77 RK_FORMAT_YCbCr_420_SP_10B = 0x20 << 8, 78 RK_FORMAT_YCrCb_420_SP_10B = 0x21 << 8, 79 RK_FORMAT_YCbCr_422_SP_10B = 0x22 << 8, 80 RK_FORMAT_YCrCb_422_SP_10B = 0x23 << 8, 81 /* For compatibility with misspellings */ 82 RK_FORMAT_YCbCr_422_10b_SP = RK_FORMAT_YCbCr_422_SP_10B, 83 RK_FORMAT_YCrCb_422_10b_SP = RK_FORMAT_YCrCb_422_SP_10B, 84 85 RK_FORMAT_BGR_565 = 0x24 << 8, 86 RK_FORMAT_BGRA_5551 = 0x25 << 8, 87 RK_FORMAT_BGRA_4444 = 0x26 << 8, 88 89 RK_FORMAT_ARGB_8888 = 0x28 << 8, 90 RK_FORMAT_XRGB_8888 = 0x29 << 8, 91 RK_FORMAT_ARGB_5551 = 0x2a << 8, 92 RK_FORMAT_ARGB_4444 = 0x2b << 8, 93 RK_FORMAT_ABGR_8888 = 0x2c << 8, 94 RK_FORMAT_XBGR_8888 = 0x2d << 8, 95 RK_FORMAT_ABGR_5551 = 0x2e << 8, 96 RK_FORMAT_ABGR_4444 = 0x2f << 8, 97 98 RK_FORMAT_RGBA2BPP = 0x30 << 8, 99 100 RK_FORMAT_UNKNOWN = 0x100 << 8, 101 } RgaSURF_FORMAT; 102 103 enum { 104 yuv2rgb_mode0 = 0x0, /* BT.601 MPEG */ 105 yuv2rgb_mode1 = 0x1, /* BT.601 JPEG */ 106 yuv2rgb_mode2 = 0x2, /* BT.709 */ 107 108 rgb2yuv_601_full = 0x1 << 8, 109 rgb2yuv_709_full = 0x2 << 8, 110 yuv2yuv_601_limit_2_709_limit = 0x3 << 8, 111 yuv2yuv_601_limit_2_709_full = 0x4 << 8, 112 yuv2yuv_709_limit_2_601_limit = 0x5 << 8, 113 yuv2yuv_709_limit_2_601_full = 0x6 << 8, //not support 114 yuv2yuv_601_full_2_709_limit = 0x7 << 8, 115 yuv2yuv_601_full_2_709_full = 0x8 << 8, //not support 116 yuv2yuv_709_full_2_601_limit = 0x9 << 8, //not support 117 yuv2yuv_709_full_2_601_full = 0xa << 8, //not support 118 full_csc_mask = 0xf00, 119 }; 120 121 enum { 122 RGA3_SCHEDULER_CORE0 = 1 << 0, 123 RGA3_SCHEDULER_CORE1 = 1 << 1, 124 RGA2_SCHEDULER_CORE0 = 1 << 2, 125 }; 126 127 /* RGA3 rd_mode */ 128 enum 129 { 130 raster_mode = 0x1 << 0, 131 fbc_mode = 0x1 << 1, 132 tile_mode = 0x1 << 2, 133 }; 134 135 #ifdef __cplusplus 136 } 137 #endif 138 139 #endif /*_RK29_IPP_DRIVER_H_*/ 140