1 /* 2 * Copyright 2015 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __RK_VENC_CMD_H__ 18 #define __RK_VENC_CMD_H__ 19 20 #include "mpp_frame.h" 21 #include "rk_venc_rc.h" 22 23 /* 24 * Configure of encoder is very complicated. So we divide configures into 25 * four parts: 26 * 27 * 1. Rate control parameter 28 * This is quality and bitrate request from user. 29 * 30 * 2. Data source MppFrame parameter 31 * This is data source buffer information. 32 * Now it is PreP config 33 * PreP : Encoder Preprocess configuration 34 * 35 * 3. Video codec infomation 36 * This is user custormized stream information. 37 * including: 38 * H.264 / H.265 / vp8 / mjpeg 39 * 40 * 4. Misc parameter 41 * including: 42 * Split : Slice split configuration 43 * GopRef: Reference gop configuration 44 * ROI : Region Of Interest 45 * OSD : On Screen Display 46 * MD : Motion Detection 47 * 48 * The module transcation flow is as follows: 49 * 50 * + + 51 * User | Mpi/Mpp | EncImpl 52 * | | Hal 53 * | | 54 * +----------+ | +---------+ | +-----------+ 55 * | | | | +-----RcCfg-----> | 56 * | RcCfg +---------> | | | EncImpl | 57 * | | | | | +-Frame-----> | 58 * +----------+ | | | | | +--+-----^--+ 59 * | | | | | | | 60 * | | | | | | | 61 * +----------+ | | | | | syntax | 62 * | | | | | | | | | 63 * | MppFrame +---------> MppEnc +---+ | | result 64 * | | | | | | | | | 65 * +----------+ | | | | | | | 66 * | | | | | +--v-----+--+ 67 * | | | +-Frame-----> | 68 * +----------+ | | | | | | 69 * | | | | +---CodecCfg----> Hal | 70 * | CodecCfg +---------> | | | | 71 * | | | | <-----Extra-----> | 72 * +----------+ | +---------+ | +-----------+ 73 * | | 74 * | | 75 * + + 76 * 77 * The function call flow is shown below: 78 * 79 * mpi mpp_enc controller hal 80 * + + + + 81 * | | | | 82 * | | | | 83 * +----------init------------> | | 84 * | | | | 85 * | | | | 86 * | PrepCfg | | | 87 * +---------control----------> PrepCfg | | 88 * | +-----control-----> | 89 * | | | PrepCfg | 90 * | +--------------------------control--------> 91 * | | | allocate 92 * | | | buffer 93 * | | | | 94 * | RcCfg | | | 95 * +---------control----------> RcCfg | | 96 * | +-----control-----> | 97 * | | rc_init | 98 * | | | | 99 * | | | | 100 * | CodecCfg | | | 101 * +---------control----------> | CodecCfg | 102 * | +--------------------------control--------> 103 * | | | generate 104 * | | | sps/pps 105 * | | | Get extra info | 106 * | +--------------------------control--------> 107 * | Get extra info | | | 108 * +---------control----------> | | 109 * | | | | 110 * | | | | 111 * | ROICfg | | | 112 * +---------control----------> | ROICfg | 113 * | +--------------------------control--------> 114 * | | | | 115 * | OSDCfg | | | 116 * +---------control----------> | OSDCfg | 117 * | +--------------------------control--------> 118 * | | | | 119 * | MDCfg | | | 120 * +---------control----------> | MDCfg | 121 * | +--------------------------control--------> 122 * | | | | 123 * | Set extra info | | | 124 * +---------control----------> | Set extra info | 125 * | +--------------------------control--------> 126 * | | | | 127 * | task | | | 128 * +----------encode----------> task | | 129 * | +-----encode------> | 130 * | | encode | 131 * | | | syntax | 132 * | +--------------------------gen_reg--------> 133 * | | | | 134 * | | | | 135 * | +---------------------------start---------> 136 * | | | | 137 * | | | | 138 * | +---------------------------wait----------> 139 * | | | | 140 * | | callback | | 141 * | +-----------------> | 142 * +--OSD-MD--encode----------> | | 143 * | . | | | 144 * | . | | | 145 * | . | | | 146 * +--OSD-MD--encode----------> | | 147 * | | | | 148 * +----------deinit----------> | | 149 * + + + + 150 */ 151 152 /* 153 * encoder query interface is only for debug usage 154 */ 155 #define MPP_ENC_QUERY_STATUS (0x00000001) 156 #define MPP_ENC_QUERY_WAIT (0x00000002) 157 #define MPP_ENC_QUERY_FPS (0x00000004) 158 #define MPP_ENC_QUERY_BPS (0x00000008) 159 #define MPP_ENC_QUERY_ENC_IN_FRM (0x00000010) 160 #define MPP_ENC_QUERY_ENC_WORK (0x00000020) 161 #define MPP_ENC_QUERY_ENC_OUT_PKT (0x00000040) 162 163 #define MPP_ENC_QUERY_ALL (MPP_ENC_QUERY_STATUS | \ 164 MPP_ENC_QUERY_WAIT | \ 165 MPP_ENC_QUERY_FPS | \ 166 MPP_ENC_QUERY_BPS | \ 167 MPP_ENC_QUERY_ENC_IN_FRM | \ 168 MPP_ENC_QUERY_ENC_WORK | \ 169 MPP_ENC_QUERY_ENC_OUT_PKT) 170 171 typedef struct MppEncQueryCfg_t { 172 /* 173 * 32 bit query flag for query data check 174 * Each bit represent a query data switch. 175 * bit 0 - for querying encoder runtime status 176 * bit 1 - for querying encoder runtime waiting status 177 * bit 2 - for querying encoder realtime encode fps 178 * bit 3 - for querying encoder realtime output bps 179 * bit 4 - for querying encoder input frame count 180 * bit 5 - for querying encoder start hardware times 181 * bit 6 - for querying encoder output packet count 182 */ 183 RK_U32 query_flag; 184 185 /* 64 bit query data output */ 186 RK_U32 rt_status; 187 RK_U32 rt_wait; 188 RK_U32 rt_fps; 189 RK_U32 rt_bps; 190 RK_U32 enc_in_frm_cnt; 191 RK_U32 enc_hw_run_cnt; 192 RK_U32 enc_out_pkt_cnt; 193 } MppEncQueryCfg; 194 195 /* 196 * base working mode parameter 197 */ 198 typedef enum MppEncBaseCfgChange_e { 199 MPP_ENC_BASE_CFG_CHANGE_LOW_DELAY = (1 << 0), 200 MPP_ENC_BASE_CFG_CHANGE_ALL = (0xFFFFFFFF), 201 } MppEncBaseCfgChange; 202 203 typedef struct MppEncBaseCfg_t { 204 RK_U32 change; 205 206 RK_S32 low_delay; 207 } MppEncBaseCfg; 208 209 /* 210 * Rate control parameter 211 */ 212 typedef enum MppEncRcCfgChange_e { 213 MPP_ENC_RC_CFG_CHANGE_RC_MODE = (1 << 0), 214 MPP_ENC_RC_CFG_CHANGE_QUALITY = (1 << 1), 215 MPP_ENC_RC_CFG_CHANGE_BPS = (1 << 2), /* change on bps target / max / min */ 216 MPP_ENC_RC_CFG_CHANGE_FPS_IN = (1 << 5), /* change on fps in flex / numerator / denorminator */ 217 MPP_ENC_RC_CFG_CHANGE_FPS_OUT = (1 << 6), /* change on fps out flex / numerator / denorminator */ 218 MPP_ENC_RC_CFG_CHANGE_GOP = (1 << 7), 219 MPP_ENC_RC_CFG_CHANGE_SKIP_CNT = (1 << 8), 220 MPP_ENC_RC_CFG_CHANGE_MAX_REENC = (1 << 9), 221 MPP_ENC_RC_CFG_CHANGE_DROP_FRM = (1 << 10), 222 MPP_ENC_RC_CFG_CHANGE_MAX_I_PROP = (1 << 11), 223 MPP_ENC_RC_CFG_CHANGE_MIN_I_PROP = (1 << 12), 224 MPP_ENC_RC_CFG_CHANGE_INIT_IP_RATIO = (1 << 13), 225 MPP_ENC_RC_CFG_CHANGE_PRIORITY = (1 << 14), 226 MPP_ENC_RC_CFG_CHANGE_SUPER_FRM = (1 << 15), 227 /* qp related change flag */ 228 MPP_ENC_RC_CFG_CHANGE_QP_INIT = (1 << 16), 229 MPP_ENC_RC_CFG_CHANGE_QP_RANGE = (1 << 17), 230 MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I = (1 << 18), 231 MPP_ENC_RC_CFG_CHANGE_QP_MAX_STEP = (1 << 19), 232 MPP_ENC_RC_CFG_CHANGE_QP_IP = (1 << 20), 233 MPP_ENC_RC_CFG_CHANGE_QP_VI = (1 << 21), 234 MPP_ENC_RC_CFG_CHANGE_QP_ROW = (1 << 22), 235 MPP_ENC_RC_CFG_CHANGE_QP_ROW_I = (1 << 23), 236 MPP_ENC_RC_CFG_CHANGE_DEBREATH = (1 << 24), 237 MPP_ENC_RC_CFG_CHANGE_HIER_QP = (1 << 25), 238 MPP_ENC_RC_CFG_CHANGE_ST_TIME = (1 << 26), 239 MPP_ENC_RC_CFG_CHANGE_REFRESH = (1 << 27), 240 MPP_ENC_RC_CFG_CHANGE_GOP_REF_CFG = (1 << 28), 241 MPP_ENC_RC_CFG_CHANGE_ALL = (0xFFFFFFFF), 242 } MppEncRcCfgChange; 243 244 typedef enum MppEncRcQuality_e { 245 MPP_ENC_RC_QUALITY_WORST, 246 MPP_ENC_RC_QUALITY_WORSE, 247 MPP_ENC_RC_QUALITY_MEDIUM, 248 MPP_ENC_RC_QUALITY_BETTER, 249 MPP_ENC_RC_QUALITY_BEST, 250 MPP_ENC_RC_QUALITY_CQP, 251 MPP_ENC_RC_QUALITY_AQ_ONLY, 252 MPP_ENC_RC_QUALITY_BUTT 253 } MppEncRcQuality; 254 255 typedef struct MppEncRcCfg_t { 256 RK_U32 change; 257 258 /* 259 * rc_mode - rate control mode 260 * 261 * mpp provide two rate control mode: 262 * 263 * Constant Bit Rate (CBR) mode 264 * - paramter 'bps*' define target bps 265 * - paramter quality and qp will not take effect 266 * 267 * Variable Bit Rate (VBR) mode 268 * - paramter 'quality' define 5 quality levels 269 * - paramter 'bps*' is used as reference but not strict condition 270 * - special Constant QP (CQP) mode is under VBR mode 271 * CQP mode will work with qp in CodecCfg. But only use for test 272 * 273 * default: CBR 274 */ 275 MppEncRcMode rc_mode; 276 277 /* 278 * quality - quality parameter, only takes effect in VBR mode 279 * 280 * Mpp does not give the direct parameter in different protocol. 281 * 282 * Mpp provide total 5 quality level: 283 * Worst - worse - Medium - better - best 284 * 285 * extra CQP level means special constant-qp (CQP) mode 286 * 287 * default value: Medium 288 */ 289 MppEncRcQuality quality; 290 291 /* 292 * bit rate parameters 293 * mpp gives three bit rate control parameter for control 294 * bps_target - target bit rate, unit: bit per second 295 * bps_max - maximun bit rate, unit: bit per second 296 * bps_min - minimun bit rate, unit: bit per second 297 * if user need constant bit rate set parameters to the similar value 298 * if user need variable bit rate set parameters as they need 299 */ 300 RK_S32 bps_target; 301 RK_S32 bps_max; 302 RK_S32 bps_min; 303 304 /* 305 * frame rate parameters have great effect on rate control 306 * 307 * fps_in_flex 308 * 0 - fix input frame rate 309 * 1 - variable input frame rate 310 * 311 * fps_in_num 312 * input frame rate numerator, if 0 then default 30 313 * 314 * fps_in_denorm 315 * input frame rate denorminator, if 0 then default 1 316 * 317 * fps_out_flex 318 * 0 - fix output frame rate 319 * 1 - variable output frame rate 320 * 321 * fps_out_num 322 * output frame rate numerator, if 0 then default 30 323 * 324 * fps_out_denorm 325 * output frame rate denorminator, if 0 then default 1 326 */ 327 RK_S32 fps_in_flex; 328 RK_S32 fps_in_num; 329 RK_S32 fps_in_denorm; 330 RK_S32 fps_out_flex; 331 RK_S32 fps_out_num; 332 RK_S32 fps_out_denorm; 333 334 /* 335 * gop - group of picture, gap between Intra frame 336 * 0 for only 1 I frame the rest are all P frames 337 * 1 for all I frame 338 * 2 for I P I P I P 339 * 3 for I P P I P P 340 * etc... 341 */ 342 RK_S32 gop; 343 void *ref_cfg; 344 345 /* 346 * skip_cnt - max continuous frame skip count 347 * 0 - frame skip is not allow 348 */ 349 RK_S32 skip_cnt; 350 351 /* 352 * max_reenc_times - max reencode time for one frame 353 * 0 - reencode is not allowed 354 * 1~3 max reencode time is limited to 3 355 */ 356 RK_U32 max_reenc_times; 357 358 /* 359 * stats_time - the time of bitrate statistics 360 */ 361 RK_S32 stats_time; 362 363 /* 364 * drop frame parameters 365 * used on bitrate is far over the max bitrate 366 * 367 * drop_mode 368 * 369 * MPP_ENC_RC_DROP_FRM_DISABLED 370 * - do not drop frame when bitrate overflow. 371 * MPP_ENC_RC_DROP_FRM_NORMAL 372 * - do not encode the dropped frame when bitrate overflow. 373 * MPP_ENC_RC_DROP_FRM_PSKIP 374 * - encode a all skip frame when bitrate overflow. 375 * 376 * drop_threshold 377 * 378 * The percentage threshold over max_bitrate for trigger frame drop. 379 * 380 * drop_gap 381 * The max continuous frame drop number 382 */ 383 MppEncRcDropFrmMode drop_mode; 384 RK_U32 drop_threshold; 385 RK_U32 drop_gap; 386 387 MppEncRcSuperFrameMode super_mode; 388 RK_U32 super_i_thd; 389 RK_U32 super_p_thd; 390 391 MppEncRcPriority rc_priority; 392 393 RK_U32 debreath_en; 394 RK_U32 debre_strength; 395 RK_S32 max_i_prop; 396 RK_S32 min_i_prop; 397 RK_S32 init_ip_ratio; 398 399 /* general qp control */ 400 RK_S32 qp_init; 401 RK_S32 qp_max; 402 RK_S32 qp_max_i; 403 RK_S32 qp_min; 404 RK_S32 qp_min_i; 405 RK_S32 qp_max_step; /* delta qp between each two P frame */ 406 RK_S32 qp_delta_ip; /* delta qp between I and P */ 407 RK_S32 qp_delta_vi; /* delta qp between vi and P */ 408 409 RK_S32 hier_qp_en; 410 RK_S32 hier_qp_delta[4]; 411 RK_S32 hier_frame_num[4]; 412 413 RK_U32 refresh_en; 414 MppEncRcRefreshMode refresh_mode; 415 RK_U32 refresh_num; 416 RK_S32 refresh_length; 417 } MppEncRcCfg; 418 419 420 typedef enum MppEncHwCfgChange_e { 421 /* qp related hardware config flag */ 422 MPP_ENC_HW_CFG_CHANGE_QP_ROW = (1 << 0), 423 MPP_ENC_HW_CFG_CHANGE_QP_ROW_I = (1 << 1), 424 MPP_ENC_HW_CFG_CHANGE_AQ_THRD_I = (1 << 2), 425 MPP_ENC_HW_CFG_CHANGE_AQ_THRD_P = (1 << 3), 426 MPP_ENC_HW_CFG_CHANGE_AQ_STEP_I = (1 << 4), 427 MPP_ENC_HW_CFG_CHANGE_AQ_STEP_P = (1 << 5), 428 MPP_ENC_HW_CFG_CHANGE_MB_RC = (1 << 6), 429 MPP_ENC_HW_CFG_CHANGE_CU_MODE_BIAS = (1 << 8), 430 MPP_ENC_HW_CFG_CHANGE_CU_SKIP_BIAS = (1 << 9), 431 MPP_ENC_HW_CFG_CHANGE_ALL = (0xFFFFFFFF), 432 } MppEncHwCfgChange; 433 434 /* 435 * Hardware related rate control config 436 * 437 * This config will open some detail feature to external user to control 438 * hardware behavior directly. 439 */ 440 typedef struct MppEncHwCfg_t { 441 RK_U32 change; 442 443 /* vepu541/vepu540 */ 444 RK_S32 qp_delta_row; /* delta qp between two row in P frame */ 445 RK_S32 qp_delta_row_i; /* delta qp between two row in I frame */ 446 RK_U32 aq_thrd_i[16]; 447 RK_U32 aq_thrd_p[16]; 448 RK_S32 aq_step_i[16]; 449 RK_S32 aq_step_p[16]; 450 451 /* vepu1/2 */ 452 RK_S32 mb_rc_disable; 453 454 /* vepu580 */ 455 RK_S32 extra_buf; 456 457 /* 458 * block mode decision bias config 459 * 0 - intra32x32 460 * 1 - intra16x16 461 * 2 - intra8x8 462 * 3 - intra4x4 463 * 4 - inter64x64 464 * 5 - inter32x32 465 * 6 - inter16x16 466 * 7 - inter8x8 467 * value range 0 ~ 15, default : 8 468 * If the value is smaller then encoder will be more likely to encode corresponding block mode. 469 */ 470 RK_S32 mode_bias[8]; 471 472 /* 473 * skip mode bias config 474 * skip_bias_en - enable flag for skip bias config 475 * skip_sad - sad threshold for skip / non-skip 476 * skip_bias - tendency for skip, value range 0 ~ 15, default : 8 477 * If the value is smaller then encoder will be more likely to encode skip block. 478 */ 479 RK_S32 skip_bias_en; 480 RK_S32 skip_sad; 481 RK_S32 skip_bias; 482 } MppEncHwCfg; 483 484 /* 485 * Mpp preprocess parameter 486 */ 487 typedef enum MppEncPrepCfgChange_e { 488 MPP_ENC_PREP_CFG_CHANGE_INPUT = (1 << 0), /* change on input config */ 489 MPP_ENC_PREP_CFG_CHANGE_FORMAT = (1 << 2), /* change on format */ 490 /* transform parameter */ 491 MPP_ENC_PREP_CFG_CHANGE_ROTATION = (1 << 4), /* change on rotation */ 492 MPP_ENC_PREP_CFG_CHANGE_MIRRORING = (1 << 5), /* change on mirroring */ 493 MPP_ENC_PREP_CFG_CHANGE_FLIP = (1 << 6), /* change on flip */ 494 /* enhancement parameter */ 495 MPP_ENC_PREP_CFG_CHANGE_DENOISE = (1 << 8), /* change on denoise */ 496 MPP_ENC_PREP_CFG_CHANGE_SHARPEN = (1 << 9), /* change on denoise */ 497 /* color related parameter */ 498 MPP_ENC_PREP_CFG_CHANGE_COLOR_RANGE = (1 << 16), /* change on color range */ 499 MPP_ENC_PREP_CFG_CHANGE_COLOR_SPACE = (1 << 17), /* change on color range */ 500 MPP_ENC_PREP_CFG_CHANGE_COLOR_PRIME = (1 << 18), /* change on color primaries */ 501 MPP_ENC_PREP_CFG_CHANGE_COLOR_TRC = (1 << 19), /* change on color transfer */ 502 503 MPP_ENC_PREP_CFG_CHANGE_ALL = (0xFFFFFFFF), 504 } MppEncPrepCfgChange; 505 506 /* 507 * Preprocess sharpen parameter 508 * 509 * 5x5 sharpen core 510 * 511 * enable_y - enable luma sharpen 512 * enable_uv - enable chroma sharpen 513 */ 514 typedef struct { 515 RK_U32 enable_y; 516 RK_U32 enable_uv; 517 RK_S32 coef[5]; 518 RK_S32 div; 519 RK_S32 threshold; 520 } MppEncPrepSharpenCfg; 521 522 /* 523 * input frame rotation parameter 524 * 0 - disable rotation 525 * 1 - 90 degree 526 * 2 - 180 degree 527 * 3 - 270 degree 528 */ 529 typedef enum MppEncRotationCfg_e { 530 MPP_ENC_ROT_0, 531 MPP_ENC_ROT_90, 532 MPP_ENC_ROT_180, 533 MPP_ENC_ROT_270, 534 MPP_ENC_ROT_BUTT 535 } MppEncRotationCfg; 536 537 typedef struct MppEncPrepCfg_t { 538 RK_U32 change; 539 540 /* 541 * Mpp encoder input data dimension config 542 * 543 * width / height / hor_stride / ver_stride / format 544 * These information will be used for buffer allocation and rc config init 545 * The output format is always YUV420. So if input is RGB then color 546 * conversion will be done internally 547 */ 548 RK_S32 width; 549 RK_S32 height; 550 RK_S32 hor_stride; 551 RK_S32 ver_stride; 552 553 /* 554 * Mpp encoder input data format config 555 */ 556 MppFrameFormat format; 557 MppFrameColorSpace color; 558 MppFrameColorPrimaries colorprim; 559 MppFrameColorTransferCharacteristic colortrc; 560 MppFrameColorRange range; 561 562 /* suffix ext means the user set config externally */ 563 MppEncRotationCfg rotation; 564 MppEncRotationCfg rotation_ext; 565 566 /* 567 * input frame mirroring parameter 568 * 0 - disable mirroring 569 * 1 - horizontal mirroring 570 */ 571 RK_S32 mirroring; 572 RK_S32 mirroring_ext; 573 574 /* 575 * input frame flip parameter 576 * 0 - disable flip 577 * 1 - flip, vertical mirror transformation 578 */ 579 RK_S32 flip; 580 581 /* 582 * TODO: 583 */ 584 RK_S32 denoise; 585 586 MppEncPrepSharpenCfg sharpen; 587 } MppEncPrepCfg; 588 589 /* 590 * Mpp Motion Detection parameter 591 * 592 * Mpp can output Motion Detection infomation for each frame. 593 * If user euqueue a encode task with KEY_MOTION_INFO by following function 594 * then encoder will output Motion Detection information to the buffer. 595 * 596 * mpp_task_meta_set_buffer(task, KEY_MOTION_INFO, buffer); 597 * 598 * Motion Detection information will be organized in this way: 599 * 1. Each 16x16 block will have a 32 bit block information which contains 600 * 15 bit SAD(Sum of Abstract Difference value 601 * 9 bit signed horizontal motion vector 602 * 8 bit signed vertical motion vector 603 * 2. The sequence of MD information in the buffer is corresponding to the 604 * block position in the frame, left-to right, top-to-bottom. 605 * 3. If the width of the frame is not a multiple of 256 pixels (16 macro 606 * blocks), DMA would extend the frame to a multiple of 256 pixels and 607 * the extended blocks' MD information are 32'h0000_0000. 608 * 4. Buffer must be ion buffer and 1024 byte aligned. 609 */ 610 typedef struct MppEncMDBlkInfo_t { 611 RK_U32 sad : 15; /* bit 0~14 - SAD */ 612 RK_S32 mvx : 9; /* bit 15~23 - signed horizontal mv */ 613 RK_S32 mvy : 8; /* bit 24~31 - signed vertical mv */ 614 } MppEncMDBlkInfo; 615 616 typedef enum MppEncHeaderMode_e { 617 /* default mode: attach vps/sps/pps only on first frame */ 618 MPP_ENC_HEADER_MODE_DEFAULT, 619 /* IDR mode: attach vps/sps/pps on each IDR frame */ 620 MPP_ENC_HEADER_MODE_EACH_IDR, 621 MPP_ENC_HEADER_MODE_BUTT, 622 } MppEncHeaderMode; 623 624 typedef enum MppEncSeiMode_e { 625 MPP_ENC_SEI_MODE_DISABLE, /* default mode, SEI writing is disabled */ 626 MPP_ENC_SEI_MODE_ONE_SEQ, /* one sequence has only one SEI */ 627 MPP_ENC_SEI_MODE_ONE_FRAME /* one frame may have one SEI, if SEI info has changed */ 628 } MppEncSeiMode; 629 630 /* 631 * Mpp codec parameter 632 * parameter is defined from here 633 */ 634 635 /* 636 * H.264 configurable parameter 637 */ 638 typedef enum MppEncH264CfgChange_e { 639 /* change on stream type */ 640 MPP_ENC_H264_CFG_STREAM_TYPE = (1 << 0), 641 /* change on svc / profile / level */ 642 MPP_ENC_H264_CFG_CHANGE_PROFILE = (1 << 1), 643 /* change on entropy_coding_mode / cabac_init_idc */ 644 MPP_ENC_H264_CFG_CHANGE_ENTROPY = (1 << 2), 645 646 /* change on transform8x8_mode */ 647 MPP_ENC_H264_CFG_CHANGE_TRANS_8x8 = (1 << 4), 648 /* change on constrained_intra_pred_mode */ 649 MPP_ENC_H264_CFG_CHANGE_CONST_INTRA = (1 << 5), 650 /* change on chroma_cb_qp_offset/ chroma_cr_qp_offset */ 651 MPP_ENC_H264_CFG_CHANGE_CHROMA_QP = (1 << 6), 652 /* change on deblock_disable / deblock_offset_alpha / deblock_offset_beta */ 653 MPP_ENC_H264_CFG_CHANGE_DEBLOCKING = (1 << 7), 654 /* change on use_longterm */ 655 MPP_ENC_H264_CFG_CHANGE_LONG_TERM = (1 << 8), 656 /* change on scaling_list_mode */ 657 MPP_ENC_H264_CFG_CHANGE_SCALING_LIST = (1 << 9), 658 /* change on poc type */ 659 MPP_ENC_H264_CFG_CHANGE_POC_TYPE = (1 << 10), 660 /* change on log2 max poc lsb minus 4 */ 661 MPP_ENC_H264_CFG_CHANGE_MAX_POC_LSB = (1 << 11), 662 /* change on log2 max frame number minus 4 */ 663 MPP_ENC_H264_CFG_CHANGE_MAX_FRM_NUM = (1 << 12), 664 /* change on gaps_in_frame_num_value_allowed_flag */ 665 MPP_ENC_H264_CFG_CHANGE_GAPS_IN_FRM_NUM = (1 << 13), 666 667 /* change on max_qp / min_qp */ 668 MPP_ENC_H264_CFG_CHANGE_QP_LIMIT = (1 << 16), 669 /* change on max_qp_i / min_qp_i */ 670 MPP_ENC_H264_CFG_CHANGE_QP_LIMIT_I = (1 << 17), 671 /* change on max_qp_step */ 672 MPP_ENC_H264_CFG_CHANGE_MAX_QP_STEP = (1 << 18), 673 /* change on qp_delta_ip */ 674 MPP_ENC_H264_CFG_CHANGE_QP_DELTA = (1 << 19), 675 /* change on intra_refresh_mode / intra_refresh_arg */ 676 MPP_ENC_H264_CFG_CHANGE_INTRA_REFRESH = (1 << 20), 677 /* change on max long-term reference frame count */ 678 MPP_ENC_H264_CFG_CHANGE_MAX_LTR = (1 << 21), 679 /* change on max temporal id */ 680 MPP_ENC_H264_CFG_CHANGE_MAX_TID = (1 << 22), 681 /* change on adding prefix nal */ 682 MPP_ENC_H264_CFG_CHANGE_ADD_PREFIX = (1 << 23), 683 /* change on base layer priority id */ 684 MPP_ENC_H264_CFG_CHANGE_BASE_LAYER_PID = (1 << 24), 685 686 /* change on vui */ 687 MPP_ENC_H264_CFG_CHANGE_VUI = (1 << 28), 688 689 /* change on constraint */ 690 MPP_ENC_H264_CFG_CHANGE_CONSTRAINT_SET = (1 << 29), 691 692 MPP_ENC_H264_CFG_CHANGE_ALL = (0xFFFFFFFF), 693 } MppEncH264CfgChange; 694 695 typedef struct MppEncH264Cfg_t { 696 RK_U32 change; 697 698 /* 699 * H.264 stream format 700 * 0 - H.264 Annex B: NAL unit starts with '00 00 00 01' 701 * 1 - Plain NAL units without startcode 702 */ 703 RK_S32 stream_type; 704 705 /* 706 * H.264 codec syntax config 707 * 708 * do NOT setup the three option below unless you are familiar with encoder detail 709 * poc_type - picture order count type 0 ~ 2 710 * log2_max_poc_lsb - used in sps with poc_type 0, 711 * log2_max_frame_num - used in sps 712 */ 713 RK_U32 poc_type; 714 RK_U32 hw_poc_type; 715 RK_U32 log2_max_poc_lsb; 716 RK_U32 log2_max_frame_num; 717 RK_U32 gaps_not_allowed; 718 719 /* 720 * H.264 profile_idc parameter 721 * 66 - Baseline profile 722 * 77 - Main profile 723 * 100 - High profile 724 */ 725 RK_S32 profile; 726 727 /* 728 * H.264 level_idc parameter 729 * 10 / 11 / 12 / 13 - qcif@15fps / cif@7.5fps / cif@15fps / cif@30fps 730 * 20 / 21 / 22 - cif@30fps / half-D1@@25fps / D1@12.5fps 731 * 30 / 31 / 32 - D1@25fps / 720p@30fps / 720p@60fps 732 * 40 / 41 / 42 - 1080p@30fps / 1080p@30fps / 1080p@60fps 733 * 50 / 51 / 52 - 4K@30fps 734 */ 735 RK_S32 level; 736 737 /* 738 * H.264 entropy coding method 739 * 0 - CAVLC 740 * 1 - CABAC 741 * When CABAC is select cabac_init_idc can be range 0~2 742 */ 743 RK_S32 entropy_coding_mode; 744 RK_S32 entropy_coding_mode_ex; 745 RK_S32 cabac_init_idc; 746 RK_S32 cabac_init_idc_ex; 747 748 /* 749 * 8x8 intra prediction and 8x8 transform enable flag 750 * This flag can only be enable under High profile 751 * 0 : disable (BP/MP) 752 * 1 : enable (HP) 753 */ 754 RK_S32 transform8x8_mode; 755 RK_S32 transform8x8_mode_ex; 756 757 /* 758 * 0 : disable 759 * 1 : enable 760 */ 761 RK_S32 constrained_intra_pred_mode; 762 763 /* 764 * 0 : flat scaling list 765 * 1 : default scaling list for all cases 766 * 2 : customized scaling list (not supported) 767 */ 768 RK_S32 scaling_list_mode; 769 770 /* 771 * chroma qp offset (-12 - 12) 772 */ 773 RK_S32 chroma_cb_qp_offset; 774 RK_S32 chroma_cr_qp_offset; 775 776 /* 777 * H.264 deblock filter mode flag 778 * 0 : enable 779 * 1 : disable 780 * 2 : disable deblocking filter at slice boundaries 781 * 782 * deblock filter offset alpha (-6 - 6) 783 * deblock filter offset beta (-6 - 6) 784 */ 785 RK_S32 deblock_disable; 786 RK_S32 deblock_offset_alpha; 787 RK_S32 deblock_offset_beta; 788 789 /* 790 * H.264 long term reference picture enable flag 791 * 0 - disable 792 * 1 - enable 793 */ 794 RK_S32 use_longterm; 795 796 /* 797 * quality config 798 * qp_max - 8 ~ 51 799 * qp_max_i - 10 ~ 40 800 * qp_min - 8 ~ 48 801 * qp_min_i - 10 ~ 40 802 * qp_max_step - max delta qp step between two frames 803 */ 804 RK_S32 qp_init; 805 RK_S16 qp_max; 806 RK_S16 qp_max_i; 807 RK_S16 qp_min; 808 RK_S16 qp_min_i; 809 RK_S16 qp_max_step; 810 RK_S16 qp_delta_ip; 811 812 /* 813 * intra fresh config 814 * 815 * intra_refresh_mode 816 * 0 - no intra refresh 817 * 1 - intra refresh by MB row 818 * 2 - intra refresh by MB column 819 * 3 - intra refresh by MB gap 820 * 821 * intra_refresh_arg 822 * mode 0 - no effect 823 * mode 1 - refresh MB row number 824 * mode 2 - refresh MB colmn number 825 * mode 3 - refresh MB gap count 826 */ 827 RK_S32 intra_refresh_mode; 828 RK_S32 intra_refresh_arg; 829 830 /* extra mode config */ 831 RK_S32 max_ltr_frames; 832 RK_S32 max_tid; 833 RK_S32 prefix_mode; 834 RK_S32 base_layer_pid; 835 /* 836 * Mpp encoder constraint_set parameter 837 * Mpp encoder constraint_set controls constraint_setx_flag in AVC. 838 * Mpp encoder constraint_set uses type RK_U32 to store force_flag and constraint_force as followed. 839 * | 00 | force_flag | 00 | constraint_force | 840 * As for force_flag and constraint_force, only low 6 bits are valid, 841 * corresponding to constraint_setx_flag from 5 to 0. 842 * If force_flag bit is enabled, constraint_setx_flag will be set correspondingly. 843 * Otherwise, constraint_setx_flag will use default value. 844 */ 845 RK_U32 constraint_set; 846 } MppEncH264Cfg; 847 848 #define H265E_MAX_ROI_NUMBER 64 849 850 typedef struct H265eRect_t { 851 RK_S32 left; 852 RK_S32 right; 853 RK_S32 top; 854 RK_S32 bottom; 855 } H265eRect; 856 857 typedef struct H265eRoi_Region_t { 858 RK_U8 level; 859 H265eRect rect; 860 } H265eRoiRegion; 861 862 /* 863 * roi region only can be setting when rc_enable = 1 864 */ 865 typedef struct MppEncH265RoiCfg_t { 866 /* 867 * the value is defined by H265eCtuMethod 868 */ 869 870 RK_U8 method; 871 /* 872 * the number of roi,the value must less than H265E_MAX_ROI_NUMBER 873 */ 874 RK_S32 num; 875 876 /* delat qp using in roi region*/ 877 RK_U32 delta_qp; 878 879 /* roi region */ 880 H265eRoiRegion region[H265E_MAX_ROI_NUMBER]; 881 } MppEncH265RoiCfg; 882 883 typedef struct H265eCtuQp_t { 884 /* the qp value using in ctu region */ 885 RK_U32 qp; 886 887 /* 888 * define the ctu region 889 * method = H265E_METHOD_CUT_SIZE, the value of rect is in ctu size 890 * method = H264E_METHOD_COORDINATE,the value of rect is in coordinates 891 */ 892 H265eRect rect; 893 } H265eCtu; 894 895 typedef struct H265eCtuRegion_t { 896 /* 897 * the value is defined by H265eCtuMethod 898 */ 899 RK_U8 method; 900 901 /* 902 * the number of ctu,the value must less than H265E_MAX_ROI_NUMBER 903 */ 904 RK_S32 num; 905 906 /* ctu region */ 907 H265eCtu ctu[H265E_MAX_ROI_NUMBER]; 908 } MppEncH265CtuCfg; 909 910 /* 911 * define the method when set CTU/ROI parameters 912 * this value is using by method in H265eCtuRegion or H265eRoi struct 913 */ 914 typedef enum { 915 H265E_METHOD_CTU_SIZE, 916 H264E_METHOD_COORDINATE, 917 } H265eCtuMethod; 918 919 /* 920 * H.265 configurable parameter 921 */ 922 typedef struct MppEncH265VuiCfg_t { 923 RK_U32 change; 924 RK_S32 vui_present; 925 RK_S32 vui_aspect_ratio; 926 RK_S32 vui_sar_size; 927 RK_S32 full_range; 928 RK_S32 time_scale; 929 } MppEncH265VuiCfg; 930 931 typedef enum MppEncH265CfgChange_e { 932 /* change on stream type */ 933 MPP_ENC_H265_CFG_PROFILE_LEVEL_TILER_CHANGE = (1 << 0), 934 MPP_ENC_H265_CFG_INTRA_QP_CHANGE = (1 << 1), 935 MPP_ENC_H265_CFG_FRAME_RATE_CHANGE = (1 << 2), 936 MPP_ENC_H265_CFG_BITRATE_CHANGE = (1 << 3), 937 MPP_ENC_H265_CFG_GOP_SIZE = (1 << 4), 938 MPP_ENC_H265_CFG_RC_QP_CHANGE = (1 << 5), 939 MPP_ENC_H265_CFG_INTRA_REFRESH_CHANGE = (1 << 6), 940 MPP_ENC_H265_CFG_INDEPEND_SLICE_CHANGE = (1 << 7), 941 MPP_ENC_H265_CFG_DEPEND_SLICE_CHANGE = (1 << 8), 942 MPP_ENC_H265_CFG_CTU_CHANGE = (1 << 9), 943 MPP_ENC_H265_CFG_ROI_CHANGE = (1 << 10), 944 MPP_ENC_H265_CFG_CU_CHANGE = (1 << 11), 945 MPP_ENC_H265_CFG_DBLK_CHANGE = (1 << 12), 946 MPP_ENC_H265_CFG_SAO_CHANGE = (1 << 13), 947 MPP_ENC_H265_CFG_TRANS_CHANGE = (1 << 14), 948 MPP_ENC_H265_CFG_SLICE_CHANGE = (1 << 15), 949 MPP_ENC_H265_CFG_ENTROPY_CHANGE = (1 << 16), 950 MPP_ENC_H265_CFG_MERGE_CHANGE = (1 << 17), 951 MPP_ENC_H265_CFG_CHANGE_VUI = (1 << 18), 952 MPP_ENC_H265_CFG_RC_I_QP_CHANGE = (1 << 19), 953 MPP_ENC_H265_CFG_RC_MAX_QP_STEP_CHANGE = (1 << 21), 954 MPP_ENC_H265_CFG_RC_IP_DELTA_QP_CHANGE = (1 << 20), 955 MPP_ENC_H265_CFG_TILE_CHANGE = (1 << 22), 956 MPP_ENC_H265_CFG_SLICE_LPFACS_CHANGE = (1 << 23), 957 MPP_ENC_H265_CFG_TILE_LPFACS_CHANGE = (1 << 24), 958 MPP_ENC_H265_CFG_CHANGE_ALL = (0xFFFFFFFF), 959 } MppEncH265CfgChange; 960 961 typedef struct MppEncH265SliceCfg_t { 962 /* default value: 0, means no slice split*/ 963 RK_U32 split_enable; 964 965 /* 0: by bits number; 1: by lcu line number*/ 966 RK_U32 split_mode; 967 968 /* 969 * when splitmode is 0, this value presents bits number, 970 * when splitmode is 1, this value presents lcu line number 971 */ 972 RK_U32 slice_size; 973 RK_U32 slice_out; 974 } MppEncH265SliceCfg; 975 976 typedef struct MppEncH265CuCfg_t { 977 RK_U32 cu32x32_en; /*default: 1 */ 978 RK_U32 cu16x16_en; /*default: 1 */ 979 RK_U32 cu8x8_en; /*default: 1 */ 980 RK_U32 cu4x4_en; /*default: 1 */ 981 982 // intra pred 983 RK_U32 constrained_intra_pred_flag; /*default: 0 */ 984 RK_U32 strong_intra_smoothing_enabled_flag; /*INTRA_SMOOTH*/ 985 RK_U32 pcm_enabled_flag; /*default: 0, enable ipcm*/ 986 RK_U32 pcm_loop_filter_disabled_flag; 987 988 } MppEncH265CuCfg; 989 990 typedef struct MppEncH265RefCfg_t { 991 RK_U32 num_lt_ref_pic; /*default: 0*/ 992 } MppEncH265RefCfg; 993 994 995 typedef struct MppEncH265DblkCfg_t { 996 RK_U32 slice_deblocking_filter_disabled_flag; /* default value: 0. {0,1} */ 997 RK_S32 slice_beta_offset_div2; /* default value: 0. [-6,+6] */ 998 RK_S32 slice_tc_offset_div2; /* default value: 0. [-6,+6] */ 999 } MppEncH265DblkCfg_t; 1000 1001 typedef struct MppEncH265SaoCfg_t { 1002 RK_U32 slice_sao_luma_disable; 1003 RK_U32 slice_sao_chroma_disable; 1004 } MppEncH265SaoCfg; 1005 1006 typedef struct MppEncH265TransCfg_t { 1007 RK_U32 transquant_bypass_enabled_flag; 1008 RK_U32 transform_skip_enabled_flag; 1009 RK_U32 defalut_ScalingList_enable; /* default: 0 */ 1010 RK_S32 cb_qp_offset; 1011 RK_S32 cr_qp_offset; 1012 } MppEncH265TransCfg; 1013 1014 typedef struct MppEncH265MergeCfg_t { 1015 RK_U32 max_mrg_cnd; 1016 RK_U32 merge_up_flag; 1017 RK_U32 merge_left_flag; 1018 } MppEncH265MergesCfg; 1019 1020 typedef struct MppEncH265EntropyCfg_t { 1021 RK_U32 cabac_init_flag; /* default: 0 */ 1022 } MppEncH265EntropyCfg; 1023 1024 typedef struct MppEncH265Cfg_t { 1025 RK_U32 change; 1026 1027 /* H.265 codec syntax config */ 1028 RK_S32 profile; 1029 RK_S32 level; 1030 RK_S32 tier; 1031 1032 /* constraint intra prediction flag */ 1033 RK_S32 const_intra_pred; 1034 RK_S32 ctu_size; 1035 RK_S32 max_cu_size; 1036 RK_S32 tmvp_enable; 1037 RK_S32 amp_enable; 1038 RK_S32 wpp_enable; 1039 RK_S32 merge_range; 1040 RK_S32 sao_enable; 1041 RK_U32 num_ref; 1042 1043 /* quality config */ 1044 RK_S32 max_qp; 1045 RK_S32 min_qp; 1046 RK_S32 max_i_qp; 1047 RK_S32 min_i_qp; 1048 RK_S32 ip_qp_delta; 1049 RK_S32 max_delta_qp; 1050 RK_S32 intra_qp; 1051 RK_S32 gop_delta_qp; 1052 RK_S32 qp_init; 1053 RK_S32 qp_max_step; 1054 RK_S32 raw_dealt_qp; 1055 RK_U8 qpmax_map[8]; 1056 RK_U8 qpmin_map[8]; 1057 RK_S32 qpmap_mode; 1058 1059 /* intra fresh config */ 1060 RK_S32 intra_refresh_mode; 1061 RK_S32 intra_refresh_arg; 1062 1063 /* slice mode config */ 1064 RK_S32 independ_slice_mode; 1065 RK_S32 independ_slice_arg; 1066 RK_S32 depend_slice_mode; 1067 RK_S32 depend_slice_arg; 1068 1069 MppEncH265CuCfg cu_cfg; 1070 MppEncH265SliceCfg slice_cfg; 1071 MppEncH265EntropyCfg entropy_cfg; 1072 MppEncH265TransCfg trans_cfg; 1073 MppEncH265SaoCfg sao_cfg; 1074 MppEncH265DblkCfg_t dblk_cfg; 1075 MppEncH265RefCfg ref_cfg; 1076 MppEncH265MergesCfg merge_cfg; 1077 RK_S32 auto_tile; 1078 RK_U32 lpf_acs_sli_en; 1079 RK_U32 lpf_acs_tile_disable; 1080 1081 /* extra info */ 1082 MppEncH265VuiCfg vui; 1083 1084 MppEncH265CtuCfg ctu; 1085 MppEncH265RoiCfg roi; 1086 } MppEncH265Cfg; 1087 1088 /* 1089 * motion jpeg configurable parameter 1090 */ 1091 typedef enum MppEncJpegCfgChange_e { 1092 /* change on quant parameter */ 1093 MPP_ENC_JPEG_CFG_CHANGE_QP = (1 << 0), 1094 MPP_ENC_JPEG_CFG_CHANGE_QTABLE = (1 << 1), 1095 MPP_ENC_JPEG_CFG_CHANGE_QFACTOR = (1 << 2), 1096 MPP_ENC_JPEG_CFG_CHANGE_ALL = (0xFFFFFFFF), 1097 } MppEncJpegCfgChange; 1098 1099 typedef struct MppEncJpegCfg_t { 1100 RK_U32 change; 1101 RK_S32 quant; 1102 /* 1103 * quality factor config 1104 * 1105 * q_factor - 1 ~ 99 1106 * qf_max - 1 ~ 99 1107 * qf_min - 1 ~ 99 1108 * qtable_y: qtable for luma 1109 * qtable_u: qtable for chroma 1110 * qtable_v: default equal qtable_u 1111 */ 1112 RK_S32 q_factor; 1113 RK_S32 qf_max; 1114 RK_S32 qf_min; 1115 RK_U8 *qtable_y; 1116 RK_U8 *qtable_u; 1117 RK_U8 *qtable_v; 1118 } MppEncJpegCfg; 1119 1120 /* 1121 * vp8 configurable parameter 1122 */ 1123 typedef enum MppEncVP8CfgChange_e { 1124 MPP_ENC_VP8_CFG_CHANGE_QP = (1 << 0), 1125 MPP_ENC_VP8_CFG_CHANGE_DIS_IVF = (1 << 1), 1126 MPP_ENC_VP8_CFG_CHANGE_ALL = (0xFFFFFFFF), 1127 } MppEncVP8CfgChange; 1128 1129 typedef struct MppEncVp8Cfg_t { 1130 RK_U32 change; 1131 RK_S32 quant; 1132 1133 RK_S32 qp_init; 1134 RK_S32 qp_max; 1135 RK_S32 qp_max_i; 1136 RK_S32 qp_min; 1137 RK_S32 qp_min_i; 1138 RK_S32 qp_max_step; 1139 RK_S32 disable_ivf; 1140 } MppEncVp8Cfg; 1141 1142 /** 1143 * @ingroup rk_mpi 1144 * @brief MPP encoder codec configuration parameters 1145 * @details The encoder codec configuration parameters are different for each 1146 * compression codings. For example, H.264 encoder can configure 1147 * profile, level, qp, etc. while jpeg encoder can configure qp 1148 * only. The detailed parameters can refer the corresponding data 1149 * structure such as MppEncH264Cfg and MppEncJpegCfg. This data 1150 * structure is associated with MPP_ENC_SET_CODEC_CFG command. 1151 */ 1152 typedef struct MppEncCodecCfg_t { 1153 MppCodingType coding; 1154 1155 union { 1156 RK_U32 change; 1157 MppEncH264Cfg h264; 1158 MppEncH265Cfg h265; 1159 MppEncJpegCfg jpeg; 1160 MppEncVp8Cfg vp8; 1161 }; 1162 } MppEncCodecCfg; 1163 1164 typedef enum MppEncSliceSplit_e { 1165 /* change on quant parameter */ 1166 MPP_ENC_SPLIT_CFG_CHANGE_MODE = (1 << 0), 1167 MPP_ENC_SPLIT_CFG_CHANGE_ARG = (1 << 1), 1168 MPP_ENC_SPLIT_CFG_CHANGE_OUTPUT = (1 << 2), 1169 MPP_ENC_SPLIT_CFG_CHANGE_ALL = (0xFFFFFFFF), 1170 } MppEncSliceSplitChange; 1171 1172 typedef enum MppEncSplitMode_e { 1173 MPP_ENC_SPLIT_NONE, 1174 MPP_ENC_SPLIT_BY_BYTE, 1175 MPP_ENC_SPLIT_BY_CTU, 1176 } MppEncSplitMode; 1177 1178 typedef enum MppEncSplitOutMode_e { 1179 MPP_ENC_SPLIT_OUT_LOWDELAY = (1 << 0), 1180 MPP_ENC_SPLIT_OUT_SEGMENT = (1 << 1), 1181 } MppEncSplitOutMode; 1182 1183 typedef struct MppEncSliceSplit_t { 1184 RK_U32 change; 1185 1186 /* 1187 * slice split mode 1188 * 1189 * MPP_ENC_SPLIT_NONE - No slice is split 1190 * MPP_ENC_SPLIT_BY_BYTE - Slice is split by byte number 1191 * MPP_ENC_SPLIT_BY_CTU - Slice is split by macroblock / ctu number 1192 */ 1193 RK_U32 split_mode; 1194 1195 /* 1196 * slice split size parameter 1197 * 1198 * When split by byte number this value is the max byte number for each 1199 * slice. 1200 * When split by macroblock / ctu number this value is the MB/CTU number 1201 * for each slice. 1202 */ 1203 RK_U32 split_arg; 1204 1205 /* 1206 * slice split output mode 1207 * 1208 * MPP_ENC_SPLIT_OUT_LOWDELAY 1209 * - When enabled encoder will lowdelay output each slice in a single packet 1210 * MPP_ENC_SPLIT_OUT_SEGMENT 1211 * - When enabled encoder will packet with segment info for each slice 1212 */ 1213 RK_U32 split_out; 1214 } MppEncSliceSplit; 1215 1216 /** 1217 * @brief Mpp ROI parameter 1218 * Region configure define a rectangle as ROI 1219 * @note x, y, w, h are calculated in pixels, which had better be 16-pixel aligned. 1220 * These parameters MUST retain in memory when encoder is running. 1221 * Both absolute qp and relative qp are supported in vepu541. 1222 * Only absolute qp is supported in rv1108 1223 */ 1224 typedef struct MppEncROIRegion_t { 1225 RK_U16 x; /**< horizontal position of top left corner */ 1226 RK_U16 y; /**< vertical position of top left corner */ 1227 RK_U16 w; /**< width of ROI rectangle */ 1228 RK_U16 h; /**< height of ROI rectangle */ 1229 RK_U16 intra; /**< flag of forced intra macroblock */ 1230 RK_S16 quality; /**< absolute / relative qp of macroblock */ 1231 RK_U16 qp_area_idx; /**< qp min max area select*/ 1232 RK_U8 area_map_en; /**< enable area map */ 1233 RK_U8 abs_qp_en; /**< absolute qp enable flag*/ 1234 } MppEncROIRegion; 1235 1236 /** 1237 * @brief MPP encoder's ROI configuration 1238 */ 1239 typedef struct MppEncROICfg_t { 1240 RK_U32 number; /**< ROI rectangle number */ 1241 MppEncROIRegion *regions; /**< ROI parameters */ 1242 } MppEncROICfg; 1243 1244 /** 1245 * @brief Mpp ROI parameter for vepu54x / vepu58x 1246 * @note These encoders have more complex roi configure structure. 1247 * User need to generate roi structure data for different soc. 1248 * And send buffers to encoder through metadata. 1249 */ 1250 typedef struct MppEncROICfg2_t { 1251 MppBuffer base_cfg_buf; 1252 MppBuffer qp_cfg_buf; 1253 MppBuffer amv_cfg_buf; 1254 MppBuffer mv_cfg_buf; 1255 1256 RK_U32 roi_qp_en : 1; 1257 RK_U32 roi_amv_en : 1; 1258 RK_U32 roi_mv_en : 1; 1259 RK_U32 reserve_bits : 29; 1260 RK_U32 reserve[3]; 1261 } MppEncROICfg2; 1262 1263 /* 1264 * Mpp OSD parameter 1265 * 1266 * Mpp OSD support total 8 regions 1267 * Mpp OSD support 256-color palette two mode palette: 1268 * 1. Configurable OSD palette 1269 * When palette is set. 1270 * 2. fixed OSD palette 1271 * When palette is NULL. 1272 * 1273 * if MppEncOSDPlt.buf != NULL , palette includes maximun 256 levels, 1274 * every level composed of 32 bits defined below: 1275 * Y : 8 bits 1276 * U : 8 bits 1277 * V : 8 bits 1278 * alpha : 8 bits 1279 */ 1280 #define MPP_ENC_OSD_PLT_WHITE ((255<<24)|(128<<16)|(128<<8)|235) 1281 #define MPP_ENC_OSD_PLT_YELLOW ((255<<24)|(146<<16)|( 16<<8)|210) 1282 #define MPP_ENC_OSD_PLT_CYAN ((255<<24)|( 16<<16)|(166<<8)|170) 1283 #define MPP_ENC_OSD_PLT_GREEN ((255<<24)|( 34<<16)|( 54<<8)|145) 1284 #define MPP_ENC_OSD_PLT_TRANS (( 0<<24)|(222<<16)|(202<<8)|106) 1285 #define MPP_ENC_OSD_PLT_RED ((255<<24)|(240<<16)|( 90<<8)| 81) 1286 #define MPP_ENC_OSD_PLT_BLUE ((255<<24)|(110<<16)|(240<<8)| 41) 1287 #define MPP_ENC_OSD_PLT_BLACK ((255<<24)|(128<<16)|(128<<8)| 16) 1288 1289 typedef enum MppEncOSDPltType_e { 1290 MPP_ENC_OSD_PLT_TYPE_DEFAULT, 1291 MPP_ENC_OSD_PLT_TYPE_USERDEF, 1292 MPP_ENC_OSD_PLT_TYPE_BUTT, 1293 } MppEncOSDPltType; 1294 1295 /* OSD palette value define */ 1296 typedef union MppEncOSDPltVal_u { 1297 struct { 1298 RK_U32 v : 8; 1299 RK_U32 u : 8; 1300 RK_U32 y : 8; 1301 RK_U32 alpha : 8; 1302 }; 1303 RK_U32 val; 1304 } MppEncOSDPltVal; 1305 1306 typedef struct MppEncOSDPlt_t { 1307 MppEncOSDPltVal data[256]; 1308 } MppEncOSDPlt; 1309 1310 typedef enum MppEncOSDPltCfgChange_e { 1311 MPP_ENC_OSD_PLT_CFG_CHANGE_MODE = (1 << 0), /* change osd plt type */ 1312 MPP_ENC_OSD_PLT_CFG_CHANGE_PLT_VAL = (1 << 1), /* change osd plt table value */ 1313 MPP_ENC_OSD_PLT_CFG_CHANGE_ALL = (0xFFFFFFFF), 1314 } MppEncOSDPltCfgChange; 1315 1316 typedef struct MppEncOSDPltCfg_t { 1317 RK_U32 change; 1318 MppEncOSDPltType type; 1319 MppEncOSDPlt *plt; 1320 } MppEncOSDPltCfg; 1321 1322 /* position info is unit in 16 pixels(one MB), and 1323 * x-directon range in pixels = (rd_pos_x - lt_pos_x + 1) * 16; 1324 * y-directon range in pixels = (rd_pos_y - lt_pos_y + 1) * 16; 1325 */ 1326 typedef struct MppEncOSDRegion_t { 1327 RK_U32 enable; 1328 RK_U32 inverse; 1329 RK_U32 start_mb_x; 1330 RK_U32 start_mb_y; 1331 RK_U32 num_mb_x; 1332 RK_U32 num_mb_y; 1333 RK_U32 buf_offset; 1334 } MppEncOSDRegion; 1335 1336 /* if num_region > 0 && region==NULL 1337 * use old osd data 1338 */ 1339 typedef struct MppEncOSDData_t { 1340 MppBuffer buf; 1341 RK_U32 num_region; 1342 MppEncOSDRegion region[8]; 1343 } MppEncOSDData; 1344 1345 typedef struct MppEncOSDRegion2_t { 1346 RK_U32 enable; 1347 RK_U32 inverse; 1348 RK_U32 start_mb_x; 1349 RK_U32 start_mb_y; 1350 RK_U32 num_mb_x; 1351 RK_U32 num_mb_y; 1352 RK_U32 buf_offset; 1353 MppBuffer buf; 1354 } MppEncOSDRegion2; 1355 1356 typedef struct MppEncOSDData2_t { 1357 RK_U32 num_region; 1358 MppEncOSDRegion2 region[8]; 1359 } MppEncOSDData2; 1360 1361 typedef struct MppEncUserData_t { 1362 RK_U32 len; 1363 void *pdata; 1364 } MppEncUserData; 1365 1366 typedef struct MppEncUserDataFull_t { 1367 RK_U32 len; 1368 RK_U8 *uuid; 1369 void *pdata; 1370 } MppEncUserDataFull; 1371 1372 typedef struct MppEncUserDataSet_t { 1373 RK_U32 count; 1374 MppEncUserDataFull *datas; 1375 } MppEncUserDataSet; 1376 1377 typedef enum MppEncSceneMode_e { 1378 MPP_ENC_SCENE_MODE_DEFAULT, 1379 MPP_ENC_SCENE_MODE_IPC, 1380 MPP_ENC_SCENE_MODE_BUTT, 1381 } MppEncSceneMode; 1382 1383 typedef enum MppEncFineTuneCfgChange_e { 1384 /* change on scene mode */ 1385 MPP_ENC_TUNE_CFG_CHANGE_SCENE_MODE = (1 << 0), 1386 } MppEncFineTuneCfgChange; 1387 1388 typedef struct MppEncFineTuneCfg_t { 1389 RK_U32 change; 1390 1391 MppEncSceneMode scene_mode; 1392 } MppEncFineTuneCfg; 1393 1394 #endif /*__RK_VENC_CMD_H__*/ 1395