1 /*
2 * Copyright 2022 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_h265e_v540c"
18
19 #include <linux/string.h>
20
21 #include <string.h>
22 #include <math.h>
23 #include <limits.h>
24
25 #include "mpp_env.h"
26 #include "mpp_mem.h"
27 #include "mpp_soc.h"
28 #include "mpp_common.h"
29 #include "mpp_frame_impl.h"
30
31 #include "hal_h265e_debug.h"
32 #include "h265e_syntax_new.h"
33 #include "hal_bufs.h"
34 #include "rkv_enc_def.h"
35 #include "vepu541_common.h"
36 #include "vepu540c_common.h"
37 #include "hal_h265e_vepu540c.h"
38 #include "hal_h265e_vepu540c_reg.h"
39
40 #define MAX_TITLE_NUM 2
41
42 #define hal_h265e_err(fmt, ...) \
43 do {\
44 mpp_err_f(fmt, ## __VA_ARGS__);\
45 } while (0)
46
47 typedef struct vepu540c_h265_fbk_t {
48 RK_U32 hw_status; /* 0:corret, 1:error */
49 RK_U32 qp_sum;
50 RK_U32 out_strm_size;
51 RK_U32 out_hw_strm_size;
52 RK_S64 sse_sum;
53 RK_U32 st_lvl64_inter_num;
54 RK_U32 st_lvl32_inter_num;
55 RK_U32 st_lvl16_inter_num;
56 RK_U32 st_lvl8_inter_num;
57 RK_U32 st_lvl32_intra_num;
58 RK_U32 st_lvl16_intra_num;
59 RK_U32 st_lvl8_intra_num;
60 RK_U32 st_lvl4_intra_num;
61 RK_U32 st_cu_num_qp[52];
62 RK_U32 st_madp;
63 RK_U32 st_madi;
64 RK_U32 st_mb_num;
65 RK_U32 st_ctu_num;
66 } vepu540c_h265_fbk;
67
68 typedef struct H265eV540cHalContext_t {
69 MppEncHalApi api;
70 MppDev dev;
71 void *regs;
72 void *reg_out[MAX_TITLE_NUM];
73
74 vepu540c_h265_fbk feedback;
75 void *dump_files;
76 RK_U32 frame_cnt_gen_ready;
77
78 RK_S32 frame_type;
79 RK_S32 last_frame_type;
80
81 /* @frame_cnt starts from ZERO */
82 RK_U32 frame_cnt;
83 void *roi_data;
84 MppEncCfgSet *cfg;
85
86 RK_U32 enc_mode;
87 RK_U32 frame_size;
88 RK_S32 max_buf_cnt;
89 RK_S32 hdr_status;
90 void *input_fmt;
91 RK_U8 *src_buf;
92 RK_U8 *dst_buf;
93 RK_S32 buf_size;
94 RK_U32 frame_num;
95 HalBufs dpb_bufs;
96 RK_S32 fbc_header_len;
97 RK_U32 title_num;
98
99 /* external line buffer over 3K */
100 MppBufferGroup ext_line_buf_grp;
101 RK_S32 ext_line_buf_size;
102 MppBuffer ext_line_buf;
103 } H265eV540cHalContext;
104
105 #define TILE_BUF_SIZE MPP_ALIGN(128 * 1024, 256)
106
107 static RK_U32 aq_thd_default[16] = {
108 0, 0, 0, 0,
109 3, 3, 5, 5,
110 8, 8, 8, 15,
111 15, 20, 25, 25
112 };
113
114 static RK_S32 aq_qp_dealt_default[16] = {
115 -8, -7, -6, -5,
116 -4, -3, -2, -1,
117 0, 1, 2, 3,
118 4, 5, 6, 8,
119 };
120
121 static RK_U32 lamd_moda_qp[52] = {
122 0x00000049, 0x0000005c, 0x00000074, 0x00000092, 0x000000b8, 0x000000e8, 0x00000124, 0x00000170,
123 0x000001cf, 0x00000248, 0x000002df, 0x0000039f, 0x0000048f, 0x000005bf, 0x0000073d, 0x0000091f,
124 0x00000b7e, 0x00000e7a, 0x0000123d, 0x000016fb, 0x00001cf4, 0x0000247b, 0x00002df6, 0x000039e9,
125 0x000048f6, 0x00005bed, 0x000073d1, 0x000091ec, 0x0000b7d9, 0x0000e7a2, 0x000123d7, 0x00016fb2,
126 0x0001cf44, 0x000247ae, 0x0002df64, 0x00039e89, 0x00048f5c, 0x0005bec8, 0x00073d12, 0x00091eb8,
127 0x000b7d90, 0x000e7a23, 0x00123d71, 0x0016fb20, 0x001cf446, 0x00247ae1, 0x002df640, 0x0039e88c,
128 0x0048f5c3, 0x005bec81, 0x0073d119, 0x0091eb85
129 };
130
131 static RK_U32 lamd_modb_qp[52] = {
132 0x00000070, 0x00000089, 0x000000b0, 0x000000e0, 0x00000112, 0x00000160, 0x000001c0, 0x00000224,
133 0x000002c0, 0x00000380, 0x00000448, 0x00000580, 0x00000700, 0x00000890, 0x00000b00, 0x00000e00,
134 0x00001120, 0x00001600, 0x00001c00, 0x00002240, 0x00002c00, 0x00003800, 0x00004480, 0x00005800,
135 0x00007000, 0x00008900, 0x0000b000, 0x0000e000, 0x00011200, 0x00016000, 0x0001c000, 0x00022400,
136 0x0002c000, 0x00038000, 0x00044800, 0x00058000, 0x00070000, 0x00089000, 0x000b0000, 0x000e0000,
137 0x00112000, 0x00160000, 0x001c0000, 0x00224000, 0x002c0000, 0x00380000, 0x00448000, 0x00580000,
138 0x00700000, 0x00890000, 0x00b00000, 0x00e00000
139 };
140
vepu540c_h265_setup_hal_bufs(H265eV540cHalContext * ctx)141 static MPP_RET vepu540c_h265_setup_hal_bufs(H265eV540cHalContext *ctx)
142 {
143 MPP_RET ret = MPP_OK;
144 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
145 RK_U32 frame_size;
146 Vepu541Fmt input_fmt = VEPU541_FMT_YUV420P;
147 RK_S32 mb_wd64, mb_h64;
148 MppEncRefCfg ref_cfg = ctx->cfg->ref_cfg;
149 MppEncPrepCfg *prep = &ctx->cfg->prep;
150 RK_S32 old_max_cnt = ctx->max_buf_cnt;
151 RK_S32 new_max_cnt = 2;
152 RK_S32 alignment = 32;
153 RK_S32 aligned_w = MPP_ALIGN(prep->width, alignment);
154
155 hal_h265e_enter();
156
157 mb_wd64 = (prep->width + 63) / 64;
158 mb_h64 = (prep->height + 63) / 64;
159
160 frame_size = MPP_ALIGN(prep->width, 16) * MPP_ALIGN(prep->height, 16);
161 vepu541_set_fmt(fmt, ctx->cfg->prep.format);
162 input_fmt = (Vepu541Fmt)fmt->format;
163 switch (input_fmt) {
164 case VEPU541_FMT_YUV420P:
165 case VEPU541_FMT_YUV420SP: {
166 frame_size = frame_size * 3 / 2;
167 } break;
168 case VEPU541_FMT_YUV422P:
169 case VEPU541_FMT_YUV422SP:
170 case VEPU541_FMT_YUYV422:
171 case VEPU541_FMT_UYVY422:
172 case VEPU541_FMT_BGR565: {
173 frame_size *= 2;
174 } break;
175 case VEPU541_FMT_BGR888: {
176 frame_size *= 3;
177 } break;
178 case VEPU541_FMT_BGRA8888: {
179 frame_size *= 4;
180 } break;
181 default: {
182 hal_h265e_err("invalid src color space: %d\n", input_fmt);
183 return MPP_NOK;
184 }
185 }
186
187 if (ref_cfg) {
188 MppEncCpbInfo *info = mpp_enc_ref_cfg_get_cpb_info(ref_cfg);
189 new_max_cnt = MPP_MAX(new_max_cnt, info->dpb_size + 1);
190 }
191
192 if (aligned_w > (3 * SZ_1K)) {
193 RK_S32 ext_line_buf_size = (aligned_w / 32 - 91) * 26 * 16;
194
195 if (NULL == ctx->ext_line_buf_grp)
196 mpp_buffer_group_get_internal(&ctx->ext_line_buf_grp, MPP_BUFFER_TYPE_ION);
197 else if (ext_line_buf_size != ctx->ext_line_buf_size) {
198 mpp_buffer_put(ctx->ext_line_buf);
199 ctx->ext_line_buf = NULL;
200 mpp_buffer_group_clear(ctx->ext_line_buf_grp);
201 }
202
203 mpp_assert(ctx->ext_line_buf_grp);
204
205 if (NULL == ctx->ext_line_buf)
206 mpp_buffer_get(ctx->ext_line_buf_grp, &ctx->ext_line_buf, ext_line_buf_size);
207
208 ctx->ext_line_buf_size = ext_line_buf_size;
209 } else {
210 if (ctx->ext_line_buf) {
211 mpp_buffer_put(ctx->ext_line_buf);
212 ctx->ext_line_buf = NULL;
213 }
214
215 if (ctx->ext_line_buf_grp) {
216 mpp_buffer_group_clear(ctx->ext_line_buf_grp);
217 mpp_buffer_group_put(ctx->ext_line_buf_grp);
218 ctx->ext_line_buf_grp = NULL;
219 }
220 ctx->ext_line_buf_size = 0;
221 }
222
223 if (frame_size > ctx->frame_size || new_max_cnt > old_max_cnt) {
224 size_t size[3] = {0};
225
226 hal_bufs_deinit(ctx->dpb_bufs);
227 hal_bufs_init(&ctx->dpb_bufs);
228
229 ctx->fbc_header_len = MPP_ALIGN(((mb_wd64 * mb_h64) << 6), SZ_8K);
230 size[0] = ctx->fbc_header_len + ((mb_wd64 * mb_h64) << 12) * 3 / 2; //fbc_h + fbc_b
231 size[1] = (mb_wd64 * mb_h64 << 8);
232 size[2] = MPP_ALIGN(mb_wd64 * mb_h64 * 16 * 4, 256) * 16;
233 new_max_cnt = MPP_MAX(new_max_cnt, old_max_cnt);
234
235 hal_h265e_dbg_detail("frame size %d -> %d max count %d -> %d\n",
236 ctx->frame_size, frame_size, old_max_cnt, new_max_cnt);
237
238 hal_bufs_setup(ctx->dpb_bufs, new_max_cnt, 3, size);
239
240 ctx->frame_size = frame_size;
241 ctx->max_buf_cnt = new_max_cnt;
242 }
243 hal_h265e_leave();
244 return ret;
245 }
246
vepu540c_h265_rdo_cfg(vepu540c_rdo_cfg * reg)247 static void vepu540c_h265_rdo_cfg (vepu540c_rdo_cfg *reg)
248 {
249 rdo_skip_par *p_rdo_skip = NULL;
250 rdo_noskip_par *p_rdo_noskip = NULL;
251 pre_cst_par *p_pre_cst = NULL;
252
253 reg->rdo_segment_cfg.rdo_segment_multi = 0;
254 reg->rdo_segment_cfg.rdo_segment_en = 0;
255 reg->rdo_smear_cfg_comb.rdo_smear_en = 0;
256 reg->rdo_smear_cfg_comb.rdo_smear_lvl16_multi = 12;
257 reg->rdo_segment_cfg.rdo_smear_lvl8_multi = 10;
258 reg->rdo_segment_cfg.rdo_smear_lvl4_multi = 8 ;
259 reg->rdo_smear_cfg_comb.rdo_smear_dlt_qp = 0 ;
260 reg->rdo_smear_cfg_comb.rdo_smear_order_state = 0;
261 reg->rdo_smear_cfg_comb.stated_mode = 0;
262 reg->rdo_smear_cfg_comb.online_en = 0;
263 reg->rdo_smear_cfg_comb.smear_stride = 0;
264 reg->rdo_smear_madp_thd0_comb.rdo_smear_madp_cur_thd0 = 0 ;
265 reg->rdo_smear_madp_thd0_comb.rdo_smear_madp_cur_thd1 = 24;
266 reg->rdo_smear_madp_thd1_comb.rdo_smear_madp_cur_thd2 = 48;
267 reg->rdo_smear_madp_thd1_comb.rdo_smear_madp_cur_thd3 = 64;
268 reg->rdo_smear_madp_thd2_comb.rdo_smear_madp_around_thd0 = 16;
269 reg->rdo_smear_madp_thd2_comb.rdo_smear_madp_around_thd1 = 32;
270 reg->rdo_smear_madp_thd3_comb.rdo_smear_madp_around_thd2 = 48;
271 reg->rdo_smear_madp_thd3_comb.rdo_smear_madp_around_thd3 = 96;
272 reg->rdo_smear_madp_thd4_comb.rdo_smear_madp_around_thd4 = 48;
273 reg->rdo_smear_madp_thd4_comb.rdo_smear_madp_around_thd5 = 24;
274 reg->rdo_smear_madp_thd5_comb.rdo_smear_madp_ref_thd0 = 96;
275 reg->rdo_smear_madp_thd5_comb.rdo_smear_madp_ref_thd1 = 48;
276 reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd0 = 1 ;
277 reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd1 = 4 ;
278 reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd2 = 1 ;
279 reg->rdo_smear_cnt_thd0_comb.rdo_smear_cnt_cur_thd3 = 4 ;
280 reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd0 = 1 ;
281 reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd1 = 4 ;
282 reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd2 = 1 ;
283 reg->rdo_smear_cnt_thd1_comb.rdo_smear_cnt_around_thd3 = 4 ;
284 reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd4 = 1 ;
285 reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd5 = 4 ;
286 reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd6 = 1 ;
287 reg->rdo_smear_cnt_thd2_comb.rdo_smear_cnt_around_thd7 = 4 ;
288 reg->rdo_smear_cnt_thd3_comb.rdo_smear_cnt_ref_thd0 = 1 ;
289 reg->rdo_smear_cnt_thd3_comb.rdo_smear_cnt_ref_thd1 = 4 ;
290 reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_small_cur_th0 = 6;
291 reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_big_cur_th0 = 8;
292 reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_small_cur_th1 = 6;
293 reg->rdo_smear_resi_thd0_comb.rdo_smear_resi_big_cur_th1 = 11;
294 reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_small_around_th0 = 6;
295 reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_big_around_th0 = 8;
296 reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_small_around_th1 = 6;
297 reg->rdo_smear_resi_thd1_comb.rdo_smear_resi_big_around_th1 = 11;
298 reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_small_around_th2 = 9;
299 reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_big_around_th2 = 20;
300 reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_small_around_th3 = 9;
301 reg->rdo_smear_resi_thd2_comb.rdo_smear_resi_big_around_th3 = 20;
302 reg->rdo_smear_resi_thd3_comb.rdo_smear_resi_small_ref_th0 = 9;
303 reg->rdo_smear_resi_thd3_comb.rdo_smear_resi_big_ref_th0 = 20;
304 reg->rdo_smear_st_thd0_comb.rdo_smear_resi_th0 = 12;
305 reg->rdo_smear_st_thd0_comb.rdo_smear_resi_th1 = 12;
306 reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th0 = 1;
307 reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th1 = 2;
308 reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th2 = 1;
309 reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th3 = 2;
310 reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th4 = 1;
311 reg->rdo_smear_st_thd1_comb.rdo_smear_madp_cnt_th5 = 2;
312
313 p_rdo_skip = ®->rdo_b32_skip;
314 p_rdo_skip->atf_thd0.madp_thd0 = 5 ;
315 p_rdo_skip->atf_thd0.madp_thd1 = 10 ;
316 p_rdo_skip->atf_thd1.madp_thd2 = 15 ;
317 p_rdo_skip->atf_thd1.madp_thd3 = 25 ;
318 p_rdo_skip->atf_wgt0.wgt0 = 14 ;
319 p_rdo_skip->atf_wgt0.wgt1 = 15 ;
320 p_rdo_skip->atf_wgt0.wgt2 = 16 ;
321 p_rdo_skip->atf_wgt0.wgt3 = 16 ;
322 p_rdo_skip->atf_wgt1.wgt4 = 20 ;
323
324 p_rdo_noskip = ®->rdo_b32_inter;
325 p_rdo_noskip->ratf_thd0.madp_thd0 = 20;
326 p_rdo_noskip->ratf_thd0.madp_thd1 = 40;
327 p_rdo_noskip->ratf_thd1.madp_thd2 = 72;
328 p_rdo_noskip->atf_wgt.wgt0 = 16;
329 p_rdo_noskip->atf_wgt.wgt1 = 16;
330 p_rdo_noskip->atf_wgt.wgt2 = 16;
331 p_rdo_noskip->atf_wgt.wgt3 = 16;
332
333 p_rdo_noskip = ®->rdo_b32_intra;
334 p_rdo_noskip->ratf_thd0.madp_thd0 = 20;
335 p_rdo_noskip->ratf_thd0.madp_thd1 = 40;
336 p_rdo_noskip->ratf_thd1.madp_thd2 = 72;
337 p_rdo_noskip->atf_wgt.wgt0 = 27;
338 p_rdo_noskip->atf_wgt.wgt1 = 25;
339 p_rdo_noskip->atf_wgt.wgt2 = 20;
340 p_rdo_noskip->atf_wgt.wgt3 = 16;
341
342 p_rdo_skip = ®->rdo_b16_skip;
343 p_rdo_skip->atf_thd0.madp_thd0 = 5 ;
344 p_rdo_skip->atf_thd0.madp_thd1 = 10 ;
345 p_rdo_skip->atf_thd1.madp_thd2 = 15 ;
346 p_rdo_skip->atf_thd1.madp_thd3 = 25 ;
347 p_rdo_skip->atf_wgt0.wgt0 = 20 ;
348 p_rdo_skip->atf_wgt0.wgt1 = 14 ;
349 p_rdo_skip->atf_wgt0.wgt2 = 15 ;
350 p_rdo_skip->atf_wgt0.wgt3 = 16 ;
351 p_rdo_skip->atf_wgt1.wgt4 = 16 ;
352
353 p_rdo_noskip = ®->rdo_b16_inter;
354 p_rdo_noskip->ratf_thd0.madp_thd0 = 20;
355 p_rdo_noskip->ratf_thd0.madp_thd1 = 40;
356 p_rdo_noskip->ratf_thd1.madp_thd2 = 72;
357 p_rdo_noskip->atf_wgt.wgt0 = 16;
358 p_rdo_noskip->atf_wgt.wgt1 = 16;
359 p_rdo_noskip->atf_wgt.wgt2 = 16;
360 p_rdo_noskip->atf_wgt.wgt3 = 16;
361
362 p_rdo_noskip = ®->rdo_b16_intra;
363 p_rdo_noskip->ratf_thd0.madp_thd0 = 20;
364 p_rdo_noskip->ratf_thd0.madp_thd1 = 40;
365 p_rdo_noskip->ratf_thd1.madp_thd2 = 72;
366 p_rdo_noskip->atf_wgt.wgt0 = 27;
367 p_rdo_noskip->atf_wgt.wgt1 = 25;
368 p_rdo_noskip->atf_wgt.wgt2 = 20;
369 p_rdo_noskip->atf_wgt.wgt3 = 16;
370
371 reg->rdo_b32_intra_atf_cnt_thd.thd0 = 14 ;
372 reg->rdo_b32_intra_atf_cnt_thd.thd1 = 15 ;
373 reg->rdo_b32_intra_atf_cnt_thd.thd2 = 16 ;
374 reg->rdo_b32_intra_atf_cnt_thd.thd3 = 17 ;
375
376 reg->rdo_b16_intra_atf_cnt_thd_comb.thd0 = 8 ;
377 reg->rdo_b16_intra_atf_cnt_thd_comb.thd1 = 9 ;
378 reg->rdo_b16_intra_atf_cnt_thd_comb.thd2 = 10 ;
379 reg->rdo_b16_intra_atf_cnt_thd_comb.thd3 = 11 ;
380 reg->rdo_atf_resi_thd_comb.big_th0 = 10;
381 reg->rdo_atf_resi_thd_comb.big_th1 = 12;
382 reg->rdo_atf_resi_thd_comb.small_th0 = 11;
383 reg->rdo_atf_resi_thd_comb.small_th1 = 13;
384
385 p_pre_cst = ®->preintra32_cst;
386 p_pre_cst->cst_madi_thd0.madi_thd0 = 2 ;
387 p_pre_cst->cst_madi_thd0.madi_thd1 = 6 ;
388 p_pre_cst->cst_madi_thd0.madi_thd2 = 16 ;
389 p_pre_cst->cst_madi_thd0.madi_thd3 = 36 ;
390 p_pre_cst->cst_madi_thd1.madi_thd4 = 16 ;
391 p_pre_cst->cst_madi_thd1.madi_thd5 = 16 ;
392 p_pre_cst->cst_wgt0.wgt0 = 16 ;
393 p_pre_cst->cst_wgt0.wgt1 = 16 ;
394 p_pre_cst->cst_wgt0.wgt2 = 16 ;
395 p_pre_cst->cst_wgt0.wgt3 = 16 ;
396 p_pre_cst->cst_wgt1.wgt4 = 16 ;
397 p_pre_cst->cst_wgt1.wgt5 = 16 ;
398 p_pre_cst->cst_wgt1.wgt6 = 16 ;
399 p_pre_cst->cst_wgt1.wgt7 = 16 ;
400 p_pre_cst->cst_wgt2.wgt8 = 16 ;
401 p_pre_cst->cst_wgt2.wgt9 = 16 ;
402 p_pre_cst->cst_wgt2.mode_th = 5 ;
403
404 p_pre_cst = ®->preintra16_cst;
405 p_pre_cst->cst_madi_thd0.madi_thd0 = 2 ;
406 p_pre_cst->cst_madi_thd0.madi_thd1 = 6 ;
407 p_pre_cst->cst_madi_thd0.madi_thd2 = 16;
408 p_pre_cst->cst_madi_thd0.madi_thd3 = 36;
409 p_pre_cst->cst_madi_thd1.madi_thd4 = 16;
410 p_pre_cst->cst_madi_thd1.madi_thd5 = 16;
411 p_pre_cst->cst_wgt0.wgt0 = 16;
412 p_pre_cst->cst_wgt0.wgt1 = 16;
413 p_pre_cst->cst_wgt0.wgt2 = 16;
414 p_pre_cst->cst_wgt0.wgt3 = 16;
415 p_pre_cst->cst_wgt1.wgt4 = 16;
416 p_pre_cst->cst_wgt1.wgt5 = 16;
417 p_pre_cst->cst_wgt1.wgt6 = 16;
418 p_pre_cst->cst_wgt1.wgt7 = 16;
419 p_pre_cst->cst_wgt2.wgt8 = 16;
420 p_pre_cst->cst_wgt2.wgt9 = 16;
421 p_pre_cst->cst_wgt2.mode_th = 5 ;
422
423 reg->preintra_sqi_cfg.pre_intra_qp_thd = 18;
424 reg->preintra_sqi_cfg.pre_intra4_lambda_mv_bit = 3;
425 reg->preintra_sqi_cfg.pre_intra8_lambda_mv_bit = 3;
426 reg->preintra_sqi_cfg.pre_intra16_lambda_mv_bit = 3;
427 reg->preintra_sqi_cfg.pre_intra32_lambda_mv_bit = 3;
428 reg->rdo_atr_i_cu32_madi_cfg0.i_cu32_madi_thd0 = 1;
429 reg->rdo_atr_i_cu32_madi_cfg0.i_cu32_madi_thd1 = 1;
430 reg->rdo_atr_i_cu32_madi_cfg0.i_cu32_madi_thd2 = 1;
431 reg->rdo_atr_i_cu32_madi_cfg1.i_cu32_madi_cnt_thd3 = 1;
432 reg->rdo_atr_i_cu32_madi_cfg1.i_cu32_madi_thd4 = 1;
433 reg->rdo_atr_i_cu32_madi_cfg1.i_cu32_madi_cost_multi = 16;
434 reg->rdo_atr_i_cu16_madi_cfg0.i_cu16_madi_thd0 = 1;
435 reg->rdo_atr_i_cu16_madi_cfg0.i_cu16_madi_thd1 = 1;
436 reg->rdo_atr_i_cu16_madi_cfg0.i_cu16_madi_cost_multi = 16;
437
438 }
439
vepu540c_h265_global_cfg_set(H265eV540cHalContext * ctx,H265eV540cRegSet * regs)440 static void vepu540c_h265_global_cfg_set(H265eV540cHalContext *ctx, H265eV540cRegSet *regs)
441 {
442 MppEncHwCfg *hw = &ctx->cfg->hw;
443 RK_U32 i;
444 hevc_vepu540c_rc_roi *rc_regs = ®s->reg_rc_roi;
445 hevc_vepu540c_wgt *reg_wgt = ®s->reg_wgt;
446 vepu540c_rdo_cfg *reg_rdo = ®s->reg_rdo;
447 vepu540c_h265_rdo_cfg(reg_rdo);
448
449 if (ctx->frame_type == INTRA_FRAME) {
450 RK_U8 *thd = (RK_U8 *)&rc_regs->aq_tthd0;
451 RK_S8 *step = (RK_S8 *)&rc_regs->aq_stp0;
452
453 for (i = 0; i < MPP_ARRAY_ELEMS(aq_thd_default); i++) {
454 thd[i] = hw->aq_thrd_i[i];
455 step[i] = hw->aq_step_i[i] & 0x3f;
456 }
457 reg_wgt->iprd_lamb_satd_ofst.lambda_satd_offset = 3;
458 memcpy(®_wgt->rdo_wgta_qp_grpa_0_51[0], lamd_moda_qp, sizeof(lamd_moda_qp));
459 } else {
460 RK_U8 *thd = (RK_U8 *)&rc_regs->aq_tthd0;
461 RK_S8 *step = (RK_S8 *)&rc_regs->aq_stp0;
462 for (i = 0; i < MPP_ARRAY_ELEMS(aq_thd_default); i++) {
463 thd[i] = hw->aq_thrd_p[i];
464 step[i] = hw->aq_step_p[i] & 0x3f;
465 }
466 reg_wgt->iprd_lamb_satd_ofst.lambda_satd_offset = 3;
467 memcpy(®_wgt->rdo_wgta_qp_grpa_0_51[0], lamd_modb_qp, sizeof(lamd_modb_qp));
468 }
469 reg_wgt->reg1484_qnt_bias_comb.qnt_bias_i = 171;
470 reg_wgt->reg1484_qnt_bias_comb.qnt_bias_p = 85;
471 /* CIME */
472 {
473 /* 0x1760 */
474 regs->reg_wgt.me_sqi_cfg.cime_pmv_num = 1;
475 regs->reg_wgt.me_sqi_cfg.cime_fuse = 1;
476 regs->reg_wgt.me_sqi_cfg.itp_mode = 0;
477 regs->reg_wgt.me_sqi_cfg.move_lambda = 2;
478 regs->reg_wgt.me_sqi_cfg.rime_lvl_mrg = 1;
479 regs->reg_wgt.me_sqi_cfg.rime_prelvl_en = 0;
480 regs->reg_wgt.me_sqi_cfg.rime_prersu_en = 0;
481
482 /* 0x1764 */
483 regs->reg_wgt.cime_mvd_th.cime_mvd_th0 = 8;
484 regs->reg_wgt.cime_mvd_th.cime_mvd_th1 = 20;
485 regs->reg_wgt.cime_mvd_th.cime_mvd_th2 = 32;
486
487 /* 0x1768 */
488 regs->reg_wgt.cime_madp_th.cime_madp_th = 16;
489
490 /* 0x176c */
491 regs->reg_wgt.cime_multi.cime_multi0 = 8;
492 regs->reg_wgt.cime_multi.cime_multi1 = 12;
493 regs->reg_wgt.cime_multi.cime_multi2 = 16;
494 regs->reg_wgt.cime_multi.cime_multi3 = 20;
495 }
496
497 /* RIME && FME */
498 {
499 /* 0x1770 */
500 regs->reg_wgt.rime_mvd_th.rime_mvd_th0 = 1;
501 regs->reg_wgt.rime_mvd_th.rime_mvd_th1 = 2;
502 regs->reg_wgt.rime_mvd_th.fme_madp_th = 0;
503
504 /* 0x1774 */
505 regs->reg_wgt.rime_madp_th.rime_madp_th0 = 8;
506 regs->reg_wgt.rime_madp_th.rime_madp_th1 = 16;
507
508 /* 0x1778 */
509 regs->reg_wgt.rime_multi.rime_multi0 = 4;
510 regs->reg_wgt.rime_multi.rime_multi1 = 8;
511 regs->reg_wgt.rime_multi.rime_multi2 = 12;
512
513 /* 0x177C */
514 regs->reg_wgt.cmv_st_th.cmv_th0 = 64;
515 regs->reg_wgt.cmv_st_th.cmv_th1 = 96;
516 regs->reg_wgt.cmv_st_th.cmv_th2 = 128;
517 }
518 }
519
hal_h265e_v540c_init(void * hal,MppEncHalCfg * cfg)520 MPP_RET hal_h265e_v540c_init(void *hal, MppEncHalCfg *cfg)
521 {
522 MPP_RET ret = MPP_OK;
523 H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal;
524 RK_U32 i = 0;
525
526 mpp_env_get_u32("hal_h265e_debug", &hal_h265e_debug, 0);
527
528 hal_h265e_enter();
529
530 for ( i = 0; i < MAX_TITLE_NUM; i++) {
531 ctx->reg_out[i] = mpp_calloc(H265eV540cStatusElem, 1);
532 }
533
534 ctx->regs = mpp_calloc(H265eV540cRegSet, 1);
535 ctx->input_fmt = mpp_calloc(VepuFmtCfg, 1);
536 ctx->cfg = cfg->cfg;
537 hal_bufs_init(&ctx->dpb_bufs);
538
539 ctx->frame_cnt = 0;
540 ctx->frame_cnt_gen_ready = 0;
541 ctx->enc_mode = 1;
542 cfg->type = VPU_CLIENT_RKVENC;
543 ret = mpp_dev_init(&cfg->dev, cfg->type);
544 if (ret) {
545 mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
546 return ret;
547 }
548
549 ctx->dev = cfg->dev;
550 ctx->frame_type = INTRA_FRAME;
551
552 { /* setup default hardware config */
553 MppEncHwCfg *hw = &cfg->cfg->hw;
554
555 hw->qp_delta_row_i = 2;
556 hw->qp_delta_row = 2;
557
558 memcpy(hw->aq_thrd_i, aq_thd_default, sizeof(hw->aq_thrd_i));
559 memcpy(hw->aq_thrd_p, aq_thd_default, sizeof(hw->aq_thrd_p));
560 memcpy(hw->aq_step_i, aq_qp_dealt_default, sizeof(hw->aq_step_i));
561 memcpy(hw->aq_step_p, aq_qp_dealt_default, sizeof(hw->aq_step_p));
562 }
563
564 hal_h265e_leave();
565 return ret;
566 }
567
hal_h265e_v540c_deinit(void * hal)568 MPP_RET hal_h265e_v540c_deinit(void *hal)
569 {
570 H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal;
571 RK_U32 i = 0;
572
573 hal_h265e_enter();
574 MPP_FREE(ctx->regs);
575
576 for ( i = 0; i < MAX_TITLE_NUM; i++) {
577 MPP_FREE(ctx->reg_out[i]);
578 }
579
580 MPP_FREE(ctx->input_fmt);
581 hal_bufs_deinit(ctx->dpb_bufs);
582
583 if (ctx->ext_line_buf) {
584 mpp_buffer_put(ctx->ext_line_buf);
585 ctx->ext_line_buf = NULL;
586 }
587
588 if (ctx->ext_line_buf_grp) {
589 mpp_buffer_group_put(ctx->ext_line_buf_grp);
590 ctx->ext_line_buf_grp = NULL;
591 }
592
593 if (ctx->dev) {
594 mpp_dev_deinit(ctx->dev);
595 ctx->dev = NULL;
596 }
597 hal_h265e_leave();
598 return MPP_OK;
599 }
600
hal_h265e_vepu540c_prepare(void * hal)601 static MPP_RET hal_h265e_vepu540c_prepare(void *hal)
602 {
603 H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal;
604 MppEncPrepCfg *prep = &ctx->cfg->prep;
605
606 hal_h265e_dbg_func("enter %p\n", hal);
607
608 if (prep->change & (MPP_ENC_PREP_CFG_CHANGE_INPUT | MPP_ENC_PREP_CFG_CHANGE_FORMAT)) {
609 RK_S32 i;
610
611 // pre-alloc required buffers to reduce first frame delay
612 vepu540c_h265_setup_hal_bufs(ctx);
613 for (i = 0; i < ctx->max_buf_cnt; i++)
614 hal_bufs_get_buf(ctx->dpb_bufs, i);
615
616 prep->change = 0;
617 }
618
619 hal_h265e_dbg_func("leave %p\n", hal);
620
621 return MPP_OK;
622 }
623
624 static MPP_RET
vepu540c_h265_set_patch_info(MppDev dev,H265eSyntax_new * syn,Vepu541Fmt input_fmt,HalEncTask * task)625 vepu540c_h265_set_patch_info(MppDev dev, H265eSyntax_new *syn, Vepu541Fmt input_fmt, HalEncTask *task)
626 {
627 MppDevRegOffsetCfg cfg_fd;
628 RK_U32 hor_stride = syn->pp.hor_stride;
629 RK_U32 ver_stride = syn->pp.ver_stride ? syn->pp.ver_stride : syn->pp.pic_height;
630 RK_U32 frame_size = hor_stride * ver_stride;
631 RK_U32 u_offset = 0, v_offset = 0;
632 MPP_RET ret = MPP_OK;
633
634
635 if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(task->frame))) {
636 u_offset = mpp_frame_get_fbc_offset(task->frame);
637 v_offset = 0;
638 mpp_log("fbc case u_offset = %d", u_offset);
639 } else {
640 switch (input_fmt) {
641 case VEPU541_FMT_YUV420P: {
642 u_offset = frame_size;
643 v_offset = frame_size * 5 / 4;
644 } break;
645 case VEPU541_FMT_YUV420SP:
646 case VEPU541_FMT_YUV422SP: {
647 u_offset = frame_size;
648 v_offset = frame_size;
649 } break;
650 case VEPU541_FMT_YUV422P: {
651 u_offset = frame_size;
652 v_offset = frame_size * 3 / 2;
653 } break;
654 case VEPU541_FMT_YUYV422:
655 case VEPU541_FMT_UYVY422: {
656 u_offset = 0;
657 v_offset = 0;
658 } break;
659 case VEPU541_FMT_BGR565:
660 case VEPU541_FMT_BGR888:
661 case VEPU541_FMT_BGRA8888: {
662 u_offset = 0;
663 v_offset = 0;
664 } break;
665 default: {
666 hal_h265e_err("unknown color space: %d\n", input_fmt);
667 u_offset = frame_size;
668 v_offset = frame_size * 5 / 4;
669 }
670 }
671 }
672
673 /* input cb addr */
674 if (u_offset) {
675 cfg_fd.reg_idx = 161;
676 cfg_fd.offset = u_offset;
677 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &cfg_fd);
678 if (ret)
679 mpp_err_f("set input cb addr offset failed %d\n", ret);
680 }
681
682 /* input cr addr */
683 if (v_offset) {
684 cfg_fd.reg_idx = 162;
685 cfg_fd.offset = v_offset;
686 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &cfg_fd);
687 if (ret)
688 mpp_err_f("set input cr addr offset failed %d\n", ret);
689 }
690
691 return ret;
692 }
693
694
695 #if 0
696 static MPP_RET vepu540c_h265_set_roi_regs(H265eV540cHalContext *ctx, hevc_vepu540c_base *regs)
697 {
698 /* memset register on start so do not clear registers again here */
699 if (ctx->roi_data) {
700 /* roi setup */
701 MppEncROICfg2 *cfg = ( MppEncROICfg2 *)ctx->roi_data;
702
703 regs->reg0192_enc_pic.roi_en = 1;
704 regs->reg0178_roi_addr = mpp_dev_get_iova_address(ctx->dev, cfg->base_cfg_buf, 0);
705 if (cfg->roi_qp_en) {
706 regs->reg0179_roi_qp_addr = mpp_dev_get_iova_address(ctx->dev, cfg->qp_cfg_buf, 0);
707 regs->reg0228_roi_en.roi_qp_en = 1;
708 }
709
710 if (cfg->roi_amv_en) {
711 regs->reg0180_roi_amv_addr = mpp_dev_get_iova_address(ctx->dev, cfg->amv_cfg_buf, 0);
712 regs->reg0228_roi_en.roi_amv_en = 1;
713 }
714
715 if (cfg->roi_mv_en) {
716 regs->reg0181_roi_mv_addr = mpp_dev_get_iova_address(ctx->dev, cfg->mv_cfg_buf, 0);
717 regs->reg0228_roi_en.roi_mv_en = 1;
718 }
719 }
720
721 return MPP_OK;
722 }
723 #endif
724
vepu540c_h265_set_rc_regs(H265eV540cHalContext * ctx,H265eV540cRegSet * regs,HalEncTask * task)725 static MPP_RET vepu540c_h265_set_rc_regs(H265eV540cHalContext *ctx, H265eV540cRegSet *regs, HalEncTask *task)
726 {
727 H265eSyntax_new *syn = (H265eSyntax_new *)task->syntax.data;
728 EncRcTaskInfo *rc_cfg = &task->rc_task->info;
729 hevc_vepu540c_base *reg_base = ®s->reg_base;
730 hevc_vepu540c_rc_roi *reg_rc = ®s->reg_rc_roi;
731 MppEncCfgSet *cfg = ctx->cfg;
732 MppEncRcCfg *rc = &cfg->rc;
733 MppEncHwCfg *hw = &cfg->hw;
734 MppEncCodecCfg *codec = &cfg->codec;
735 MppEncH265Cfg *h265 = &codec->h265;
736 RK_S32 mb_wd32 = (syn->pp.pic_width + 31) / 32;
737 RK_S32 mb_h32 = (syn->pp.pic_height + 31) / 32;
738
739 RK_U32 ctu_target_bits_mul_16 = (rc_cfg->bit_target << 4) / (mb_wd32 * mb_h32);
740 RK_U32 ctu_target_bits;
741 RK_S32 negative_bits_thd, positive_bits_thd;
742
743 if (rc->rc_mode == MPP_ENC_RC_MODE_FIXQP) {
744 reg_base->reg0192_enc_pic.pic_qp = rc_cfg->quality_target;
745 reg_base->reg0240_synt_sli1.sli_qp = rc_cfg->quality_target;
746
747 reg_base->reg213_rc_qp.rc_max_qp = rc_cfg->quality_target;
748 reg_base->reg213_rc_qp.rc_min_qp = rc_cfg->quality_target;
749 } else {
750 if (ctu_target_bits_mul_16 >= 0x100000) {
751 ctu_target_bits_mul_16 = 0x50000;
752 }
753 ctu_target_bits = (ctu_target_bits_mul_16 * mb_wd32) >> 4;
754 negative_bits_thd = 0 - 5 * ctu_target_bits / 16;
755 positive_bits_thd = 5 * ctu_target_bits / 16;
756
757 reg_base->reg0192_enc_pic.pic_qp = rc_cfg->quality_target;
758 reg_base->reg0240_synt_sli1.sli_qp = rc_cfg->quality_target;
759 reg_base->reg212_rc_cfg.rc_en = 1;
760 reg_base->reg212_rc_cfg.aq_en = 1;
761 reg_base->reg212_rc_cfg.aq_mode = 0;
762 reg_base->reg212_rc_cfg.rc_ctu_num = mb_wd32;
763 reg_base->reg213_rc_qp.rc_qp_range = (ctx->frame_type == INTRA_FRAME) ?
764 hw->qp_delta_row_i : hw->qp_delta_row;
765 reg_base->reg213_rc_qp.rc_max_qp = rc_cfg->quality_max;
766 reg_base->reg213_rc_qp.rc_min_qp = rc_cfg->quality_min;
767 reg_base->reg214_rc_tgt.ctu_ebit = ctu_target_bits_mul_16;
768
769 reg_rc->rc_dthd_0_8[0] = 2 * negative_bits_thd;
770 reg_rc->rc_dthd_0_8[1] = negative_bits_thd;
771 reg_rc->rc_dthd_0_8[2] = positive_bits_thd;
772 reg_rc->rc_dthd_0_8[3] = 2 * positive_bits_thd;
773 reg_rc->rc_dthd_0_8[4] = 0x7FFFFFFF;
774 reg_rc->rc_dthd_0_8[5] = 0x7FFFFFFF;
775 reg_rc->rc_dthd_0_8[6] = 0x7FFFFFFF;
776 reg_rc->rc_dthd_0_8[7] = 0x7FFFFFFF;
777 reg_rc->rc_dthd_0_8[8] = 0x7FFFFFFF;
778
779 reg_rc->rc_adj0.qp_adj0 = -2;
780 reg_rc->rc_adj0.qp_adj1 = -1;
781 reg_rc->rc_adj0.qp_adj2 = 0;
782 reg_rc->rc_adj0.qp_adj3 = 1;
783 reg_rc->rc_adj0.qp_adj4 = 2;
784 reg_rc->rc_adj1.qp_adj5 = 0;
785 reg_rc->rc_adj1.qp_adj6 = 0;
786 reg_rc->rc_adj1.qp_adj7 = 0;
787 reg_rc->rc_adj1.qp_adj8 = 0;
788
789 reg_rc->roi_qthd0.qpmin_area0 = h265->qpmin_map[0] > 0 ? h265->qpmin_map[0] : rc_cfg->quality_min;
790 reg_rc->roi_qthd0.qpmax_area0 = h265->qpmax_map[0] > 0 ? h265->qpmax_map[0] : rc_cfg->quality_max;
791 reg_rc->roi_qthd0.qpmin_area1 = h265->qpmin_map[1] > 0 ? h265->qpmin_map[1] : rc_cfg->quality_min;
792 reg_rc->roi_qthd0.qpmax_area1 = h265->qpmax_map[1] > 0 ? h265->qpmax_map[1] : rc_cfg->quality_max;
793 reg_rc->roi_qthd0.qpmin_area2 = h265->qpmin_map[2] > 0 ? h265->qpmin_map[2] : rc_cfg->quality_min;;
794 reg_rc->roi_qthd1.qpmax_area2 = h265->qpmax_map[2] > 0 ? h265->qpmax_map[2] : rc_cfg->quality_max;
795 reg_rc->roi_qthd1.qpmin_area3 = h265->qpmin_map[3] > 0 ? h265->qpmin_map[3] : rc_cfg->quality_min;;
796 reg_rc->roi_qthd1.qpmax_area3 = h265->qpmax_map[3] > 0 ? h265->qpmax_map[3] : rc_cfg->quality_max;
797 reg_rc->roi_qthd1.qpmin_area4 = h265->qpmin_map[4] > 0 ? h265->qpmin_map[4] : rc_cfg->quality_min;;
798 reg_rc->roi_qthd1.qpmax_area4 = h265->qpmax_map[4] > 0 ? h265->qpmax_map[4] : rc_cfg->quality_max;
799 reg_rc->roi_qthd2.qpmin_area5 = h265->qpmin_map[5] > 0 ? h265->qpmin_map[5] : rc_cfg->quality_min;;
800 reg_rc->roi_qthd2.qpmax_area5 = h265->qpmax_map[5] > 0 ? h265->qpmax_map[5] : rc_cfg->quality_max;
801 reg_rc->roi_qthd2.qpmin_area6 = h265->qpmin_map[6] > 0 ? h265->qpmin_map[6] : rc_cfg->quality_min;;
802 reg_rc->roi_qthd2.qpmax_area6 = h265->qpmax_map[6] > 0 ? h265->qpmax_map[6] : rc_cfg->quality_max;
803 reg_rc->roi_qthd2.qpmin_area7 = h265->qpmin_map[7] > 0 ? h265->qpmin_map[7] : rc_cfg->quality_min;;
804 reg_rc->roi_qthd3.qpmax_area7 = h265->qpmax_map[7] > 0 ? h265->qpmax_map[7] : rc_cfg->quality_max;
805 reg_rc->roi_qthd3.qpmap_mode = h265->qpmap_mode;
806 }
807 return MPP_OK;
808 }
809
vepu540c_h265_set_pp_regs(H265eV540cRegSet * regs,VepuFmtCfg * fmt,MppEncPrepCfg * prep_cfg)810 static MPP_RET vepu540c_h265_set_pp_regs(H265eV540cRegSet *regs, VepuFmtCfg *fmt, MppEncPrepCfg *prep_cfg)
811 {
812 hevc_vepu540c_control_cfg *reg_ctl = ®s->reg_ctl;
813 hevc_vepu540c_base *reg_base = ®s->reg_base;
814 RK_S32 stridey = 0;
815 RK_S32 stridec = 0;
816
817 reg_ctl->reg0012_dtrns_map.src_bus_edin = fmt->src_endian;
818 reg_base->reg0198_src_fmt.src_cfmt = fmt->format;
819 reg_base->reg0198_src_fmt.alpha_swap = fmt->alpha_swap;
820 reg_base->reg0198_src_fmt.rbuv_swap = fmt->rbuv_swap;
821
822 // reg_base->reg0198_src_fmt.src_range = fmt->src_range;
823 reg_base->reg0198_src_fmt.out_fmt = 1;
824
825 reg_base->reg0203_src_proc.src_mirr = prep_cfg->mirroring > 0;
826 reg_base->reg0203_src_proc.src_rot = prep_cfg->rotation;
827
828 if (prep_cfg->hor_stride) {
829 stridey = prep_cfg->hor_stride;
830 } else {
831 if (reg_base->reg0198_src_fmt.src_cfmt == VEPU541_FMT_BGRA8888 )
832 stridey = prep_cfg->width * 4;
833 else if (reg_base->reg0198_src_fmt.src_cfmt == VEPU541_FMT_BGR888 )
834 stridey = prep_cfg->width * 3;
835 else if (reg_base->reg0198_src_fmt.src_cfmt == VEPU541_FMT_BGR565 ||
836 reg_base->reg0198_src_fmt.src_cfmt == VEPU541_FMT_YUYV422 ||
837 reg_base->reg0198_src_fmt.src_cfmt == VEPU541_FMT_UYVY422)
838 stridey = prep_cfg->width * 2;
839 }
840
841 stridec = (reg_base->reg0198_src_fmt.src_cfmt == VEPU541_FMT_YUV422SP ||
842 reg_base->reg0198_src_fmt.src_cfmt == VEPU541_FMT_YUV420SP) ?
843 stridey : stridey / 2;
844
845 if (reg_base->reg0198_src_fmt.src_cfmt < VEPU541_FMT_NONE) {
846 reg_base->reg0199_src_udfy.csc_wgt_r2y = 66;
847 reg_base->reg0199_src_udfy.csc_wgt_g2y = 129;
848 reg_base->reg0199_src_udfy.csc_wgt_b2y = 25;
849
850 reg_base->reg0200_src_udfu.csc_wgt_r2u = -38;
851 reg_base->reg0200_src_udfu.csc_wgt_g2u = -74;
852 reg_base->reg0200_src_udfu.csc_wgt_b2u = 112;
853
854 reg_base->reg0201_src_udfv.csc_wgt_r2v = 112;
855 reg_base->reg0201_src_udfv.csc_wgt_g2v = -94;
856 reg_base->reg0201_src_udfv.csc_wgt_b2v = -18;
857
858 reg_base->reg0202_src_udfo.csc_ofst_y = 16;
859 reg_base->reg0202_src_udfo.csc_ofst_u = 128;
860 reg_base->reg0202_src_udfo.csc_ofst_v = 128;
861 }
862
863 reg_base->reg0205_src_strd0.src_strd0 = stridey;
864 reg_base->reg0206_src_strd1.src_strd1 = stridec;
865
866 return MPP_OK;
867 }
868
vepu540c_h265_set_slice_regs(H265eSyntax_new * syn,hevc_vepu540c_base * regs)869 static void vepu540c_h265_set_slice_regs(H265eSyntax_new *syn, hevc_vepu540c_base *regs)
870 {
871 regs->reg0237_synt_sps.smpl_adpt_ofst_e = syn->pp.sample_adaptive_offset_enabled_flag;
872 regs->reg0237_synt_sps.num_st_ref_pic = syn->pp.num_short_term_ref_pic_sets;
873 regs->reg0237_synt_sps.num_lt_ref_pic = syn->pp.num_long_term_ref_pics_sps;
874 regs->reg0237_synt_sps.lt_ref_pic_prsnt = syn->pp.long_term_ref_pics_present_flag;
875 regs->reg0237_synt_sps.tmpl_mvp_e = syn->pp.sps_temporal_mvp_enabled_flag;
876 regs->reg0237_synt_sps.log2_max_poc_lsb = syn->pp.log2_max_pic_order_cnt_lsb_minus4;
877 regs->reg0237_synt_sps.strg_intra_smth = syn->pp.strong_intra_smoothing_enabled_flag;
878
879 regs->reg0238_synt_pps.dpdnt_sli_seg_en = syn->pp.dependent_slice_segments_enabled_flag;
880 regs->reg0238_synt_pps.out_flg_prsnt_flg = syn->pp.output_flag_present_flag;
881 regs->reg0238_synt_pps.num_extr_sli_hdr = syn->pp.num_extra_slice_header_bits;
882 regs->reg0238_synt_pps.sgn_dat_hid_en = syn->pp.sign_data_hiding_enabled_flag;
883 regs->reg0238_synt_pps.cbc_init_prsnt_flg = syn->pp.cabac_init_present_flag;
884 regs->reg0238_synt_pps.pic_init_qp = syn->pp.init_qp_minus26 + 26;
885 regs->reg0238_synt_pps.cu_qp_dlt_en = syn->pp.cu_qp_delta_enabled_flag;
886 regs->reg0238_synt_pps.chrm_qp_ofst_prsn = syn->pp.pps_slice_chroma_qp_offsets_present_flag;
887 regs->reg0238_synt_pps.lp_fltr_acrs_sli = syn->pp.pps_loop_filter_across_slices_enabled_flag;
888 regs->reg0238_synt_pps.dblk_fltr_ovrd_en = syn->pp.deblocking_filter_override_enabled_flag;
889 regs->reg0238_synt_pps.lst_mdfy_prsnt_flg = syn->pp.lists_modification_present_flag;
890 regs->reg0238_synt_pps.sli_seg_hdr_extn = syn->pp.slice_segment_header_extension_present_flag;
891 regs->reg0238_synt_pps.cu_qp_dlt_depth = syn->pp.diff_cu_qp_delta_depth;
892 regs->reg0238_synt_pps.lpf_fltr_acrs_til = syn->pp.loop_filter_across_tiles_enabled_flag;
893
894 regs->reg0239_synt_sli0.cbc_init_flg = syn->sp.cbc_init_flg;
895 regs->reg0239_synt_sli0.mvd_l1_zero_flg = syn->sp.mvd_l1_zero_flg;
896 regs->reg0239_synt_sli0.mrg_up_flg = syn->sp.merge_up_flag;
897 regs->reg0239_synt_sli0.mrg_lft_flg = syn->sp.merge_left_flag;
898 regs->reg0239_synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0;
899
900 regs->reg0239_synt_sli0.num_refidx_l1_act = syn->sp.num_refidx_l1_act;
901 regs->reg0239_synt_sli0.num_refidx_l0_act = syn->sp.num_refidx_l0_act;
902
903 regs->reg0239_synt_sli0.num_refidx_act_ovrd = syn->sp.num_refidx_act_ovrd;
904
905 regs->reg0239_synt_sli0.sli_sao_chrm_flg = syn->sp.sli_sao_chrm_flg;
906 regs->reg0239_synt_sli0.sli_sao_luma_flg = syn->sp.sli_sao_luma_flg;
907 regs->reg0239_synt_sli0.sli_tmprl_mvp_e = syn->sp.sli_tmprl_mvp_en;
908 regs->reg0192_enc_pic.num_pic_tot_cur = syn->sp.tot_poc_num;
909
910 regs->reg0239_synt_sli0.pic_out_flg = syn->sp.pic_out_flg;
911 regs->reg0239_synt_sli0.sli_type = syn->sp.slice_type;
912 regs->reg0239_synt_sli0.sli_rsrv_flg = syn->sp.slice_rsrv_flg;
913 regs->reg0239_synt_sli0.dpdnt_sli_seg_flg = syn->sp.dpdnt_sli_seg_flg;
914 regs->reg0239_synt_sli0.sli_pps_id = syn->sp.sli_pps_id;
915 regs->reg0239_synt_sli0.no_out_pri_pic = syn->sp.no_out_pri_pic;
916
917
918 regs->reg0240_synt_sli1.sp_tc_ofst_div2 = syn->sp.sli_tc_ofst_div2;;
919 regs->reg0240_synt_sli1.sp_beta_ofst_div2 = syn->sp.sli_beta_ofst_div2;
920 regs->reg0240_synt_sli1.sli_lp_fltr_acrs_sli = syn->sp.sli_lp_fltr_acrs_sli;
921 regs->reg0240_synt_sli1.sp_dblk_fltr_dis = syn->sp.sli_dblk_fltr_dis;
922 regs->reg0240_synt_sli1.dblk_fltr_ovrd_flg = syn->sp.dblk_fltr_ovrd_flg;
923 regs->reg0240_synt_sli1.sli_cb_qp_ofst = syn->sp.sli_cb_qp_ofst;
924 regs->reg0240_synt_sli1.max_mrg_cnd = syn->sp.max_mrg_cnd;
925
926 regs->reg0240_synt_sli1.col_ref_idx = syn->sp.col_ref_idx;
927 regs->reg0240_synt_sli1.col_frm_l0_flg = syn->sp.col_frm_l0_flg;
928 regs->reg0241_synt_sli2.sli_poc_lsb = syn->sp.sli_poc_lsb;
929 regs->reg0241_synt_sli2.sli_hdr_ext_len = syn->sp.sli_hdr_ext_len;
930
931 }
932
vepu540c_h265_set_ref_regs(H265eSyntax_new * syn,hevc_vepu540c_base * regs)933 static void vepu540c_h265_set_ref_regs(H265eSyntax_new *syn, hevc_vepu540c_base *regs)
934 {
935 regs->reg0242_synt_refm0.st_ref_pic_flg = syn->sp.st_ref_pic_flg;
936 regs->reg0242_synt_refm0.poc_lsb_lt0 = syn->sp.poc_lsb_lt0;
937 regs->reg0242_synt_refm0.num_lt_pic = syn->sp.num_lt_pic;
938
939 regs->reg0243_synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0;
940 regs->reg0243_synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0;
941 regs->reg0243_synt_refm1.used_by_lt_flg0 = syn->sp.used_by_lt_flg0;
942 regs->reg0243_synt_refm1.used_by_lt_flg1 = syn->sp.used_by_lt_flg1;
943 regs->reg0243_synt_refm1.used_by_lt_flg2 = syn->sp.used_by_lt_flg2;
944 regs->reg0243_synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0;
945 regs->reg0243_synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0;
946 regs->reg0243_synt_refm1.dlt_poc_msb_prsnt1 = syn->sp.dlt_poc_msb_prsnt1;
947 regs->reg0243_synt_refm1.num_negative_pics = syn->sp.num_neg_pic;
948 regs->reg0243_synt_refm1.num_pos_pic = syn->sp.num_pos_pic;
949
950 regs->reg0243_synt_refm1.used_by_s0_flg = syn->sp.used_by_s0_flg;
951 regs->reg0244_synt_refm2.dlt_poc_s0_m10 = syn->sp.dlt_poc_s0_m10;
952 regs->reg0244_synt_refm2.dlt_poc_s0_m11 = syn->sp.dlt_poc_s0_m11;
953 regs->reg0245_synt_refm3.dlt_poc_s0_m12 = syn->sp.dlt_poc_s0_m12;
954 regs->reg0245_synt_refm3.dlt_poc_s0_m13 = syn->sp.dlt_poc_s0_m13;
955
956 regs->reg0246_synt_long_refm0.poc_lsb_lt1 = syn->sp.poc_lsb_lt1;
957 regs->reg0247_synt_long_refm1.dlt_poc_msb_cycl1 = syn->sp.dlt_poc_msb_cycl1;
958 regs->reg0246_synt_long_refm0.poc_lsb_lt2 = syn->sp.poc_lsb_lt2;
959 regs->reg0243_synt_refm1.dlt_poc_msb_prsnt2 = syn->sp.dlt_poc_msb_prsnt2;
960 regs->reg0247_synt_long_refm1.dlt_poc_msb_cycl2 = syn->sp.dlt_poc_msb_cycl2;
961 regs->reg0240_synt_sli1.lst_entry_l0 = syn->sp.lst_entry_l0;
962 regs->reg0239_synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0;
963
964 return;
965 }
vepu540c_h265_set_me_regs(H265eV540cHalContext * ctx,H265eSyntax_new * syn,hevc_vepu540c_base * regs)966 static void vepu540c_h265_set_me_regs(H265eV540cHalContext *ctx, H265eSyntax_new *syn, hevc_vepu540c_base *regs)
967 {
968
969 RK_S32 x_gmv = 0;
970 RK_S32 y_gmv = 0;
971 RK_S32 srch_lftw, srch_rgtw, srch_uph, srch_dwnh;
972 RK_S32 frm_sta = 0, frm_end = 0, pic_w = 0;
973 RK_S32 pic_wdt_align = ((regs->reg0196_enc_rsl.pic_wd8_m1 + 1) * 8 + 31) / 32 ;
974
975
976 regs->reg0220_me_rnge.cime_srch_dwnh = 15;
977 regs->reg0220_me_rnge.cime_srch_uph = 14;
978 regs->reg0220_me_rnge.cime_srch_rgtw = 12;
979 regs->reg0220_me_rnge.cime_srch_lftw = 12;
980 regs->reg0221_me_cfg.rme_srch_h = 3;
981 regs->reg0221_me_cfg.rme_srch_v = 3;
982
983 regs->reg0221_me_cfg.srgn_max_num = 72;
984 regs->reg0221_me_cfg.cime_dist_thre = 1024;
985 regs->reg0221_me_cfg.rme_dis = 0;
986 regs->reg0221_me_cfg.fme_dis = 0;
987 regs->reg0220_me_rnge.dlt_frm_num = 0x1;
988 srch_lftw = regs->reg0220_me_rnge.cime_srch_lftw * 4;
989 srch_rgtw = regs->reg0220_me_rnge.cime_srch_rgtw * 4;
990 srch_uph = regs->reg0220_me_rnge.cime_srch_uph * 2;
991 srch_dwnh = regs->reg0220_me_rnge.cime_srch_dwnh * 2;
992
993 if (syn->pp.sps_temporal_mvp_enabled_flag &&
994 (ctx->frame_type != INTRA_FRAME)) {
995 if (ctx->last_frame_type == INTRA_FRAME) {
996 regs->reg0222_me_cach.colmv_load = 0;
997 } else {
998 regs->reg0222_me_cach.colmv_load = 1;
999 }
1000 regs->reg0222_me_cach.colmv_stor = 1;
1001 }
1002 // calc cme_linebuf_w
1003 {
1004 if (x_gmv - srch_lftw < 0) {
1005 frm_sta = (x_gmv - srch_lftw - 15) / 16;
1006 } else {
1007 frm_sta = (x_gmv - srch_lftw) / 16;
1008 }
1009 if (x_gmv + srch_rgtw < 0) {
1010 frm_end = pic_wdt_align - 1 + (x_gmv + srch_rgtw) / 16;
1011 } else {
1012 frm_end = pic_wdt_align - 1 + (x_gmv + srch_rgtw + 15) / 16;
1013 }
1014
1015 if (frm_sta < 0) {
1016 frm_sta = 0;
1017 } else if (frm_sta > pic_wdt_align - 1) {
1018 frm_sta = pic_wdt_align - 1;
1019 }
1020 frm_end = mpp_clip(frm_end, 0, pic_wdt_align - 1);
1021 pic_w = (frm_end - frm_sta + 1) * 32;
1022 regs->reg0222_me_cach.cme_linebuf_w = pic_w / 32;
1023 }
1024
1025 // calc cime_hgt_rama and cime_size_rama
1026 {
1027 RK_U32 rama_size = 1796;
1028 RK_U32 ramb_h;
1029 RK_U32 ctu_2_h = 4;
1030 RK_U32 ctu_8_w = 1 ;
1031 RK_U32 cur_srch_8_w, cur_srch_2_h, cur_srch_h;
1032
1033 if ((y_gmv % 8 - srch_uph % 8) < 0) {
1034 cur_srch_2_h = (8 + (y_gmv % 8 - srch_uph % 8) % 8 + srch_uph + srch_dwnh) / 2 + ctu_2_h;
1035 } else {
1036 cur_srch_2_h = ((y_gmv % 8 - srch_uph % 8) % 8 + srch_uph + srch_dwnh) / 2 + ctu_2_h;
1037 }
1038 regs->reg0222_me_cach.cime_size_rama = (cur_srch_2_h + 3) / 4 * 4;
1039
1040 if ((x_gmv % 8 - srch_lftw % 8) < 0) {
1041 cur_srch_8_w = (8 + (x_gmv % 8 - srch_lftw % 8) % 8 + srch_lftw + srch_rgtw + 7) / 8 + ctu_8_w;
1042 } else {
1043 cur_srch_8_w = ((x_gmv % 8 - srch_lftw % 8) % 8 + srch_lftw + srch_rgtw + 7) / 8 + ctu_8_w;
1044 }
1045
1046 cur_srch_h = ctu_2_h;
1047 ramb_h = cur_srch_2_h;
1048 while ((rama_size > ((cur_srch_h - ctu_2_h) * regs->reg0222_me_cach.cme_linebuf_w + (ramb_h * cur_srch_8_w)))
1049 && (cur_srch_h < regs->reg0222_me_cach.cime_size_rama)) {
1050 cur_srch_h = cur_srch_h + ctu_2_h;
1051 if (ramb_h > ctu_2_h * 2) {
1052 ramb_h = ramb_h - ctu_2_h;
1053 } else {
1054 ramb_h = ctu_2_h;
1055 }
1056 }
1057
1058 if (cur_srch_2_h == ctu_2_h * 2) {
1059 cur_srch_h = cur_srch_h + ctu_2_h;
1060 ramb_h = ctu_2_h;
1061 }
1062
1063 if (rama_size < ((cur_srch_h - ctu_2_h) * regs->reg0222_me_cach.cme_linebuf_w + (ramb_h * cur_srch_8_w))) {
1064 cur_srch_h = cur_srch_h - ctu_2_h;
1065 }
1066
1067 regs->reg0222_me_cach.cime_size_rama = ((cur_srch_h - ctu_2_h) * regs->reg0222_me_cach.cme_linebuf_w + ctu_2_h * cur_srch_8_w) / 4;
1068 regs->reg0222_me_cach.cime_hgt_rama = cur_srch_h / 2;
1069 regs->reg0222_me_cach.fme_prefsu_en = 0;
1070 }
1071
1072 }
1073
vepu540c_h265_set_hw_address(H265eV540cHalContext * ctx,hevc_vepu540c_base * regs,HalEncTask * task)1074 void vepu540c_h265_set_hw_address(H265eV540cHalContext *ctx, hevc_vepu540c_base *regs, HalEncTask *task)
1075 {
1076 HalEncTask *enc_task = task;
1077 HalBuf *recon_buf, *ref_buf;
1078 MppBuffer md_info_buf = enc_task->md_info;
1079 H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data;
1080
1081 hal_h265e_enter();
1082
1083 regs->reg0160_adr_src0 = mpp_buffer_get_fd(enc_task->input);
1084 regs->reg0161_adr_src1 = regs->reg0160_adr_src0;
1085 regs->reg0162_adr_src2 = regs->reg0160_adr_src0;
1086
1087 recon_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.recon_pic.slot_idx);
1088 ref_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.ref_pic.slot_idx);
1089
1090 if (!syn->sp.non_reference_flag) {
1091 regs->reg0163_rfpw_h_addr = mpp_buffer_get_fd(recon_buf->buf[0]);
1092 regs->reg0164_rfpw_b_addr = regs->reg0163_rfpw_h_addr;
1093 mpp_dev_set_reg_offset(ctx->dev, 164, ctx->fbc_header_len);
1094 }
1095 regs->reg0165_rfpr_h_addr = mpp_buffer_get_fd(ref_buf->buf[0]);
1096 regs->reg0166_rfpr_b_addr = regs->reg0165_rfpr_h_addr;
1097 regs->reg0167_cmvw_addr = mpp_buffer_get_fd(recon_buf->buf[2]);
1098 regs->reg0168_cmvr_addr = mpp_buffer_get_fd(ref_buf->buf[2]);
1099 regs->reg0169_dspw_addr = mpp_buffer_get_fd(recon_buf->buf[1]);
1100 regs->reg0170_dspr_addr = mpp_buffer_get_fd(ref_buf->buf[1]);
1101
1102 mpp_dev_set_reg_offset(ctx->dev, 166, ctx->fbc_header_len);
1103
1104 if (md_info_buf) {
1105 regs->reg0192_enc_pic.mei_stor = 1;
1106 regs->reg0171_meiw_addr = mpp_buffer_get_fd(md_info_buf);
1107 } else {
1108 regs->reg0192_enc_pic.mei_stor = 0;
1109 regs->reg0171_meiw_addr = 0;
1110 }
1111
1112 regs->reg0172_bsbt_addr = mpp_buffer_get_fd(enc_task->output);
1113 /* TODO: stream size relative with syntax */
1114 regs->reg0173_bsbb_addr = regs->reg0172_bsbt_addr;
1115 regs->reg0175_bsbr_addr = regs->reg0172_bsbt_addr;
1116 regs->reg0174_adr_bsbs = regs->reg0172_bsbt_addr;
1117
1118 regs->reg0180_adr_rfpt_h = 0xffffffff;
1119 regs->reg0181_adr_rfpb_h = 0;
1120 regs->reg0182_adr_rfpt_b = 0xffffffff;
1121 regs->reg0183_adr_rfpb_b = 0;
1122
1123
1124 mpp_dev_set_reg_offset(ctx->dev, 174, mpp_packet_get_length(task->packet));
1125 mpp_dev_set_reg_offset(ctx->dev, 172, mpp_buffer_get_size(enc_task->output));
1126
1127 regs->reg0204_pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
1128 regs->reg0204_pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
1129 }
1130
setup_vepu540c_ext_line_buf(H265eV540cHalContext * ctx,H265eV540cRegSet * regs)1131 static void setup_vepu540c_ext_line_buf(H265eV540cHalContext *ctx, H265eV540cRegSet *regs)
1132 {
1133 if (ctx->ext_line_buf) {
1134 RK_S32 fd = mpp_buffer_get_fd(ctx->ext_line_buf);
1135
1136 regs->reg_base.reg0179_adr_ebufb = fd;
1137 regs->reg_base.reg0178_adr_ebuft = fd;
1138 mpp_dev_set_reg_offset(ctx->dev, 178, ctx->ext_line_buf_size);
1139 } else {
1140 regs->reg_base.reg0179_adr_ebufb = 0;
1141 regs->reg_base.reg0178_adr_ebuft = 0;
1142 }
1143 }
1144
hal_h265e_v540c_gen_regs(void * hal,HalEncTask * task)1145 MPP_RET hal_h265e_v540c_gen_regs(void *hal, HalEncTask *task)
1146 {
1147 H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal;
1148 HalEncTask *enc_task = task;
1149 H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data;
1150 H265eV540cRegSet *regs = ctx->regs;
1151 RK_U32 pic_width_align8, pic_height_align8;
1152 RK_S32 pic_wd32, pic_h32;
1153 VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
1154 hevc_vepu540c_control_cfg *reg_ctl = ®s->reg_ctl;
1155 hevc_vepu540c_base *reg_base = ®s->reg_base;
1156 hevc_vepu540c_rc_roi *reg_klut = ®s->reg_rc_roi;
1157
1158 hal_h265e_enter();
1159 pic_width_align8 = (syn->pp.pic_width + 7) & (~7);
1160 pic_height_align8 = (syn->pp.pic_height + 7) & (~7);
1161 pic_wd32 = (syn->pp.pic_width + 31) / 32;
1162 pic_h32 = (syn->pp.pic_height + 31) / 32;
1163
1164 hal_h265e_dbg_simple("frame %d | type %d | start gen regs",
1165 ctx->frame_cnt, ctx->frame_type);
1166
1167 memset(regs, 0, sizeof(H265eV540cRegSet));
1168
1169 reg_ctl->reg0004_enc_strt.lkt_num = 0;
1170 reg_ctl->reg0004_enc_strt.vepu_cmd = ctx->enc_mode;
1171 reg_ctl->reg0005_enc_clr.safe_clr = 0x0;
1172 reg_ctl->reg0005_enc_clr.force_clr = 0x0;
1173
1174 reg_ctl->reg0008_int_en.enc_done_en = 1;
1175 reg_ctl->reg0008_int_en.lkt_node_done_en = 1;
1176 reg_ctl->reg0008_int_en.sclr_done_en = 1;
1177 reg_ctl->reg0008_int_en.vslc_done_en = 1;
1178 reg_ctl->reg0008_int_en.vbsf_oflw_en = 1;
1179 reg_ctl->reg0008_int_en.vbuf_lens_en = 1;
1180 reg_ctl->reg0008_int_en.enc_err_en = 1;
1181 reg_ctl->reg0008_int_en.dvbm_fcfg_en = 1;
1182 reg_ctl->reg0008_int_en.wdg_en = 1;
1183 reg_ctl->reg0008_int_en.lkt_err_int_en = 0;
1184 reg_ctl->reg0008_int_en.lkt_err_stop_en = 1;
1185 reg_ctl->reg0008_int_en.lkt_force_stop_en = 1;
1186 reg_ctl->reg0008_int_en.jslc_done_en = 1;
1187 reg_ctl->reg0008_int_en.jbsf_oflw_en = 1;
1188 reg_ctl->reg0008_int_en.jbuf_lens_en = 1;
1189 reg_ctl->reg0008_int_en.dvbm_dcnt_en = 1;
1190
1191 reg_ctl->reg0012_dtrns_map.jpeg_bus_edin = 0x0;
1192 reg_ctl->reg0012_dtrns_map.src_bus_edin = 0x0;
1193 reg_ctl->reg0012_dtrns_map.meiw_bus_edin = 0x0;
1194 reg_ctl->reg0012_dtrns_map.bsw_bus_edin = 0x7;
1195 reg_ctl->reg0012_dtrns_map.lktr_bus_edin = 0x0;
1196 reg_ctl->reg0012_dtrns_map.roir_bus_edin = 0x0;
1197 reg_ctl->reg0012_dtrns_map.lktw_bus_edin = 0x0;
1198 reg_ctl->reg0012_dtrns_map.rec_nfbc_bus_edin = 0x0;
1199
1200 // reg_ctl->reg0013_dtrns_cfg.dspr_otsd = (ctx->frame_type == INTER_P_FRAME);
1201 reg_ctl->reg0013_dtrns_cfg.axi_brsp_cke = 0x0;
1202 reg_ctl->reg0014_enc_wdg.vs_load_thd = 0x1fffff;
1203 reg_ctl->reg0014_enc_wdg.rfp_load_thd = 0;
1204
1205 reg_ctl->reg0021_func_en.cke = 1;
1206 reg_ctl->reg0021_func_en.resetn_hw_en = 1;
1207 reg_ctl->reg0021_func_en.enc_done_tmvp_en = 1;
1208
1209 reg_base->reg0196_enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1;
1210 reg_base->reg0197_src_fill.pic_wfill = (syn->pp.pic_width & 0x7)
1211 ? (8 - (syn->pp.pic_width & 0x7)) : 0;
1212 reg_base->reg0196_enc_rsl.pic_hd8_m1 = pic_height_align8 / 8 - 1;
1213 reg_base->reg0197_src_fill.pic_hfill = (syn->pp.pic_height & 0x7)
1214 ? (8 - (syn->pp.pic_height & 0x7)) : 0;
1215
1216 reg_base->reg0192_enc_pic.enc_stnd = 1; //H265
1217 reg_base->reg0192_enc_pic.cur_frm_ref = !syn->sp.non_reference_flag; //current frame will be refered
1218 reg_base->reg0192_enc_pic.bs_scp = 1;
1219 reg_base->reg0192_enc_pic.log2_ctu_num = mpp_ceil_log2(pic_wd32 * pic_h32);
1220
1221 reg_base->reg0203_src_proc.src_mirr = 0;
1222 reg_base->reg0203_src_proc.src_rot = 0;
1223
1224 reg_klut->klut_ofst.chrm_klut_ofst = (ctx->frame_type == INTRA_FRAME) ? 0 : 3;
1225
1226 reg_base->reg0216_sli_splt.sli_splt_mode = syn->sp.sli_splt_mode;
1227 reg_base->reg0216_sli_splt.sli_splt_cpst = syn->sp.sli_splt_cpst;
1228 reg_base->reg0216_sli_splt.sli_splt = syn->sp.sli_splt;
1229 reg_base->reg0216_sli_splt.sli_flsh = syn->sp.sli_flsh;
1230 reg_base->reg0216_sli_splt.sli_max_num_m1 = syn->sp.sli_max_num_m1;
1231
1232 reg_base->reg0218_sli_cnum.sli_splt_cnum_m1 = syn->sp.sli_splt_cnum_m1;
1233 reg_base->reg0217_sli_byte.sli_splt_byte = syn->sp.sli_splt_byte;
1234
1235 vepu540c_h265_set_me_regs(ctx, syn, reg_base);
1236
1237 reg_base->reg0232_rdo_cfg.chrm_spcl = 0;
1238 reg_base->reg0232_rdo_cfg.cu_inter_e = 0x0092;
1239 reg_base->reg0232_rdo_cfg.cu_intra_e = 0xe;
1240
1241 if (syn->pp.num_long_term_ref_pics_sps) {
1242 reg_base->reg0232_rdo_cfg.ltm_col = 0;
1243 reg_base->reg0232_rdo_cfg.ltm_idx0l0 = 1;
1244 } else {
1245 reg_base->reg0232_rdo_cfg.ltm_col = 0;
1246 reg_base->reg0232_rdo_cfg.ltm_idx0l0 = 0;
1247 }
1248
1249 reg_base->reg0232_rdo_cfg.ccwa_e = 1;
1250 reg_base->reg0232_rdo_cfg.scl_lst_sel = syn->pp.scaling_list_enabled_flag;
1251 {
1252 RK_U32 i_nal_type = 0;
1253
1254 /* TODO: extend syn->frame_coding_type definition */
1255 if (ctx->frame_type == INTRA_FRAME) {
1256 /* reset ref pictures */
1257 i_nal_type = NAL_IDR_W_RADL;
1258 } else if (ctx->frame_type == INTER_P_FRAME ) {
1259 i_nal_type = NAL_TRAIL_R;
1260 } else {
1261 i_nal_type = NAL_TRAIL_R;
1262 }
1263 reg_base->reg0236_synt_nal.nal_unit_type = i_nal_type;
1264 }
1265
1266 vepu540c_h265_set_hw_address(ctx, reg_base, task);
1267 vepu540c_h265_set_pp_regs(regs, fmt, &ctx->cfg->prep);
1268 vepu540c_h265_set_rc_regs(ctx, regs, task);
1269 vepu540c_h265_set_slice_regs(syn, reg_base);
1270 vepu540c_h265_set_ref_regs(syn, reg_base);
1271 vepu540c_h265_set_patch_info(ctx->dev, syn, (Vepu541Fmt)fmt->format, enc_task);
1272 setup_vepu540c_ext_line_buf(ctx, ctx->regs);
1273
1274 /* ROI configure */
1275 if (ctx->roi_data)
1276 vepu540c_set_roi(®s->reg_rc_roi.roi_cfg, ctx->roi_data,
1277 ctx->cfg->prep.width, ctx->cfg->prep.height);
1278 /*paramet cfg*/
1279 vepu540c_h265_global_cfg_set(ctx, regs);
1280
1281 ctx->frame_num++;
1282
1283 hal_h265e_leave();
1284 return MPP_OK;
1285 }
1286
hal_h265e_v540c_start(void * hal,HalEncTask * enc_task)1287 MPP_RET hal_h265e_v540c_start(void *hal, HalEncTask *enc_task)
1288 {
1289 MPP_RET ret = MPP_OK;
1290 H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal;
1291 RK_U32 *regs = (RK_U32*)ctx->regs;
1292 H265eV540cRegSet *hw_regs = ctx->regs;
1293 H265eV540cStatusElem *reg_out = (H265eV540cStatusElem *)ctx->reg_out[0];
1294 MppDevRegWrCfg cfg;
1295 MppDevRegRdCfg cfg1;
1296 RK_U32 i = 0;
1297 hal_h265e_enter();
1298
1299 if (enc_task->flags.err) {
1300 hal_h265e_err("enc_task->flags.err %08x, return e arly",
1301 enc_task->flags.err);
1302 return MPP_NOK;
1303 }
1304
1305 cfg.reg = (RK_U32*)&hw_regs->reg_ctl;
1306 cfg.size = sizeof(hevc_vepu540c_control_cfg);
1307 cfg.offset = VEPU540C_CTL_OFFSET;
1308
1309 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
1310 if (ret) {
1311 mpp_err_f("set register write failed %d\n", ret);
1312 return ret;
1313 }
1314
1315 if (hal_h265e_debug & HAL_H265E_DBG_CTL_REGS) {
1316 regs = (RK_U32*)&hw_regs->reg_ctl;
1317 for (i = 0; i < sizeof(hevc_vepu540c_control_cfg) / 4; i++) {
1318 hal_h265e_dbg_ctl("ctl reg[%04x]: 0%08x\n", i * 4, regs[i]);
1319 }
1320 }
1321
1322 cfg.reg = &hw_regs->reg_base;
1323 cfg.size = sizeof(hevc_vepu540c_base);
1324 cfg.offset = VEPU540C_BASE_OFFSET;
1325
1326 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
1327 if (ret) {
1328 mpp_err_f("set register write failed %d\n", ret);
1329 return ret;
1330 }
1331
1332 if (hal_h265e_debug & HAL_H265E_DBG_REGS) {
1333 regs = (RK_U32*)(&hw_regs->reg_base);
1334 for (i = 0; i < 32; i++) {
1335 hal_h265e_dbg_regs("hw add cfg reg[%04x]: 0%08x\n", i * 4, regs[i]);
1336 }
1337 regs += 32;
1338 for (i = 0; i < (sizeof(hevc_vepu540c_base) - 128) / 4; i++) {
1339 hal_h265e_dbg_regs("set reg[%04x]: 0%08x\n", i * 4, regs[i]);
1340 }
1341 }
1342 cfg.reg = &hw_regs->reg_rc_roi;
1343 cfg.size = sizeof(hevc_vepu540c_rc_roi);
1344 cfg.offset = VEPU540C_RCROI_OFFSET;
1345
1346 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
1347 if (ret) {
1348 mpp_err_f("set register write failed %d\n", ret);
1349 return ret;
1350 }
1351
1352 if (hal_h265e_debug & HAL_H265E_DBG_RCKUT_REGS) {
1353 regs = (RK_U32*)&hw_regs->reg_rc_roi;
1354 for (i = 0; i < sizeof(hevc_vepu540c_rc_roi) / 4; i++) {
1355 hal_h265e_dbg_rckut("set reg[%04x]: 0%08x\n", i * 4, regs[i]);
1356 }
1357 }
1358
1359 cfg.reg = &hw_regs->reg_wgt;
1360 cfg.size = sizeof(hevc_vepu540c_wgt);
1361 cfg.offset = VEPU540C_WEG_OFFSET;
1362
1363 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
1364 if (ret) {
1365 mpp_err_f("set register write failed %d\n", ret);
1366 return ret;
1367 }
1368
1369 if (hal_h265e_debug & HAL_H265E_DBG_WGT_REGS) {
1370 regs = (RK_U32*)&hw_regs->reg_wgt;
1371 for (i = 0; i < sizeof(hevc_vepu540c_wgt) / 4; i++) {
1372 hal_h265e_dbg_wgt("set reg[%04x]: 0%08x\n", i * 4, regs[i]);
1373 }
1374 }
1375
1376 cfg.reg = &hw_regs->reg_rdo;
1377 cfg.size = sizeof(vepu540c_rdo_cfg);
1378 cfg.offset = VEPU540C_RDOCFG_OFFSET;
1379
1380 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
1381 if (ret) {
1382 mpp_err_f("set register write failed %d\n", ret);
1383 return ret;
1384 }
1385
1386 cfg1.reg = ®_out->hw_status;
1387 cfg1.size = sizeof(RK_U32);
1388 cfg1.offset = VEPU540C_REG_BASE_HW_STATUS;
1389
1390 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
1391 if (ret) {
1392 mpp_err_f("set register read failed %d\n", ret);
1393 return ret;
1394 }
1395
1396 cfg1.reg = ®_out->st;
1397 cfg1.size = sizeof(H265eV540cStatusElem) - 4;
1398 cfg1.offset = VEPU540C_STATUS_OFFSET;
1399
1400 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
1401 if (ret) {
1402 mpp_err_f("set register read failed %d\n", ret);
1403 return ret;
1404 }
1405
1406 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
1407 if (ret) {
1408 mpp_err_f("send cmd failed %d\n", ret);
1409 }
1410 hal_h265e_leave();
1411 return ret;
1412 }
1413
vepu540c_h265_set_feedback(H265eV540cHalContext * ctx,HalEncTask * enc_task)1414 static MPP_RET vepu540c_h265_set_feedback(H265eV540cHalContext *ctx, HalEncTask *enc_task)
1415 {
1416 EncRcTaskInfo *hal_rc_ret = (EncRcTaskInfo *)&enc_task->rc_task->info;
1417 vepu540c_h265_fbk *fb = &ctx->feedback;
1418 MppEncCfgSet *cfg = ctx->cfg;
1419 RK_S32 mb64_num = ((cfg->prep.width + 63) / 64) * ((cfg->prep.height + 63) / 64);
1420 RK_S32 mb8_num = (mb64_num << 6);
1421 RK_S32 mb4_num = (mb8_num << 2);
1422 H265eV540cStatusElem *elem = (H265eV540cStatusElem *)ctx->reg_out[0];
1423 RK_U32 hw_status = elem->hw_status;
1424
1425 hal_h265e_enter();
1426
1427 fb->qp_sum += elem->st.qp_sum;
1428
1429 fb->out_strm_size += elem->st.bs_lgth_l32;
1430
1431 fb->sse_sum += (RK_S64)(elem->st.sse_h32 << 16) +
1432 ((elem->st.st_sse_bsl.sse_l16 >> 16) & 0xffff) ;
1433
1434 fb->hw_status = hw_status;
1435 hal_h265e_dbg_detail("hw_status: 0x%08x", hw_status);
1436 if (hw_status & RKV_ENC_INT_LINKTABLE_FINISH)
1437 hal_h265e_err("RKV_ENC_INT_LINKTABLE_FINISH");
1438
1439 if (hw_status & RKV_ENC_INT_ONE_FRAME_FINISH)
1440 hal_h265e_dbg_detail("RKV_ENC_INT_ONE_FRAME_FINISH");
1441
1442 if (hw_status & RKV_ENC_INT_ONE_SLICE_FINISH)
1443 hal_h265e_err("RKV_ENC_INT_ONE_SLICE_FINISH");
1444
1445 if (hw_status & RKV_ENC_INT_SAFE_CLEAR_FINISH)
1446 hal_h265e_err("RKV_ENC_INT_SAFE_CLEAR_FINISH");
1447
1448 if (hw_status & RKV_ENC_INT_BIT_STREAM_OVERFLOW)
1449 hal_h265e_err("RKV_ENC_INT_BIT_STREAM_OVERFLOW");
1450
1451 if (hw_status & RKV_ENC_INT_BUS_WRITE_FULL)
1452 hal_h265e_err("RKV_ENC_INT_BUS_WRITE_FULL");
1453
1454 if (hw_status & RKV_ENC_INT_BUS_WRITE_ERROR)
1455 hal_h265e_err("RKV_ENC_INT_BUS_WRITE_ERROR");
1456
1457 if (hw_status & RKV_ENC_INT_BUS_READ_ERROR)
1458 hal_h265e_err("RKV_ENC_INT_BUS_READ_ERROR");
1459
1460 if (hw_status & RKV_ENC_INT_TIMEOUT_ERROR)
1461 hal_h265e_err("RKV_ENC_INT_TIMEOUT_ERROR");
1462
1463 // fb->st_madi += elem->st.madi;
1464 //fb->st_madp += elem->st.madp;
1465 fb->st_mb_num += elem->st.st_bnum_b16.num_b16;
1466 // fb->st_ctu_num += elem->st.st_bnum_cme.num_ctu;
1467
1468 fb->st_lvl64_inter_num += elem->st.st_pnum_p64.pnum_p64;
1469 fb->st_lvl32_inter_num += elem->st.st_pnum_p32.pnum_p32;
1470 fb->st_lvl32_intra_num += elem->st.st_pnum_i32.pnum_i32;
1471 fb->st_lvl16_inter_num += elem->st.st_pnum_p16.pnum_p16;
1472 fb->st_lvl16_intra_num += elem->st.st_pnum_i16.pnum_i16;
1473 fb->st_lvl8_inter_num += elem->st.st_pnum_p8.pnum_p8;
1474 fb->st_lvl8_intra_num += elem->st.st_pnum_i8.pnum_i8;
1475 fb->st_lvl4_intra_num += elem->st.st_pnum_i4.pnum_i4;
1476 memcpy(&fb->st_cu_num_qp[0], &elem->st.st_b8_qp, 52 * sizeof(RK_U32));
1477
1478 hal_rc_ret->bit_real += fb->out_strm_size * 8;
1479
1480 if (fb->st_mb_num) {
1481 fb->st_madi = fb->st_madi / fb->st_mb_num;
1482 } else {
1483 fb->st_madi = 0;
1484 }
1485 if (fb->st_ctu_num) {
1486 fb->st_madp = fb->st_madp / fb->st_ctu_num;
1487 } else {
1488 fb->st_madp = 0;
1489 }
1490
1491 if (mb4_num > 0)
1492 hal_rc_ret->iblk4_prop = ((((fb->st_lvl4_intra_num + fb->st_lvl8_intra_num) << 2) +
1493 (fb->st_lvl16_intra_num << 4) +
1494 (fb->st_lvl32_intra_num << 6)) << 8) / mb4_num;
1495
1496 if (mb64_num > 0) {
1497 /*
1498 hal_cfg[k].inter_lv8_prop = ((fb->st_lvl8_inter_num + (fb->st_lvl16_inter_num << 2) +
1499 (fb->st_lvl32_inter_num << 4) +
1500 (fb->st_lvl64_inter_num << 6)) << 8) / mb8_num;*/
1501
1502 hal_rc_ret->quality_real = fb->qp_sum / mb8_num;
1503 // hal_cfg[k].sse = fb->sse_sum / mb64_num;
1504 }
1505
1506 hal_rc_ret->madi = fb->st_madi;
1507 hal_rc_ret->madp = fb->st_madp;
1508 hal_h265e_leave();
1509 return MPP_OK;
1510 }
1511
1512
1513 //#define DUMP_DATA
hal_h265e_v540c_wait(void * hal,HalEncTask * task)1514 MPP_RET hal_h265e_v540c_wait(void *hal, HalEncTask *task)
1515 {
1516 MPP_RET ret = MPP_OK;
1517 H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal;
1518 HalEncTask *enc_task = task;
1519 H265eV540cStatusElem *elem = (H265eV540cStatusElem *)ctx->reg_out;
1520 hal_h265e_enter();
1521
1522 if (enc_task->flags.err) {
1523 hal_h265e_err("enc_task->flags.err %08x, return early",
1524 enc_task->flags.err);
1525 return MPP_NOK;
1526 }
1527
1528 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
1529
1530 #ifdef DUMP_DATA
1531 static FILE *fp_fbd = NULL;
1532 static FILE *fp_fbh = NULL;
1533 static FILE *fp_dws = NULL;
1534 HalBuf *recon_buf;
1535 static RK_U32 frm_num = 0;
1536 H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data;
1537 recon_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.recon_pic.slot_idx);
1538 char file_name[20] = "";
1539 size_t rec_size = mpp_buffer_get_size(recon_buf->buf[0]);
1540 size_t dws_size = mpp_buffer_get_size(recon_buf->buf[1]);
1541
1542 void *ptr = mpp_buffer_get_ptr(recon_buf->buf[0]);
1543 void *dws_ptr = mpp_buffer_get_ptr(recon_buf->buf[1]);
1544
1545 sprintf(&file_name[0], "fbd%d.bin", frm_num);
1546 if (fp_fbd != NULL) {
1547 fclose(fp_fbd);
1548 fp_fbd = NULL;
1549 } else {
1550 fp_fbd = fopen(file_name, "wb+");
1551 }
1552 if (fp_fbd) {
1553 fwrite(ptr + ctx->fbc_header_len, 1, rec_size - ctx->fbc_header_len, fp_fbd);
1554 fflush(fp_fbd);
1555 }
1556
1557 sprintf(&file_name[0], "fbh%d.bin", frm_num);
1558
1559 if (fp_fbh != NULL) {
1560 fclose(fp_fbh);
1561 fp_fbh = NULL;
1562 } else {
1563 fp_fbh = fopen(file_name, "wb+");
1564 }
1565
1566 if (fp_fbh) {
1567 fwrite(ptr , 1, ctx->fbc_header_len, fp_fbh);
1568 fflush(fp_fbh);
1569 }
1570
1571
1572 sprintf(&file_name[0], "dws%d.bin", frm_num);
1573
1574 if (fp_dws != NULL) {
1575 fclose(fp_dws);
1576 fp_dws = NULL;
1577 } else {
1578 fp_dws = fopen(file_name, "wb+");
1579 }
1580
1581 if (fp_dws) {
1582 fwrite(dws_ptr , 1, dws_size, fp_dws);
1583 fflush(fp_dws);
1584 }
1585 frm_num++;
1586 #endif
1587 if (ret)
1588 mpp_err_f("poll cmd failed %d status %d \n", ret, elem->hw_status);
1589
1590 hal_h265e_leave();
1591 return ret;
1592 }
1593
hal_h265e_v540c_get_task(void * hal,HalEncTask * task)1594 MPP_RET hal_h265e_v540c_get_task(void *hal, HalEncTask *task)
1595 {
1596 H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal;
1597 MppFrame frame = task->frame;
1598 EncFrmStatus *frm_status = &task->rc_task->frm;
1599
1600 hal_h265e_enter();
1601
1602 if (vepu540c_h265_setup_hal_bufs(ctx)) {
1603 hal_h265e_err("vepu541_h265_allocate_buffers failed, free buffers and return\n");
1604 task->flags.err |= HAL_ENC_TASK_ERR_ALLOC;
1605 return MPP_ERR_MALLOC;
1606 }
1607
1608 ctx->last_frame_type = ctx->frame_type;
1609 if (frm_status->is_intra) {
1610 ctx->frame_type = INTRA_FRAME;
1611 } else {
1612 ctx->frame_type = INTER_P_FRAME;
1613 }
1614 if (!frm_status->reencode && mpp_frame_has_meta(task->frame)) {
1615 MppMeta meta = mpp_frame_get_meta(frame);
1616
1617 mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data);
1618 }
1619 memset(&ctx->feedback, 0, sizeof(vepu540c_h265_fbk));
1620
1621 hal_h265e_leave();
1622 return MPP_OK;
1623 }
1624
hal_h265e_v540c_ret_task(void * hal,HalEncTask * task)1625 MPP_RET hal_h265e_v540c_ret_task(void *hal, HalEncTask *task)
1626 {
1627 H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal;
1628 HalEncTask *enc_task = task;
1629 vepu540c_h265_fbk *fb = &ctx->feedback;
1630 hal_h265e_enter();
1631
1632 vepu540c_h265_set_feedback(ctx, enc_task);
1633 enc_task->hw_length = fb->out_strm_size;
1634 enc_task->length += fb->out_strm_size;
1635
1636 hal_h265e_dbg_detail("output stream size %d\n", fb->out_strm_size);
1637
1638 hal_h265e_leave();
1639 return MPP_OK;
1640 }
1641
1642 const MppEncHalApi hal_h265e_vepu540c = {
1643 "hal_h265e_v540c",
1644 MPP_VIDEO_CodingHEVC,
1645 sizeof(H265eV540cHalContext),
1646 0,
1647 hal_h265e_v540c_init,
1648 hal_h265e_v540c_deinit,
1649 hal_h265e_vepu540c_prepare,
1650 hal_h265e_v540c_get_task,
1651 hal_h265e_v540c_gen_regs,
1652 hal_h265e_v540c_start,
1653 hal_h265e_v540c_wait,
1654 NULL,
1655 NULL,
1656 hal_h265e_v540c_ret_task,
1657 };
1658