1 /* 2 * Copyright 2015 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __RK_VENC_CMD_H__ 18 #define __RK_VENC_CMD_H__ 19 20 #include "mpp_frame.h" 21 #include "rk_venc_rc.h" 22 23 /* 24 * Configure of encoder is very complicated. So we divide configures into 25 * four parts: 26 * 27 * 1. Rate control parameter 28 * This is quality and bitrate request from user. 29 * 30 * 2. Data source MppFrame parameter 31 * This is data source buffer information. 32 * Now it is PreP config 33 * PreP : Encoder Preprocess configuration 34 * 35 * 3. Video codec infomation 36 * This is user custormized stream information. 37 * including: 38 * H.264 / H.265 / vp8 / mjpeg 39 * 40 * 4. Misc parameter 41 * including: 42 * Split : Slice split configuration 43 * GopRef: Reference gop configuration 44 * ROI : Region Of Interest 45 * OSD : On Screen Display 46 * MD : Motion Detection 47 * 48 * The module transcation flow is as follows: 49 * 50 * + + 51 * User | Mpi/Mpp | EncImpl 52 * | | Hal 53 * | | 54 * +----------+ | +---------+ | +-----------+ 55 * | | | | +-----RcCfg-----> | 56 * | RcCfg +---------> | | | EncImpl | 57 * | | | | | +-Frame-----> | 58 * +----------+ | | | | | +--+-----^--+ 59 * | | | | | | | 60 * | | | | | | | 61 * +----------+ | | | | | syntax | 62 * | | | | | | | | | 63 * | MppFrame +---------> MppEnc +---+ | | result 64 * | | | | | | | | | 65 * +----------+ | | | | | | | 66 * | | | | | +--v-----+--+ 67 * | | | +-Frame-----> | 68 * +----------+ | | | | | | 69 * | | | | +---CodecCfg----> Hal | 70 * | CodecCfg +---------> | | | | 71 * | | | | <-----Extra-----> | 72 * +----------+ | +---------+ | +-----------+ 73 * | | 74 * | | 75 * + + 76 * 77 * The function call flow is shown below: 78 * 79 * mpi mpp_enc controller hal 80 * + + + + 81 * | | | | 82 * | | | | 83 * +----------init------------> | | 84 * | | | | 85 * | | | | 86 * | PrepCfg | | | 87 * +---------control----------> PrepCfg | | 88 * | +-----control-----> | 89 * | | | PrepCfg | 90 * | +--------------------------control--------> 91 * | | | allocate 92 * | | | buffer 93 * | | | | 94 * | RcCfg | | | 95 * +---------control----------> RcCfg | | 96 * | +-----control-----> | 97 * | | rc_init | 98 * | | | | 99 * | | | | 100 * | CodecCfg | | | 101 * +---------control----------> | CodecCfg | 102 * | +--------------------------control--------> 103 * | | | generate 104 * | | | sps/pps 105 * | | | Get extra info | 106 * | +--------------------------control--------> 107 * | Get extra info | | | 108 * +---------control----------> | | 109 * | | | | 110 * | | | | 111 * | ROICfg | | | 112 * +---------control----------> | ROICfg | 113 * | +--------------------------control--------> 114 * | | | | 115 * | OSDCfg | | | 116 * +---------control----------> | OSDCfg | 117 * | +--------------------------control--------> 118 * | | | | 119 * | MDCfg | | | 120 * +---------control----------> | MDCfg | 121 * | +--------------------------control--------> 122 * | | | | 123 * | Set extra info | | | 124 * +---------control----------> | Set extra info | 125 * | +--------------------------control--------> 126 * | | | | 127 * | task | | | 128 * +----------encode----------> task | | 129 * | +-----encode------> | 130 * | | encode | 131 * | | | syntax | 132 * | +--------------------------gen_reg--------> 133 * | | | | 134 * | | | | 135 * | +---------------------------start---------> 136 * | | | | 137 * | | | | 138 * | +---------------------------wait----------> 139 * | | | | 140 * | | callback | | 141 * | +-----------------> | 142 * +--OSD-MD--encode----------> | | 143 * | . | | | 144 * | . | | | 145 * | . | | | 146 * +--OSD-MD--encode----------> | | 147 * | | | | 148 * +----------deinit----------> | | 149 * + + + + 150 */ 151 152 /* 153 * encoder query interface is only for debug usage 154 */ 155 #define MPP_ENC_QUERY_STATUS (0x00000001) 156 #define MPP_ENC_QUERY_WAIT (0x00000002) 157 #define MPP_ENC_QUERY_FPS (0x00000004) 158 #define MPP_ENC_QUERY_BPS (0x00000008) 159 #define MPP_ENC_QUERY_ENC_IN_FRM (0x00000010) 160 #define MPP_ENC_QUERY_ENC_WORK (0x00000020) 161 #define MPP_ENC_QUERY_ENC_OUT_PKT (0x00000040) 162 163 #define MPP_ENC_QUERY_ALL (MPP_ENC_QUERY_STATUS | \ 164 MPP_ENC_QUERY_WAIT | \ 165 MPP_ENC_QUERY_FPS | \ 166 MPP_ENC_QUERY_BPS | \ 167 MPP_ENC_QUERY_ENC_IN_FRM | \ 168 MPP_ENC_QUERY_ENC_WORK | \ 169 MPP_ENC_QUERY_ENC_OUT_PKT) 170 171 typedef struct MppEncQueryCfg_t { 172 /* 173 * 32 bit query flag for query data check 174 * Each bit represent a query data switch. 175 * bit 0 - for querying encoder runtime status 176 * bit 1 - for querying encoder runtime waiting status 177 * bit 2 - for querying encoder realtime encode fps 178 * bit 3 - for querying encoder realtime output bps 179 * bit 4 - for querying encoder input frame count 180 * bit 5 - for querying encoder start hardware times 181 * bit 6 - for querying encoder output packet count 182 */ 183 RK_U32 query_flag; 184 185 /* 64 bit query data output */ 186 RK_U32 rt_status; 187 RK_U32 rt_wait; 188 RK_U32 rt_fps; 189 RK_U32 rt_bps; 190 RK_U32 enc_in_frm_cnt; 191 RK_U32 enc_hw_run_cnt; 192 RK_U32 enc_out_pkt_cnt; 193 } MppEncQueryCfg; 194 195 /* 196 * base working mode parameter 197 */ 198 typedef enum MppEncBaseCfgChange_e { 199 MPP_ENC_BASE_CFG_CHANGE_LOW_DELAY = (1 << 0), 200 MPP_ENC_BASE_CFG_CHANGE_ALL = (0xFFFFFFFF), 201 } MppEncBaseCfgChange; 202 203 typedef struct MppEncBaseCfg_t { 204 RK_U32 change; 205 206 RK_S32 low_delay; 207 } MppEncBaseCfg; 208 209 /* 210 * Rate control parameter 211 */ 212 typedef enum MppEncRcCfgChange_e { 213 MPP_ENC_RC_CFG_CHANGE_RC_MODE = (1 << 0), 214 MPP_ENC_RC_CFG_CHANGE_QUALITY = (1 << 1), 215 MPP_ENC_RC_CFG_CHANGE_BPS = (1 << 2), /* change on bps target / max / min */ 216 MPP_ENC_RC_CFG_CHANGE_FPS_IN = (1 << 5), /* change on fps in flex / numerator / denorminator */ 217 MPP_ENC_RC_CFG_CHANGE_FPS_OUT = (1 << 6), /* change on fps out flex / numerator / denorminator */ 218 MPP_ENC_RC_CFG_CHANGE_GOP = (1 << 7), 219 MPP_ENC_RC_CFG_CHANGE_SKIP_CNT = (1 << 8), 220 MPP_ENC_RC_CFG_CHANGE_MAX_REENC = (1 << 9), 221 MPP_ENC_RC_CFG_CHANGE_DROP_FRM = (1 << 10), 222 MPP_ENC_RC_CFG_CHANGE_MAX_I_PROP = (1 << 11), 223 MPP_ENC_RC_CFG_CHANGE_MIN_I_PROP = (1 << 12), 224 MPP_ENC_RC_CFG_CHANGE_INIT_IP_RATIO = (1 << 13), 225 MPP_ENC_RC_CFG_CHANGE_PRIORITY = (1 << 14), 226 MPP_ENC_RC_CFG_CHANGE_SUPER_FRM = (1 << 15), 227 /* qp related change flag */ 228 MPP_ENC_RC_CFG_CHANGE_QP_INIT = (1 << 16), 229 MPP_ENC_RC_CFG_CHANGE_QP_RANGE = (1 << 17), 230 MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I = (1 << 18), 231 MPP_ENC_RC_CFG_CHANGE_QP_MAX_STEP = (1 << 19), 232 MPP_ENC_RC_CFG_CHANGE_QP_IP = (1 << 20), 233 MPP_ENC_RC_CFG_CHANGE_QP_VI = (1 << 21), 234 MPP_ENC_RC_CFG_CHANGE_QP_ROW = (1 << 22), 235 MPP_ENC_RC_CFG_CHANGE_QP_ROW_I = (1 << 23), 236 MPP_ENC_RC_CFG_CHANGE_DEBREATH = (1 << 24), 237 MPP_ENC_RC_CFG_CHANGE_HIER_QP = (1 << 25), 238 MPP_ENC_RC_CFG_CHANGE_ST_TIME = (1 << 26), 239 MPP_ENC_RC_CFG_CHANGE_REFRESH = (1 << 27), 240 MPP_ENC_RC_CFG_CHANGE_GOP_REF_CFG = (1 << 28), 241 MPP_ENC_RC_CFG_CHANGE_ALL = (0xFFFFFFFF), 242 } MppEncRcCfgChange; 243 244 typedef enum MppEncRcQuality_e { 245 MPP_ENC_RC_QUALITY_WORST, 246 MPP_ENC_RC_QUALITY_WORSE, 247 MPP_ENC_RC_QUALITY_MEDIUM, 248 MPP_ENC_RC_QUALITY_BETTER, 249 MPP_ENC_RC_QUALITY_BEST, 250 MPP_ENC_RC_QUALITY_CQP, 251 MPP_ENC_RC_QUALITY_AQ_ONLY, 252 MPP_ENC_RC_QUALITY_BUTT 253 } MppEncRcQuality; 254 255 typedef struct MppEncRcCfg_t { 256 RK_U32 change; 257 258 /* 259 * rc_mode - rate control mode 260 * 261 * mpp provide two rate control mode: 262 * 263 * Constant Bit Rate (CBR) mode 264 * - paramter 'bps*' define target bps 265 * - paramter quality and qp will not take effect 266 * 267 * Variable Bit Rate (VBR) mode 268 * - paramter 'quality' define 5 quality levels 269 * - paramter 'bps*' is used as reference but not strict condition 270 * - special Constant QP (CQP) mode is under VBR mode 271 * CQP mode will work with qp in CodecCfg. But only use for test 272 * 273 * default: CBR 274 */ 275 MppEncRcMode rc_mode; 276 277 /* 278 * quality - quality parameter, only takes effect in VBR mode 279 * 280 * Mpp does not give the direct parameter in different protocol. 281 * 282 * Mpp provide total 5 quality level: 283 * Worst - worse - Medium - better - best 284 * 285 * extra CQP level means special constant-qp (CQP) mode 286 * 287 * default value: Medium 288 */ 289 MppEncRcQuality quality; 290 291 /* 292 * bit rate parameters 293 * mpp gives three bit rate control parameter for control 294 * bps_target - target bit rate, unit: bit per second 295 * bps_max - maximun bit rate, unit: bit per second 296 * bps_min - minimun bit rate, unit: bit per second 297 * if user need constant bit rate set parameters to the similar value 298 * if user need variable bit rate set parameters as they need 299 */ 300 RK_S32 bps_target; 301 RK_S32 bps_max; 302 RK_S32 bps_min; 303 304 /* 305 * frame rate parameters have great effect on rate control 306 * 307 * fps_in_flex 308 * 0 - fix input frame rate 309 * 1 - variable input frame rate 310 * 311 * fps_in_num 312 * input frame rate numerator, if 0 then default 30 313 * 314 * fps_in_denorm 315 * input frame rate denorminator, if 0 then default 1 316 * 317 * fps_out_flex 318 * 0 - fix output frame rate 319 * 1 - variable output frame rate 320 * 321 * fps_out_num 322 * output frame rate numerator, if 0 then default 30 323 * 324 * fps_out_denorm 325 * output frame rate denorminator, if 0 then default 1 326 */ 327 RK_S32 fps_in_flex; 328 RK_S32 fps_in_num; 329 RK_S32 fps_in_denorm; 330 RK_S32 fps_out_flex; 331 RK_S32 fps_out_num; 332 RK_S32 fps_out_denorm; 333 334 /* 335 * gop - group of picture, gap between Intra frame 336 * 0 for only 1 I frame the rest are all P frames 337 * 1 for all I frame 338 * 2 for I P I P I P 339 * 3 for I P P I P P 340 * etc... 341 */ 342 RK_S32 gop; 343 void *ref_cfg; 344 345 /* 346 * skip_cnt - max continuous frame skip count 347 * 0 - frame skip is not allow 348 */ 349 RK_S32 skip_cnt; 350 351 /* 352 * max_reenc_times - max reencode time for one frame 353 * 0 - reencode is not allowed 354 * 1~3 max reencode time is limited to 3 355 */ 356 RK_U32 max_reenc_times; 357 358 /* 359 * stats_time - the time of bitrate statistics 360 */ 361 RK_S32 stats_time; 362 363 /* 364 * drop frame parameters 365 * used on bitrate is far over the max bitrate 366 * 367 * drop_mode 368 * 369 * MPP_ENC_RC_DROP_FRM_DISABLED 370 * - do not drop frame when bitrate overflow. 371 * MPP_ENC_RC_DROP_FRM_NORMAL 372 * - do not encode the dropped frame when bitrate overflow. 373 * MPP_ENC_RC_DROP_FRM_PSKIP 374 * - encode a all skip frame when bitrate overflow. 375 * 376 * drop_threshold 377 * 378 * The percentage threshold over max_bitrate for trigger frame drop. 379 * 380 * drop_gap 381 * The max continuous frame drop number 382 */ 383 MppEncRcDropFrmMode drop_mode; 384 RK_U32 drop_threshold; 385 RK_U32 drop_gap; 386 387 MppEncRcSuperFrameMode super_mode; 388 RK_U32 super_i_thd; 389 RK_U32 super_p_thd; 390 391 MppEncRcPriority rc_priority; 392 393 RK_U32 debreath_en; 394 RK_U32 debre_strength; 395 RK_S32 max_i_prop; 396 RK_S32 min_i_prop; 397 RK_S32 init_ip_ratio; 398 399 /* general qp control */ 400 RK_S32 qp_init; 401 RK_S32 qp_max; 402 RK_S32 qp_max_i; 403 RK_S32 qp_min; 404 RK_S32 qp_min_i; 405 RK_S32 qp_max_step; /* delta qp between each two P frame */ 406 RK_S32 qp_delta_ip; /* delta qp between I and P */ 407 RK_S32 qp_delta_vi; /* delta qp between vi and P */ 408 409 RK_S32 hier_qp_en; 410 RK_S32 hier_qp_delta[4]; 411 RK_S32 hier_frame_num[4]; 412 413 RK_U32 refresh_en; 414 MppEncRcRefreshMode refresh_mode; 415 RK_U32 refresh_num; 416 RK_S32 refresh_length; 417 } MppEncRcCfg; 418 419 420 typedef enum MppEncHwCfgChange_e { 421 /* qp related hardware config flag */ 422 MPP_ENC_HW_CFG_CHANGE_QP_ROW = (1 << 0), 423 MPP_ENC_HW_CFG_CHANGE_QP_ROW_I = (1 << 1), 424 MPP_ENC_HW_CFG_CHANGE_AQ_THRD_I = (1 << 2), 425 MPP_ENC_HW_CFG_CHANGE_AQ_THRD_P = (1 << 3), 426 MPP_ENC_HW_CFG_CHANGE_AQ_STEP_I = (1 << 4), 427 MPP_ENC_HW_CFG_CHANGE_AQ_STEP_P = (1 << 5), 428 MPP_ENC_HW_CFG_CHANGE_MB_RC = (1 << 6), 429 MPP_ENC_HW_CFG_CHANGE_CU_MODE_BIAS = (1 << 8), 430 MPP_ENC_HW_CFG_CHANGE_CU_SKIP_BIAS = (1 << 9), 431 MPP_ENC_HW_CFG_CHANGE_ALL = (0xFFFFFFFF), 432 } MppEncHwCfgChange; 433 434 /* 435 * Hardware related rate control config 436 * 437 * This config will open some detail feature to external user to control 438 * hardware behavior directly. 439 */ 440 typedef struct MppEncHwCfg_t { 441 RK_U32 change; 442 443 /* vepu541/vepu540 */ 444 RK_S32 qp_delta_row; /* delta qp between two row in P frame */ 445 RK_S32 qp_delta_row_i; /* delta qp between two row in I frame */ 446 RK_U32 aq_thrd_i[16]; 447 RK_U32 aq_thrd_p[16]; 448 RK_S32 aq_step_i[16]; 449 RK_S32 aq_step_p[16]; 450 451 /* vepu1/2 */ 452 RK_S32 mb_rc_disable; 453 454 /* vepu580 */ 455 RK_S32 extra_buf; 456 457 /* 458 * block mode decision bias config 459 * 0 - intra32x32 460 * 1 - intra16x16 461 * 2 - intra8x8 462 * 3 - intra4x4 463 * 4 - inter64x64 464 * 5 - inter32x32 465 * 6 - inter16x16 466 * 7 - inter8x8 467 * value range 0 ~ 15, default : 8 468 * If the value is smaller then encoder will be more likely to encode corresponding block mode. 469 */ 470 RK_S32 mode_bias[8]; 471 472 /* 473 * skip mode bias config 474 * skip_bias_en - enable flag for skip bias config 475 * skip_sad - sad threshold for skip / non-skip 476 * skip_bias - tendency for skip, value range 0 ~ 15, default : 8 477 * If the value is smaller then encoder will be more likely to encode skip block. 478 */ 479 RK_S32 skip_bias_en; 480 RK_S32 skip_sad; 481 RK_S32 skip_bias; 482 } MppEncHwCfg; 483 484 /* 485 * Mpp preprocess parameter 486 */ 487 typedef enum MppEncPrepCfgChange_e { 488 MPP_ENC_PREP_CFG_CHANGE_INPUT = (1 << 0), /* change on input config */ 489 MPP_ENC_PREP_CFG_CHANGE_FORMAT = (1 << 2), /* change on format */ 490 /* transform parameter */ 491 MPP_ENC_PREP_CFG_CHANGE_ROTATION = (1 << 4), /* change on rotation */ 492 MPP_ENC_PREP_CFG_CHANGE_MIRRORING = (1 << 5), /* change on mirroring */ 493 MPP_ENC_PREP_CFG_CHANGE_FLIP = (1 << 6), /* change on flip */ 494 /* enhancement parameter */ 495 MPP_ENC_PREP_CFG_CHANGE_DENOISE = (1 << 8), /* change on denoise */ 496 MPP_ENC_PREP_CFG_CHANGE_SHARPEN = (1 << 9), /* change on denoise */ 497 /* color related parameter */ 498 MPP_ENC_PREP_CFG_CHANGE_COLOR_RANGE = (1 << 16), /* change on color range */ 499 MPP_ENC_PREP_CFG_CHANGE_COLOR_SPACE = (1 << 17), /* change on color range */ 500 MPP_ENC_PREP_CFG_CHANGE_COLOR_PRIME = (1 << 18), /* change on color primaries */ 501 MPP_ENC_PREP_CFG_CHANGE_COLOR_TRC = (1 << 19), /* change on color transfer */ 502 503 MPP_ENC_PREP_CFG_CHANGE_ALL = (0xFFFFFFFF), 504 } MppEncPrepCfgChange; 505 506 /* 507 * Preprocess sharpen parameter 508 * 509 * 5x5 sharpen core 510 * 511 * enable_y - enable luma sharpen 512 * enable_uv - enable chroma sharpen 513 */ 514 typedef struct { 515 RK_U32 enable_y; 516 RK_U32 enable_uv; 517 RK_S32 coef[5]; 518 RK_S32 div; 519 RK_S32 threshold; 520 } MppEncPrepSharpenCfg; 521 522 /* 523 * input frame rotation parameter 524 * 0 - disable rotation 525 * 1 - 90 degree 526 * 2 - 180 degree 527 * 3 - 270 degree 528 */ 529 typedef enum MppEncRotationCfg_e { 530 MPP_ENC_ROT_0, 531 MPP_ENC_ROT_90, 532 MPP_ENC_ROT_180, 533 MPP_ENC_ROT_270, 534 MPP_ENC_ROT_BUTT 535 } MppEncRotationCfg; 536 537 typedef struct MppEncPrepCfg_t { 538 RK_U32 change; 539 540 /* 541 * Mpp encoder input data dimension config 542 * 543 * width / height / hor_stride / ver_stride / format 544 * These information will be used for buffer allocation and rc config init 545 * The output format is always YUV420. So if input is RGB then color 546 * conversion will be done internally 547 */ 548 RK_S32 width; 549 RK_S32 height; 550 RK_S32 hor_stride; 551 RK_S32 ver_stride; 552 553 /* 554 * Mpp encoder input data format config 555 */ 556 MppFrameFormat format; 557 MppFrameColorSpace color; 558 MppFrameColorPrimaries colorprim; 559 MppFrameColorTransferCharacteristic colortrc; 560 MppFrameColorRange range; 561 562 /* suffix ext means the user set config externally */ 563 MppEncRotationCfg rotation; 564 MppEncRotationCfg rotation_ext; 565 566 /* 567 * input frame mirroring parameter 568 * 0 - disable mirroring 569 * 1 - horizontal mirroring 570 */ 571 RK_S32 mirroring; 572 RK_S32 mirroring_ext; 573 574 /* 575 * input frame flip parameter 576 * 0 - disable flip 577 * 1 - flip, vertical mirror transformation 578 */ 579 RK_S32 flip; 580 581 /* 582 * TODO: 583 */ 584 RK_S32 denoise; 585 586 MppEncPrepSharpenCfg sharpen; 587 } MppEncPrepCfg; 588 589 /* 590 * Mpp Motion Detection parameter 591 * 592 * Mpp can output Motion Detection infomation for each frame. 593 * If user euqueue a encode task with KEY_MOTION_INFO by following function 594 * then encoder will output Motion Detection information to the buffer. 595 * 596 * mpp_task_meta_set_buffer(task, KEY_MOTION_INFO, buffer); 597 * 598 * Motion Detection information will be organized in this way: 599 * 1. Each 16x16 block will have a 32 bit block information which contains 600 * 15 bit SAD(Sum of Abstract Difference value 601 * 9 bit signed horizontal motion vector 602 * 8 bit signed vertical motion vector 603 * 2. The sequence of MD information in the buffer is corresponding to the 604 * block position in the frame, left-to right, top-to-bottom. 605 * 3. If the width of the frame is not a multiple of 256 pixels (16 macro 606 * blocks), DMA would extend the frame to a multiple of 256 pixels and 607 * the extended blocks' MD information are 32'h0000_0000. 608 * 4. Buffer must be ion buffer and 1024 byte aligned. 609 */ 610 typedef struct MppEncMDBlkInfo_t { 611 RK_U32 sad : 15; /* bit 0~14 - SAD */ 612 RK_S32 mvx : 9; /* bit 15~23 - signed horizontal mv */ 613 RK_S32 mvy : 8; /* bit 24~31 - signed vertical mv */ 614 } MppEncMDBlkInfo; 615 616 typedef enum MppEncHeaderMode_e { 617 /* default mode: attach vps/sps/pps only on first frame */ 618 MPP_ENC_HEADER_MODE_DEFAULT, 619 /* IDR mode: attach vps/sps/pps on each IDR frame */ 620 MPP_ENC_HEADER_MODE_EACH_IDR, 621 MPP_ENC_HEADER_MODE_BUTT, 622 } MppEncHeaderMode; 623 624 typedef enum MppEncSeiMode_e { 625 MPP_ENC_SEI_MODE_DISABLE, /* default mode, SEI writing is disabled */ 626 MPP_ENC_SEI_MODE_ONE_SEQ, /* one sequence has only one SEI */ 627 MPP_ENC_SEI_MODE_ONE_FRAME /* one frame may have one SEI, if SEI info has changed */ 628 } MppEncSeiMode; 629 630 /* 631 * Mpp codec parameter 632 * parameter is defined from here 633 */ 634 635 /* 636 * H.264 configurable parameter 637 */ 638 typedef enum MppEncH264CfgChange_e { 639 /* change on stream type */ 640 MPP_ENC_H264_CFG_STREAM_TYPE = (1 << 0), 641 /* change on svc / profile / level */ 642 MPP_ENC_H264_CFG_CHANGE_PROFILE = (1 << 1), 643 /* change on entropy_coding_mode / cabac_init_idc */ 644 MPP_ENC_H264_CFG_CHANGE_ENTROPY = (1 << 2), 645 646 /* change on transform8x8_mode */ 647 MPP_ENC_H264_CFG_CHANGE_TRANS_8x8 = (1 << 4), 648 /* change on constrained_intra_pred_mode */ 649 MPP_ENC_H264_CFG_CHANGE_CONST_INTRA = (1 << 5), 650 /* change on chroma_cb_qp_offset/ chroma_cr_qp_offset */ 651 MPP_ENC_H264_CFG_CHANGE_CHROMA_QP = (1 << 6), 652 /* change on deblock_disable / deblock_offset_alpha / deblock_offset_beta */ 653 MPP_ENC_H264_CFG_CHANGE_DEBLOCKING = (1 << 7), 654 /* change on use_longterm */ 655 MPP_ENC_H264_CFG_CHANGE_LONG_TERM = (1 << 8), 656 /* change on scaling_list_mode */ 657 MPP_ENC_H264_CFG_CHANGE_SCALING_LIST = (1 << 9), 658 /* change on poc type */ 659 MPP_ENC_H264_CFG_CHANGE_POC_TYPE = (1 << 10), 660 /* change on log2 max poc lsb minus 4 */ 661 MPP_ENC_H264_CFG_CHANGE_MAX_POC_LSB = (1 << 11), 662 /* change on log2 max frame number minus 4 */ 663 MPP_ENC_H264_CFG_CHANGE_MAX_FRM_NUM = (1 << 12), 664 /* change on gaps_in_frame_num_value_allowed_flag */ 665 MPP_ENC_H264_CFG_CHANGE_GAPS_IN_FRM_NUM = (1 << 13), 666 667 /* change on max_qp / min_qp */ 668 MPP_ENC_H264_CFG_CHANGE_QP_LIMIT = (1 << 16), 669 /* change on max_qp_i / min_qp_i */ 670 MPP_ENC_H264_CFG_CHANGE_QP_LIMIT_I = (1 << 17), 671 /* change on max_qp_step */ 672 MPP_ENC_H264_CFG_CHANGE_MAX_QP_STEP = (1 << 18), 673 /* change on qp_delta_ip */ 674 MPP_ENC_H264_CFG_CHANGE_QP_DELTA = (1 << 19), 675 /* change on intra_refresh_mode / intra_refresh_arg */ 676 MPP_ENC_H264_CFG_CHANGE_INTRA_REFRESH = (1 << 20), 677 /* change on max long-term reference frame count */ 678 MPP_ENC_H264_CFG_CHANGE_MAX_LTR = (1 << 21), 679 /* change on max temporal id */ 680 MPP_ENC_H264_CFG_CHANGE_MAX_TID = (1 << 22), 681 /* change on adding prefix nal */ 682 MPP_ENC_H264_CFG_CHANGE_ADD_PREFIX = (1 << 23), 683 /* change on base layer priority id */ 684 MPP_ENC_H264_CFG_CHANGE_BASE_LAYER_PID = (1 << 24), 685 686 /* change on vui */ 687 MPP_ENC_H264_CFG_CHANGE_VUI = (1 << 28), 688 689 /* change on constraint */ 690 MPP_ENC_H264_CFG_CHANGE_CONSTRAINT_SET = (1 << 29), 691 692 MPP_ENC_H264_CFG_CHANGE_ALL = (0xFFFFFFFF), 693 } MppEncH264CfgChange; 694 695 /* default H.264 hardware config */ 696 typedef struct MppEncH264HwCfg_t { 697 /* 698 * VEPU 1/2 : 2 699 * others : 0 700 */ 701 RK_U32 hw_poc_type; 702 /* 703 * VEPU 1/2 : fixed to 12 704 * others : changeable, default 12 705 */ 706 RK_U32 hw_log2_max_frame_num_minus4; 707 } MppEncH264HwCfg; 708 709 typedef struct MppEncH264Cfg_t { 710 RK_U32 change; 711 712 /* 713 * H.264 stream format 714 * 0 - H.264 Annex B: NAL unit starts with '00 00 00 01' 715 * 1 - Plain NAL units without startcode 716 */ 717 RK_S32 stream_type; 718 719 /* 720 * H.264 codec syntax config 721 * 722 * do NOT setup the three option below unless you are familiar with encoder detail 723 * poc_type - picture order count type 0 ~ 2 724 * log2_max_poc_lsb - used in sps with poc_type 0, 725 * log2_max_frame_num - used in sps 726 */ 727 RK_U32 poc_type; 728 RK_U32 log2_max_poc_lsb; 729 RK_U32 log2_max_frame_num; /* actually log2_max_frame_num_minus4 */ 730 RK_U32 gaps_not_allowed; 731 732 MppEncH264HwCfg hw_cfg; 733 734 /* 735 * H.264 profile_idc parameter 736 * 66 - Baseline profile 737 * 77 - Main profile 738 * 100 - High profile 739 */ 740 RK_S32 profile; 741 742 /* 743 * H.264 level_idc parameter 744 * 10 / 11 / 12 / 13 - qcif@15fps / cif@7.5fps / cif@15fps / cif@30fps 745 * 20 / 21 / 22 - cif@30fps / half-D1@@25fps / D1@12.5fps 746 * 30 / 31 / 32 - D1@25fps / 720p@30fps / 720p@60fps 747 * 40 / 41 / 42 - 1080p@30fps / 1080p@30fps / 1080p@60fps 748 * 50 / 51 / 52 - 4K@30fps 749 */ 750 RK_S32 level; 751 752 /* 753 * H.264 entropy coding method 754 * 0 - CAVLC 755 * 1 - CABAC 756 * When CABAC is select cabac_init_idc can be range 0~2 757 */ 758 RK_S32 entropy_coding_mode; 759 RK_S32 entropy_coding_mode_ex; 760 RK_S32 cabac_init_idc; 761 RK_S32 cabac_init_idc_ex; 762 763 /* 764 * 8x8 intra prediction and 8x8 transform enable flag 765 * This flag can only be enable under High profile 766 * 0 : disable (BP/MP) 767 * 1 : enable (HP) 768 */ 769 RK_S32 transform8x8_mode; 770 RK_S32 transform8x8_mode_ex; 771 772 /* 773 * 0 : disable 774 * 1 : enable 775 */ 776 RK_S32 constrained_intra_pred_mode; 777 778 /* 779 * 0 : flat scaling list 780 * 1 : default scaling list for all cases 781 * 2 : customized scaling list (not supported) 782 */ 783 RK_S32 scaling_list_mode; 784 785 /* 786 * chroma qp offset (-12 - 12) 787 */ 788 RK_S32 chroma_cb_qp_offset; 789 RK_S32 chroma_cr_qp_offset; 790 791 /* 792 * H.264 deblock filter mode flag 793 * 0 : enable 794 * 1 : disable 795 * 2 : disable deblocking filter at slice boundaries 796 * 797 * deblock filter offset alpha (-6 - 6) 798 * deblock filter offset beta (-6 - 6) 799 */ 800 RK_S32 deblock_disable; 801 RK_S32 deblock_offset_alpha; 802 RK_S32 deblock_offset_beta; 803 804 /* 805 * H.264 long term reference picture enable flag 806 * 0 - disable 807 * 1 - enable 808 */ 809 RK_S32 use_longterm; 810 811 /* 812 * quality config 813 * qp_max - 8 ~ 51 814 * qp_max_i - 10 ~ 40 815 * qp_min - 8 ~ 48 816 * qp_min_i - 10 ~ 40 817 * qp_max_step - max delta qp step between two frames 818 */ 819 RK_S32 qp_init; 820 RK_S16 qp_max; 821 RK_S16 qp_max_i; 822 RK_S16 qp_min; 823 RK_S16 qp_min_i; 824 RK_S16 qp_max_step; 825 RK_S16 qp_delta_ip; 826 827 /* 828 * intra fresh config 829 * 830 * intra_refresh_mode 831 * 0 - no intra refresh 832 * 1 - intra refresh by MB row 833 * 2 - intra refresh by MB column 834 * 3 - intra refresh by MB gap 835 * 836 * intra_refresh_arg 837 * mode 0 - no effect 838 * mode 1 - refresh MB row number 839 * mode 2 - refresh MB colmn number 840 * mode 3 - refresh MB gap count 841 */ 842 RK_S32 intra_refresh_mode; 843 RK_S32 intra_refresh_arg; 844 845 /* extra mode config */ 846 RK_S32 max_ltr_frames; 847 RK_S32 max_tid; 848 RK_S32 prefix_mode; 849 RK_S32 base_layer_pid; 850 /* 851 * Mpp encoder constraint_set parameter 852 * Mpp encoder constraint_set controls constraint_setx_flag in AVC. 853 * Mpp encoder constraint_set uses type RK_U32 to store force_flag and constraint_force as followed. 854 * | 00 | force_flag | 00 | constraint_force | 855 * As for force_flag and constraint_force, only low 6 bits are valid, 856 * corresponding to constraint_setx_flag from 5 to 0. 857 * If force_flag bit is enabled, constraint_setx_flag will be set correspondingly. 858 * Otherwise, constraint_setx_flag will use default value. 859 */ 860 RK_U32 constraint_set; 861 } MppEncH264Cfg; 862 863 #define H265E_MAX_ROI_NUMBER 64 864 865 typedef struct H265eRect_t { 866 RK_S32 left; 867 RK_S32 right; 868 RK_S32 top; 869 RK_S32 bottom; 870 } H265eRect; 871 872 typedef struct H265eRoi_Region_t { 873 RK_U8 level; 874 H265eRect rect; 875 } H265eRoiRegion; 876 877 /* 878 * roi region only can be setting when rc_enable = 1 879 */ 880 typedef struct MppEncH265RoiCfg_t { 881 /* 882 * the value is defined by H265eCtuMethod 883 */ 884 885 RK_U8 method; 886 /* 887 * the number of roi,the value must less than H265E_MAX_ROI_NUMBER 888 */ 889 RK_S32 num; 890 891 /* delat qp using in roi region*/ 892 RK_U32 delta_qp; 893 894 /* roi region */ 895 H265eRoiRegion region[H265E_MAX_ROI_NUMBER]; 896 } MppEncH265RoiCfg; 897 898 typedef struct H265eCtuQp_t { 899 /* the qp value using in ctu region */ 900 RK_U32 qp; 901 902 /* 903 * define the ctu region 904 * method = H265E_METHOD_CUT_SIZE, the value of rect is in ctu size 905 * method = H264E_METHOD_COORDINATE,the value of rect is in coordinates 906 */ 907 H265eRect rect; 908 } H265eCtu; 909 910 typedef struct H265eCtuRegion_t { 911 /* 912 * the value is defined by H265eCtuMethod 913 */ 914 RK_U8 method; 915 916 /* 917 * the number of ctu,the value must less than H265E_MAX_ROI_NUMBER 918 */ 919 RK_S32 num; 920 921 /* ctu region */ 922 H265eCtu ctu[H265E_MAX_ROI_NUMBER]; 923 } MppEncH265CtuCfg; 924 925 /* 926 * define the method when set CTU/ROI parameters 927 * this value is using by method in H265eCtuRegion or H265eRoi struct 928 */ 929 typedef enum { 930 H265E_METHOD_CTU_SIZE, 931 H264E_METHOD_COORDINATE, 932 } H265eCtuMethod; 933 934 /* 935 * H.265 configurable parameter 936 */ 937 typedef struct MppEncH265VuiCfg_t { 938 RK_U32 change; 939 RK_S32 vui_present; 940 RK_S32 vui_aspect_ratio; 941 RK_S32 vui_sar_size; 942 RK_S32 full_range; 943 RK_S32 time_scale; 944 } MppEncH265VuiCfg; 945 946 typedef enum MppEncH265CfgChange_e { 947 /* change on stream type */ 948 MPP_ENC_H265_CFG_PROFILE_LEVEL_TILER_CHANGE = (1 << 0), 949 MPP_ENC_H265_CFG_INTRA_QP_CHANGE = (1 << 1), 950 MPP_ENC_H265_CFG_FRAME_RATE_CHANGE = (1 << 2), 951 MPP_ENC_H265_CFG_BITRATE_CHANGE = (1 << 3), 952 MPP_ENC_H265_CFG_GOP_SIZE = (1 << 4), 953 MPP_ENC_H265_CFG_RC_QP_CHANGE = (1 << 5), 954 MPP_ENC_H265_CFG_INTRA_REFRESH_CHANGE = (1 << 6), 955 MPP_ENC_H265_CFG_INDEPEND_SLICE_CHANGE = (1 << 7), 956 MPP_ENC_H265_CFG_DEPEND_SLICE_CHANGE = (1 << 8), 957 MPP_ENC_H265_CFG_CTU_CHANGE = (1 << 9), 958 MPP_ENC_H265_CFG_ROI_CHANGE = (1 << 10), 959 MPP_ENC_H265_CFG_CU_CHANGE = (1 << 11), 960 MPP_ENC_H265_CFG_DBLK_CHANGE = (1 << 12), 961 MPP_ENC_H265_CFG_SAO_CHANGE = (1 << 13), 962 MPP_ENC_H265_CFG_TRANS_CHANGE = (1 << 14), 963 MPP_ENC_H265_CFG_SLICE_CHANGE = (1 << 15), 964 MPP_ENC_H265_CFG_ENTROPY_CHANGE = (1 << 16), 965 MPP_ENC_H265_CFG_MERGE_CHANGE = (1 << 17), 966 MPP_ENC_H265_CFG_CHANGE_VUI = (1 << 18), 967 MPP_ENC_H265_CFG_RC_I_QP_CHANGE = (1 << 19), 968 MPP_ENC_H265_CFG_RC_MAX_QP_STEP_CHANGE = (1 << 21), 969 MPP_ENC_H265_CFG_RC_IP_DELTA_QP_CHANGE = (1 << 20), 970 MPP_ENC_H265_CFG_TILE_CHANGE = (1 << 22), 971 MPP_ENC_H265_CFG_SLICE_LPFACS_CHANGE = (1 << 23), 972 MPP_ENC_H265_CFG_TILE_LPFACS_CHANGE = (1 << 24), 973 MPP_ENC_H265_CFG_CHANGE_ALL = (0xFFFFFFFF), 974 } MppEncH265CfgChange; 975 976 typedef struct MppEncH265SliceCfg_t { 977 /* default value: 0, means no slice split*/ 978 RK_U32 split_enable; 979 980 /* 0: by bits number; 1: by lcu line number*/ 981 RK_U32 split_mode; 982 983 /* 984 * when splitmode is 0, this value presents bits number, 985 * when splitmode is 1, this value presents lcu line number 986 */ 987 RK_U32 slice_size; 988 RK_U32 slice_out; 989 } MppEncH265SliceCfg; 990 991 typedef struct MppEncH265CuCfg_t { 992 RK_U32 cu32x32_en; /*default: 1 */ 993 RK_U32 cu16x16_en; /*default: 1 */ 994 RK_U32 cu8x8_en; /*default: 1 */ 995 RK_U32 cu4x4_en; /*default: 1 */ 996 997 // intra pred 998 RK_U32 constrained_intra_pred_flag; /*default: 0 */ 999 RK_U32 strong_intra_smoothing_enabled_flag; /*INTRA_SMOOTH*/ 1000 RK_U32 pcm_enabled_flag; /*default: 0, enable ipcm*/ 1001 RK_U32 pcm_loop_filter_disabled_flag; 1002 1003 } MppEncH265CuCfg; 1004 1005 typedef struct MppEncH265RefCfg_t { 1006 RK_U32 num_lt_ref_pic; /*default: 0*/ 1007 } MppEncH265RefCfg; 1008 1009 1010 typedef struct MppEncH265DblkCfg_t { 1011 RK_U32 slice_deblocking_filter_disabled_flag; /* default value: 0. {0,1} */ 1012 RK_S32 slice_beta_offset_div2; /* default value: 0. [-6,+6] */ 1013 RK_S32 slice_tc_offset_div2; /* default value: 0. [-6,+6] */ 1014 } MppEncH265DblkCfg_t; 1015 1016 typedef struct MppEncH265SaoCfg_t { 1017 RK_U32 slice_sao_luma_disable; 1018 RK_U32 slice_sao_chroma_disable; 1019 } MppEncH265SaoCfg; 1020 1021 typedef struct MppEncH265TransCfg_t { 1022 RK_U32 transquant_bypass_enabled_flag; 1023 RK_U32 transform_skip_enabled_flag; 1024 RK_U32 defalut_ScalingList_enable; /* default: 0 */ 1025 RK_S32 cb_qp_offset; 1026 RK_S32 cr_qp_offset; 1027 } MppEncH265TransCfg; 1028 1029 typedef struct MppEncH265MergeCfg_t { 1030 RK_U32 max_mrg_cnd; 1031 RK_U32 merge_up_flag; 1032 RK_U32 merge_left_flag; 1033 } MppEncH265MergesCfg; 1034 1035 typedef struct MppEncH265EntropyCfg_t { 1036 RK_U32 cabac_init_flag; /* default: 0 */ 1037 } MppEncH265EntropyCfg; 1038 1039 typedef struct MppEncH265Cfg_t { 1040 RK_U32 change; 1041 1042 /* H.265 codec syntax config */ 1043 RK_S32 profile; 1044 RK_S32 level; 1045 RK_S32 tier; 1046 1047 /* constraint intra prediction flag */ 1048 RK_S32 const_intra_pred; 1049 RK_S32 ctu_size; 1050 RK_S32 max_cu_size; 1051 RK_S32 tmvp_enable; 1052 RK_S32 amp_enable; 1053 RK_S32 wpp_enable; 1054 RK_S32 merge_range; 1055 RK_S32 sao_enable; 1056 RK_U32 num_ref; 1057 1058 /* quality config */ 1059 RK_S32 max_qp; 1060 RK_S32 min_qp; 1061 RK_S32 max_i_qp; 1062 RK_S32 min_i_qp; 1063 RK_S32 ip_qp_delta; 1064 RK_S32 max_delta_qp; 1065 RK_S32 intra_qp; 1066 RK_S32 gop_delta_qp; 1067 RK_S32 qp_init; 1068 RK_S32 qp_max_step; 1069 RK_S32 raw_dealt_qp; 1070 RK_U8 qpmax_map[8]; 1071 RK_U8 qpmin_map[8]; 1072 RK_S32 qpmap_mode; 1073 1074 /* intra fresh config */ 1075 RK_S32 intra_refresh_mode; 1076 RK_S32 intra_refresh_arg; 1077 1078 /* slice mode config */ 1079 RK_S32 independ_slice_mode; 1080 RK_S32 independ_slice_arg; 1081 RK_S32 depend_slice_mode; 1082 RK_S32 depend_slice_arg; 1083 1084 MppEncH265CuCfg cu_cfg; 1085 MppEncH265SliceCfg slice_cfg; 1086 MppEncH265EntropyCfg entropy_cfg; 1087 MppEncH265TransCfg trans_cfg; 1088 MppEncH265SaoCfg sao_cfg; 1089 MppEncH265DblkCfg_t dblk_cfg; 1090 MppEncH265RefCfg ref_cfg; 1091 MppEncH265MergesCfg merge_cfg; 1092 RK_S32 auto_tile; 1093 RK_U32 lpf_acs_sli_en; 1094 RK_U32 lpf_acs_tile_disable; 1095 1096 /* extra info */ 1097 MppEncH265VuiCfg vui; 1098 1099 MppEncH265CtuCfg ctu; 1100 MppEncH265RoiCfg roi; 1101 } MppEncH265Cfg; 1102 1103 /* 1104 * motion jpeg configurable parameter 1105 */ 1106 typedef enum MppEncJpegCfgChange_e { 1107 /* change on quant parameter */ 1108 MPP_ENC_JPEG_CFG_CHANGE_QP = (1 << 0), 1109 MPP_ENC_JPEG_CFG_CHANGE_QTABLE = (1 << 1), 1110 MPP_ENC_JPEG_CFG_CHANGE_QFACTOR = (1 << 2), 1111 MPP_ENC_JPEG_CFG_CHANGE_ALL = (0xFFFFFFFF), 1112 } MppEncJpegCfgChange; 1113 1114 typedef struct MppEncJpegCfg_t { 1115 RK_U32 change; 1116 RK_S32 quant; 1117 /* 1118 * quality factor config 1119 * 1120 * q_factor - 1 ~ 99 1121 * qf_max - 1 ~ 99 1122 * qf_min - 1 ~ 99 1123 * qtable_y: qtable for luma 1124 * qtable_u: qtable for chroma 1125 * qtable_v: default equal qtable_u 1126 */ 1127 RK_S32 q_factor; 1128 RK_S32 qf_max; 1129 RK_S32 qf_min; 1130 RK_U8 *qtable_y; 1131 RK_U8 *qtable_u; 1132 RK_U8 *qtable_v; 1133 } MppEncJpegCfg; 1134 1135 /* 1136 * vp8 configurable parameter 1137 */ 1138 typedef enum MppEncVP8CfgChange_e { 1139 MPP_ENC_VP8_CFG_CHANGE_QP = (1 << 0), 1140 MPP_ENC_VP8_CFG_CHANGE_DIS_IVF = (1 << 1), 1141 MPP_ENC_VP8_CFG_CHANGE_ALL = (0xFFFFFFFF), 1142 } MppEncVP8CfgChange; 1143 1144 typedef struct MppEncVp8Cfg_t { 1145 RK_U32 change; 1146 RK_S32 quant; 1147 1148 RK_S32 qp_init; 1149 RK_S32 qp_max; 1150 RK_S32 qp_max_i; 1151 RK_S32 qp_min; 1152 RK_S32 qp_min_i; 1153 RK_S32 qp_max_step; 1154 RK_S32 disable_ivf; 1155 } MppEncVp8Cfg; 1156 1157 /** 1158 * @ingroup rk_mpi 1159 * @brief MPP encoder codec configuration parameters 1160 * @details The encoder codec configuration parameters are different for each 1161 * compression codings. For example, H.264 encoder can configure 1162 * profile, level, qp, etc. while jpeg encoder can configure qp 1163 * only. The detailed parameters can refer the corresponding data 1164 * structure such as MppEncH264Cfg and MppEncJpegCfg. This data 1165 * structure is associated with MPP_ENC_SET_CODEC_CFG command. 1166 */ 1167 typedef struct MppEncCodecCfg_t { 1168 MppCodingType coding; 1169 1170 union { 1171 RK_U32 change; 1172 MppEncH264Cfg h264; 1173 MppEncH265Cfg h265; 1174 MppEncJpegCfg jpeg; 1175 MppEncVp8Cfg vp8; 1176 }; 1177 } MppEncCodecCfg; 1178 1179 typedef enum MppEncSliceSplit_e { 1180 /* change on quant parameter */ 1181 MPP_ENC_SPLIT_CFG_CHANGE_MODE = (1 << 0), 1182 MPP_ENC_SPLIT_CFG_CHANGE_ARG = (1 << 1), 1183 MPP_ENC_SPLIT_CFG_CHANGE_OUTPUT = (1 << 2), 1184 MPP_ENC_SPLIT_CFG_CHANGE_ALL = (0xFFFFFFFF), 1185 } MppEncSliceSplitChange; 1186 1187 typedef enum MppEncSplitMode_e { 1188 MPP_ENC_SPLIT_NONE, 1189 MPP_ENC_SPLIT_BY_BYTE, 1190 MPP_ENC_SPLIT_BY_CTU, 1191 } MppEncSplitMode; 1192 1193 typedef enum MppEncSplitOutMode_e { 1194 MPP_ENC_SPLIT_OUT_LOWDELAY = (1 << 0), 1195 MPP_ENC_SPLIT_OUT_SEGMENT = (1 << 1), 1196 } MppEncSplitOutMode; 1197 1198 typedef struct MppEncSliceSplit_t { 1199 RK_U32 change; 1200 1201 /* 1202 * slice split mode 1203 * 1204 * MPP_ENC_SPLIT_NONE - No slice is split 1205 * MPP_ENC_SPLIT_BY_BYTE - Slice is split by byte number 1206 * MPP_ENC_SPLIT_BY_CTU - Slice is split by macroblock / ctu number 1207 */ 1208 RK_U32 split_mode; 1209 1210 /* 1211 * slice split size parameter 1212 * 1213 * When split by byte number this value is the max byte number for each 1214 * slice. 1215 * When split by macroblock / ctu number this value is the MB/CTU number 1216 * for each slice. 1217 */ 1218 RK_U32 split_arg; 1219 1220 /* 1221 * slice split output mode 1222 * 1223 * MPP_ENC_SPLIT_OUT_LOWDELAY 1224 * - When enabled encoder will lowdelay output each slice in a single packet 1225 * MPP_ENC_SPLIT_OUT_SEGMENT 1226 * - When enabled encoder will packet with segment info for each slice 1227 */ 1228 RK_U32 split_out; 1229 } MppEncSliceSplit; 1230 1231 /** 1232 * @brief Mpp ROI parameter 1233 * Region configure define a rectangle as ROI 1234 * @note x, y, w, h are calculated in pixels, which had better be 16-pixel aligned. 1235 * These parameters MUST retain in memory when encoder is running. 1236 * Both absolute qp and relative qp are supported in vepu541. 1237 * Only absolute qp is supported in rv1108 1238 */ 1239 typedef struct MppEncROIRegion_t { 1240 RK_U16 x; /**< horizontal position of top left corner */ 1241 RK_U16 y; /**< vertical position of top left corner */ 1242 RK_U16 w; /**< width of ROI rectangle */ 1243 RK_U16 h; /**< height of ROI rectangle */ 1244 RK_U16 intra; /**< flag of forced intra macroblock */ 1245 RK_S16 quality; /**< absolute / relative qp of macroblock */ 1246 RK_U16 qp_area_idx; /**< qp min max area select*/ 1247 RK_U8 area_map_en; /**< enable area map */ 1248 RK_U8 abs_qp_en; /**< absolute qp enable flag*/ 1249 } MppEncROIRegion; 1250 1251 /** 1252 * @brief MPP encoder's ROI configuration 1253 */ 1254 typedef struct MppEncROICfg_t { 1255 RK_U32 number; /**< ROI rectangle number */ 1256 MppEncROIRegion *regions; /**< ROI parameters */ 1257 } MppEncROICfg; 1258 1259 /** 1260 * @brief Mpp ROI parameter for vepu54x / vepu58x 1261 * @note These encoders have more complex roi configure structure. 1262 * User need to generate roi structure data for different soc. 1263 * And send buffers to encoder through metadata. 1264 */ 1265 typedef struct MppEncROICfg2_t { 1266 MppBuffer base_cfg_buf; 1267 MppBuffer qp_cfg_buf; 1268 MppBuffer amv_cfg_buf; 1269 MppBuffer mv_cfg_buf; 1270 1271 RK_U32 roi_qp_en : 1; 1272 RK_U32 roi_amv_en : 1; 1273 RK_U32 roi_mv_en : 1; 1274 RK_U32 reserve_bits : 29; 1275 RK_U32 reserve[3]; 1276 } MppEncROICfg2; 1277 1278 /* 1279 * Mpp OSD parameter 1280 * 1281 * Mpp OSD support total 8 regions 1282 * Mpp OSD support 256-color palette two mode palette: 1283 * 1. Configurable OSD palette 1284 * When palette is set. 1285 * 2. fixed OSD palette 1286 * When palette is NULL. 1287 * 1288 * if MppEncOSDPlt.buf != NULL , palette includes maximun 256 levels, 1289 * every level composed of 32 bits defined below: 1290 * Y : 8 bits 1291 * U : 8 bits 1292 * V : 8 bits 1293 * alpha : 8 bits 1294 */ 1295 #define MPP_ENC_OSD_PLT_WHITE ((255<<24)|(128<<16)|(128<<8)|235) 1296 #define MPP_ENC_OSD_PLT_YELLOW ((255<<24)|(146<<16)|( 16<<8)|210) 1297 #define MPP_ENC_OSD_PLT_CYAN ((255<<24)|( 16<<16)|(166<<8)|170) 1298 #define MPP_ENC_OSD_PLT_GREEN ((255<<24)|( 34<<16)|( 54<<8)|145) 1299 #define MPP_ENC_OSD_PLT_TRANS (( 0<<24)|(222<<16)|(202<<8)|106) 1300 #define MPP_ENC_OSD_PLT_RED ((255<<24)|(240<<16)|( 90<<8)| 81) 1301 #define MPP_ENC_OSD_PLT_BLUE ((255<<24)|(110<<16)|(240<<8)| 41) 1302 #define MPP_ENC_OSD_PLT_BLACK ((255<<24)|(128<<16)|(128<<8)| 16) 1303 1304 typedef enum MppEncOSDPltType_e { 1305 MPP_ENC_OSD_PLT_TYPE_DEFAULT, 1306 MPP_ENC_OSD_PLT_TYPE_USERDEF, 1307 MPP_ENC_OSD_PLT_TYPE_BUTT, 1308 } MppEncOSDPltType; 1309 1310 /* OSD palette value define */ 1311 typedef union MppEncOSDPltVal_u { 1312 struct { 1313 RK_U32 v : 8; 1314 RK_U32 u : 8; 1315 RK_U32 y : 8; 1316 RK_U32 alpha : 8; 1317 }; 1318 RK_U32 val; 1319 } MppEncOSDPltVal; 1320 1321 typedef struct MppEncOSDPlt_t { 1322 MppEncOSDPltVal data[256]; 1323 } MppEncOSDPlt; 1324 1325 typedef enum MppEncOSDPltCfgChange_e { 1326 MPP_ENC_OSD_PLT_CFG_CHANGE_MODE = (1 << 0), /* change osd plt type */ 1327 MPP_ENC_OSD_PLT_CFG_CHANGE_PLT_VAL = (1 << 1), /* change osd plt table value */ 1328 MPP_ENC_OSD_PLT_CFG_CHANGE_ALL = (0xFFFFFFFF), 1329 } MppEncOSDPltCfgChange; 1330 1331 typedef struct MppEncOSDPltCfg_t { 1332 RK_U32 change; 1333 MppEncOSDPltType type; 1334 MppEncOSDPlt *plt; 1335 } MppEncOSDPltCfg; 1336 1337 /* position info is unit in 16 pixels(one MB), and 1338 * x-directon range in pixels = (rd_pos_x - lt_pos_x + 1) * 16; 1339 * y-directon range in pixels = (rd_pos_y - lt_pos_y + 1) * 16; 1340 */ 1341 typedef struct MppEncOSDRegion_t { 1342 RK_U32 enable; 1343 RK_U32 inverse; 1344 RK_U32 start_mb_x; 1345 RK_U32 start_mb_y; 1346 RK_U32 num_mb_x; 1347 RK_U32 num_mb_y; 1348 RK_U32 buf_offset; 1349 } MppEncOSDRegion; 1350 1351 /* if num_region > 0 && region==NULL 1352 * use old osd data 1353 */ 1354 typedef struct MppEncOSDData_t { 1355 MppBuffer buf; 1356 RK_U32 num_region; 1357 MppEncOSDRegion region[8]; 1358 } MppEncOSDData; 1359 1360 typedef struct MppEncOSDRegion2_t { 1361 RK_U32 enable; 1362 RK_U32 inverse; 1363 RK_U32 start_mb_x; 1364 RK_U32 start_mb_y; 1365 RK_U32 num_mb_x; 1366 RK_U32 num_mb_y; 1367 RK_U32 buf_offset; 1368 MppBuffer buf; 1369 } MppEncOSDRegion2; 1370 1371 typedef struct MppEncOSDData2_t { 1372 RK_U32 num_region; 1373 MppEncOSDRegion2 region[8]; 1374 } MppEncOSDData2; 1375 1376 typedef struct MppEncUserData_t { 1377 RK_U32 len; 1378 void *pdata; 1379 } MppEncUserData; 1380 1381 typedef struct MppEncUserDataFull_t { 1382 RK_U32 len; 1383 RK_U8 *uuid; 1384 void *pdata; 1385 } MppEncUserDataFull; 1386 1387 typedef struct MppEncUserDataSet_t { 1388 RK_U32 count; 1389 MppEncUserDataFull *datas; 1390 } MppEncUserDataSet; 1391 1392 typedef enum MppEncSceneMode_e { 1393 MPP_ENC_SCENE_MODE_DEFAULT, 1394 MPP_ENC_SCENE_MODE_IPC, 1395 MPP_ENC_SCENE_MODE_BUTT, 1396 } MppEncSceneMode; 1397 1398 typedef enum MppEncFineTuneCfgChange_e { 1399 /* change on scene mode */ 1400 MPP_ENC_TUNE_CFG_CHANGE_SCENE_MODE = (1 << 0), 1401 } MppEncFineTuneCfgChange; 1402 1403 typedef struct MppEncFineTuneCfg_t { 1404 RK_U32 change; 1405 1406 MppEncSceneMode scene_mode; 1407 } MppEncFineTuneCfg; 1408 1409 #endif /*__RK_VENC_CMD_H__*/ 1410