1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2015 Rockchip Electronics Co. LTD 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Licensed under the Apache License, Version 2.0 (the "License"); 5*4882a593Smuzhiyun * you may not use this file except in compliance with the License. 6*4882a593Smuzhiyun * You may obtain a copy of the License at 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * http://www.apache.org/licenses/LICENSE-2.0 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Unless required by applicable law or agreed to in writing, software 11*4882a593Smuzhiyun * distributed under the License is distributed on an "AS IS" BASIS, 12*4882a593Smuzhiyun * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13*4882a593Smuzhiyun * See the License for the specific language governing permissions and 14*4882a593Smuzhiyun * limitations under the License. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef __RK_MPI_CMD_H__ 18*4882a593Smuzhiyun #define __RK_MPI_CMD_H__ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * Command id bit usage is defined as follows: 22*4882a593Smuzhiyun * bit 20 - 23 - module id 23*4882a593Smuzhiyun * bit 16 - 19 - contex id 24*4882a593Smuzhiyun * bit 0 - 15 - command id 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #define CMD_MODULE_ID_MASK (0x00F00000) 27*4882a593Smuzhiyun #define CMD_MODULE_OSAL (0x00100000) 28*4882a593Smuzhiyun #define CMD_MODULE_MPP (0x00200000) 29*4882a593Smuzhiyun #define CMD_MODULE_CODEC (0x00300000) 30*4882a593Smuzhiyun #define CMD_MODULE_HAL (0x00400000) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define CMD_CTX_ID_MASK (0x000F0000) 33*4882a593Smuzhiyun #define CMD_CTX_ID_DEC (0x00010000) 34*4882a593Smuzhiyun #define CMD_CTX_ID_ENC (0x00020000) 35*4882a593Smuzhiyun #define CMD_CTX_ID_ISP (0x00030000) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* separate encoder / decoder control command to different segment */ 38*4882a593Smuzhiyun #define CMD_CFG_ID_MASK (0x0000FF00) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* mpp status control command */ 41*4882a593Smuzhiyun #define CMD_STATE_OPS (0x00000100) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* decoder control command */ 44*4882a593Smuzhiyun #define CMD_DEC_CFG_ALL (0x00000000) 45*4882a593Smuzhiyun #define CMD_DEC_QUERY (0x00000100) 46*4882a593Smuzhiyun #define CMD_DEC_CFG (0x00000200) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* encoder control command */ 49*4882a593Smuzhiyun #define CMD_ENC_CFG_ALL (0x00000000) 50*4882a593Smuzhiyun #define CMD_ENC_QUERY (0x00000100) 51*4882a593Smuzhiyun #define CMD_ENC_CFG_RC_API (0x00000200) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define CMD_ENC_CFG_MISC (0x00008000) 54*4882a593Smuzhiyun #define CMD_ENC_CFG_SPLIT (0x00008100) 55*4882a593Smuzhiyun #define CMD_ENC_CFG_REF (0x00008200) 56*4882a593Smuzhiyun #define CMD_ENC_CFG_ROI (0x00008300) 57*4882a593Smuzhiyun #define CMD_ENC_CFG_OSD (0x00008400) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun typedef enum { 60*4882a593Smuzhiyun MPP_OSAL_CMD_BASE = CMD_MODULE_OSAL, 61*4882a593Smuzhiyun MPP_OSAL_CMD_END, 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun MPP_CMD_BASE = CMD_MODULE_MPP, 64*4882a593Smuzhiyun MPP_ENABLE_DEINTERLACE, 65*4882a593Smuzhiyun MPP_SET_INPUT_BLOCK, /* deprecated */ 66*4882a593Smuzhiyun MPP_SET_INTPUT_BLOCK_TIMEOUT, /* deprecated */ 67*4882a593Smuzhiyun MPP_SET_OUTPUT_BLOCK, /* deprecated */ 68*4882a593Smuzhiyun MPP_SET_OUTPUT_BLOCK_TIMEOUT, /* deprecated */ 69*4882a593Smuzhiyun /* 70*4882a593Smuzhiyun * timeout setup, refer to MPP_TIMEOUT_XXX 71*4882a593Smuzhiyun * zero - non block 72*4882a593Smuzhiyun * negative - block with no timeout 73*4882a593Smuzhiyun * positive - timeout in milisecond 74*4882a593Smuzhiyun */ 75*4882a593Smuzhiyun MPP_SET_INPUT_TIMEOUT, /* parameter type RK_S64 */ 76*4882a593Smuzhiyun MPP_SET_OUTPUT_TIMEOUT, /* parameter type RK_S64 */ 77*4882a593Smuzhiyun MPP_SET_DISABLE_THREAD, /* MPP no thread mode and use external thread to decode */ 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun MPP_STATE_CMD_BASE = CMD_MODULE_MPP | CMD_STATE_OPS, 80*4882a593Smuzhiyun MPP_START, 81*4882a593Smuzhiyun MPP_STOP, 82*4882a593Smuzhiyun MPP_PAUSE, 83*4882a593Smuzhiyun MPP_RESUME, 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun MPP_CMD_END, 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun MPP_CODEC_CMD_BASE = CMD_MODULE_CODEC, 88*4882a593Smuzhiyun MPP_CODEC_GET_FRAME_INFO, 89*4882a593Smuzhiyun MPP_CODEC_CMD_END, 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun MPP_DEC_CMD_BASE = CMD_MODULE_CODEC | CMD_CTX_ID_DEC, 92*4882a593Smuzhiyun MPP_DEC_SET_FRAME_INFO, /* vpu api legacy control for buffer slot dimension init */ 93*4882a593Smuzhiyun MPP_DEC_SET_EXT_BUF_GROUP, /* IMPORTANT: set external buffer group to mpp decoder */ 94*4882a593Smuzhiyun MPP_DEC_SET_INFO_CHANGE_READY, 95*4882a593Smuzhiyun MPP_DEC_SET_PRESENT_TIME_ORDER, /* use input time order for output */ 96*4882a593Smuzhiyun MPP_DEC_SET_PARSER_SPLIT_MODE, /* Need to setup before init */ 97*4882a593Smuzhiyun MPP_DEC_SET_PARSER_FAST_MODE, /* Need to setup before init */ 98*4882a593Smuzhiyun MPP_DEC_GET_STREAM_COUNT, 99*4882a593Smuzhiyun MPP_DEC_GET_VPUMEM_USED_COUNT, 100*4882a593Smuzhiyun MPP_DEC_SET_VC1_EXTRA_DATA, 101*4882a593Smuzhiyun MPP_DEC_SET_OUTPUT_FORMAT, 102*4882a593Smuzhiyun MPP_DEC_SET_DISABLE_ERROR, /* When set it will disable sw/hw error (H.264 / H.265) */ 103*4882a593Smuzhiyun MPP_DEC_SET_IMMEDIATE_OUT, 104*4882a593Smuzhiyun MPP_DEC_SET_ENABLE_DEINTERLACE, /* MPP enable deinterlace by default. Vpuapi can disable it */ 105*4882a593Smuzhiyun MPP_DEC_SET_ENABLE_FAST_PLAY, /* enable idr output immediately */ 106*4882a593Smuzhiyun MPP_DEC_SET_DISABLE_THREAD, /* MPP no thread mode and use external thread to decode */ 107*4882a593Smuzhiyun MPP_DEC_SET_MAX_USE_BUFFER_SIZE, 108*4882a593Smuzhiyun MPP_DEC_SET_ENABLE_MVC, /* enable MVC decoding*/ 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun MPP_DEC_CMD_QUERY = CMD_MODULE_CODEC | CMD_CTX_ID_DEC | CMD_DEC_QUERY, 111*4882a593Smuzhiyun /* query decoder runtime information for decode stage */ 112*4882a593Smuzhiyun MPP_DEC_QUERY, /* set and get MppDecQueryCfg structure */ 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun CMD_DEC_CMD_CFG = CMD_MODULE_CODEC | CMD_CTX_ID_DEC | CMD_DEC_CFG, 115*4882a593Smuzhiyun MPP_DEC_SET_CFG, /* set MppDecCfg structure */ 116*4882a593Smuzhiyun MPP_DEC_GET_CFG, /* get MppDecCfg structure */ 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun MPP_DEC_CMD_END, 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun MPP_ENC_CMD_BASE = CMD_MODULE_CODEC | CMD_CTX_ID_ENC, 121*4882a593Smuzhiyun /* basic encoder setup control */ 122*4882a593Smuzhiyun MPP_ENC_SET_CFG, /* set MppEncCfg structure */ 123*4882a593Smuzhiyun MPP_ENC_GET_CFG, /* get MppEncCfg structure */ 124*4882a593Smuzhiyun MPP_ENC_SET_PREP_CFG, /* deprecated set MppEncPrepCfg structure, use MPP_ENC_SET_CFG instead */ 125*4882a593Smuzhiyun MPP_ENC_GET_PREP_CFG, /* deprecated get MppEncPrepCfg structure, use MPP_ENC_GET_CFG instead */ 126*4882a593Smuzhiyun MPP_ENC_SET_RC_CFG, /* deprecated set MppEncRcCfg structure, use MPP_ENC_SET_CFG instead */ 127*4882a593Smuzhiyun MPP_ENC_GET_RC_CFG, /* deprecated get MppEncRcCfg structure, use MPP_ENC_GET_CFG instead */ 128*4882a593Smuzhiyun MPP_ENC_SET_CODEC_CFG, /* deprecated set MppEncCodecCfg structure, use MPP_ENC_SET_CFG instead */ 129*4882a593Smuzhiyun MPP_ENC_GET_CODEC_CFG, /* deprecated get MppEncCodecCfg structure, use MPP_ENC_GET_CFG instead */ 130*4882a593Smuzhiyun /* runtime encoder setup control */ 131*4882a593Smuzhiyun MPP_ENC_SET_IDR_FRAME, /* next frame will be encoded as intra frame */ 132*4882a593Smuzhiyun MPP_ENC_SET_OSD_LEGACY_0, /* deprecated */ 133*4882a593Smuzhiyun MPP_ENC_SET_OSD_LEGACY_1, /* deprecated */ 134*4882a593Smuzhiyun MPP_ENC_SET_OSD_LEGACY_2, /* deprecated */ 135*4882a593Smuzhiyun MPP_ENC_GET_HDR_SYNC, /* get vps / sps / pps which has better sync behavior parameter is MppPacket */ 136*4882a593Smuzhiyun MPP_ENC_GET_EXTRA_INFO, /* deprecated */ 137*4882a593Smuzhiyun MPP_ENC_SET_SEI_CFG, /* SEI: Supplement Enhancemant Information, parameter is MppSeiMode */ 138*4882a593Smuzhiyun MPP_ENC_GET_SEI_DATA, /* SEI: Supplement Enhancemant Information, parameter is MppPacket */ 139*4882a593Smuzhiyun MPP_ENC_PRE_ALLOC_BUFF, /* deprecated */ 140*4882a593Smuzhiyun MPP_ENC_SET_QP_RANGE, /* used for adjusting qp range, the parameter can be 1 or 2 */ 141*4882a593Smuzhiyun MPP_ENC_SET_ROI_CFG, /* set MppEncROICfg structure */ 142*4882a593Smuzhiyun MPP_ENC_SET_CTU_QP, /* for H265 Encoder,set CTU's size and QP */ 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun MPP_ENC_CMD_QUERY = CMD_MODULE_CODEC | CMD_CTX_ID_ENC | CMD_ENC_QUERY, 145*4882a593Smuzhiyun /* query encoder runtime information for encode stage */ 146*4882a593Smuzhiyun MPP_ENC_QUERY, /* set and get MppEncQueryCfg structure */ 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* User define rate control stategy API control */ 149*4882a593Smuzhiyun MPP_ENC_CFG_RC_API = CMD_MODULE_CODEC | CMD_CTX_ID_ENC | CMD_ENC_CFG_RC_API, 150*4882a593Smuzhiyun /* 151*4882a593Smuzhiyun * Get RcApiQueryAll structure 152*4882a593Smuzhiyun * Get all available rate control stategy string and count 153*4882a593Smuzhiyun */ 154*4882a593Smuzhiyun MPP_ENC_GET_RC_API_ALL = MPP_ENC_CFG_RC_API + 1, 155*4882a593Smuzhiyun /* 156*4882a593Smuzhiyun * Get RcApiQueryType structure 157*4882a593Smuzhiyun * Get available rate control stategy string with certain type 158*4882a593Smuzhiyun */ 159*4882a593Smuzhiyun MPP_ENC_GET_RC_API_BY_TYPE = MPP_ENC_CFG_RC_API + 2, 160*4882a593Smuzhiyun /* 161*4882a593Smuzhiyun * Set RcImplApi structure 162*4882a593Smuzhiyun * Add new or update rate control stategy function pointers 163*4882a593Smuzhiyun */ 164*4882a593Smuzhiyun MPP_ENC_SET_RC_API_CFG = MPP_ENC_CFG_RC_API + 3, 165*4882a593Smuzhiyun /* 166*4882a593Smuzhiyun * Get RcApiBrief structure 167*4882a593Smuzhiyun * Get current used rate control stategy brief information (type and name) 168*4882a593Smuzhiyun */ 169*4882a593Smuzhiyun MPP_ENC_GET_RC_API_CURRENT = MPP_ENC_CFG_RC_API + 4, 170*4882a593Smuzhiyun /* 171*4882a593Smuzhiyun * Set RcApiBrief structure 172*4882a593Smuzhiyun * Set current used rate control stategy brief information (type and name) 173*4882a593Smuzhiyun */ 174*4882a593Smuzhiyun MPP_ENC_SET_RC_API_CURRENT = MPP_ENC_CFG_RC_API + 5, 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun MPP_ENC_CFG_MISC = CMD_MODULE_CODEC | CMD_CTX_ID_ENC | CMD_ENC_CFG_MISC, 177*4882a593Smuzhiyun MPP_ENC_SET_HEADER_MODE, /* set MppEncHeaderMode */ 178*4882a593Smuzhiyun MPP_ENC_GET_HEADER_MODE, /* get MppEncHeaderMode */ 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun MPP_ENC_CFG_SPLIT = CMD_MODULE_CODEC | CMD_CTX_ID_ENC | CMD_ENC_CFG_SPLIT, 181*4882a593Smuzhiyun MPP_ENC_SET_SPLIT, /* set MppEncSliceSplit structure */ 182*4882a593Smuzhiyun MPP_ENC_GET_SPLIT, /* get MppEncSliceSplit structure */ 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun MPP_ENC_CFG_REF = CMD_MODULE_CODEC | CMD_CTX_ID_ENC | CMD_ENC_CFG_REF, 185*4882a593Smuzhiyun MPP_ENC_SET_REF_CFG, /* set MppEncRefCfg structure */ 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun MPP_ENC_CFG_OSD = CMD_MODULE_CODEC | CMD_CTX_ID_ENC | CMD_ENC_CFG_OSD, 188*4882a593Smuzhiyun MPP_ENC_SET_OSD_PLT_CFG, /* set OSD palette, parameter should be pointer to MppEncOSDPltCfg */ 189*4882a593Smuzhiyun MPP_ENC_GET_OSD_PLT_CFG, /* get OSD palette, parameter should be pointer to MppEncOSDPltCfg */ 190*4882a593Smuzhiyun MPP_ENC_SET_OSD_DATA_CFG, /* set OSD data with at most 8 regions, parameter should be pointer to MppEncOSDData */ 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun MPP_ENC_CMD_END, 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun MPP_ISP_CMD_BASE = CMD_MODULE_CODEC | CMD_CTX_ID_ISP, 195*4882a593Smuzhiyun MPP_ISP_CMD_END, 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun MPP_HAL_CMD_BASE = CMD_MODULE_HAL, 198*4882a593Smuzhiyun MPP_HAL_CMD_END, 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun MPI_CMD_BUTT, 201*4882a593Smuzhiyun } MpiCmd; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun #include "rk_vdec_cmd.h" 204*4882a593Smuzhiyun #include "rk_vdec_cfg.h" 205*4882a593Smuzhiyun #include "rk_venc_cmd.h" 206*4882a593Smuzhiyun #include "rk_venc_cfg.h" 207*4882a593Smuzhiyun #include "rk_venc_ref.h" 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun #endif /*__RK_MPI_CMD_H__*/ 210