1 /* 2 * Copyright 2015 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __RK_MPI_CMD_H__ 18 #define __RK_MPI_CMD_H__ 19 20 /* 21 * Command id bit usage is defined as follows: 22 * bit 20 - 23 - module id 23 * bit 16 - 19 - contex id 24 * bit 0 - 15 - command id 25 */ 26 #define CMD_MODULE_ID_MASK (0x00F00000) 27 #define CMD_MODULE_OSAL (0x00100000) 28 #define CMD_MODULE_MPP (0x00200000) 29 #define CMD_MODULE_CODEC (0x00300000) 30 #define CMD_MODULE_HAL (0x00400000) 31 32 #define CMD_CTX_ID_MASK (0x000F0000) 33 #define CMD_CTX_ID_DEC (0x00010000) 34 #define CMD_CTX_ID_ENC (0x00020000) 35 #define CMD_CTX_ID_ISP (0x00030000) 36 37 /* separate encoder / decoder control command to different segment */ 38 #define CMD_CFG_ID_MASK (0x0000FF00) 39 40 /* mpp status control command */ 41 #define CMD_STATE_OPS (0x00000100) 42 43 /* decoder control command */ 44 #define CMD_DEC_CFG_ALL (0x00000000) 45 #define CMD_DEC_QUERY (0x00000100) 46 #define CMD_DEC_CFG (0x00000200) 47 48 /* encoder control command */ 49 #define CMD_ENC_CFG_ALL (0x00000000) 50 #define CMD_ENC_QUERY (0x00000100) 51 #define CMD_ENC_CFG_RC_API (0x00000200) 52 53 #define CMD_ENC_CFG_MISC (0x00008000) 54 #define CMD_ENC_CFG_SPLIT (0x00008100) 55 #define CMD_ENC_CFG_REF (0x00008200) 56 #define CMD_ENC_CFG_ROI (0x00008300) 57 #define CMD_ENC_CFG_OSD (0x00008400) 58 59 typedef enum { 60 MPP_OSAL_CMD_BASE = CMD_MODULE_OSAL, 61 MPP_OSAL_CMD_END, 62 63 MPP_CMD_BASE = CMD_MODULE_MPP, 64 MPP_ENABLE_DEINTERLACE, 65 MPP_SET_INPUT_BLOCK, /* deprecated */ 66 MPP_SET_INTPUT_BLOCK_TIMEOUT, /* deprecated */ 67 MPP_SET_OUTPUT_BLOCK, /* deprecated */ 68 MPP_SET_OUTPUT_BLOCK_TIMEOUT, /* deprecated */ 69 /* 70 * timeout setup, refer to MPP_TIMEOUT_XXX 71 * zero - non block 72 * negative - block with no timeout 73 * positive - timeout in milisecond 74 */ 75 MPP_SET_INPUT_TIMEOUT, /* parameter type RK_S64 */ 76 MPP_SET_OUTPUT_TIMEOUT, /* parameter type RK_S64 */ 77 MPP_SET_DISABLE_THREAD, /* MPP no thread mode and use external thread to decode */ 78 79 MPP_STATE_CMD_BASE = CMD_MODULE_MPP | CMD_STATE_OPS, 80 MPP_START, 81 MPP_STOP, 82 MPP_PAUSE, 83 MPP_RESUME, 84 85 MPP_CMD_END, 86 87 MPP_CODEC_CMD_BASE = CMD_MODULE_CODEC, 88 MPP_CODEC_GET_FRAME_INFO, 89 MPP_CODEC_CMD_END, 90 91 MPP_DEC_CMD_BASE = CMD_MODULE_CODEC | CMD_CTX_ID_DEC, 92 MPP_DEC_SET_FRAME_INFO, /* vpu api legacy control for buffer slot dimension init */ 93 MPP_DEC_SET_EXT_BUF_GROUP, /* IMPORTANT: set external buffer group to mpp decoder */ 94 MPP_DEC_SET_INFO_CHANGE_READY, 95 MPP_DEC_SET_PRESENT_TIME_ORDER, /* use input time order for output */ 96 MPP_DEC_SET_PARSER_SPLIT_MODE, /* Need to setup before init */ 97 MPP_DEC_SET_PARSER_FAST_MODE, /* Need to setup before init */ 98 MPP_DEC_GET_STREAM_COUNT, 99 MPP_DEC_GET_VPUMEM_USED_COUNT, 100 MPP_DEC_SET_VC1_EXTRA_DATA, 101 MPP_DEC_SET_OUTPUT_FORMAT, 102 MPP_DEC_SET_DISABLE_ERROR, /* When set it will disable sw/hw error (H.264 / H.265) */ 103 MPP_DEC_SET_IMMEDIATE_OUT, 104 MPP_DEC_SET_ENABLE_DEINTERLACE, /* MPP enable deinterlace by default. Vpuapi can disable it */ 105 MPP_DEC_SET_ENABLE_FAST_PLAY, /* enable idr output immediately */ 106 MPP_DEC_SET_DISABLE_THREAD, /* MPP no thread mode and use external thread to decode */ 107 MPP_DEC_SET_MAX_USE_BUFFER_SIZE, 108 MPP_DEC_SET_ENABLE_MVC, /* enable MVC decoding*/ 109 110 MPP_DEC_CMD_QUERY = CMD_MODULE_CODEC | CMD_CTX_ID_DEC | CMD_DEC_QUERY, 111 /* query decoder runtime information for decode stage */ 112 MPP_DEC_QUERY, /* set and get MppDecQueryCfg structure */ 113 114 CMD_DEC_CMD_CFG = CMD_MODULE_CODEC | CMD_CTX_ID_DEC | CMD_DEC_CFG, 115 MPP_DEC_SET_CFG, /* set MppDecCfg structure */ 116 MPP_DEC_GET_CFG, /* get MppDecCfg structure */ 117 118 MPP_DEC_CMD_END, 119 120 MPP_ENC_CMD_BASE = CMD_MODULE_CODEC | CMD_CTX_ID_ENC, 121 /* basic encoder setup control */ 122 MPP_ENC_SET_CFG, /* set MppEncCfg structure */ 123 MPP_ENC_GET_CFG, /* get MppEncCfg structure */ 124 MPP_ENC_SET_PREP_CFG, /* deprecated set MppEncPrepCfg structure, use MPP_ENC_SET_CFG instead */ 125 MPP_ENC_GET_PREP_CFG, /* deprecated get MppEncPrepCfg structure, use MPP_ENC_GET_CFG instead */ 126 MPP_ENC_SET_RC_CFG, /* deprecated set MppEncRcCfg structure, use MPP_ENC_SET_CFG instead */ 127 MPP_ENC_GET_RC_CFG, /* deprecated get MppEncRcCfg structure, use MPP_ENC_GET_CFG instead */ 128 MPP_ENC_SET_CODEC_CFG, /* deprecated set MppEncCodecCfg structure, use MPP_ENC_SET_CFG instead */ 129 MPP_ENC_GET_CODEC_CFG, /* deprecated get MppEncCodecCfg structure, use MPP_ENC_GET_CFG instead */ 130 /* runtime encoder setup control */ 131 MPP_ENC_SET_IDR_FRAME, /* next frame will be encoded as intra frame */ 132 MPP_ENC_SET_OSD_LEGACY_0, /* deprecated */ 133 MPP_ENC_SET_OSD_LEGACY_1, /* deprecated */ 134 MPP_ENC_SET_OSD_LEGACY_2, /* deprecated */ 135 MPP_ENC_GET_HDR_SYNC, /* get vps / sps / pps which has better sync behavior parameter is MppPacket */ 136 MPP_ENC_GET_EXTRA_INFO, /* deprecated */ 137 MPP_ENC_SET_SEI_CFG, /* SEI: Supplement Enhancemant Information, parameter is MppSeiMode */ 138 MPP_ENC_GET_SEI_DATA, /* SEI: Supplement Enhancemant Information, parameter is MppPacket */ 139 MPP_ENC_PRE_ALLOC_BUFF, /* deprecated */ 140 MPP_ENC_SET_QP_RANGE, /* used for adjusting qp range, the parameter can be 1 or 2 */ 141 MPP_ENC_SET_ROI_CFG, /* set MppEncROICfg structure */ 142 MPP_ENC_SET_CTU_QP, /* for H265 Encoder,set CTU's size and QP */ 143 144 MPP_ENC_CMD_QUERY = CMD_MODULE_CODEC | CMD_CTX_ID_ENC | CMD_ENC_QUERY, 145 /* query encoder runtime information for encode stage */ 146 MPP_ENC_QUERY, /* set and get MppEncQueryCfg structure */ 147 148 /* User define rate control stategy API control */ 149 MPP_ENC_CFG_RC_API = CMD_MODULE_CODEC | CMD_CTX_ID_ENC | CMD_ENC_CFG_RC_API, 150 /* 151 * Get RcApiQueryAll structure 152 * Get all available rate control stategy string and count 153 */ 154 MPP_ENC_GET_RC_API_ALL = MPP_ENC_CFG_RC_API + 1, 155 /* 156 * Get RcApiQueryType structure 157 * Get available rate control stategy string with certain type 158 */ 159 MPP_ENC_GET_RC_API_BY_TYPE = MPP_ENC_CFG_RC_API + 2, 160 /* 161 * Set RcImplApi structure 162 * Add new or update rate control stategy function pointers 163 */ 164 MPP_ENC_SET_RC_API_CFG = MPP_ENC_CFG_RC_API + 3, 165 /* 166 * Get RcApiBrief structure 167 * Get current used rate control stategy brief information (type and name) 168 */ 169 MPP_ENC_GET_RC_API_CURRENT = MPP_ENC_CFG_RC_API + 4, 170 /* 171 * Set RcApiBrief structure 172 * Set current used rate control stategy brief information (type and name) 173 */ 174 MPP_ENC_SET_RC_API_CURRENT = MPP_ENC_CFG_RC_API + 5, 175 176 MPP_ENC_CFG_MISC = CMD_MODULE_CODEC | CMD_CTX_ID_ENC | CMD_ENC_CFG_MISC, 177 MPP_ENC_SET_HEADER_MODE, /* set MppEncHeaderMode */ 178 MPP_ENC_GET_HEADER_MODE, /* get MppEncHeaderMode */ 179 180 MPP_ENC_CFG_SPLIT = CMD_MODULE_CODEC | CMD_CTX_ID_ENC | CMD_ENC_CFG_SPLIT, 181 MPP_ENC_SET_SPLIT, /* set MppEncSliceSplit structure */ 182 MPP_ENC_GET_SPLIT, /* get MppEncSliceSplit structure */ 183 184 MPP_ENC_CFG_REF = CMD_MODULE_CODEC | CMD_CTX_ID_ENC | CMD_ENC_CFG_REF, 185 MPP_ENC_SET_REF_CFG, /* set MppEncRefCfg structure */ 186 187 MPP_ENC_CFG_OSD = CMD_MODULE_CODEC | CMD_CTX_ID_ENC | CMD_ENC_CFG_OSD, 188 MPP_ENC_SET_OSD_PLT_CFG, /* set OSD palette, parameter should be pointer to MppEncOSDPltCfg */ 189 MPP_ENC_GET_OSD_PLT_CFG, /* get OSD palette, parameter should be pointer to MppEncOSDPltCfg */ 190 MPP_ENC_SET_OSD_DATA_CFG, /* set OSD data with at most 8 regions, parameter should be pointer to MppEncOSDData */ 191 192 MPP_ENC_CMD_END, 193 194 MPP_ISP_CMD_BASE = CMD_MODULE_CODEC | CMD_CTX_ID_ISP, 195 MPP_ISP_CMD_END, 196 197 MPP_HAL_CMD_BASE = CMD_MODULE_HAL, 198 MPP_HAL_CMD_END, 199 200 MPI_CMD_BUTT, 201 } MpiCmd; 202 203 #include "rk_vdec_cmd.h" 204 #include "rk_vdec_cfg.h" 205 #include "rk_venc_cmd.h" 206 #include "rk_venc_cfg.h" 207 #include "rk_venc_ref.h" 208 209 #endif /*__RK_MPI_CMD_H__*/ 210