1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2016 Rockchip Electronics Co., Ltd. 3*4882a593Smuzhiyun * Authors: 4*4882a593Smuzhiyun * Zhiqin Wei <wzq@rock-chips.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Licensed under the Apache License, Version 2.0 (the "License"); 7*4882a593Smuzhiyun * you may not use this file except in compliance with the License. 8*4882a593Smuzhiyun * You may obtain a copy of the License at 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * http://www.apache.org/licenses/LICENSE-2.0 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * Unless required by applicable law or agreed to in writing, software 13*4882a593Smuzhiyun * distributed under the License is distributed on an "AS IS" BASIS, 14*4882a593Smuzhiyun * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15*4882a593Smuzhiyun * See the License for the specific language governing permissions and 16*4882a593Smuzhiyun * limitations under the License. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #ifndef _RGA_DRIVER_H_ 20*4882a593Smuzhiyun #define _RGA_DRIVER_H_ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #ifndef ENABLE 24*4882a593Smuzhiyun #define ENABLE 1 25*4882a593Smuzhiyun #endif 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #ifndef DISABLE 28*4882a593Smuzhiyun #define DISABLE 0 29*4882a593Smuzhiyun #endif 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #ifdef __cplusplus 32*4882a593Smuzhiyun extern "C" 33*4882a593Smuzhiyun { 34*4882a593Smuzhiyun #endif 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* In order to be compatible with RK_FORMAT_XX and HAL_PIXEL_FORMAT_XX, 37*4882a593Smuzhiyun * RK_FORMAT_XX is shifted to the left by 8 bits to distinguish. */ 38*4882a593Smuzhiyun typedef enum _Rga_SURF_FORMAT { 39*4882a593Smuzhiyun RK_FORMAT_RGBA_8888 = 0x0 << 8, /* [0:31] R:G:B:A 8:8:8:8 little endian */ 40*4882a593Smuzhiyun RK_FORMAT_RGBX_8888 = 0x1 << 8, /* [0:31] R:G:B:X 8:8:8:8 little endian */ 41*4882a593Smuzhiyun RK_FORMAT_RGB_888 = 0x2 << 8, /* [0:23] R:G:B 8:8:8 little endian */ 42*4882a593Smuzhiyun RK_FORMAT_BGRA_8888 = 0x3 << 8, /* [0:31] B:G:R:A 8:8:8:8 little endian */ 43*4882a593Smuzhiyun RK_FORMAT_RGB_565 = 0x4 << 8, /* [0:15] R:G:B 5:6:5 little endian */ 44*4882a593Smuzhiyun RK_FORMAT_RGBA_5551 = 0x5 << 8, /* [0:15] R:G:B:A 5:5:5:1 little endian */ 45*4882a593Smuzhiyun RK_FORMAT_RGBA_4444 = 0x6 << 8, /* [0:15] R:G:B:A 4:4:4:4 little endian */ 46*4882a593Smuzhiyun RK_FORMAT_BGR_888 = 0x7 << 8, /* [0:23] B:G:R 8:8:8 little endian */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun RK_FORMAT_YCbCr_422_SP = 0x8 << 8, /* 2 plane YCbCr little endian 49*4882a593Smuzhiyun * plane 0: [0:7] Y 50*4882a593Smuzhiyun * plane 1: 2x1 subsampled [0:15] Cb:Cr 8:8 */ 51*4882a593Smuzhiyun RK_FORMAT_YCbCr_422_P = 0x9 << 8, /* 3 plane YCbCr little endian 52*4882a593Smuzhiyun * plane 0: [0:7] Y 53*4882a593Smuzhiyun * plane 1: 2x1 subsampled [0:7] Cb 54*4882a593Smuzhiyun * plane 2: 2x1 subsampled [0:7] Cr */ 55*4882a593Smuzhiyun RK_FORMAT_YCbCr_420_SP = 0xa << 8, /* 2 plane YCbCr little endian 56*4882a593Smuzhiyun * plane 0: [0:7] Y 57*4882a593Smuzhiyun * plane 1: 2x2 subsampled [0:15] Cr:Cb 8:8 */ 58*4882a593Smuzhiyun RK_FORMAT_YCbCr_420_P = 0xb << 8, /* 3 plane YCbCr little endian 59*4882a593Smuzhiyun * plane 0: [0:7] Y 60*4882a593Smuzhiyun * plane 1: 2x2 subsampled [0:7] Cb 61*4882a593Smuzhiyun * plane 2: 2x2 subsampled [0:7] Cr */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun RK_FORMAT_YCrCb_422_SP = 0xc << 8, /* 2 plane YCbCr little endian 64*4882a593Smuzhiyun * plane 0: [0:7] Y 65*4882a593Smuzhiyun * plane 1: 2x1 subsampled [0:15] Cb:Cr 8:8 */ 66*4882a593Smuzhiyun RK_FORMAT_YCrCb_422_P = 0xd << 8, /* 3 plane YCbCr little endian 67*4882a593Smuzhiyun * plane 0: [0:7] Y 68*4882a593Smuzhiyun * plane 1: 2x1 subsampled [0:7] Cr 69*4882a593Smuzhiyun * plane 2: 2x1 subsampled [0:7] Cb */ 70*4882a593Smuzhiyun RK_FORMAT_YCrCb_420_SP = 0xe << 8, /* 2 plane YCbCr little endian 71*4882a593Smuzhiyun * plane 0: [0:7] Y 72*4882a593Smuzhiyun * plane 1: 2x2 subsampled [0:15] Cb:Cr 8:8 */ 73*4882a593Smuzhiyun RK_FORMAT_YCrCb_420_P = 0xf << 8, /* 3 plane YCbCr little endian 74*4882a593Smuzhiyun * plane 0: [0:7] Y 75*4882a593Smuzhiyun * plane 1: 2x2 subsampled [0:7] Cr 76*4882a593Smuzhiyun * plane 2: 2x2 subsampled [0:7] Cb */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun RK_FORMAT_BPP1 = 0x10 << 8, /* [0] little endian */ 79*4882a593Smuzhiyun RK_FORMAT_BPP2 = 0x11 << 8, /* [0:1] little endian */ 80*4882a593Smuzhiyun RK_FORMAT_BPP4 = 0x12 << 8, /* [0:3] little endian */ 81*4882a593Smuzhiyun RK_FORMAT_BPP8 = 0x13 << 8, /* [0:7] little endian */ 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun RK_FORMAT_Y4 = 0x14 << 8, /* [0:3] Y little endian */ 84*4882a593Smuzhiyun RK_FORMAT_YCbCr_400 = 0x15 << 8, /* [0:7] Y little endian */ 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun RK_FORMAT_BGRX_8888 = 0x16 << 8, /* [0:31] B:G:R:X 8:8:8:8 little endian */ 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun RK_FORMAT_YVYU_422 = 0x18 << 8, /* [0:31] Y0:Cr0:Y1:cb0 8:8:8:8 little endian */ 89*4882a593Smuzhiyun RK_FORMAT_YVYU_420 = 0x19 << 8, /* ODD : [0:31] Y0:Cr0:Y1:cb0 8:8:8:8 little endian 90*4882a593Smuzhiyun * EVEN: [0:31] Y2:Y3:X:X 8:8:8:8 little endian */ 91*4882a593Smuzhiyun RK_FORMAT_VYUY_422 = 0x1a << 8, /* [0:31] Cr0:Y0:Cb0:Y1 8:8:8:8 little endian */ 92*4882a593Smuzhiyun RK_FORMAT_VYUY_420 = 0x1b << 8, /* ODD : [0:31] Cr0:Y0:Cb0:Y1 8:8:8:8 little endian 93*4882a593Smuzhiyun * EVEN: [0:31] Y2:Y3:X:X 8:8:8:8 little endian */ 94*4882a593Smuzhiyun RK_FORMAT_YUYV_422 = 0x1c << 8, /* [0:31] Y0:Cb0:Y1:cr0 8:8:8:8 little endian */ 95*4882a593Smuzhiyun RK_FORMAT_YUYV_420 = 0x1d << 8, /* ODD : [0:31] Y0:Cb0:Y1:cr0 8:8:8:8 little endian 96*4882a593Smuzhiyun * EVEN: [0:31] Y2:Y3:X:X 8:8:8:8 little endian */ 97*4882a593Smuzhiyun RK_FORMAT_UYVY_422 = 0x1e << 8, /* [0:31] Cb0:Y0:Cr0:Y1 8:8:8:8 little endian */ 98*4882a593Smuzhiyun RK_FORMAT_UYVY_420 = 0x1f << 8, /* ODD : [0:31] Cb0:Y0:Cr0:Y1 8:8:8:8 little endian 99*4882a593Smuzhiyun * EVEN: [0:31] Y2:Y3:X:X 8:8:8:8 little endian */ 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun RK_FORMAT_YCbCr_420_SP_10B = 0x20 << 8, /* 2 plane YCbCr little endian 102*4882a593Smuzhiyun * plane 0: [0:9] Y 103*4882a593Smuzhiyun * plane 1: 2x2 subsampled [0:19] Cb:Cr 10: 10 (default) 104*4882a593Smuzhiyun * or 105*4882a593Smuzhiyun * plane 1: 2x2 subsampled [0:23] Cb:Cr 16: 16 */ 106*4882a593Smuzhiyun RK_FORMAT_YCrCb_420_SP_10B = 0x21 << 8, /* 2 plane YCbCr little endian 107*4882a593Smuzhiyun * plane 0: [0:9] Y 108*4882a593Smuzhiyun * plane 1: 2x2 subsampled [0:19] Cr:Cb 10: 10 (default) 109*4882a593Smuzhiyun * or 110*4882a593Smuzhiyun * plane 1: 2x2 subsampled [0:23] Cr:Cb 16: 16 */ 111*4882a593Smuzhiyun RK_FORMAT_YCbCr_422_SP_10B = 0x22 << 8, /* 2 plane YCbCr little endian 112*4882a593Smuzhiyun * plane 0: [0:9] Y 113*4882a593Smuzhiyun * plane 1: 2x1 subsampled [0:19] Cb:Cr 10:10 (default) 114*4882a593Smuzhiyun * or 115*4882a593Smuzhiyun * plane 1: 2x1 subsampled [0:23] Cb:Cr 16: 16 */ 116*4882a593Smuzhiyun RK_FORMAT_YCrCb_422_SP_10B = 0x23 << 8, /* 2 plane YCbCr little endian 117*4882a593Smuzhiyun * plane 0: [0:9] Y 118*4882a593Smuzhiyun * plane 1: 2x1 subsampled [0:19] Cr:Cb 10:10 (default) 119*4882a593Smuzhiyun * or 120*4882a593Smuzhiyun * plane 1: 2x1 subsampled [0:23] Cr:Cb 16: 16 */ 121*4882a593Smuzhiyun /* For compatibility with misspellings */ 122*4882a593Smuzhiyun RK_FORMAT_YCbCr_422_10b_SP = RK_FORMAT_YCbCr_422_SP_10B << 8, 123*4882a593Smuzhiyun RK_FORMAT_YCrCb_422_10b_SP = RK_FORMAT_YCrCb_422_SP_10B << 8, 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun RK_FORMAT_BGR_565 = 0x24 << 8, /* [0:16] B:G:R 5:6:5 little endian */ 126*4882a593Smuzhiyun RK_FORMAT_BGRA_5551 = 0x25 << 8, /* [0:16] B:G:R:A 5:5:5:1 little endian */ 127*4882a593Smuzhiyun RK_FORMAT_BGRA_4444 = 0x26 << 8, /* [0:16] B:G:R:A 4:4:4:4 little endian */ 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun RK_FORMAT_ARGB_8888 = 0x28 << 8, /* [0:31] A:R:G:B 8:8:8:8 little endian */ 130*4882a593Smuzhiyun RK_FORMAT_XRGB_8888 = 0x29 << 8, /* [0:31] X:R:G:B 8:8:8:8 little endian */ 131*4882a593Smuzhiyun RK_FORMAT_ARGB_5551 = 0x2a << 8, /* [0:16] A:R:G:B 5:5:5:1 little endian */ 132*4882a593Smuzhiyun RK_FORMAT_ARGB_4444 = 0x2b << 8, /* [0:16] A:R:G:B 4:4:4:4 little endian */ 133*4882a593Smuzhiyun RK_FORMAT_ABGR_8888 = 0x2c << 8, /* [0:31] A:B:G:R 8:8:8:8 little endian */ 134*4882a593Smuzhiyun RK_FORMAT_XBGR_8888 = 0x2d << 8, /* [0:31] X:B:G:R 8:8:8:8 little endian */ 135*4882a593Smuzhiyun RK_FORMAT_ABGR_5551 = 0x2e << 8, /* [0:16] A:B:G:R 5:5:5:1 little endian */ 136*4882a593Smuzhiyun RK_FORMAT_ABGR_4444 = 0x2f << 8, /* [0:16] A:B:G:R 4:4:4:4 little endian */ 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun RK_FORMAT_RGBA2BPP = 0x30 << 8, /* [0:1] Color:Alpha 1:1 little endian */ 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun RK_FORMAT_UNKNOWN = 0x100 << 8, 141*4882a593Smuzhiyun } RgaSURF_FORMAT; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun enum { 144*4882a593Smuzhiyun yuv2rgb_mode0 = 0x0, /* BT.601 MPEG */ 145*4882a593Smuzhiyun yuv2rgb_mode1 = 0x1, /* BT.601 JPEG */ 146*4882a593Smuzhiyun yuv2rgb_mode2 = 0x2, /* BT.709 */ 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun rgb2yuv_601_full = 0x1 << 8, 149*4882a593Smuzhiyun rgb2yuv_709_full = 0x2 << 8, 150*4882a593Smuzhiyun yuv2yuv_601_limit_2_709_limit = 0x3 << 8, 151*4882a593Smuzhiyun yuv2yuv_601_limit_2_709_full = 0x4 << 8, 152*4882a593Smuzhiyun yuv2yuv_709_limit_2_601_limit = 0x5 << 8, 153*4882a593Smuzhiyun yuv2yuv_709_limit_2_601_full = 0x6 << 8, //not support 154*4882a593Smuzhiyun yuv2yuv_601_full_2_709_limit = 0x7 << 8, 155*4882a593Smuzhiyun yuv2yuv_601_full_2_709_full = 0x8 << 8, //not support 156*4882a593Smuzhiyun yuv2yuv_709_full_2_601_limit = 0x9 << 8, //not support 157*4882a593Smuzhiyun yuv2yuv_709_full_2_601_full = 0xa << 8, //not support 158*4882a593Smuzhiyun full_csc_mask = 0xf00, 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun enum { 162*4882a593Smuzhiyun RGA3_SCHEDULER_CORE0 = 1 << 0, 163*4882a593Smuzhiyun RGA3_SCHEDULER_CORE1 = 1 << 1, 164*4882a593Smuzhiyun RGA2_SCHEDULER_CORE0 = 1 << 2, 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun /* RGA3 rd_mode */ 168*4882a593Smuzhiyun enum 169*4882a593Smuzhiyun { 170*4882a593Smuzhiyun raster_mode = 0x1 << 0, 171*4882a593Smuzhiyun fbc_mode = 0x1 << 1, 172*4882a593Smuzhiyun tile_mode = 0x1 << 2, 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun #ifdef __cplusplus 176*4882a593Smuzhiyun } 177*4882a593Smuzhiyun #endif 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun #endif /*_RK29_IPP_DRIVER_H_*/ 180