1 /* 2 * Copyright (C) 2016 Rockchip Electronics Co., Ltd. 3 * Authors: 4 * Zhiqin Wei <wzq@rock-chips.com> 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 */ 18 19 #ifndef _RGA_DRIVER_H_ 20 #define _RGA_DRIVER_H_ 21 22 23 #ifndef ENABLE 24 #define ENABLE 1 25 #endif 26 27 #ifndef DISABLE 28 #define DISABLE 0 29 #endif 30 31 #ifdef __cplusplus 32 extern "C" 33 { 34 #endif 35 36 /* In order to be compatible with RK_FORMAT_XX and HAL_PIXEL_FORMAT_XX, 37 * RK_FORMAT_XX is shifted to the left by 8 bits to distinguish. */ 38 typedef enum _Rga_SURF_FORMAT { 39 RK_FORMAT_RGBA_8888 = 0x0 << 8, /* [0:31] R:G:B:A 8:8:8:8 little endian */ 40 RK_FORMAT_RGBX_8888 = 0x1 << 8, /* [0:31] R:G:B:X 8:8:8:8 little endian */ 41 RK_FORMAT_RGB_888 = 0x2 << 8, /* [0:23] R:G:B 8:8:8 little endian */ 42 RK_FORMAT_BGRA_8888 = 0x3 << 8, /* [0:31] B:G:R:A 8:8:8:8 little endian */ 43 RK_FORMAT_RGB_565 = 0x4 << 8, /* [0:15] R:G:B 5:6:5 little endian */ 44 RK_FORMAT_RGBA_5551 = 0x5 << 8, /* [0:15] R:G:B:A 5:5:5:1 little endian */ 45 RK_FORMAT_RGBA_4444 = 0x6 << 8, /* [0:15] R:G:B:A 4:4:4:4 little endian */ 46 RK_FORMAT_BGR_888 = 0x7 << 8, /* [0:23] B:G:R 8:8:8 little endian */ 47 48 RK_FORMAT_YCbCr_422_SP = 0x8 << 8, /* 2 plane YCbCr little endian 49 * plane 0: [0:7] Y 50 * plane 1: 2x1 subsampled [0:15] Cb:Cr 8:8 */ 51 RK_FORMAT_YCbCr_422_P = 0x9 << 8, /* 3 plane YCbCr little endian 52 * plane 0: [0:7] Y 53 * plane 1: 2x1 subsampled [0:7] Cb 54 * plane 2: 2x1 subsampled [0:7] Cr */ 55 RK_FORMAT_YCbCr_420_SP = 0xa << 8, /* 2 plane YCbCr little endian 56 * plane 0: [0:7] Y 57 * plane 1: 2x2 subsampled [0:15] Cr:Cb 8:8 */ 58 RK_FORMAT_YCbCr_420_P = 0xb << 8, /* 3 plane YCbCr little endian 59 * plane 0: [0:7] Y 60 * plane 1: 2x2 subsampled [0:7] Cb 61 * plane 2: 2x2 subsampled [0:7] Cr */ 62 63 RK_FORMAT_YCrCb_422_SP = 0xc << 8, /* 2 plane YCbCr little endian 64 * plane 0: [0:7] Y 65 * plane 1: 2x1 subsampled [0:15] Cb:Cr 8:8 */ 66 RK_FORMAT_YCrCb_422_P = 0xd << 8, /* 3 plane YCbCr little endian 67 * plane 0: [0:7] Y 68 * plane 1: 2x1 subsampled [0:7] Cr 69 * plane 2: 2x1 subsampled [0:7] Cb */ 70 RK_FORMAT_YCrCb_420_SP = 0xe << 8, /* 2 plane YCbCr little endian 71 * plane 0: [0:7] Y 72 * plane 1: 2x2 subsampled [0:15] Cb:Cr 8:8 */ 73 RK_FORMAT_YCrCb_420_P = 0xf << 8, /* 3 plane YCbCr little endian 74 * plane 0: [0:7] Y 75 * plane 1: 2x2 subsampled [0:7] Cr 76 * plane 2: 2x2 subsampled [0:7] Cb */ 77 78 RK_FORMAT_BPP1 = 0x10 << 8, /* [0] little endian */ 79 RK_FORMAT_BPP2 = 0x11 << 8, /* [0:1] little endian */ 80 RK_FORMAT_BPP4 = 0x12 << 8, /* [0:3] little endian */ 81 RK_FORMAT_BPP8 = 0x13 << 8, /* [0:7] little endian */ 82 83 RK_FORMAT_Y4 = 0x14 << 8, /* [0:3] Y little endian */ 84 RK_FORMAT_YCbCr_400 = 0x15 << 8, /* [0:7] Y little endian */ 85 86 RK_FORMAT_BGRX_8888 = 0x16 << 8, /* [0:31] B:G:R:X 8:8:8:8 little endian */ 87 88 RK_FORMAT_YVYU_422 = 0x18 << 8, /* [0:31] Y0:Cr0:Y1:cb0 8:8:8:8 little endian */ 89 RK_FORMAT_YVYU_420 = 0x19 << 8, /* ODD : [0:31] Y0:Cr0:Y1:cb0 8:8:8:8 little endian 90 * EVEN: [0:31] Y2:Y3:X:X 8:8:8:8 little endian */ 91 RK_FORMAT_VYUY_422 = 0x1a << 8, /* [0:31] Cr0:Y0:Cb0:Y1 8:8:8:8 little endian */ 92 RK_FORMAT_VYUY_420 = 0x1b << 8, /* ODD : [0:31] Cr0:Y0:Cb0:Y1 8:8:8:8 little endian 93 * EVEN: [0:31] Y2:Y3:X:X 8:8:8:8 little endian */ 94 RK_FORMAT_YUYV_422 = 0x1c << 8, /* [0:31] Y0:Cb0:Y1:cr0 8:8:8:8 little endian */ 95 RK_FORMAT_YUYV_420 = 0x1d << 8, /* ODD : [0:31] Y0:Cb0:Y1:cr0 8:8:8:8 little endian 96 * EVEN: [0:31] Y2:Y3:X:X 8:8:8:8 little endian */ 97 RK_FORMAT_UYVY_422 = 0x1e << 8, /* [0:31] Cb0:Y0:Cr0:Y1 8:8:8:8 little endian */ 98 RK_FORMAT_UYVY_420 = 0x1f << 8, /* ODD : [0:31] Cb0:Y0:Cr0:Y1 8:8:8:8 little endian 99 * EVEN: [0:31] Y2:Y3:X:X 8:8:8:8 little endian */ 100 101 RK_FORMAT_YCbCr_420_SP_10B = 0x20 << 8, /* 2 plane YCbCr little endian 102 * plane 0: [0:9] Y 103 * plane 1: 2x2 subsampled [0:19] Cb:Cr 10: 10 (default) 104 * or 105 * plane 1: 2x2 subsampled [0:23] Cb:Cr 16: 16 */ 106 RK_FORMAT_YCrCb_420_SP_10B = 0x21 << 8, /* 2 plane YCbCr little endian 107 * plane 0: [0:9] Y 108 * plane 1: 2x2 subsampled [0:19] Cr:Cb 10: 10 (default) 109 * or 110 * plane 1: 2x2 subsampled [0:23] Cr:Cb 16: 16 */ 111 RK_FORMAT_YCbCr_422_SP_10B = 0x22 << 8, /* 2 plane YCbCr little endian 112 * plane 0: [0:9] Y 113 * plane 1: 2x1 subsampled [0:19] Cb:Cr 10:10 (default) 114 * or 115 * plane 1: 2x1 subsampled [0:23] Cb:Cr 16: 16 */ 116 RK_FORMAT_YCrCb_422_SP_10B = 0x23 << 8, /* 2 plane YCbCr little endian 117 * plane 0: [0:9] Y 118 * plane 1: 2x1 subsampled [0:19] Cr:Cb 10:10 (default) 119 * or 120 * plane 1: 2x1 subsampled [0:23] Cr:Cb 16: 16 */ 121 /* For compatibility with misspellings */ 122 RK_FORMAT_YCbCr_422_10b_SP = RK_FORMAT_YCbCr_422_SP_10B << 8, 123 RK_FORMAT_YCrCb_422_10b_SP = RK_FORMAT_YCrCb_422_SP_10B << 8, 124 125 RK_FORMAT_BGR_565 = 0x24 << 8, /* [0:16] B:G:R 5:6:5 little endian */ 126 RK_FORMAT_BGRA_5551 = 0x25 << 8, /* [0:16] B:G:R:A 5:5:5:1 little endian */ 127 RK_FORMAT_BGRA_4444 = 0x26 << 8, /* [0:16] B:G:R:A 4:4:4:4 little endian */ 128 129 RK_FORMAT_ARGB_8888 = 0x28 << 8, /* [0:31] A:R:G:B 8:8:8:8 little endian */ 130 RK_FORMAT_XRGB_8888 = 0x29 << 8, /* [0:31] X:R:G:B 8:8:8:8 little endian */ 131 RK_FORMAT_ARGB_5551 = 0x2a << 8, /* [0:16] A:R:G:B 5:5:5:1 little endian */ 132 RK_FORMAT_ARGB_4444 = 0x2b << 8, /* [0:16] A:R:G:B 4:4:4:4 little endian */ 133 RK_FORMAT_ABGR_8888 = 0x2c << 8, /* [0:31] A:B:G:R 8:8:8:8 little endian */ 134 RK_FORMAT_XBGR_8888 = 0x2d << 8, /* [0:31] X:B:G:R 8:8:8:8 little endian */ 135 RK_FORMAT_ABGR_5551 = 0x2e << 8, /* [0:16] A:B:G:R 5:5:5:1 little endian */ 136 RK_FORMAT_ABGR_4444 = 0x2f << 8, /* [0:16] A:B:G:R 4:4:4:4 little endian */ 137 138 RK_FORMAT_RGBA2BPP = 0x30 << 8, /* [0:1] Color:Alpha 1:1 little endian */ 139 140 RK_FORMAT_UNKNOWN = 0x100 << 8, 141 } RgaSURF_FORMAT; 142 143 enum { 144 yuv2rgb_mode0 = 0x0, /* BT.601 MPEG */ 145 yuv2rgb_mode1 = 0x1, /* BT.601 JPEG */ 146 yuv2rgb_mode2 = 0x2, /* BT.709 */ 147 148 rgb2yuv_601_full = 0x1 << 8, 149 rgb2yuv_709_full = 0x2 << 8, 150 yuv2yuv_601_limit_2_709_limit = 0x3 << 8, 151 yuv2yuv_601_limit_2_709_full = 0x4 << 8, 152 yuv2yuv_709_limit_2_601_limit = 0x5 << 8, 153 yuv2yuv_709_limit_2_601_full = 0x6 << 8, //not support 154 yuv2yuv_601_full_2_709_limit = 0x7 << 8, 155 yuv2yuv_601_full_2_709_full = 0x8 << 8, //not support 156 yuv2yuv_709_full_2_601_limit = 0x9 << 8, //not support 157 yuv2yuv_709_full_2_601_full = 0xa << 8, //not support 158 full_csc_mask = 0xf00, 159 }; 160 161 enum { 162 RGA3_SCHEDULER_CORE0 = 1 << 0, 163 RGA3_SCHEDULER_CORE1 = 1 << 1, 164 RGA2_SCHEDULER_CORE0 = 1 << 2, 165 }; 166 167 /* RGA3 rd_mode */ 168 enum 169 { 170 raster_mode = 0x1 << 0, 171 fbc_mode = 0x1 << 1, 172 tile_mode = 0x1 << 2, 173 }; 174 175 #ifdef __cplusplus 176 } 177 #endif 178 179 #endif /*_RK29_IPP_DRIVER_H_*/ 180