1 /* 2 * Copyright (C) 2016 Rockchip Electronics Co., Ltd. 3 * Authors: 4 * Zhiqin Wei <wzq@rock-chips.com> 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 */ 18 19 #ifndef _RGA_DRIVER_H_ 20 #define _RGA_DRIVER_H_ 21 22 #ifdef __cplusplus 23 extern "C" 24 { 25 #endif 26 27 28 29 #define RGA_BLIT_SYNC 0x5017 30 #define RGA_BLIT_ASYNC 0x5018 31 #define RGA_FLUSH 0x5019 32 #define RGA_GET_RESULT 0x501a 33 #define RGA_GET_VERSION 0x501b 34 35 36 #define RGA_REG_CTRL_LEN 0x8 /* 8 */ 37 #define RGA_REG_CMD_LEN 0x1c /* 28 */ 38 #define RGA_CMD_BUF_SIZE 0x700 /* 16*28*4 */ 39 40 41 42 #ifndef ENABLE 43 #define ENABLE 1 44 #endif 45 46 47 #ifndef DISABLE 48 #define DISABLE 0 49 #endif 50 51 52 53 /* RGA process mode enum */ 54 enum { 55 bitblt_mode = 0x0, 56 color_palette_mode = 0x1, 57 color_fill_mode = 0x2, 58 line_point_drawing_mode = 0x3, 59 blur_sharp_filter_mode = 0x4, 60 pre_scaling_mode = 0x5, 61 update_palette_table_mode = 0x6, 62 update_patten_buff_mode = 0x7, 63 }; 64 65 66 enum { 67 rop_enable_mask = 0x2, 68 dither_enable_mask = 0x8, 69 fading_enable_mask = 0x10, 70 PD_enbale_mask = 0x20, 71 }; 72 73 enum { 74 yuv2rgb_mode0 = 0x0, /* BT.601 MPEG */ 75 yuv2rgb_mode1 = 0x1, /* BT.601 JPEG */ 76 yuv2rgb_mode2 = 0x2, /* BT.709 */ 77 }; 78 79 80 /* RGA rotate mode */ 81 enum { 82 rotate_mode0 = 0x0, /* no rotate */ 83 rotate_mode1 = 0x1, /* rotate */ 84 rotate_mode2 = 0x2, /* x_mirror */ 85 rotate_mode3 = 0x3, /* y_mirror */ 86 }; 87 88 enum { 89 color_palette_mode0 = 0x0, /* 1K */ 90 color_palette_mode1 = 0x1, /* 2K */ 91 color_palette_mode2 = 0x2, /* 4K */ 92 color_palette_mode3 = 0x3, /* 8K */ 93 }; 94 95 enum { 96 BB_BYPASS = 0x0, /* no rotate */ 97 BB_ROTATE = 0x1, /* rotate */ 98 BB_X_MIRROR = 0x2, /* x_mirror */ 99 BB_Y_MIRROR = 0x3 /* y_mirror */ 100 }; 101 102 enum { 103 nearby = 0x0, /* no rotate */ 104 bilinear = 0x1, /* rotate */ 105 bicubic = 0x2, /* x_mirror */ 106 }; 107 108 109 110 111 112 /* 113 // Alpha Red Green Blue 114 { 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888 115 { 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888 116 { 3, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGB_888 117 { 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_BGRA }, // RK_FORMAT_BGRA_8888 118 { 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565 119 { 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551 120 { 2, 16, {{ 4, 0, 16,12, 12, 8, 8, 4 }}, GGL_RGBA }, // RK_FORMAT_RGBA_4444 121 { 3, 24, {{ 0, 0, 24,16, 16, 8, 8, 0 }}, GGL_BGR }, // RK_FORMAT_BGB_888 122 123 */ 124 /* In order to be compatible with RK_FORMAT_XX and HAL_PIXEL_FORMAT_XX, 125 * RK_FORMAT_XX is shifted to the left by 8 bits to distinguish. */ 126 typedef enum _Rga_SURF_FORMAT { 127 RK_FORMAT_RGBA_8888 = 0x0 << 8, 128 RK_FORMAT_RGBX_8888 = 0x1 << 8, 129 RK_FORMAT_RGB_888 = 0x2 << 8, 130 RK_FORMAT_BGRA_8888 = 0x3 << 8, 131 RK_FORMAT_RGB_565 = 0x4 << 8, 132 RK_FORMAT_RGBA_5551 = 0x5 << 8, 133 RK_FORMAT_RGBA_4444 = 0x6 << 8, 134 RK_FORMAT_BGR_888 = 0x7 << 8, 135 136 RK_FORMAT_YCbCr_422_SP = 0x8 << 8, 137 RK_FORMAT_YCbCr_422_P = 0x9 << 8, 138 RK_FORMAT_YCbCr_420_SP = 0xa << 8, 139 RK_FORMAT_YCbCr_420_P = 0xb << 8, 140 141 RK_FORMAT_YCrCb_422_SP = 0xc << 8, 142 RK_FORMAT_YCrCb_422_P = 0xd << 8, 143 RK_FORMAT_YCrCb_420_SP = 0xe << 8, 144 RK_FORMAT_YCrCb_420_P = 0xf << 8, 145 146 RK_FORMAT_BPP1 = 0x10 << 8, 147 RK_FORMAT_BPP2 = 0x11 << 8, 148 RK_FORMAT_BPP4 = 0x12 << 8, 149 RK_FORMAT_BPP8 = 0x13 << 8, 150 151 RK_FORMAT_Y4 = 0x14 << 8, 152 RK_FORMAT_YCbCr_400 = 0x15 << 8, 153 154 RK_FORMAT_BGRX_8888 = 0x16 << 8, 155 156 RK_FORMAT_YVYU_422 = 0x18 << 8, 157 RK_FORMAT_YVYU_420 = 0x19 << 8, 158 RK_FORMAT_VYUY_422 = 0x1a << 8, 159 RK_FORMAT_VYUY_420 = 0x1b << 8, 160 RK_FORMAT_YUYV_422 = 0x1c << 8, 161 RK_FORMAT_YUYV_420 = 0x1d << 8, 162 RK_FORMAT_UYVY_422 = 0x1e << 8, 163 RK_FORMAT_UYVY_420 = 0x1f << 8, 164 165 RK_FORMAT_YCbCr_420_SP_10B = 0x20 << 8, 166 RK_FORMAT_YCrCb_420_SP_10B = 0x21 << 8, 167 RK_FORMAT_YCbCr_422_10b_SP = 0x22 << 8, 168 RK_FORMAT_YCrCb_422_10b_SP = 0x23 << 8, 169 RK_FORMAT_UNKNOWN = 0x100 << 8, 170 } RgaSURF_FORMAT; 171 172 173 typedef struct rga_img_info_t { 174 #if defined(__arm64__) || defined(__aarch64__) 175 unsigned long yrgb_addr; /* yrgb mem addr */ 176 unsigned long uv_addr; /* cb/cr mem addr */ 177 unsigned long v_addr; /* cr mem addr */ 178 #else 179 unsigned int yrgb_addr; /* yrgb mem addr */ 180 unsigned int uv_addr; /* cb/cr mem addr */ 181 unsigned int v_addr; /* cr mem addr */ 182 #endif 183 unsigned int format; //definition by RK_FORMAT 184 unsigned short act_w; 185 unsigned short act_h; 186 unsigned short x_offset; 187 unsigned short y_offset; 188 189 unsigned short vir_w; 190 unsigned short vir_h; 191 192 unsigned short endian_mode; //for BPP 193 unsigned short alpha_swap; 194 } 195 rga_img_info_t; 196 197 198 typedef struct mdp_img_act { 199 unsigned short w; // width 200 unsigned short h; // height 201 short x_off; // x offset for the vir 202 short y_off; // y offset for the vir 203 } 204 mdp_img_act; 205 206 207 208 typedef struct RANGE { 209 unsigned short min; 210 unsigned short max; 211 } 212 RANGE; 213 214 typedef struct POINT { 215 unsigned short x; 216 unsigned short y; 217 } 218 POINT; 219 220 typedef struct RECT { 221 unsigned short xmin; 222 unsigned short xmax; // width - 1 223 unsigned short ymin; 224 unsigned short ymax; // height - 1 225 } RECT; 226 227 typedef struct RGB { 228 unsigned char r; 229 unsigned char g; 230 unsigned char b; 231 unsigned char res; 232 }RGB; 233 234 235 typedef struct MMU { 236 unsigned char mmu_en; 237 #if defined(__arm64__) || defined(__aarch64__) 238 unsigned long base_addr; 239 #else 240 unsigned int base_addr; 241 #endif 242 unsigned int mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/ 243 } MMU; 244 245 246 247 248 typedef struct COLOR_FILL { 249 short gr_x_a; 250 short gr_y_a; 251 short gr_x_b; 252 short gr_y_b; 253 short gr_x_g; 254 short gr_y_g; 255 short gr_x_r; 256 short gr_y_r; 257 258 //u8 cp_gr_saturation; 259 } 260 COLOR_FILL; 261 262 typedef struct FADING { 263 unsigned char b; 264 unsigned char g; 265 unsigned char r; 266 unsigned char res; 267 } 268 FADING; 269 270 271 typedef struct line_draw_t { 272 POINT start_point; /* LineDraw_start_point */ 273 POINT end_point; /* LineDraw_end_point */ 274 unsigned int color; /* LineDraw_color */ 275 unsigned int flag; /* (enum) LineDrawing mode sel */ 276 unsigned int line_width; /* range 1~16 */ 277 } 278 line_draw_t; 279 280 281 282 struct rga_req { 283 unsigned char render_mode; /* (enum) process mode sel */ 284 285 rga_img_info_t src; /* src image info */ 286 rga_img_info_t dst; /* dst image info */ 287 rga_img_info_t pat; /* patten image info */ 288 289 #if defined(__arm64__) || defined(__aarch64__) 290 unsigned long rop_mask_addr; /* rop4 mask addr */ 291 unsigned long LUT_addr; /* LUT addr */ 292 #else 293 unsigned int rop_mask_addr; /* rop4 mask addr */ 294 unsigned int LUT_addr; /* LUT addr */ 295 #endif 296 297 RECT clip; /* dst clip window default value is dst_vir */ 298 /* value from [0, w-1] / [0, h-1]*/ 299 300 int sina; /* dst angle default value 0 16.16 scan from table */ 301 int cosa; /* dst angle default value 0 16.16 scan from table */ 302 303 unsigned short alpha_rop_flag; /* alpha rop process flag */ 304 /* ([0] = 1 alpha_rop_enable) */ 305 /* ([1] = 1 rop enable) */ 306 /* ([2] = 1 fading_enable) */ 307 /* ([3] = 1 PD_enable) */ 308 /* ([4] = 1 alpha cal_mode_sel) */ 309 /* ([5] = 1 dither_enable) */ 310 /* ([6] = 1 gradient fill mode sel) */ 311 /* ([7] = 1 AA_enable) */ 312 /* ([8] = 1 nn_quantize) */ 313 /* ([9] = 1 Real color mode) */ 314 315 unsigned char scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */ 316 317 unsigned int color_key_max; /* color key max */ 318 unsigned int color_key_min; /* color key min */ 319 320 unsigned int fg_color; /* foreground color */ 321 unsigned int bg_color; /* background color */ 322 323 COLOR_FILL gr_color; /* color fill use gradient */ 324 325 line_draw_t line_draw_info; 326 327 FADING fading; 328 329 unsigned char PD_mode; /* porter duff alpha mode sel */ 330 331 unsigned char alpha_global_value; /* global alpha value */ 332 333 unsigned short rop_code; /* rop2/3/4 code scan from rop code table*/ 334 335 unsigned char bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/ 336 337 unsigned char palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/ 338 339 unsigned char yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ 340 341 unsigned char endian_mode; /* 0/big endian 1/little endian*/ 342 343 unsigned char rotate_mode; /* (enum) rotate mode */ 344 /* 0x0, no rotate */ 345 /* 0x1, rotate */ 346 /* 0x2, x_mirror */ 347 /* 0x3, y_mirror */ 348 349 unsigned char color_fill_mode; /* 0 solid color / 1 patten color */ 350 351 MMU mmu_info; /* mmu information */ 352 353 unsigned char alpha_rop_mode; /* ([0~1] alpha mode) */ 354 /* ([2~3] rop mode) */ 355 /* ([4] zero mode en) */ 356 /* ([5] dst alpha mode) */ 357 358 unsigned char src_trans_mode; 359 360 unsigned char dither_mode; 361 362 unsigned char CMD_fin_int_enable; 363 364 /* completion is reported through a callback */ 365 void (*complete)(int retval); 366 }; 367 368 #if 0 369 typedef struct TILE_INFO { 370 int64_t matrix[4]; 371 372 uint16_t tile_x_num; /* x axis tile num / tile size is 8x8 pixel */ 373 uint16_t tile_y_num; /* y axis tile num */ 374 375 int16_t dst_x_tmp; /* dst pos x = (xstart - xoff) default value 0 */ 376 int16_t dst_y_tmp; /* dst pos y = (ystart - yoff) default value 0 */ 377 378 uint16_t tile_w; 379 uint16_t tile_h; 380 int16_t tile_start_x_coor; 381 int16_t tile_start_y_coor; 382 int32_t tile_xoff; 383 int32_t tile_yoff; 384 385 int32_t tile_temp_xstart; 386 int32_t tile_temp_ystart; 387 388 /* src tile incr */ 389 int32_t x_dx; 390 int32_t x_dy; 391 int32_t y_dx; 392 int32_t y_dy; 393 394 mdp_img_act dst_ctrl; 395 396 } 397 TILE_INFO; 398 #endif 399 400 #if 0 401 402 #define RGA_BASE 0x10114000 403 404 //General Registers 405 #define RGA_SYS_CTRL 0x000 406 #define RGA_CMD_CTRL 0x004 407 #define RGA_CMD_ADDR 0x008 408 #define RGA_STATUS 0x00c 409 #define RGA_INT 0x010 410 #define RGA_AXI_ID 0x014 411 #define RGA_MMU_STA_CTRL 0x018 412 #define RGA_MMU_STA 0x01c 413 414 //Command code start 415 #define RGA_MODE_CTRL 0x100 416 417 //Source Image Registers 418 #define RGA_SRC_Y_MST 0x104 419 #define RGA_SRC_CB_MST 0x108 420 #define RGA_MASK_READ_MST 0x108 //repeat 421 #define RGA_SRC_CR_MST 0x10c 422 #define RGA_SRC_VIR_INFO 0x110 423 #define RGA_SRC_ACT_INFO 0x114 424 #define RGA_SRC_X_PARA 0x118 425 #define RGA_SRC_Y_PARA 0x11c 426 #define RGA_SRC_TILE_XINFO 0x120 427 #define RGA_SRC_TILE_YINFO 0x124 428 #define RGA_SRC_TILE_H_INCR 0x128 429 #define RGA_SRC_TILE_V_INCR 0x12c 430 #define RGA_SRC_TILE_OFFSETX 0x130 431 #define RGA_SRC_TILE_OFFSETY 0x134 432 #define RGA_SRC_BG_COLOR 0x138 433 #define RGA_SRC_FG_COLOR 0x13c 434 #define RGA_LINE_DRAWING_COLOR 0x13c //repeat 435 #define RGA_SRC_TR_COLOR0 0x140 436 #define RGA_CP_GR_A 0x140 //repeat 437 #define RGA_SRC_TR_COLOR1 0x144 438 #define RGA_CP_GR_B 0x144 //repeat 439 440 #define RGA_LINE_DRAW 0x148 441 #define RGA_PAT_START_POINT 0x148 //repeat 442 443 //Destination Image Registers 444 #define RGA_DST_MST 0x14c 445 #define RGA_LUT_MST 0x14c //repeat 446 #define RGA_PAT_MST 0x14c //repeat 447 #define RGA_LINE_DRAWING_MST 0x14c //repeat 448 449 #define RGA_DST_VIR_INFO 0x150 450 451 #define RGA_DST_CTR_INFO 0x154 452 #define RGA_LINE_DRAW_XY_INFO 0x154 //repeat 453 454 //Alpha/ROP Registers 455 #define RGA_ALPHA_CON 0x158 456 457 #define RGA_PAT_CON 0x15c 458 #define RGA_DST_VIR_WIDTH_PIX 0x15c //repeat 459 460 #define RGA_ROP_CON0 0x160 461 #define RGA_CP_GR_G 0x160 //repeat 462 #define RGA_PRESCL_CB_MST 0x160 //repeat 463 464 #define RGA_ROP_CON1 0x164 465 #define RGA_CP_GR_R 0x164 //repeat 466 #define RGA_PRESCL_CR_MST 0x164 //repeat 467 468 //MMU Register 469 #define RGA_FADING_CON 0x168 470 #define RGA_MMU_CTRL 0x168 //repeat 471 472 #define RGA_MMU_TBL 0x16c //repeat 473 474 475 #define RGA_BLIT_COMPLETE_EVENT 1 476 477 #endif 478 479 int 480 RGA_set_src_act_info( 481 struct rga_req *req, 482 unsigned int width, /* act width */ 483 unsigned int height, /* act height */ 484 unsigned int x_off, /* x_off */ 485 unsigned int y_off /* y_off */ 486 ); 487 488 #if defined(__arm64__) || defined(__aarch64__) 489 int 490 RGA_set_src_vir_info( 491 struct rga_req *req, 492 unsigned long yrgb_addr, /* yrgb_addr */ 493 unsigned long uv_addr, /* uv_addr */ 494 unsigned long v_addr, /* v_addr */ 495 unsigned int vir_w, /* vir width */ 496 unsigned int vir_h, /* vir height */ 497 unsigned char format, /* format */ 498 unsigned char a_swap_en /* only for 32bit RGB888 format */ 499 ); 500 #else 501 int 502 RGA_set_src_vir_info( 503 struct rga_req *req, 504 unsigned int yrgb_addr, /* yrgb_addr */ 505 unsigned int uv_addr, /* uv_addr */ 506 unsigned int v_addr, /* v_addr */ 507 unsigned int vir_w, /* vir width */ 508 unsigned int vir_h, /* vir height */ 509 unsigned char format, /* format */ 510 unsigned char a_swap_en /* only for 32bit RGB888 format */ 511 ); 512 #endif 513 514 int 515 RGA_set_dst_act_info( 516 struct rga_req *req, 517 unsigned int width, /* act width */ 518 unsigned int height, /* act height */ 519 unsigned int x_off, /* x_off */ 520 unsigned int y_off /* y_off */ 521 ); 522 523 #if defined(__arm64__) || defined(__aarch64__) 524 int 525 RGA_set_dst_vir_info( 526 struct rga_req *msg, 527 unsigned long yrgb_addr, /* yrgb_addr */ 528 unsigned long uv_addr, /* uv_addr */ 529 unsigned long v_addr, /* v_addr */ 530 unsigned int vir_w, /* vir width */ 531 unsigned int vir_h, /* vir height */ 532 RECT *clip, /* clip window */ 533 unsigned char format, /* format */ 534 unsigned char a_swap_en 535 ); 536 #else 537 int 538 RGA_set_dst_vir_info( 539 struct rga_req *msg, 540 unsigned int yrgb_addr, /* yrgb_addr */ 541 unsigned int uv_addr, /* uv_addr */ 542 unsigned int v_addr, /* v_addr */ 543 unsigned int vir_w, /* vir width */ 544 unsigned int vir_h, /* vir height */ 545 RECT *clip, /* clip window */ 546 unsigned char format, /* format */ 547 unsigned char a_swap_en 548 ); 549 #endif 550 551 int 552 RGA_set_pat_info( 553 struct rga_req *msg, 554 unsigned int width, 555 unsigned int height, 556 unsigned int x_off, 557 unsigned int y_off, 558 unsigned int pat_format 559 ); 560 561 #if defined(__arm64__) || defined(__aarch64__) 562 int 563 RGA_set_rop_mask_info( 564 struct rga_req *msg, 565 unsigned long rop_mask_addr, 566 unsigned int rop_mask_endian_mode 567 ); 568 #else 569 int 570 RGA_set_rop_mask_info( 571 struct rga_req *msg, 572 unsigned int rop_mask_addr, 573 unsigned int rop_mask_endian_mode 574 ); 575 #endif 576 577 int RGA_set_alpha_en_info( 578 struct rga_req *msg, 579 unsigned int alpha_cal_mode, /* 0:alpha' = alpha + (alpha>>7) | alpha' = alpha */ 580 unsigned int alpha_mode, /* 0 global alpha / 1 per pixel alpha / 2 mix mode */ 581 unsigned int global_a_value, 582 unsigned int PD_en, /* porter duff alpha mode en */ 583 unsigned int PD_mode, 584 unsigned int dst_alpha_en ); /* use dst alpha */ 585 586 int 587 RGA_set_rop_en_info( 588 struct rga_req *msg, 589 unsigned int ROP_mode, 590 unsigned int ROP_code, 591 unsigned int color_mode, 592 unsigned int solid_color 593 ); 594 595 596 int 597 RGA_set_fading_en_info( 598 struct rga_req *msg, 599 unsigned char r, 600 unsigned char g, 601 unsigned char b 602 ); 603 604 int 605 RGA_set_src_trans_mode_info( 606 struct rga_req *msg, 607 unsigned char trans_mode, 608 unsigned char a_en, 609 unsigned char b_en, 610 unsigned char g_en, 611 unsigned char r_en, 612 unsigned char color_key_min, 613 unsigned char color_key_max, 614 unsigned char zero_mode_en 615 ); 616 617 618 int 619 RGA_set_bitblt_mode( 620 struct rga_req *msg, 621 unsigned char scale_mode, // 0/near 1/bilnear 2/bicubic 622 unsigned char rotate_mode, // 0/copy 1/rotate_scale 2/x_mirror 3/y_mirror 623 unsigned int angle, // rotate angle 624 unsigned int dither_en, // dither en flag 625 unsigned int AA_en, // AA flag 626 unsigned int yuv2rgb_mode 627 ); 628 629 630 int 631 RGA_set_color_palette_mode( 632 struct rga_req *msg, 633 unsigned char palette_mode, /* 1bpp/2bpp/4bpp/8bpp */ 634 unsigned char endian_mode, /* src endian mode sel */ 635 unsigned int bpp1_0_color, /* BPP1 = 0 */ 636 unsigned int bpp1_1_color /* BPP1 = 1 */ 637 ); 638 639 640 int 641 RGA_set_color_fill_mode( 642 struct rga_req *msg, 643 COLOR_FILL *gr_color, /* gradient color part */ 644 unsigned char gr_satur_mode, /* saturation mode */ 645 unsigned char cf_mode, /* patten fill or solid fill */ 646 unsigned int color, /* solid color */ 647 unsigned short pat_width, /* pattern width */ 648 unsigned short pat_height, /* pattern height */ 649 unsigned char pat_x_off, /* pattern x offset */ 650 unsigned char pat_y_off, /* pattern y offset */ 651 unsigned char aa_en /* alpha en */ 652 ); 653 654 655 int 656 RGA_set_line_point_drawing_mode( 657 struct rga_req *msg, 658 POINT sp, /* start point */ 659 POINT ep, /* end point */ 660 unsigned int color, /* line point drawing color */ 661 unsigned int line_width, /* line width */ 662 unsigned char AA_en, /* AA en */ 663 unsigned char last_point_en /* last point en */ 664 ); 665 666 667 int 668 RGA_set_blur_sharp_filter_mode( 669 struct rga_req *msg, 670 unsigned char filter_mode, /* blur/sharpness */ 671 unsigned char filter_type, /* filter intensity */ 672 unsigned char dither_en /* dither_en flag */ 673 ); 674 675 int 676 RGA_set_pre_scaling_mode( 677 struct rga_req *msg, 678 unsigned char dither_en 679 ); 680 681 #if defined(__arm64__) || defined(__aarch64__) 682 int 683 RGA_update_palette_table_mode( 684 struct rga_req *msg, 685 unsigned long LUT_addr, /* LUT table addr */ 686 unsigned int palette_mode /* 1bpp/2bpp/4bpp/8bpp */ 687 ); 688 #else 689 int 690 RGA_update_palette_table_mode( 691 struct rga_req *msg, 692 unsigned int LUT_addr, /* LUT table addr */ 693 unsigned int palette_mode /* 1bpp/2bpp/4bpp/8bpp */ 694 ); 695 #endif 696 697 int 698 RGA_set_update_patten_buff_mode( 699 struct rga_req *msg, 700 unsigned int pat_addr, /* patten addr */ 701 unsigned int w, /* patten width */ 702 unsigned int h, /* patten height */ 703 unsigned int format /* patten format */ 704 ); 705 706 #if defined(__arm64__) || defined(__aarch64__) 707 int 708 RGA_set_mmu_info( 709 struct rga_req *msg, 710 unsigned char mmu_en, 711 unsigned char src_flush, 712 unsigned char dst_flush, 713 unsigned char cmd_flush, 714 unsigned long base_addr, 715 unsigned char page_size 716 ); 717 #else 718 int 719 RGA_set_mmu_info( 720 struct rga_req *msg, 721 unsigned char mmu_en, 722 unsigned char src_flush, 723 unsigned char dst_flush, 724 unsigned char cmd_flush, 725 unsigned int base_addr, 726 unsigned char page_size 727 ); 728 #endif 729 730 void rga_set_fds_offsets( 731 struct rga_req *rga_request, 732 unsigned short src_fd, 733 unsigned short dst_fd, 734 unsigned int src_offset, 735 unsigned int dst_offset); 736 737 int 738 RGA_set_src_fence_flag( 739 struct rga_req *msg, 740 int acq_fence, 741 int src_flag 742 ); 743 744 745 int 746 RGA_set_dst_fence_flag( 747 struct rga_req *msg, 748 int dst_flag 749 ); 750 751 int 752 RGA_get_dst_fence( 753 struct rga_req *msg 754 ); 755 #ifdef __cplusplus 756 } 757 #endif 758 759 #endif /*_RK29_IPP_DRIVER_H_*/ 760