1 /* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR MIT) 2 * 3 * Rockchip isp2 driver 4 * Copyright (C) 2017 Rockchip Electronics Co., Ltd. 5 */ 6 7 #ifndef _UAPI_RKISP2_CONFIG_H 8 #define _UAPI_RKISP2_CONFIG_H 9 10 #include <linux/types.h> 11 #include <linux/v4l2-controls.h> 12 13 #include "rk_isp20_hw.h" 14 15 #define RKISP_API_VERSION KERNEL_VERSION(2, 1, 0) 16 17 #ifndef BIT 18 #define BIT(x) (~0ULL & (1ULL << x)) 19 #endif 20 21 /****************ISP SUBDEV IOCTL*****************************/ 22 23 #define RKISP_CMD_TRIGGER_READ_BACK \ 24 _IOW('V', BASE_VIDIOC_PRIVATE + 0, struct isp2x_csi_trigger) 25 26 #define RKISP_CMD_GET_ISP_INFO \ 27 _IOR('V', BASE_VIDIOC_PRIVATE + 1, struct rkisp_isp_info) 28 29 #define RKISP_CMD_GET_SHARED_BUF \ 30 _IOR('V', BASE_VIDIOC_PRIVATE + 2, struct rkisp_thunderboot_resmem) 31 32 #define RKISP_CMD_FREE_SHARED_BUF \ 33 _IO('V', BASE_VIDIOC_PRIVATE + 3) 34 35 #define RKISP_CMD_GET_LDCHBUF_INFO \ 36 _IOR('V', BASE_VIDIOC_PRIVATE + 4, struct rkisp_ldchbuf_info) 37 38 #define RKISP_CMD_SET_LDCHBUF_SIZE \ 39 _IOW('V', BASE_VIDIOC_PRIVATE + 5, struct rkisp_ldchbuf_size) 40 41 #define RKISP_CMD_GET_SHM_BUFFD \ 42 _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct rkisp_thunderboot_shmem) 43 44 #define RKISP_CMD_GET_FBCBUF_FD \ 45 _IOR('V', BASE_VIDIOC_PRIVATE + 7, struct isp2x_buf_idxfd) 46 47 #define RKISP_CMD_GET_MESHBUF_INFO \ 48 _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct rkisp_meshbuf_info) 49 50 #define RKISP_CMD_SET_MESHBUF_SIZE \ 51 _IOW('V', BASE_VIDIOC_PRIVATE + 9, struct rkisp_meshbuf_size) 52 53 #define RKISP_CMD_INFO2DDR \ 54 _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct rkisp_info2ddr) 55 56 #define RKISP_CMD_MESHBUF_FREE \ 57 _IOW('V', BASE_VIDIOC_PRIVATE + 11, long long) 58 59 /* BASE_VIDIOC_PRIVATE + 12 for RKISP_CMD_GET_TB_HEAD_V32 */ 60 61 /* for all isp device stop and no power off but resolution change */ 62 #define RKISP_CMD_MULTI_DEV_FORCE_ENUM \ 63 _IO('V', BASE_VIDIOC_PRIVATE + 13) 64 65 /****************ISP VIDEO IOCTL******************************/ 66 67 #define RKISP_CMD_GET_CSI_MEMORY_MODE \ 68 _IOR('V', BASE_VIDIOC_PRIVATE + 100, int) 69 70 #define RKISP_CMD_SET_CSI_MEMORY_MODE \ 71 _IOW('V', BASE_VIDIOC_PRIVATE + 101, int) 72 73 #define RKISP_CMD_GET_CMSK \ 74 _IOR('V', BASE_VIDIOC_PRIVATE + 102, struct rkisp_cmsk_cfg) 75 76 #define RKISP_CMD_SET_CMSK \ 77 _IOW('V', BASE_VIDIOC_PRIVATE + 103, struct rkisp_cmsk_cfg) 78 79 #define RKISP_CMD_GET_STREAM_INFO \ 80 _IOR('V', BASE_VIDIOC_PRIVATE + 104, struct rkisp_stream_info) 81 82 #define RKISP_CMD_GET_MIRROR_FLIP \ 83 _IOR('V', BASE_VIDIOC_PRIVATE + 105, struct rkisp_mirror_flip) 84 85 #define RKISP_CMD_SET_MIRROR_FLIP \ 86 _IOW('V', BASE_VIDIOC_PRIVATE + 106, struct rkisp_mirror_flip) 87 88 #define RKISP_CMD_GET_WRAP_LINE \ 89 _IOR('V', BASE_VIDIOC_PRIVATE + 107, struct rkisp_wrap_info) 90 /* set wrap line before VIDIOC_S_FMT */ 91 #define RKISP_CMD_SET_WRAP_LINE \ 92 _IOW('V', BASE_VIDIOC_PRIVATE + 108, struct rkisp_wrap_info) 93 94 #define RKISP_CMD_SET_FPS \ 95 _IOW('V', BASE_VIDIOC_PRIVATE + 109, int) 96 97 #define RKISP_CMD_GET_FPS \ 98 _IOR('V', BASE_VIDIOC_PRIVATE + 110, int) 99 100 #define RKISP_CMD_GET_TB_STREAM_INFO \ 101 _IOR('V', BASE_VIDIOC_PRIVATE + 111, struct rkisp_tb_stream_info) 102 103 #define RKISP_CMD_FREE_TB_STREAM_BUF \ 104 _IO('V', BASE_VIDIOC_PRIVATE + 112) 105 106 /* Private v4l2 event */ 107 #define CIFISP_V4L2_EVENT_STREAM_START \ 108 (V4L2_EVENT_PRIVATE_START + 1) 109 110 #define CIFISP_V4L2_EVENT_STREAM_STOP \ 111 (V4L2_EVENT_PRIVATE_START + 2) 112 113 #define RKISP_CMD_SET_IQTOOL_CONN_ID \ 114 _IOW('V', BASE_VIDIOC_PRIVATE + 113, int) 115 /*************************************************************/ 116 117 #define ISP2X_ID_DPCC (0) 118 #define ISP2X_ID_BLS (1) 119 #define ISP2X_ID_SDG (2) 120 #define ISP2X_ID_SIHST (3) 121 #define ISP2X_ID_LSC (4) 122 #define ISP2X_ID_AWB_GAIN (5) 123 #define ISP2X_ID_BDM (7) 124 #define ISP2X_ID_CCM (8) 125 #define ISP2X_ID_GOC (9) 126 #define ISP2X_ID_CPROC (10) 127 #define ISP2X_ID_SIAF (11) 128 #define ISP2X_ID_SIAWB (12) 129 #define ISP2X_ID_IE (13) 130 #define ISP2X_ID_YUVAE (14) 131 #define ISP2X_ID_WDR (15) 132 #define ISP2X_ID_RK_IESHARP (16) 133 #define ISP2X_ID_RAWAF (17) 134 #define ISP2X_ID_RAWAE0 (18) 135 #define ISP2X_ID_RAWAE1 (19) 136 #define ISP2X_ID_RAWAE2 (20) 137 #define ISP2X_ID_RAWAE3 (21) 138 #define ISP2X_ID_RAWAWB (22) 139 #define ISP2X_ID_RAWHIST0 (23) 140 #define ISP2X_ID_RAWHIST1 (24) 141 #define ISP2X_ID_RAWHIST2 (25) 142 #define ISP2X_ID_RAWHIST3 (26) 143 #define ISP2X_ID_HDRMGE (27) 144 #define ISP2X_ID_RAWNR (28) 145 #define ISP2X_ID_HDRTMO (29) 146 #define ISP2X_ID_GIC (30) 147 #define ISP2X_ID_DHAZ (31) 148 #define ISP2X_ID_3DLUT (32) 149 #define ISP2X_ID_LDCH (33) 150 #define ISP2X_ID_GAIN (34) 151 #define ISP2X_ID_DEBAYER (35) 152 #define ISP2X_ID_MAX (63) 153 154 #define ISP2X_MODULE_DPCC BIT_ULL(ISP2X_ID_DPCC) 155 #define ISP2X_MODULE_BLS BIT_ULL(ISP2X_ID_BLS) 156 #define ISP2X_MODULE_SDG BIT_ULL(ISP2X_ID_SDG) 157 #define ISP2X_MODULE_SIHST BIT_ULL(ISP2X_ID_SIHST) 158 #define ISP2X_MODULE_LSC BIT_ULL(ISP2X_ID_LSC) 159 #define ISP2X_MODULE_AWB_GAIN BIT_ULL(ISP2X_ID_AWB_GAIN) 160 #define ISP2X_MODULE_BDM BIT_ULL(ISP2X_ID_BDM) 161 #define ISP2X_MODULE_CCM BIT_ULL(ISP2X_ID_CCM) 162 #define ISP2X_MODULE_GOC BIT_ULL(ISP2X_ID_GOC) 163 #define ISP2X_MODULE_CPROC BIT_ULL(ISP2X_ID_CPROC) 164 #define ISP2X_MODULE_SIAF BIT_ULL(ISP2X_ID_SIAF) 165 #define ISP2X_MODULE_SIAWB BIT_ULL(ISP2X_ID_SIAWB) 166 #define ISP2X_MODULE_IE BIT_ULL(ISP2X_ID_IE) 167 #define ISP2X_MODULE_YUVAE BIT_ULL(ISP2X_ID_YUVAE) 168 #define ISP2X_MODULE_WDR BIT_ULL(ISP2X_ID_WDR) 169 #define ISP2X_MODULE_RK_IESHARP BIT_ULL(ISP2X_ID_RK_IESHARP) 170 #define ISP2X_MODULE_RAWAF BIT_ULL(ISP2X_ID_RAWAF) 171 #define ISP2X_MODULE_RAWAE0 BIT_ULL(ISP2X_ID_RAWAE0) 172 #define ISP2X_MODULE_RAWAE1 BIT_ULL(ISP2X_ID_RAWAE1) 173 #define ISP2X_MODULE_RAWAE2 BIT_ULL(ISP2X_ID_RAWAE2) 174 #define ISP2X_MODULE_RAWAE3 BIT_ULL(ISP2X_ID_RAWAE3) 175 #define ISP2X_MODULE_RAWAWB BIT_ULL(ISP2X_ID_RAWAWB) 176 #define ISP2X_MODULE_RAWHIST0 BIT_ULL(ISP2X_ID_RAWHIST0) 177 #define ISP2X_MODULE_RAWHIST1 BIT_ULL(ISP2X_ID_RAWHIST1) 178 #define ISP2X_MODULE_RAWHIST2 BIT_ULL(ISP2X_ID_RAWHIST2) 179 #define ISP2X_MODULE_RAWHIST3 BIT_ULL(ISP2X_ID_RAWHIST3) 180 #define ISP2X_MODULE_HDRMGE BIT_ULL(ISP2X_ID_HDRMGE) 181 #define ISP2X_MODULE_RAWNR BIT_ULL(ISP2X_ID_RAWNR) 182 #define ISP2X_MODULE_HDRTMO BIT_ULL(ISP2X_ID_HDRTMO) 183 #define ISP2X_MODULE_GIC BIT_ULL(ISP2X_ID_GIC) 184 #define ISP2X_MODULE_DHAZ BIT_ULL(ISP2X_ID_DHAZ) 185 #define ISP2X_MODULE_3DLUT BIT_ULL(ISP2X_ID_3DLUT) 186 #define ISP2X_MODULE_LDCH BIT_ULL(ISP2X_ID_LDCH) 187 #define ISP2X_MODULE_GAIN BIT_ULL(ISP2X_ID_GAIN) 188 #define ISP2X_MODULE_DEBAYER BIT_ULL(ISP2X_ID_DEBAYER) 189 190 #define ISP2X_MODULE_FORCE BIT_ULL(ISP2X_ID_MAX) 191 192 /* 193 * Measurement types 194 */ 195 #define ISP2X_STAT_SIAWB BIT(0) 196 #define ISP2X_STAT_YUVAE BIT(1) 197 #define ISP2X_STAT_SIAF BIT(2) 198 #define ISP2X_STAT_SIHST BIT(3) 199 #define ISP2X_STAT_EMB_DATA BIT(4) 200 #define ISP2X_STAT_RAWAWB BIT(5) 201 #define ISP2X_STAT_RAWAF BIT(6) 202 #define ISP2X_STAT_RAWAE0 BIT(7) 203 #define ISP2X_STAT_RAWAE1 BIT(8) 204 #define ISP2X_STAT_RAWAE2 BIT(9) 205 #define ISP2X_STAT_RAWAE3 BIT(10) 206 #define ISP2X_STAT_RAWHST0 BIT(11) 207 #define ISP2X_STAT_RAWHST1 BIT(12) 208 #define ISP2X_STAT_RAWHST2 BIT(13) 209 #define ISP2X_STAT_RAWHST3 BIT(14) 210 #define ISP2X_STAT_BLS BIT(15) 211 #define ISP2X_STAT_HDRTMO BIT(16) 212 #define ISP2X_STAT_DHAZ BIT(17) 213 214 #define ISP2X_LSC_GRAD_TBL_SIZE 8 215 #define ISP2X_LSC_SIZE_TBL_SIZE 8 216 #define ISP2X_LSC_DATA_TBL_SIZE 290 217 218 #define ISP2X_DEGAMMA_CURVE_SIZE 17 219 220 #define ISP2X_GAIN_HDRMGE_GAIN_NUM 3 221 #define ISP2X_GAIN_IDX_NUM 15 222 #define ISP2X_GAIN_LUT_NUM 17 223 224 #define ISP2X_AWB_MAX_GRID 1 225 #define ISP2X_RAWAWB_SUM_NUM 7 226 #define ISP2X_RAWAWB_MULWD_NUM 8 227 #define ISP2X_RAWAWB_RAMDATA_NUM 225 228 229 #define ISP2X_RAWAEBIG_SUBWIN_NUM 4 230 #define ISP2X_RAWAEBIG_MEAN_NUM 225 231 #define ISP2X_RAWAELITE_MEAN_NUM 25 232 #define ISP2X_YUVAE_SUBWIN_NUM 4 233 #define ISP2X_YUVAE_MEAN_NUM 225 234 235 #define ISP2X_RAWHISTBIG_SUBWIN_NUM 225 236 #define ISP2X_RAWHISTLITE_SUBWIN_NUM 25 237 #define ISP2X_SIHIST_WIN_NUM 1 238 #define ISP2X_HIST_WEIGHT_NUM 225 239 #define ISP2X_HIST_BIN_N_MAX 256 240 #define ISP2X_SIHIST_BIN_N_MAX 32 241 242 #define ISP2X_RAWAF_WIN_NUM 2 243 #define ISP2X_RAWAF_LINE_NUM 5 244 #define ISP2X_RAWAF_GAMMA_NUM 17 245 #define ISP2X_RAWAF_SUMDATA_ROW 15 246 #define ISP2X_RAWAF_SUMDATA_COLUMN 15 247 #define ISP2X_RAWAF_SUMDATA_NUM 225 248 #define ISP2X_AFM_MAX_WINDOWS 3 249 250 #define ISP2X_DPCC_PDAF_POINT_NUM 16 251 252 #define ISP2X_HDRMGE_L_CURVE_NUM 17 253 #define ISP2X_HDRMGE_E_CURVE_NUM 17 254 255 #define ISP2X_RAWNR_LUMA_RATION_NUM 8 256 257 #define ISP2X_HDRTMO_MINMAX_NUM 32 258 259 #define ISP2X_GIC_SIGMA_Y_NUM 15 260 261 #define ISP2X_CCM_CURVE_NUM 17 262 263 /* WDR */ 264 #define ISP2X_WDR_SIZE 48 265 266 #define ISP2X_DHAZ_CONV_COEFF_NUM 6 267 #define ISP2X_DHAZ_HIST_IIR_NUM 64 268 269 #define ISP2X_GAMMA_OUT_MAX_SAMPLES 45 270 271 #define ISP2X_MIPI_LUMA_MEAN_MAX 16 272 #define ISP2X_MIPI_RAW_MAX 3 273 #define ISP2X_RAW0_Y_STATE (1 << 0) 274 #define ISP2X_RAW1_Y_STATE (1 << 1) 275 #define ISP2X_RAW2_Y_STATE (1 << 2) 276 277 #define ISP2X_3DLUT_DATA_NUM 729 278 279 #define ISP2X_LDCH_MESH_XY_NUM 0x80000 280 #define ISP2X_LDCH_BUF_NUM 2 281 282 #define ISP2X_THUNDERBOOT_VIDEO_BUF_NUM 30 283 284 #define ISP2X_FBCBUF_FD_NUM 64 285 286 #define ISP2X_MESH_BUF_NUM 2 287 288 enum rkisp_isp_mode { 289 /* frame input related */ 290 RKISP_ISP_NORMAL = BIT(0), 291 RKISP_ISP_HDR2 = BIT(1), 292 RKISP_ISP_HDR3 = BIT(2), 293 RKISP_ISP_COMPR = BIT(3), 294 295 /* isp function related */ 296 RKISP_ISP_BIGMODE = BIT(28), 297 }; 298 299 struct rkisp_isp_info { 300 enum rkisp_isp_mode mode; 301 u32 act_width; 302 u32 act_height; 303 u8 compr_bit; 304 } __attribute__ ((packed)); 305 306 enum isp2x_mesh_buf_stat { 307 MESH_BUF_INIT = 0, 308 MESH_BUF_WAIT2CHIP, 309 MESH_BUF_CHIPINUSE, 310 }; 311 312 struct rkisp_meshbuf_info { 313 u64 module_id; 314 u32 unite_isp_id; 315 s32 buf_fd[ISP2X_MESH_BUF_NUM]; 316 u32 buf_size[ISP2X_MESH_BUF_NUM]; 317 } __attribute__ ((packed)); 318 319 struct rkisp_meshbuf_size { 320 u64 module_id; 321 u32 unite_isp_id; 322 u32 meas_width; 323 u32 meas_height; 324 int buf_cnt; 325 } __attribute__ ((packed)); 326 327 struct isp2x_mesh_head { 328 enum isp2x_mesh_buf_stat stat; 329 u32 data_oft; 330 } __attribute__ ((packed)); 331 332 #define RKISP_CMSK_WIN_MAX 12 333 #define RKISP_CMSK_WIN_MAX_V30 8 334 #define RKISP_CMSK_MOSAIC_MODE 0 335 #define RKISP_CMSK_COVER_MODE 1 336 337 /* struct rkisp_cmsk_win 338 * Priacy Mask Window configture, support windows 339 * RKISP_CMSK_WIN_MAX_V30 for rk3588 support 8 windows, and 340 * support for mainpath and selfpath output stream channel. 341 * 342 * RKISP_CMSK_WIN_MAX for rv1106 support 12 windows, and 343 * support for mainpath selfpath and bypasspath output stream channel. 344 * 345 * mode: 0:mosaic mode, 1:cover mode 346 * win_index: window index 0~11. windows overlap, priority win11 > win0. 347 * cover_color_y: cover mode effective, share for stream channel when same win_index. 348 * cover_color_u: cover mode effective, share for stream channel when same win_index. 349 * cover_color_v: cover mode effective, share for stream channel when same win_index. 350 * 351 * h_offs: window horizontal offset, share for stream channel when same win_index. 2 align. 352 * v_offs: window vertical offset, share for stream channel when same win_index. 2 align. 353 * h_size: window horizontal size, share for stream channel when same win_index. 8 align for rk3588, 2 align for rv1106. 354 * v_size: window vertical size, share for stream channel when same win_index. 8 align for rk3588, 2 align for rv1106. 355 */ 356 struct rkisp_cmsk_win { 357 unsigned short mode; 358 unsigned short win_en; 359 360 unsigned char cover_color_y; 361 unsigned char cover_color_u; 362 unsigned char cover_color_v; 363 364 unsigned short h_offs; 365 unsigned short v_offs; 366 unsigned short h_size; 367 unsigned short v_size; 368 } __attribute__ ((packed)); 369 370 /* struct rkisp_cmsk_cfg 371 * win: priacy mask window 372 * mosaic_block: Mosaic block size, 0:8x8 1:16x16 2:32x32 3:64x64, share for all windows 373 * width_ro: isp full resolution, h_offs + h_size <= width_ro. 374 * height_ro: isp full resolution, v_offs + v_size <= height_ro. 375 */ 376 struct rkisp_cmsk_cfg { 377 struct rkisp_cmsk_win win[RKISP_CMSK_WIN_MAX]; 378 unsigned int mosaic_block; 379 unsigned int width_ro; 380 unsigned int height_ro; 381 } __attribute__ ((packed)); 382 383 /* struct rkisp_stream_info 384 * cur_frame_id: stream current frame id 385 * input_frame_loss: isp input frame loss num 386 * output_frame_loss: stream output frame loss num 387 * stream_on: stream on/off 388 */ 389 struct rkisp_stream_info { 390 unsigned int cur_frame_id; 391 unsigned int input_frame_loss; 392 unsigned int output_frame_loss; 393 unsigned char stream_on; 394 unsigned char stream_id; 395 } __attribute__ ((packed)); 396 397 /* struct rkisp_mirror_flip 398 * mirror: global for all output stream 399 * flip: independent for all output stream 400 */ 401 struct rkisp_mirror_flip { 402 unsigned char mirror; 403 unsigned char flip; 404 } __attribute__ ((packed)); 405 406 struct rkisp_wrap_info { 407 int width; 408 int height; 409 }; 410 411 #define RKISP_TB_STREAM_BUF_MAX 5 412 struct rkisp_tb_stream_buf { 413 unsigned int dma_addr; 414 unsigned int sequence; 415 long long timestamp; 416 } __attribute__ ((packed)); 417 418 /* struct rkisp_tb_stream_info 419 * frame_size: nv12 frame buf size, bytesperline * height_16align * 1.5 420 * buf_max: memory size / frame_size 421 * buf_cnt: the num of frame write to buf. 422 */ 423 struct rkisp_tb_stream_info { 424 unsigned int width; 425 unsigned int height; 426 unsigned int bytesperline; 427 unsigned int frame_size; 428 unsigned int buf_max; 429 unsigned int buf_cnt; 430 struct rkisp_tb_stream_buf buf[RKISP_TB_STREAM_BUF_MAX]; 431 } __attribute__ ((packed)); 432 433 /* trigger event mode 434 * T_TRY: trigger maybe with retry 435 * T_TRY_YES: trigger to retry 436 * T_TRY_NO: trigger no to retry 437 * 438 * T_START_X1: isp read one frame 439 * T_START_X2: isp read hdr two frame 440 * T_START_X3: isp read hdr three frame 441 * T_START_C: isp read hdr linearised and compressed data 442 */ 443 enum isp2x_trigger_mode { 444 T_TRY = BIT(0), 445 T_TRY_YES = BIT(1), 446 T_TRY_NO = BIT(2), 447 448 T_START_X1 = BIT(4), 449 T_START_X2 = BIT(5), 450 T_START_X3 = BIT(6), 451 T_START_C = BIT(7), 452 }; 453 454 struct isp2x_csi_trigger { 455 /* timestamp in ns */ 456 u64 sof_timestamp; 457 u64 frame_timestamp; 458 u32 frame_id; 459 int times; 460 enum isp2x_trigger_mode mode; 461 } __attribute__ ((packed)); 462 463 /* isp csi dmatx/dmarx memory mode 464 * 0: raw12/raw10/raw8 8bit memory compact 465 * 1: raw12/raw10 16bit memory one pixel 466 * big endian for rv1126/rv1109 467 * |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| 468 * | 3| 2| 1| 0| -| -| -| -|11|10| 9| 8| 7| 6| 5| 4| 469 * little align for rk356x 470 * |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| 471 * | -| -| -| -|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| 472 * 2: raw12/raw10 16bit memory one pixel 473 * big align for rv1126/rv1109/rk356x 474 * |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| 475 * |11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| -| -| -| -| 476 */ 477 enum isp_csi_memory { 478 CSI_MEM_COMPACT = 0, 479 CSI_MEM_WORD_BIG_END = 1, 480 CSI_MEM_WORD_LITTLE_ALIGN = 1, 481 CSI_MEM_WORD_BIG_ALIGN = 2, 482 }; 483 484 #define RKISP_INFO2DDR_BUF_MAX 4 485 /* 32bit flag for user set to memory after buf used */ 486 #define RKISP_INFO2DDR_BUF_INIT 0x5AA5 487 488 enum rkisp_info2ddr_owner { 489 RKISP_INFO2DRR_OWNER_NULL, 490 RKISP_INFO2DRR_OWNER_GAIN, 491 RKISP_INFO2DRR_OWNER_AWB, 492 }; 493 494 /* struct rkisp_info2ddr 495 * awb and gain debug info write to ddr 496 * 497 * owner: 0: off, 1: gain, 2: awb. 498 * u: gain or awb mode parameters. 499 * buf_cnt: buf num to request. return actual result. 500 * buf_fd: fd of memory alloc result. 501 * wsize: data width to request. if useless to 0. return actual result. 502 * vsize: data height to request. if useless to 0. return actual result. 503 */ 504 struct rkisp_info2ddr { 505 enum rkisp_info2ddr_owner owner; 506 507 union { 508 struct { 509 u8 gain2ddr_mode; 510 } gain; 511 512 struct { 513 u8 awb2ddr_sel; 514 } awb; 515 } u; 516 517 u8 buf_cnt; 518 s32 buf_fd[RKISP_INFO2DDR_BUF_MAX]; 519 520 u32 wsize; 521 u32 vsize; 522 } __attribute__ ((packed)); 523 524 struct isp2x_ispgain_buf { 525 u32 gain_dmaidx; 526 u32 mfbc_dmaidx; 527 u32 gain_size; 528 u32 mfbc_size; 529 u32 frame_id; 530 } __attribute__ ((packed)); 531 532 struct isp2x_buf_idxfd { 533 u32 buf_num; 534 u32 index[ISP2X_FBCBUF_FD_NUM]; 535 s32 dmafd[ISP2X_FBCBUF_FD_NUM]; 536 } __attribute__ ((packed)); 537 538 struct isp2x_window { 539 u16 h_offs; 540 u16 v_offs; 541 u16 h_size; 542 u16 v_size; 543 } __attribute__ ((packed)); 544 545 struct isp2x_bls_fixed_val { 546 s16 r; 547 s16 gr; 548 s16 gb; 549 s16 b; 550 } __attribute__ ((packed)); 551 552 struct isp2x_bls_cfg { 553 u8 enable_auto; 554 u8 en_windows; 555 struct isp2x_window bls_window1; 556 struct isp2x_window bls_window2; 557 u8 bls_samples; 558 struct isp2x_bls_fixed_val fixed_val; 559 } __attribute__ ((packed)); 560 561 struct isp2x_bls_stat { 562 u16 meas_r; 563 u16 meas_gr; 564 u16 meas_gb; 565 u16 meas_b; 566 } __attribute__ ((packed)); 567 568 struct isp2x_dpcc_pdaf_point { 569 u8 y; 570 u8 x; 571 } __attribute__ ((packed)); 572 573 struct isp2x_dpcc_cfg { 574 //mode 0x0000 575 u8 stage1_enable; 576 u8 grayscale_mode; 577 578 //output_mode 0x0004 579 u8 sw_rk_out_sel; 580 u8 sw_dpcc_output_sel; 581 u8 stage1_rb_3x3; 582 u8 stage1_g_3x3; 583 u8 stage1_incl_rb_center; 584 u8 stage1_incl_green_center; 585 586 //set_use 0x0008 587 u8 stage1_use_fix_set; 588 u8 stage1_use_set_3; 589 u8 stage1_use_set_2; 590 u8 stage1_use_set_1; 591 592 //methods_set_1 0x000c 593 u8 sw_rk_red_blue1_en; 594 u8 rg_red_blue1_enable; 595 u8 rnd_red_blue1_enable; 596 u8 ro_red_blue1_enable; 597 u8 lc_red_blue1_enable; 598 u8 pg_red_blue1_enable; 599 u8 sw_rk_green1_en; 600 u8 rg_green1_enable; 601 u8 rnd_green1_enable; 602 u8 ro_green1_enable; 603 u8 lc_green1_enable; 604 u8 pg_green1_enable; 605 606 //methods_set_2 0x0010 607 u8 sw_rk_red_blue2_en; 608 u8 rg_red_blue2_enable; 609 u8 rnd_red_blue2_enable; 610 u8 ro_red_blue2_enable; 611 u8 lc_red_blue2_enable; 612 u8 pg_red_blue2_enable; 613 u8 sw_rk_green2_en; 614 u8 rg_green2_enable; 615 u8 rnd_green2_enable; 616 u8 ro_green2_enable; 617 u8 lc_green2_enable; 618 u8 pg_green2_enable; 619 620 //methods_set_3 0x0014 621 u8 sw_rk_red_blue3_en; 622 u8 rg_red_blue3_enable; 623 u8 rnd_red_blue3_enable; 624 u8 ro_red_blue3_enable; 625 u8 lc_red_blue3_enable; 626 u8 pg_red_blue3_enable; 627 u8 sw_rk_green3_en; 628 u8 rg_green3_enable; 629 u8 rnd_green3_enable; 630 u8 ro_green3_enable; 631 u8 lc_green3_enable; 632 u8 pg_green3_enable; 633 634 //line_thresh_1 0x0018 635 u8 sw_mindis1_rb; 636 u8 sw_mindis1_g; 637 u8 line_thr_1_rb; 638 u8 line_thr_1_g; 639 640 //line_mad_fac_1 0x001c 641 u8 sw_dis_scale_min1; 642 u8 sw_dis_scale_max1; 643 u8 line_mad_fac_1_rb; 644 u8 line_mad_fac_1_g; 645 646 //pg_fac_1 0x0020 647 u8 pg_fac_1_rb; 648 u8 pg_fac_1_g; 649 650 //rnd_thresh_1 0x0024 651 u8 rnd_thr_1_rb; 652 u8 rnd_thr_1_g; 653 654 //rg_fac_1 0x0028 655 u8 rg_fac_1_rb; 656 u8 rg_fac_1_g; 657 658 //line_thresh_2 0x002c 659 u8 sw_mindis2_rb; 660 u8 sw_mindis2_g; 661 u8 line_thr_2_rb; 662 u8 line_thr_2_g; 663 664 //line_mad_fac_2 0x0030 665 u8 sw_dis_scale_min2; 666 u8 sw_dis_scale_max2; 667 u8 line_mad_fac_2_rb; 668 u8 line_mad_fac_2_g; 669 670 //pg_fac_2 0x0034 671 u8 pg_fac_2_rb; 672 u8 pg_fac_2_g; 673 674 //rnd_thresh_2 0x0038 675 u8 rnd_thr_2_rb; 676 u8 rnd_thr_2_g; 677 678 //rg_fac_2 0x003c 679 u8 rg_fac_2_rb; 680 u8 rg_fac_2_g; 681 682 //line_thresh_3 0x0040 683 u8 sw_mindis3_rb; 684 u8 sw_mindis3_g; 685 u8 line_thr_3_rb; 686 u8 line_thr_3_g; 687 688 //line_mad_fac_3 0x0044 689 u8 sw_dis_scale_min3; 690 u8 sw_dis_scale_max3; 691 u8 line_mad_fac_3_rb; 692 u8 line_mad_fac_3_g; 693 694 //pg_fac_3 0x0048 695 u8 pg_fac_3_rb; 696 u8 pg_fac_3_g; 697 698 //rnd_thresh_3 0x004c 699 u8 rnd_thr_3_rb; 700 u8 rnd_thr_3_g; 701 702 //rg_fac_3 0x0050 703 u8 rg_fac_3_rb; 704 u8 rg_fac_3_g; 705 706 //ro_limits 0x0054 707 u8 ro_lim_3_rb; 708 u8 ro_lim_3_g; 709 u8 ro_lim_2_rb; 710 u8 ro_lim_2_g; 711 u8 ro_lim_1_rb; 712 u8 ro_lim_1_g; 713 714 //rnd_offs 0x0058 715 u8 rnd_offs_3_rb; 716 u8 rnd_offs_3_g; 717 u8 rnd_offs_2_rb; 718 u8 rnd_offs_2_g; 719 u8 rnd_offs_1_rb; 720 u8 rnd_offs_1_g; 721 722 //bpt_ctrl 0x005c 723 u8 bpt_rb_3x3; 724 u8 bpt_g_3x3; 725 u8 bpt_incl_rb_center; 726 u8 bpt_incl_green_center; 727 u8 bpt_use_fix_set; 728 u8 bpt_use_set_3; 729 u8 bpt_use_set_2; 730 u8 bpt_use_set_1; 731 u8 bpt_cor_en; 732 u8 bpt_det_en; 733 734 //bpt_number 0x0060 735 u16 bp_number; 736 737 //bpt_addr 0x0064 738 u16 bp_table_addr; 739 740 //bpt_data 0x0068 741 u16 bpt_v_addr; 742 u16 bpt_h_addr; 743 744 //bp_cnt 0x006c 745 u32 bp_cnt; 746 747 //pdaf_en 0x0070 748 u8 sw_pdaf_en; 749 750 //pdaf_point_en 0x0074 751 u8 pdaf_point_en[ISP2X_DPCC_PDAF_POINT_NUM]; 752 753 //pdaf_offset 0x0078 754 u16 pdaf_offsety; 755 u16 pdaf_offsetx; 756 757 //pdaf_wrap 0x007c 758 u16 pdaf_wrapy; 759 u16 pdaf_wrapx; 760 761 //pdaf_scope 0x0080 762 u16 pdaf_wrapy_num; 763 u16 pdaf_wrapx_num; 764 765 //pdaf_point_0 0x0084 766 struct isp2x_dpcc_pdaf_point point[ISP2X_DPCC_PDAF_POINT_NUM]; 767 768 //pdaf_forward_med 0x00a4 769 u8 pdaf_forward_med; 770 } __attribute__ ((packed)); 771 772 struct isp2x_hdrmge_curve { 773 u16 curve_1[ISP2X_HDRMGE_L_CURVE_NUM]; 774 u16 curve_0[ISP2X_HDRMGE_L_CURVE_NUM]; 775 } __attribute__ ((packed)); 776 777 struct isp2x_hdrmge_cfg { 778 u8 mode; 779 780 u16 gain0_inv; 781 u16 gain0; 782 783 u16 gain1_inv; 784 u16 gain1; 785 786 u8 gain2; 787 788 u8 lm_dif_0p15; 789 u8 lm_dif_0p9; 790 u8 ms_diff_0p15; 791 u8 ms_dif_0p8; 792 793 struct isp2x_hdrmge_curve curve; 794 u16 e_y[ISP2X_HDRMGE_E_CURVE_NUM]; 795 } __attribute__ ((packed)); 796 797 struct isp2x_rawnr_cfg { 798 u8 gauss_en; 799 u8 log_bypass; 800 801 u16 filtpar0; 802 u16 filtpar1; 803 u16 filtpar2; 804 805 u32 dgain0; 806 u32 dgain1; 807 u32 dgain2; 808 809 u16 luration[ISP2X_RAWNR_LUMA_RATION_NUM]; 810 u16 lulevel[ISP2X_RAWNR_LUMA_RATION_NUM]; 811 812 u32 gauss; 813 u16 sigma; 814 u16 pix_diff; 815 816 u32 thld_diff; 817 818 u8 gas_weig_scl2; 819 u8 gas_weig_scl1; 820 u16 thld_chanelw; 821 822 u16 lamda; 823 824 u16 fixw0; 825 u16 fixw1; 826 u16 fixw2; 827 u16 fixw3; 828 829 u32 wlamda0; 830 u32 wlamda1; 831 u32 wlamda2; 832 833 u16 rgain_filp; 834 u16 bgain_filp; 835 } __attribute__ ((packed)); 836 837 struct isp2x_lsc_cfg { 838 u16 r_data_tbl[ISP2X_LSC_DATA_TBL_SIZE]; 839 u16 gr_data_tbl[ISP2X_LSC_DATA_TBL_SIZE]; 840 u16 gb_data_tbl[ISP2X_LSC_DATA_TBL_SIZE]; 841 u16 b_data_tbl[ISP2X_LSC_DATA_TBL_SIZE]; 842 843 u16 x_grad_tbl[ISP2X_LSC_GRAD_TBL_SIZE]; 844 u16 y_grad_tbl[ISP2X_LSC_GRAD_TBL_SIZE]; 845 846 u16 x_size_tbl[ISP2X_LSC_SIZE_TBL_SIZE]; 847 u16 y_size_tbl[ISP2X_LSC_SIZE_TBL_SIZE]; 848 } __attribute__ ((packed)); 849 850 enum isp2x_goc_mode { 851 ISP2X_GOC_MODE_LOGARITHMIC, 852 ISP2X_GOC_MODE_EQUIDISTANT 853 }; 854 855 struct isp2x_goc_cfg { 856 enum isp2x_goc_mode mode; 857 u8 gamma_y[17]; 858 } __attribute__ ((packed)); 859 860 struct isp2x_hdrtmo_predict { 861 u8 global_tmo; 862 s32 iir_max; 863 s32 global_tmo_strength; 864 865 u8 scene_stable; 866 s32 k_rolgmean; 867 s32 iir; 868 } __attribute__ ((packed)); 869 870 struct isp2x_hdrtmo_cfg { 871 u16 cnt_vsize; 872 u8 gain_ld_off2; 873 u8 gain_ld_off1; 874 u8 big_en; 875 u8 nobig_en; 876 u8 newhst_en; 877 u8 cnt_mode; 878 879 u16 expl_lgratio; 880 u8 lgscl_ratio; 881 u8 cfg_alpha; 882 883 u16 set_gainoff; 884 u16 set_palpha; 885 886 u16 set_lgmax; 887 u16 set_lgmin; 888 889 u8 set_weightkey; 890 u16 set_lgmean; 891 892 u16 set_lgrange1; 893 u16 set_lgrange0; 894 895 u16 set_lgavgmax; 896 897 u8 clipgap1_i; 898 u8 clipgap0_i; 899 u8 clipratio1; 900 u8 clipratio0; 901 u8 ratiol; 902 903 u16 lgscl_inv; 904 u16 lgscl; 905 906 u16 lgmax; 907 908 u16 hist_low; 909 u16 hist_min; 910 911 u8 hist_shift; 912 u16 hist_0p3; 913 u16 hist_high; 914 915 u16 palpha_lwscl; 916 u16 palpha_lw0p5; 917 u16 palpha_0p18; 918 919 u16 maxgain; 920 u16 maxpalpha; 921 922 struct isp2x_hdrtmo_predict predict; 923 } __attribute__ ((packed)); 924 925 struct isp2x_hdrtmo_stat { 926 u16 lglow; 927 u16 lgmin; 928 u16 lghigh; 929 u16 lgmax; 930 u16 weightkey; 931 u16 lgmean; 932 u16 lgrange1; 933 u16 lgrange0; 934 u16 palpha; 935 u16 lgavgmax; 936 u16 linecnt; 937 u32 min_max[ISP2X_HDRTMO_MINMAX_NUM]; 938 } __attribute__ ((packed)); 939 940 struct isp2x_gic_cfg { 941 u8 edge_open; 942 943 u16 regmingradthrdark2; 944 u16 regmingradthrdark1; 945 u16 regminbusythre; 946 947 u16 regdarkthre; 948 u16 regmaxcorvboth; 949 u16 regdarktthrehi; 950 951 u8 regkgrad2dark; 952 u8 regkgrad1dark; 953 u8 regstrengthglobal_fix; 954 u8 regdarkthrestep; 955 u8 regkgrad2; 956 u8 regkgrad1; 957 u8 reggbthre; 958 959 u16 regmaxcorv; 960 u16 regmingradthr2; 961 u16 regmingradthr1; 962 963 u8 gr_ratio; 964 u16 dnloscale; 965 u16 dnhiscale; 966 u8 reglumapointsstep; 967 968 u16 gvaluelimitlo; 969 u16 gvaluelimithi; 970 u8 fusionratiohilimt1; 971 972 u8 regstrength_fix; 973 974 u16 sigma_y[ISP2X_GIC_SIGMA_Y_NUM]; 975 976 u8 noise_cut_en; 977 u16 noise_coe_a; 978 979 u16 noise_coe_b; 980 u16 diff_clip; 981 } __attribute__ ((packed)); 982 983 struct isp2x_debayer_cfg { 984 u8 filter_c_en; 985 u8 filter_g_en; 986 987 u8 thed1; 988 u8 thed0; 989 u8 dist_scale; 990 u8 max_ratio; 991 u8 clip_en; 992 993 s8 filter1_coe5; 994 s8 filter1_coe4; 995 s8 filter1_coe3; 996 s8 filter1_coe2; 997 s8 filter1_coe1; 998 999 s8 filter2_coe5; 1000 s8 filter2_coe4; 1001 s8 filter2_coe3; 1002 s8 filter2_coe2; 1003 s8 filter2_coe1; 1004 1005 u16 hf_offset; 1006 u8 gain_offset; 1007 u8 offset; 1008 1009 u8 shift_num; 1010 u8 order_max; 1011 u8 order_min; 1012 } __attribute__ ((packed)); 1013 1014 struct isp2x_ccm_cfg { 1015 s16 coeff0_r; 1016 s16 coeff1_r; 1017 s16 coeff2_r; 1018 s16 offset_r; 1019 1020 s16 coeff0_g; 1021 s16 coeff1_g; 1022 s16 coeff2_g; 1023 s16 offset_g; 1024 1025 s16 coeff0_b; 1026 s16 coeff1_b; 1027 s16 coeff2_b; 1028 s16 offset_b; 1029 1030 u16 coeff0_y; 1031 u16 coeff1_y; 1032 u16 coeff2_y; 1033 1034 u16 alp_y[ISP2X_CCM_CURVE_NUM]; 1035 1036 u8 bound_bit; 1037 } __attribute__ ((packed)); 1038 1039 struct isp2x_gammaout_cfg { 1040 u8 equ_segm; 1041 u16 offset; 1042 u16 gamma_y[ISP2X_GAMMA_OUT_MAX_SAMPLES]; 1043 } __attribute__ ((packed)); 1044 1045 enum isp2x_wdr_mode { 1046 ISP2X_WDR_MODE_BLOCK, 1047 ISP2X_WDR_MODE_GLOBAL 1048 }; 1049 1050 struct isp2x_wdr_cfg { 1051 enum isp2x_wdr_mode mode; 1052 unsigned int c_wdr[ISP2X_WDR_SIZE]; 1053 } __attribute__ ((packed)); 1054 1055 struct isp2x_dhaz_cfg { 1056 u8 enhance_en; 1057 u8 hist_chn; 1058 u8 hpara_en; 1059 u8 hist_en; 1060 u8 dc_en; 1061 u8 big_en; 1062 u8 nobig_en; 1063 1064 u8 yblk_th; 1065 u8 yhist_th; 1066 u8 dc_max_th; 1067 u8 dc_min_th; 1068 1069 u16 wt_max; 1070 u8 bright_max; 1071 u8 bright_min; 1072 1073 u8 tmax_base; 1074 u8 dark_th; 1075 u8 air_max; 1076 u8 air_min; 1077 1078 u16 tmax_max; 1079 u16 tmax_off; 1080 1081 u8 hist_th_off; 1082 u8 hist_gratio; 1083 1084 u16 hist_min; 1085 u16 hist_k; 1086 1087 u16 enhance_value; 1088 u16 hist_scale; 1089 1090 u16 iir_wt_sigma; 1091 u16 iir_sigma; 1092 u16 stab_fnum; 1093 1094 u16 iir_tmax_sigma; 1095 u16 iir_air_sigma; 1096 1097 u16 cfg_wt; 1098 u16 cfg_air; 1099 u16 cfg_alpha; 1100 1101 u16 cfg_gratio; 1102 u16 cfg_tmax; 1103 1104 u16 dc_weitcur; 1105 u16 dc_thed; 1106 1107 u8 sw_dhaz_dc_bf_h3; 1108 u8 sw_dhaz_dc_bf_h2; 1109 u8 sw_dhaz_dc_bf_h1; 1110 u8 sw_dhaz_dc_bf_h0; 1111 1112 u8 sw_dhaz_dc_bf_h5; 1113 u8 sw_dhaz_dc_bf_h4; 1114 1115 u16 air_weitcur; 1116 u16 air_thed; 1117 1118 u8 air_bf_h2; 1119 u8 air_bf_h1; 1120 u8 air_bf_h0; 1121 1122 u8 gaus_h2; 1123 u8 gaus_h1; 1124 u8 gaus_h0; 1125 1126 u8 conv_t0[ISP2X_DHAZ_CONV_COEFF_NUM]; 1127 u8 conv_t1[ISP2X_DHAZ_CONV_COEFF_NUM]; 1128 u8 conv_t2[ISP2X_DHAZ_CONV_COEFF_NUM]; 1129 } __attribute__ ((packed)); 1130 1131 struct isp2x_dhaz_stat { 1132 u16 dhaz_adp_air_base; 1133 u16 dhaz_adp_wt; 1134 1135 u16 dhaz_adp_gratio; 1136 u16 dhaz_adp_tmax; 1137 1138 u16 h_r_iir[ISP2X_DHAZ_HIST_IIR_NUM]; 1139 u16 h_g_iir[ISP2X_DHAZ_HIST_IIR_NUM]; 1140 u16 h_b_iir[ISP2X_DHAZ_HIST_IIR_NUM]; 1141 } __attribute__ ((packed)); 1142 1143 struct isp2x_cproc_cfg { 1144 u8 c_out_range; 1145 u8 y_in_range; 1146 u8 y_out_range; 1147 u8 contrast; 1148 u8 brightness; 1149 u8 sat; 1150 u8 hue; 1151 } __attribute__ ((packed)); 1152 1153 struct isp2x_ie_cfg { 1154 u16 effect; 1155 u16 color_sel; 1156 u16 eff_mat_1; 1157 u16 eff_mat_2; 1158 u16 eff_mat_3; 1159 u16 eff_mat_4; 1160 u16 eff_mat_5; 1161 u16 eff_tint; 1162 } __attribute__ ((packed)); 1163 1164 struct isp2x_rkiesharp_cfg { 1165 u8 coring_thr; 1166 u8 full_range; 1167 u8 switch_avg; 1168 u8 yavg_thr[4]; 1169 u8 delta1[5]; 1170 u8 delta2[5]; 1171 u8 maxnumber[5]; 1172 u8 minnumber[5]; 1173 u8 gauss_flat_coe[9]; 1174 u8 gauss_noise_coe[9]; 1175 u8 gauss_other_coe[9]; 1176 u8 line1_filter_coe[6]; 1177 u8 line2_filter_coe[9]; 1178 u8 line3_filter_coe[6]; 1179 u16 grad_seq[4]; 1180 u8 sharp_factor[5]; 1181 u8 uv_gauss_flat_coe[15]; 1182 u8 uv_gauss_noise_coe[15]; 1183 u8 uv_gauss_other_coe[15]; 1184 u8 lap_mat_coe[9]; 1185 } __attribute__ ((packed)); 1186 1187 struct isp2x_superimp_cfg { 1188 u8 transparency_mode; 1189 u8 ref_image; 1190 1191 u16 offset_x; 1192 u16 offset_y; 1193 1194 u8 y_comp; 1195 u8 cb_comp; 1196 u8 cr_comp; 1197 } __attribute__ ((packed)); 1198 1199 struct isp2x_gamma_corr_curve { 1200 u16 gamma_y[ISP2X_DEGAMMA_CURVE_SIZE]; 1201 } __attribute__ ((packed)); 1202 1203 struct isp2x_gamma_curve_x_axis_pnts { 1204 u32 gamma_dx0; 1205 u32 gamma_dx1; 1206 } __attribute__ ((packed)); 1207 1208 struct isp2x_sdg_cfg { 1209 struct isp2x_gamma_corr_curve curve_r; 1210 struct isp2x_gamma_corr_curve curve_g; 1211 struct isp2x_gamma_corr_curve curve_b; 1212 struct isp2x_gamma_curve_x_axis_pnts xa_pnts; 1213 } __attribute__ ((packed)); 1214 1215 struct isp2x_bdm_config { 1216 unsigned char demosaic_th; 1217 } __attribute__ ((packed)); 1218 1219 struct isp2x_gain_cfg { 1220 u8 dhaz_en; 1221 u8 wdr_en; 1222 u8 tmo_en; 1223 u8 lsc_en; 1224 u8 mge_en; 1225 1226 u32 mge_gain[ISP2X_GAIN_HDRMGE_GAIN_NUM]; 1227 u16 idx[ISP2X_GAIN_IDX_NUM]; 1228 u16 lut[ISP2X_GAIN_LUT_NUM]; 1229 } __attribute__ ((packed)); 1230 1231 struct isp2x_3dlut_cfg { 1232 u8 bypass_en; 1233 u32 actual_size; // word unit 1234 u16 lut_r[ISP2X_3DLUT_DATA_NUM]; 1235 u16 lut_g[ISP2X_3DLUT_DATA_NUM]; 1236 u16 lut_b[ISP2X_3DLUT_DATA_NUM]; 1237 } __attribute__ ((packed)); 1238 1239 enum isp2x_ldch_buf_stat { 1240 LDCH_BUF_INIT = 0, 1241 LDCH_BUF_WAIT2CHIP, 1242 LDCH_BUF_CHIPINUSE, 1243 }; 1244 1245 struct rkisp_ldchbuf_info { 1246 s32 buf_fd[ISP2X_LDCH_BUF_NUM]; 1247 u32 buf_size[ISP2X_LDCH_BUF_NUM]; 1248 } __attribute__ ((packed)); 1249 1250 struct rkisp_ldchbuf_size { 1251 u32 meas_width; 1252 u32 meas_height; 1253 } __attribute__ ((packed)); 1254 1255 struct isp2x_ldch_head { 1256 enum isp2x_ldch_buf_stat stat; 1257 u32 data_oft; 1258 } __attribute__ ((packed)); 1259 1260 struct isp2x_ldch_cfg { 1261 u32 hsize; 1262 u32 vsize; 1263 s32 buf_fd; 1264 } __attribute__ ((packed)); 1265 1266 struct isp2x_awb_gain_cfg { 1267 u16 gain_red; 1268 u16 gain_green_r; 1269 u16 gain_blue; 1270 u16 gain_green_b; 1271 } __attribute__ ((packed)); 1272 1273 struct isp2x_siawb_meas_cfg { 1274 struct isp2x_window awb_wnd; 1275 u8 awb_mode; 1276 u8 max_y; 1277 u8 min_y; 1278 u8 max_csum; 1279 u8 min_c; 1280 u8 frames; 1281 u8 awb_ref_cr; 1282 u8 awb_ref_cb; 1283 u8 enable_ymax_cmp; 1284 } __attribute__ ((packed)); 1285 1286 struct isp2x_rawawb_meas_cfg { 1287 u8 rawawb_sel; 1288 u8 sw_rawawb_light_num; //CTRL 1289 u8 sw_rawawb_wind_size; //CTRL 1290 u8 sw_rawawb_c_range; //CTRL 1291 u8 sw_rawawb_y_range; //CTRL 1292 u8 sw_rawawb_3dyuv_ls_idx3; //CTRL 1293 u8 sw_rawawb_3dyuv_ls_idx2; //CTRL 1294 u8 sw_rawawb_3dyuv_ls_idx1; //CTRL 1295 u8 sw_rawawb_3dyuv_ls_idx0; //CTRL 1296 u8 sw_rawawb_xy_en; //CTRL 1297 u8 sw_rawawb_uv_en; //CTRL 1298 u8 sw_rawlsc_bypass_en; //CTRL 1299 u8 sw_rawawb_blk_measure_mode; //BLK_CTRL 1300 u8 sw_rawawb_store_wp_flag_ls_idx2; //BLK_CTRL 1301 u8 sw_rawawb_store_wp_flag_ls_idx1; //BLK_CTRL 1302 u8 sw_rawawb_store_wp_flag_ls_idx0; //BLK_CTRL 1303 u16 sw_rawawb_store_wp_th0; //BLK_CTRL 1304 u16 sw_rawawb_store_wp_th1; //BLK_CTRL 1305 u16 sw_rawawb_store_wp_th2; //RAW_CTRL 1306 u16 sw_rawawb_v_offs; //WIN_OFFS 1307 u16 sw_rawawb_h_offs; //WIN_OFFS 1308 u16 sw_rawawb_v_size; //WIN_SIZE 1309 u16 sw_rawawb_h_size; //WIN_SIZE 1310 u16 sw_rawawb_g_max; //LIMIT_RG_MAX 1311 u16 sw_rawawb_r_max; //LIMIT_RG_MAX 1312 u16 sw_rawawb_y_max; //LIMIT_BY_MAX 1313 u16 sw_rawawb_b_max; //LIMIT_BY_MAX 1314 u16 sw_rawawb_g_min; //LIMIT_RG_MIN 1315 u16 sw_rawawb_r_min; //LIMIT_RG_MIN 1316 u16 sw_rawawb_y_min; //LIMIT_BY_MIN 1317 u16 sw_rawawb_b_min; //LIMIT_BY_MIN 1318 u16 sw_rawawb_coeff_y_g; //RGB2Y_0 1319 u16 sw_rawawb_coeff_y_r; //RGB2Y_0 1320 u16 sw_rawawb_coeff_y_b; //RGB2Y_1 1321 u16 sw_rawawb_coeff_u_g; //RGB2U_0 1322 u16 sw_rawawb_coeff_u_r; //RGB2U_0 1323 u16 sw_rawawb_coeff_u_b; //RGB2U_1 1324 u16 sw_rawawb_coeff_v_g; //RGB2V_0 1325 u16 sw_rawawb_coeff_v_r; //RGB2V_0 1326 u16 sw_rawawb_coeff_v_b; //RGB2V_1 1327 u16 sw_rawawb_vertex0_v_0; //UV_DETC_VERTEX0_0 1328 u16 sw_rawawb_vertex0_u_0; //UV_DETC_VERTEX0_0 1329 u16 sw_rawawb_vertex1_v_0; //UV_DETC_VERTEX1_0 1330 u16 sw_rawawb_vertex1_u_0; //UV_DETC_VERTEX1_0 1331 u16 sw_rawawb_vertex2_v_0; //UV_DETC_VERTEX2_0 1332 u16 sw_rawawb_vertex2_u_0; //UV_DETC_VERTEX2_0 1333 u16 sw_rawawb_vertex3_v_0; //UV_DETC_VERTEX3_0 1334 u16 sw_rawawb_vertex3_u_0; //UV_DETC_VERTEX3_0 1335 u32 sw_rawawb_islope01_0; //UV_DETC_ISLOPE01_0 1336 u32 sw_rawawb_islope12_0; //UV_DETC_ISLOPE12_0 1337 u32 sw_rawawb_islope23_0; //UV_DETC_ISLOPE23_0 1338 u32 sw_rawawb_islope30_0; //UV_DETC_ISLOPE30_0 1339 u16 sw_rawawb_vertex0_v_1; //UV_DETC_VERTEX0_1 1340 u16 sw_rawawb_vertex0_u_1; //UV_DETC_VERTEX0_1 1341 u16 sw_rawawb_vertex1_v_1; //UV_DETC_VERTEX1_1 1342 u16 sw_rawawb_vertex1_u_1; //UV_DETC_VERTEX1_1 1343 u16 sw_rawawb_vertex2_v_1; //UV_DETC_VERTEX2_1 1344 u16 sw_rawawb_vertex2_u_1; //UV_DETC_VERTEX2_1 1345 u16 sw_rawawb_vertex3_v_1; //UV_DETC_VERTEX3_1 1346 u16 sw_rawawb_vertex3_u_1; //UV_DETC_VERTEX3_1 1347 u32 sw_rawawb_islope01_1; //UV_DETC_ISLOPE01_1 1348 u32 sw_rawawb_islope12_1; //UV_DETC_ISLOPE12_1 1349 u32 sw_rawawb_islope23_1; //UV_DETC_ISLOPE23_1 1350 u32 sw_rawawb_islope30_1; //UV_DETC_ISLOPE30_1 1351 u16 sw_rawawb_vertex0_v_2; //UV_DETC_VERTEX0_2 1352 u16 sw_rawawb_vertex0_u_2; //UV_DETC_VERTEX0_2 1353 u16 sw_rawawb_vertex1_v_2; //UV_DETC_VERTEX1_2 1354 u16 sw_rawawb_vertex1_u_2; //UV_DETC_VERTEX1_2 1355 u16 sw_rawawb_vertex2_v_2; //UV_DETC_VERTEX2_2 1356 u16 sw_rawawb_vertex2_u_2; //UV_DETC_VERTEX2_2 1357 u16 sw_rawawb_vertex3_v_2; //UV_DETC_VERTEX3_2 1358 u16 sw_rawawb_vertex3_u_2; //UV_DETC_VERTEX3_2 1359 u32 sw_rawawb_islope01_2; //UV_DETC_ISLOPE01_2 1360 u32 sw_rawawb_islope12_2; //UV_DETC_ISLOPE12_2 1361 u32 sw_rawawb_islope23_2; //UV_DETC_ISLOPE23_2 1362 u32 sw_rawawb_islope30_2; //UV_DETC_ISLOPE30_2 1363 u16 sw_rawawb_vertex0_v_3; //UV_DETC_VERTEX0_3 1364 u16 sw_rawawb_vertex0_u_3; //UV_DETC_VERTEX0_3 1365 u16 sw_rawawb_vertex1_v_3; //UV_DETC_VERTEX1_3 1366 u16 sw_rawawb_vertex1_u_3; //UV_DETC_VERTEX1_3 1367 u16 sw_rawawb_vertex2_v_3; //UV_DETC_VERTEX2_3 1368 u16 sw_rawawb_vertex2_u_3; //UV_DETC_VERTEX2_3 1369 u16 sw_rawawb_vertex3_v_3; //UV_DETC_VERTEX3_3 1370 u16 sw_rawawb_vertex3_u_3; //UV_DETC_VERTEX3_3 1371 u32 sw_rawawb_islope01_3; //UV_DETC_ISLOPE01_3 1372 u32 sw_rawawb_islope12_3; //UV_DETC_ISLOPE12_3 1373 u32 sw_rawawb_islope23_3; //UV_DETC_ISLOPE23_3 1374 u32 sw_rawawb_islope30_3; //UV_DETC_ISLOPE30_3 1375 u16 sw_rawawb_vertex0_v_4; //UV_DETC_VERTEX0_4 1376 u16 sw_rawawb_vertex0_u_4; //UV_DETC_VERTEX0_4 1377 u16 sw_rawawb_vertex1_v_4; //UV_DETC_VERTEX1_4 1378 u16 sw_rawawb_vertex1_u_4; //UV_DETC_VERTEX1_4 1379 u16 sw_rawawb_vertex2_v_4; //UV_DETC_VERTEX2_4 1380 u16 sw_rawawb_vertex2_u_4; //UV_DETC_VERTEX2_4 1381 u16 sw_rawawb_vertex3_v_4; //UV_DETC_VERTEX3_4 1382 u16 sw_rawawb_vertex3_u_4; //UV_DETC_VERTEX3_4 1383 u32 sw_rawawb_islope01_4; //UV_DETC_ISLOPE01_4 1384 u32 sw_rawawb_islope12_4; //UV_DETC_ISLOPE12_4 1385 u32 sw_rawawb_islope23_4; //UV_DETC_ISLOPE23_4 1386 u32 sw_rawawb_islope30_4; //UV_DETC_ISLOPE30_4 1387 u16 sw_rawawb_vertex0_v_5; //UV_DETC_VERTEX0_5 1388 u16 sw_rawawb_vertex0_u_5; //UV_DETC_VERTEX0_5 1389 u16 sw_rawawb_vertex1_v_5; //UV_DETC_VERTEX1_5 1390 u16 sw_rawawb_vertex1_u_5; //UV_DETC_VERTEX1_5 1391 u16 sw_rawawb_vertex2_v_5; //UV_DETC_VERTEX2_5 1392 u16 sw_rawawb_vertex2_u_5; //UV_DETC_VERTEX2_5 1393 u16 sw_rawawb_vertex3_v_5; //UV_DETC_VERTEX3_5 1394 u16 sw_rawawb_vertex3_u_5; //UV_DETC_VERTEX3_5 1395 u32 sw_rawawb_islope01_5; //UV_DETC_ISLOPE01_5 1396 u32 sw_rawawb_islope12_5; //UV_DETC_ISLOPE10_5 1397 u32 sw_rawawb_islope23_5; //UV_DETC_ISLOPE23_5 1398 u32 sw_rawawb_islope30_5; //UV_DETC_ISLOPE30_5 1399 u16 sw_rawawb_vertex0_v_6; //UV_DETC_VERTEX0_6 1400 u16 sw_rawawb_vertex0_u_6; //UV_DETC_VERTEX0_6 1401 u16 sw_rawawb_vertex1_v_6; //UV_DETC_VERTEX1_6 1402 u16 sw_rawawb_vertex1_u_6; //UV_DETC_VERTEX1_6 1403 u16 sw_rawawb_vertex2_v_6; //UV_DETC_VERTEX2_6 1404 u16 sw_rawawb_vertex2_u_6; //UV_DETC_VERTEX2_6 1405 u16 sw_rawawb_vertex3_v_6; //UV_DETC_VERTEX3_6 1406 u16 sw_rawawb_vertex3_u_6; //UV_DETC_VERTEX3_6 1407 u32 sw_rawawb_islope01_6; //UV_DETC_ISLOPE01_6 1408 u32 sw_rawawb_islope12_6; //UV_DETC_ISLOPE10_6 1409 u32 sw_rawawb_islope23_6; //UV_DETC_ISLOPE23_6 1410 u32 sw_rawawb_islope30_6; //UV_DETC_ISLOPE30_6 1411 u32 sw_rawawb_b_uv_0; //YUV_DETC_B_UV_0 1412 u32 sw_rawawb_slope_vtcuv_0; //YUV_DETC_SLOPE_VTCUV_0 1413 u32 sw_rawawb_inv_dslope_0; //YUV_DETC_INV_DSLOPE_0 1414 u32 sw_rawawb_slope_ydis_0; //YUV_DETC_SLOPE_YDIS_0 1415 u32 sw_rawawb_b_ydis_0; //YUV_DETC_B_YDIS_0 1416 u32 sw_rawawb_b_uv_1; //YUV_DETC_B_UV_1 1417 u32 sw_rawawb_slope_vtcuv_1; //YUV_DETC_SLOPE_VTCUV_1 1418 u32 sw_rawawb_inv_dslope_1; //YUV_DETC_INV_DSLOPE_1 1419 u32 sw_rawawb_slope_ydis_1; //YUV_DETC_SLOPE_YDIS_1 1420 u32 sw_rawawb_b_ydis_1; //YUV_DETC_B_YDIS_1 1421 u32 sw_rawawb_b_uv_2; //YUV_DETC_B_UV_2 1422 u32 sw_rawawb_slope_vtcuv_2; //YUV_DETC_SLOPE_VTCUV_2 1423 u32 sw_rawawb_inv_dslope_2; //YUV_DETC_INV_DSLOPE_2 1424 u32 sw_rawawb_slope_ydis_2; //YUV_DETC_SLOPE_YDIS_2 1425 u32 sw_rawawb_b_ydis_2; //YUV_DETC_B_YDIS_2 1426 u32 sw_rawawb_b_uv_3; //YUV_DETC_B_UV_3 1427 u32 sw_rawawb_slope_vtcuv_3; //YUV_DETC_SLOPE_VTCUV_3 1428 u32 sw_rawawb_inv_dslope_3; //YUV_DETC_INV_DSLOPE_3 1429 u32 sw_rawawb_slope_ydis_3; //YUV_DETC_SLOPE_YDIS_3 1430 u32 sw_rawawb_b_ydis_3; //YUV_DETC_B_YDIS_3 1431 u32 sw_rawawb_ref_u; //YUV_DETC_REF_U 1432 u8 sw_rawawb_ref_v_3; //YUV_DETC_REF_V_1 1433 u8 sw_rawawb_ref_v_2; //YUV_DETC_REF_V_1 1434 u8 sw_rawawb_ref_v_1; //YUV_DETC_REF_V_1 1435 u8 sw_rawawb_ref_v_0; //YUV_DETC_REF_V_1 1436 u16 sw_rawawb_dis1_0; //YUV_DETC_DIS01_0 1437 u16 sw_rawawb_dis0_0; //YUV_DETC_DIS01_0 1438 u16 sw_rawawb_dis3_0; //YUV_DETC_DIS23_0 1439 u16 sw_rawawb_dis2_0; //YUV_DETC_DIS23_0 1440 u16 sw_rawawb_dis5_0; //YUV_DETC_DIS45_0 1441 u16 sw_rawawb_dis4_0; //YUV_DETC_DIS45_0 1442 u8 sw_rawawb_th3_0; //YUV_DETC_TH03_0 1443 u8 sw_rawawb_th2_0; //YUV_DETC_TH03_0 1444 u8 sw_rawawb_th1_0; //YUV_DETC_TH03_0 1445 u8 sw_rawawb_th0_0; //YUV_DETC_TH03_0 1446 u8 sw_rawawb_th5_0; //YUV_DETC_TH45_0 1447 u8 sw_rawawb_th4_0; //YUV_DETC_TH45_0 1448 u16 sw_rawawb_dis1_1; //YUV_DETC_DIS01_1 1449 u16 sw_rawawb_dis0_1; //YUV_DETC_DIS01_1 1450 u16 sw_rawawb_dis3_1; //YUV_DETC_DIS23_1 1451 u16 sw_rawawb_dis2_1; //YUV_DETC_DIS23_1 1452 u16 sw_rawawb_dis5_1; //YUV_DETC_DIS45_1 1453 u16 sw_rawawb_dis4_1; //YUV_DETC_DIS45_1 1454 u8 sw_rawawb_th3_1; //YUV_DETC_TH03_1 1455 u8 sw_rawawb_th2_1; //YUV_DETC_TH03_1 1456 u8 sw_rawawb_th1_1; //YUV_DETC_TH03_1 1457 u8 sw_rawawb_th0_1; //YUV_DETC_TH03_1 1458 u8 sw_rawawb_th5_1; //YUV_DETC_TH45_1 1459 u8 sw_rawawb_th4_1; //YUV_DETC_TH45_1 1460 u16 sw_rawawb_dis1_2; //YUV_DETC_DIS01_2 1461 u16 sw_rawawb_dis0_2; //YUV_DETC_DIS01_2 1462 u16 sw_rawawb_dis3_2; //YUV_DETC_DIS23_2 1463 u16 sw_rawawb_dis2_2; //YUV_DETC_DIS23_2 1464 u16 sw_rawawb_dis5_2; //YUV_DETC_DIS45_2 1465 u16 sw_rawawb_dis4_2; //YUV_DETC_DIS45_2 1466 u8 sw_rawawb_th3_2; //YUV_DETC_TH03_2 1467 u8 sw_rawawb_th2_2; //YUV_DETC_TH03_2 1468 u8 sw_rawawb_th1_2; //YUV_DETC_TH03_2 1469 u8 sw_rawawb_th0_2; //YUV_DETC_TH03_2 1470 u8 sw_rawawb_th5_2; //YUV_DETC_TH45_2 1471 u8 sw_rawawb_th4_2; //YUV_DETC_TH45_2 1472 u16 sw_rawawb_dis1_3; //YUV_DETC_DIS01_3 1473 u16 sw_rawawb_dis0_3; //YUV_DETC_DIS01_3 1474 u16 sw_rawawb_dis3_3; //YUV_DETC_DIS23_3 1475 u16 sw_rawawb_dis2_3; //YUV_DETC_DIS23_3 1476 u16 sw_rawawb_dis5_3; //YUV_DETC_DIS45_3 1477 u16 sw_rawawb_dis4_3; //YUV_DETC_DIS45_3 1478 u8 sw_rawawb_th3_3; //YUV_DETC_TH03_3 1479 u8 sw_rawawb_th2_3; //YUV_DETC_TH03_3 1480 u8 sw_rawawb_th1_3; //YUV_DETC_TH03_3 1481 u8 sw_rawawb_th0_3; //YUV_DETC_TH03_3 1482 u8 sw_rawawb_th5_3; //YUV_DETC_TH45_3 1483 u8 sw_rawawb_th4_3; //YUV_DETC_TH45_3 1484 u16 sw_rawawb_wt1; //RGB2XY_WT01 1485 u16 sw_rawawb_wt0; //RGB2XY_WT01 1486 u16 sw_rawawb_wt2; //RGB2XY_WT2 1487 u16 sw_rawawb_mat0_y; //RGB2XY_MAT0_XY 1488 u16 sw_rawawb_mat0_x; //RGB2XY_MAT0_XY 1489 u16 sw_rawawb_mat1_y; //RGB2XY_MAT1_XY 1490 u16 sw_rawawb_mat1_x; //RGB2XY_MAT1_XY 1491 u16 sw_rawawb_mat2_y; //RGB2XY_MAT2_XY 1492 u16 sw_rawawb_mat2_x; //RGB2XY_MAT2_XY 1493 u16 sw_rawawb_nor_x1_0; //XY_DETC_NOR_X_0 1494 u16 sw_rawawb_nor_x0_0; //XY_DETC_NOR_X_0 1495 u16 sw_rawawb_nor_y1_0; //XY_DETC_NOR_Y_0 1496 u16 sw_rawawb_nor_y0_0; //XY_DETC_NOR_Y_0 1497 u16 sw_rawawb_big_x1_0; //XY_DETC_BIG_X_0 1498 u16 sw_rawawb_big_x0_0; //XY_DETC_BIG_X_0 1499 u16 sw_rawawb_big_y1_0; //XY_DETC_BIG_Y_0 1500 u16 sw_rawawb_big_y0_0; //XY_DETC_BIG_Y_0 1501 u16 sw_rawawb_sma_x1_0; //XY_DETC_SMA_X_0 1502 u16 sw_rawawb_sma_x0_0; //XY_DETC_SMA_X_0 1503 u16 sw_rawawb_sma_y1_0; //XY_DETC_SMA_Y_0 1504 u16 sw_rawawb_sma_y0_0; //XY_DETC_SMA_Y_0 1505 u16 sw_rawawb_nor_x1_1; //XY_DETC_NOR_X_1 1506 u16 sw_rawawb_nor_x0_1; //XY_DETC_NOR_X_1 1507 u16 sw_rawawb_nor_y1_1; //XY_DETC_NOR_Y_1 1508 u16 sw_rawawb_nor_y0_1; //XY_DETC_NOR_Y_1 1509 u16 sw_rawawb_big_x1_1; //XY_DETC_BIG_X_1 1510 u16 sw_rawawb_big_x0_1; //XY_DETC_BIG_X_1 1511 u16 sw_rawawb_big_y1_1; //XY_DETC_BIG_Y_1 1512 u16 sw_rawawb_big_y0_1; //XY_DETC_BIG_Y_1 1513 u16 sw_rawawb_sma_x1_1; //XY_DETC_SMA_X_1 1514 u16 sw_rawawb_sma_x0_1; //XY_DETC_SMA_X_1 1515 u16 sw_rawawb_sma_y1_1; //XY_DETC_SMA_Y_1 1516 u16 sw_rawawb_sma_y0_1; //XY_DETC_SMA_Y_1 1517 u16 sw_rawawb_nor_x1_2; //XY_DETC_NOR_X_2 1518 u16 sw_rawawb_nor_x0_2; //XY_DETC_NOR_X_2 1519 u16 sw_rawawb_nor_y1_2; //XY_DETC_NOR_Y_2 1520 u16 sw_rawawb_nor_y0_2; //XY_DETC_NOR_Y_2 1521 u16 sw_rawawb_big_x1_2; //XY_DETC_BIG_X_2 1522 u16 sw_rawawb_big_x0_2; //XY_DETC_BIG_X_2 1523 u16 sw_rawawb_big_y1_2; //XY_DETC_BIG_Y_2 1524 u16 sw_rawawb_big_y0_2; //XY_DETC_BIG_Y_2 1525 u16 sw_rawawb_sma_x1_2; //XY_DETC_SMA_X_2 1526 u16 sw_rawawb_sma_x0_2; //XY_DETC_SMA_X_2 1527 u16 sw_rawawb_sma_y1_2; //XY_DETC_SMA_Y_2 1528 u16 sw_rawawb_sma_y0_2; //XY_DETC_SMA_Y_2 1529 u16 sw_rawawb_nor_x1_3; //XY_DETC_NOR_X_3 1530 u16 sw_rawawb_nor_x0_3; //XY_DETC_NOR_X_3 1531 u16 sw_rawawb_nor_y1_3; //XY_DETC_NOR_Y_3 1532 u16 sw_rawawb_nor_y0_3; //XY_DETC_NOR_Y_3 1533 u16 sw_rawawb_big_x1_3; //XY_DETC_BIG_X_3 1534 u16 sw_rawawb_big_x0_3; //XY_DETC_BIG_X_3 1535 u16 sw_rawawb_big_y1_3; //XY_DETC_BIG_Y_3 1536 u16 sw_rawawb_big_y0_3; //XY_DETC_BIG_Y_3 1537 u16 sw_rawawb_sma_x1_3; //XY_DETC_SMA_X_3 1538 u16 sw_rawawb_sma_x0_3; //XY_DETC_SMA_X_3 1539 u16 sw_rawawb_sma_y1_3; //XY_DETC_SMA_Y_3 1540 u16 sw_rawawb_sma_y0_3; //XY_DETC_SMA_Y_3 1541 u16 sw_rawawb_nor_x1_4; //XY_DETC_NOR_X_4 1542 u16 sw_rawawb_nor_x0_4; //XY_DETC_NOR_X_4 1543 u16 sw_rawawb_nor_y1_4; //XY_DETC_NOR_Y_4 1544 u16 sw_rawawb_nor_y0_4; //XY_DETC_NOR_Y_4 1545 u16 sw_rawawb_big_x1_4; //XY_DETC_BIG_X_4 1546 u16 sw_rawawb_big_x0_4; //XY_DETC_BIG_X_4 1547 u16 sw_rawawb_big_y1_4; //XY_DETC_BIG_Y_4 1548 u16 sw_rawawb_big_y0_4; //XY_DETC_BIG_Y_4 1549 u16 sw_rawawb_sma_x1_4; //XY_DETC_SMA_X_4 1550 u16 sw_rawawb_sma_x0_4; //XY_DETC_SMA_X_4 1551 u16 sw_rawawb_sma_y1_4; //XY_DETC_SMA_Y_4 1552 u16 sw_rawawb_sma_y0_4; //XY_DETC_SMA_Y_4 1553 u16 sw_rawawb_nor_x1_5; //XY_DETC_NOR_X_5 1554 u16 sw_rawawb_nor_x0_5; //XY_DETC_NOR_X_5 1555 u16 sw_rawawb_nor_y1_5; //XY_DETC_NOR_Y_5 1556 u16 sw_rawawb_nor_y0_5; //XY_DETC_NOR_Y_5 1557 u16 sw_rawawb_big_x1_5; //XY_DETC_BIG_X_5 1558 u16 sw_rawawb_big_x0_5; //XY_DETC_BIG_X_5 1559 u16 sw_rawawb_big_y1_5; //XY_DETC_BIG_Y_5 1560 u16 sw_rawawb_big_y0_5; //XY_DETC_BIG_Y_5 1561 u16 sw_rawawb_sma_x1_5; //XY_DETC_SMA_X_5 1562 u16 sw_rawawb_sma_x0_5; //XY_DETC_SMA_X_5 1563 u16 sw_rawawb_sma_y1_5; //XY_DETC_SMA_Y_5 1564 u16 sw_rawawb_sma_y0_5; //XY_DETC_SMA_Y_5 1565 u16 sw_rawawb_nor_x1_6; //XY_DETC_NOR_X_6 1566 u16 sw_rawawb_nor_x0_6; //XY_DETC_NOR_X_6 1567 u16 sw_rawawb_nor_y1_6; //XY_DETC_NOR_Y_6 1568 u16 sw_rawawb_nor_y0_6; //XY_DETC_NOR_Y_6 1569 u16 sw_rawawb_big_x1_6; //XY_DETC_BIG_X_6 1570 u16 sw_rawawb_big_x0_6; //XY_DETC_BIG_X_6 1571 u16 sw_rawawb_big_y1_6; //XY_DETC_BIG_Y_6 1572 u16 sw_rawawb_big_y0_6; //XY_DETC_BIG_Y_6 1573 u16 sw_rawawb_sma_x1_6; //XY_DETC_SMA_X_6 1574 u16 sw_rawawb_sma_x0_6; //XY_DETC_SMA_X_6 1575 u16 sw_rawawb_sma_y1_6; //XY_DETC_SMA_Y_6 1576 u16 sw_rawawb_sma_y0_6; //XY_DETC_SMA_Y_6 1577 u8 sw_rawawb_multiwindow_en; //MULTIWINDOW_EXC_CTRL 1578 u8 sw_rawawb_exc_wp_region6_domain; //MULTIWINDOW_EXC_CTRL 1579 u8 sw_rawawb_exc_wp_region6_measen; //MULTIWINDOW_EXC_CTRL 1580 u8 sw_rawawb_exc_wp_region6_excen; //MULTIWINDOW_EXC_CTRL 1581 u8 sw_rawawb_exc_wp_region5_domain; //MULTIWINDOW_EXC_CTRL 1582 u8 sw_rawawb_exc_wp_region5_measen; //MULTIWINDOW_EXC_CTRL 1583 u8 sw_rawawb_exc_wp_region5_excen; //MULTIWINDOW_EXC_CTRL 1584 u8 sw_rawawb_exc_wp_region4_domain; //MULTIWINDOW_EXC_CTRL 1585 u8 sw_rawawb_exc_wp_region4_measen; //MULTIWINDOW_EXC_CTRL 1586 u8 sw_rawawb_exc_wp_region4_excen; //MULTIWINDOW_EXC_CTRL 1587 u8 sw_rawawb_exc_wp_region3_domain; //MULTIWINDOW_EXC_CTRL 1588 u8 sw_rawawb_exc_wp_region3_measen; //MULTIWINDOW_EXC_CTRL 1589 u8 sw_rawawb_exc_wp_region3_excen; //MULTIWINDOW_EXC_CTRL 1590 u8 sw_rawawb_exc_wp_region2_domain; //MULTIWINDOW_EXC_CTRL 1591 u8 sw_rawawb_exc_wp_region2_measen; //MULTIWINDOW_EXC_CTRL 1592 u8 sw_rawawb_exc_wp_region2_excen; //MULTIWINDOW_EXC_CTRL 1593 u8 sw_rawawb_exc_wp_region1_domain; //MULTIWINDOW_EXC_CTRL 1594 u8 sw_rawawb_exc_wp_region1_measen; //MULTIWINDOW_EXC_CTRL 1595 u8 sw_rawawb_exc_wp_region1_excen; //MULTIWINDOW_EXC_CTRL 1596 u8 sw_rawawb_exc_wp_region0_domain; //MULTIWINDOW_EXC_CTRL 1597 u8 sw_rawawb_exc_wp_region0_measen; //MULTIWINDOW_EXC_CTRL 1598 u8 sw_rawawb_exc_wp_region0_excen; //MULTIWINDOW_EXC_CTRL 1599 u16 sw_rawawb_multiwindow0_v_offs; //MULTIWINDOW0_OFFS 1600 u16 sw_rawawb_multiwindow0_h_offs; //MULTIWINDOW0_OFFS 1601 u16 sw_rawawb_multiwindow0_v_size; //MULTIWINDOW0_SIZE 1602 u16 sw_rawawb_multiwindow0_h_size; //MULTIWINDOW0_SIZE 1603 u16 sw_rawawb_multiwindow1_v_offs; //MULTIWINDOW1_OFFS 1604 u16 sw_rawawb_multiwindow1_h_offs; //MULTIWINDOW1_OFFS 1605 u16 sw_rawawb_multiwindow1_v_size; //MULTIWINDOW1_SIZE 1606 u16 sw_rawawb_multiwindow1_h_size; //MULTIWINDOW1_SIZE 1607 u16 sw_rawawb_multiwindow2_v_offs; //MULTIWINDOW2_OFFS 1608 u16 sw_rawawb_multiwindow2_h_offs; //MULTIWINDOW2_OFFS 1609 u16 sw_rawawb_multiwindow2_v_size; //MULTIWINDOW2_SIZE 1610 u16 sw_rawawb_multiwindow2_h_size; //MULTIWINDOW2_SIZE 1611 u16 sw_rawawb_multiwindow3_v_offs; //MULTIWINDOW3_OFFS 1612 u16 sw_rawawb_multiwindow3_h_offs; //MULTIWINDOW3_OFFS 1613 u16 sw_rawawb_multiwindow3_v_size; //MULTIWINDOW3_SIZE 1614 u16 sw_rawawb_multiwindow3_h_size; //MULTIWINDOW3_SIZE 1615 u16 sw_rawawb_multiwindow4_v_offs; //MULTIWINDOW4_OFFS 1616 u16 sw_rawawb_multiwindow4_h_offs; //MULTIWINDOW4_OFFS 1617 u16 sw_rawawb_multiwindow4_v_size; //MULTIWINDOW4_SIZE 1618 u16 sw_rawawb_multiwindow4_h_size; //MULTIWINDOW4_SIZE 1619 u16 sw_rawawb_multiwindow5_v_offs; //MULTIWINDOW5_OFFS 1620 u16 sw_rawawb_multiwindow5_h_offs; //MULTIWINDOW5_OFFS 1621 u16 sw_rawawb_multiwindow5_v_size; //MULTIWINDOW5_SIZE 1622 u16 sw_rawawb_multiwindow5_h_size; //MULTIWINDOW5_SIZE 1623 u16 sw_rawawb_multiwindow6_v_offs; //MULTIWINDOW6_OFFS 1624 u16 sw_rawawb_multiwindow6_h_offs; //MULTIWINDOW6_OFFS 1625 u16 sw_rawawb_multiwindow6_v_size; //MULTIWINDOW6_SIZE 1626 u16 sw_rawawb_multiwindow6_h_size; //MULTIWINDOW6_SIZE 1627 u16 sw_rawawb_multiwindow7_v_offs; //MULTIWINDOW7_OFFS 1628 u16 sw_rawawb_multiwindow7_h_offs; //MULTIWINDOW7_OFFS 1629 u16 sw_rawawb_multiwindow7_v_size; //MULTIWINDOW7_SIZE 1630 u16 sw_rawawb_multiwindow7_h_size; //MULTIWINDOW7_SIZE 1631 u16 sw_rawawb_exc_wp_region0_xu1; //EXC_WP_REGION0_XU 1632 u16 sw_rawawb_exc_wp_region0_xu0; //EXC_WP_REGION0_XU 1633 u16 sw_rawawb_exc_wp_region0_yv1; //EXC_WP_REGION0_YV 1634 u16 sw_rawawb_exc_wp_region0_yv0; //EXC_WP_REGION0_YV 1635 u16 sw_rawawb_exc_wp_region1_xu1; //EXC_WP_REGION1_XU 1636 u16 sw_rawawb_exc_wp_region1_xu0; //EXC_WP_REGION1_XU 1637 u16 sw_rawawb_exc_wp_region1_yv1; //EXC_WP_REGION1_YV 1638 u16 sw_rawawb_exc_wp_region1_yv0; //EXC_WP_REGION1_YV 1639 u16 sw_rawawb_exc_wp_region2_xu1; //EXC_WP_REGION2_XU 1640 u16 sw_rawawb_exc_wp_region2_xu0; //EXC_WP_REGION2_XU 1641 u16 sw_rawawb_exc_wp_region2_yv1; //EXC_WP_REGION2_YV 1642 u16 sw_rawawb_exc_wp_region2_yv0; //EXC_WP_REGION2_YV 1643 u16 sw_rawawb_exc_wp_region3_xu1; //EXC_WP_REGION3_XU 1644 u16 sw_rawawb_exc_wp_region3_xu0; //EXC_WP_REGION3_XU 1645 u16 sw_rawawb_exc_wp_region3_yv1; //EXC_WP_REGION3_YV 1646 u16 sw_rawawb_exc_wp_region3_yv0; //EXC_WP_REGION3_YV 1647 u16 sw_rawawb_exc_wp_region4_xu1; //EXC_WP_REGION4_XU 1648 u16 sw_rawawb_exc_wp_region4_xu0; //EXC_WP_REGION4_XU 1649 u16 sw_rawawb_exc_wp_region4_yv1; //EXC_WP_REGION4_YV 1650 u16 sw_rawawb_exc_wp_region4_yv0; //EXC_WP_REGION4_YV 1651 u16 sw_rawawb_exc_wp_region5_xu1; //EXC_WP_REGION5_XU 1652 u16 sw_rawawb_exc_wp_region5_xu0; //EXC_WP_REGION5_XU 1653 u16 sw_rawawb_exc_wp_region5_yv1; //EXC_WP_REGION5_YV 1654 u16 sw_rawawb_exc_wp_region5_yv0; //EXC_WP_REGION5_YV 1655 u16 sw_rawawb_exc_wp_region6_xu1; //EXC_WP_REGION6_XU 1656 u16 sw_rawawb_exc_wp_region6_xu0; //EXC_WP_REGION6_XU 1657 u16 sw_rawawb_exc_wp_region6_yv1; //EXC_WP_REGION6_YV 1658 u16 sw_rawawb_exc_wp_region6_yv0; //EXC_WP_REGION6_YV 1659 } __attribute__ ((packed)); 1660 1661 struct isp2x_rawaebig_meas_cfg { 1662 u8 rawae_sel; 1663 u8 wnd_num; 1664 u8 subwin_en[ISP2X_RAWAEBIG_SUBWIN_NUM]; 1665 struct isp2x_window win; 1666 struct isp2x_window subwin[ISP2X_RAWAEBIG_SUBWIN_NUM]; 1667 } __attribute__ ((packed)); 1668 1669 struct isp2x_rawaelite_meas_cfg { 1670 u8 rawae_sel; 1671 u8 wnd_num; 1672 struct isp2x_window win; 1673 } __attribute__ ((packed)); 1674 1675 struct isp2x_yuvae_meas_cfg { 1676 u8 ysel; 1677 u8 wnd_num; 1678 u8 subwin_en[ISP2X_YUVAE_SUBWIN_NUM]; 1679 struct isp2x_window win; 1680 struct isp2x_window subwin[ISP2X_YUVAE_SUBWIN_NUM]; 1681 } __attribute__ ((packed)); 1682 1683 struct isp2x_rawaf_meas_cfg { 1684 u8 rawaf_sel; 1685 u8 num_afm_win; 1686 u8 gaus_en; 1687 u8 gamma_en; 1688 struct isp2x_window win[ISP2X_RAWAF_WIN_NUM]; 1689 u8 line_en[ISP2X_RAWAF_LINE_NUM]; 1690 u8 line_num[ISP2X_RAWAF_LINE_NUM]; 1691 u8 gaus_coe_h2; 1692 u8 gaus_coe_h1; 1693 u8 gaus_coe_h0; 1694 u16 afm_thres; 1695 u8 lum_var_shift[ISP2X_RAWAF_WIN_NUM]; 1696 u8 afm_var_shift[ISP2X_RAWAF_WIN_NUM]; 1697 u16 gamma_y[ISP2X_RAWAF_GAMMA_NUM]; 1698 } __attribute__ ((packed)); 1699 1700 struct isp2x_siaf_win_cfg { 1701 u8 sum_shift; 1702 u8 lum_shift; 1703 struct isp2x_window win; 1704 } __attribute__ ((packed)); 1705 1706 struct isp2x_siaf_cfg { 1707 u8 num_afm_win; 1708 u32 thres; 1709 struct isp2x_siaf_win_cfg afm_win[ISP2X_AFM_MAX_WINDOWS]; 1710 } __attribute__ ((packed)); 1711 1712 struct isp2x_rawhistbig_cfg { 1713 u8 wnd_num; 1714 u8 data_sel; 1715 u8 waterline; 1716 u8 mode; 1717 u8 stepsize; 1718 u8 off; 1719 u8 bcc; 1720 u8 gcc; 1721 u8 rcc; 1722 struct isp2x_window win; 1723 u8 weight[ISP2X_RAWHISTBIG_SUBWIN_NUM]; 1724 } __attribute__ ((packed)); 1725 1726 struct isp2x_rawhistlite_cfg { 1727 u8 data_sel; 1728 u8 waterline; 1729 u8 mode; 1730 u8 stepsize; 1731 u8 off; 1732 u8 bcc; 1733 u8 gcc; 1734 u8 rcc; 1735 struct isp2x_window win; 1736 u8 weight[ISP2X_RAWHISTLITE_SUBWIN_NUM]; 1737 } __attribute__ ((packed)); 1738 1739 struct isp2x_sihst_win_cfg { 1740 u8 data_sel; 1741 u8 waterline; 1742 u8 auto_stop; 1743 u8 mode; 1744 u8 stepsize; 1745 struct isp2x_window win; 1746 } __attribute__ ((packed)); 1747 1748 struct isp2x_sihst_cfg { 1749 u8 wnd_num; 1750 struct isp2x_sihst_win_cfg win_cfg[ISP2X_SIHIST_WIN_NUM]; 1751 u8 hist_weight[ISP2X_HIST_WEIGHT_NUM]; 1752 } __attribute__ ((packed)); 1753 1754 struct isp2x_isp_other_cfg { 1755 struct isp2x_bls_cfg bls_cfg; 1756 struct isp2x_dpcc_cfg dpcc_cfg; 1757 struct isp2x_hdrmge_cfg hdrmge_cfg; 1758 struct isp2x_rawnr_cfg rawnr_cfg; 1759 struct isp2x_lsc_cfg lsc_cfg; 1760 struct isp2x_awb_gain_cfg awb_gain_cfg; 1761 //struct isp2x_goc_cfg goc_cfg; 1762 struct isp2x_gic_cfg gic_cfg; 1763 struct isp2x_debayer_cfg debayer_cfg; 1764 struct isp2x_ccm_cfg ccm_cfg; 1765 struct isp2x_gammaout_cfg gammaout_cfg; 1766 struct isp2x_wdr_cfg wdr_cfg; 1767 struct isp2x_cproc_cfg cproc_cfg; 1768 struct isp2x_ie_cfg ie_cfg; 1769 struct isp2x_rkiesharp_cfg rkiesharp_cfg; 1770 struct isp2x_superimp_cfg superimp_cfg; 1771 struct isp2x_sdg_cfg sdg_cfg; 1772 struct isp2x_bdm_config bdm_cfg; 1773 struct isp2x_hdrtmo_cfg hdrtmo_cfg; 1774 struct isp2x_dhaz_cfg dhaz_cfg; 1775 struct isp2x_gain_cfg gain_cfg; 1776 struct isp2x_3dlut_cfg isp3dlut_cfg; 1777 struct isp2x_ldch_cfg ldch_cfg; 1778 } __attribute__ ((packed)); 1779 1780 struct isp2x_isp_meas_cfg { 1781 struct isp2x_siawb_meas_cfg siawb; 1782 struct isp2x_rawawb_meas_cfg rawawb; 1783 struct isp2x_rawaelite_meas_cfg rawae0; 1784 struct isp2x_rawaebig_meas_cfg rawae1; 1785 struct isp2x_rawaebig_meas_cfg rawae2; 1786 struct isp2x_rawaebig_meas_cfg rawae3; 1787 struct isp2x_yuvae_meas_cfg yuvae; 1788 struct isp2x_rawaf_meas_cfg rawaf; 1789 struct isp2x_siaf_cfg siaf; 1790 struct isp2x_rawhistlite_cfg rawhist0; 1791 struct isp2x_rawhistbig_cfg rawhist1; 1792 struct isp2x_rawhistbig_cfg rawhist2; 1793 struct isp2x_rawhistbig_cfg rawhist3; 1794 struct isp2x_sihst_cfg sihst; 1795 } __attribute__ ((packed)); 1796 1797 struct sensor_exposure_s { 1798 u32 fine_integration_time; 1799 u32 coarse_integration_time; 1800 u32 analog_gain_code_global; 1801 u32 digital_gain_global; 1802 u32 isp_digital_gain; 1803 } __attribute__ ((packed)); 1804 1805 struct sensor_exposure_cfg { 1806 struct sensor_exposure_s linear_exp; 1807 struct sensor_exposure_s hdr_exp[3]; 1808 } __attribute__ ((packed)); 1809 1810 struct isp2x_isp_params_cfg { 1811 u64 module_en_update; 1812 u64 module_ens; 1813 u64 module_cfg_update; 1814 1815 u32 frame_id; 1816 struct isp2x_isp_meas_cfg meas; 1817 struct isp2x_isp_other_cfg others; 1818 struct sensor_exposure_cfg exposure; 1819 } __attribute__ ((packed)); 1820 1821 struct isp2x_siawb_meas { 1822 u32 cnt; 1823 u8 mean_y_or_g; 1824 u8 mean_cb_or_b; 1825 u8 mean_cr_or_r; 1826 } __attribute__ ((packed)); 1827 1828 struct isp2x_siawb_stat { 1829 struct isp2x_siawb_meas awb_mean[ISP2X_AWB_MAX_GRID]; 1830 } __attribute__ ((packed)); 1831 1832 struct isp2x_rawawb_ramdata { 1833 u32 wp; 1834 u32 r; 1835 u32 g; 1836 u32 b; 1837 }; 1838 1839 struct isp2x_rawawb_meas_stat { 1840 u32 ro_rawawb_sum_r_nor[ISP2X_RAWAWB_SUM_NUM]; //SUM_R_NOR_0 1841 u32 ro_rawawb_sum_g_nor[ISP2X_RAWAWB_SUM_NUM]; //SUM_G_NOR_0 1842 u32 ro_rawawb_sum_b_nor[ISP2X_RAWAWB_SUM_NUM]; //SUM_B_NOR_0 1843 u32 ro_rawawb_wp_num_nor[ISP2X_RAWAWB_SUM_NUM]; //WP_NUM_NOR_0 1844 u32 ro_rawawb_sum_r_big[ISP2X_RAWAWB_SUM_NUM]; //SUM_R_BIG_0 1845 u32 ro_rawawb_sum_g_big[ISP2X_RAWAWB_SUM_NUM]; //SUM_G_BIG_0 1846 u32 ro_rawawb_sum_b_big[ISP2X_RAWAWB_SUM_NUM]; //SUM_B_BIG_0 1847 u32 ro_rawawb_wp_num_big[ISP2X_RAWAWB_SUM_NUM]; //WP_NUM_BIG_0 1848 u32 ro_rawawb_sum_r_sma[ISP2X_RAWAWB_SUM_NUM]; //SUM_R_SMA_0 1849 u32 ro_rawawb_sum_g_sma[ISP2X_RAWAWB_SUM_NUM]; //SUM_G_SMA_0 1850 u32 ro_rawawb_sum_b_sma[ISP2X_RAWAWB_SUM_NUM]; //SUM_B_SMA_0 1851 u32 ro_rawawb_wp_num_sma[ISP2X_RAWAWB_SUM_NUM]; 1852 u32 ro_sum_r_nor_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //SUM_R_NOR_MULTIWINDOW_0 1853 u32 ro_sum_g_nor_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //SUM_G_NOR_MULTIWINDOW_0 1854 u32 ro_sum_b_nor_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //SUM_B_NOR_MULTIWINDOW_0 1855 u32 ro_wp_nm_nor_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //WP_NM_NOR_MULTIWINDOW_0 1856 u32 ro_sum_r_big_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //SUM_R_BIG_MULTIWINDOW_0 1857 u32 ro_sum_g_big_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //SUM_G_BIG_MULTIWINDOW_0 1858 u32 ro_sum_b_big_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //SUM_B_BIG_MULTIWINDOW_0 1859 u32 ro_wp_nm_big_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //WP_NM_BIG_MULTIWINDOW_0 1860 u32 ro_sum_r_sma_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //SUM_R_SMA_MULTIWINDOW_0 1861 u32 ro_sum_g_sma_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //SUM_G_SMA_MULTIWINDOW_0 1862 u32 ro_sum_b_sma_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //SUM_B_SMA_MULTIWINDOW_0 1863 u32 ro_wp_nm_sma_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; //WP_NM_SMA_MULTIWINDOW_0 1864 u32 ro_sum_r_exc[ISP2X_RAWAWB_SUM_NUM]; 1865 u32 ro_sum_g_exc[ISP2X_RAWAWB_SUM_NUM]; 1866 u32 ro_sum_b_exc[ISP2X_RAWAWB_SUM_NUM]; 1867 u32 ro_wp_nm_exc[ISP2X_RAWAWB_SUM_NUM]; 1868 struct isp2x_rawawb_ramdata ramdata[ISP2X_RAWAWB_RAMDATA_NUM]; 1869 } __attribute__ ((packed)); 1870 1871 struct isp2x_rawae_meas_data { 1872 u16 channelr_xy; 1873 u16 channelb_xy; 1874 u16 channelg_xy; 1875 }; 1876 1877 struct isp2x_rawaebig_stat { 1878 u32 sumr[ISP2X_RAWAEBIG_SUBWIN_NUM]; 1879 u32 sumg[ISP2X_RAWAEBIG_SUBWIN_NUM]; 1880 u32 sumb[ISP2X_RAWAEBIG_SUBWIN_NUM]; 1881 struct isp2x_rawae_meas_data data[ISP2X_RAWAEBIG_MEAN_NUM]; 1882 } __attribute__ ((packed)); 1883 1884 struct isp2x_rawaelite_stat { 1885 struct isp2x_rawae_meas_data data[ISP2X_RAWAELITE_MEAN_NUM]; 1886 } __attribute__ ((packed)); 1887 1888 struct isp2x_yuvae_stat { 1889 u32 ro_yuvae_sumy[ISP2X_YUVAE_SUBWIN_NUM]; 1890 u8 mean[ISP2X_YUVAE_MEAN_NUM]; 1891 } __attribute__ ((packed)); 1892 1893 struct isp2x_rawaf_stat { 1894 u32 int_state; 1895 u32 afm_sum[ISP2X_RAWAF_WIN_NUM]; 1896 u32 afm_lum[ISP2X_RAWAF_WIN_NUM]; 1897 u32 ramdata[ISP2X_RAWAF_SUMDATA_NUM]; 1898 } __attribute__ ((packed)); 1899 1900 struct isp2x_siaf_meas_val { 1901 u32 sum; 1902 u32 lum; 1903 } __attribute__ ((packed)); 1904 1905 struct isp2x_siaf_stat { 1906 struct isp2x_siaf_meas_val win[ISP2X_AFM_MAX_WINDOWS]; 1907 } __attribute__ ((packed)); 1908 1909 struct isp2x_rawhistbig_stat { 1910 u32 hist_bin[ISP2X_HIST_BIN_N_MAX]; 1911 } __attribute__ ((packed)); 1912 1913 struct isp2x_rawhistlite_stat { 1914 u32 hist_bin[ISP2X_HIST_BIN_N_MAX]; 1915 } __attribute__ ((packed)); 1916 1917 struct isp2x_sihst_win_stat { 1918 u32 hist_bins[ISP2X_SIHIST_BIN_N_MAX]; 1919 } __attribute__ ((packed)); 1920 1921 struct isp2x_sihst_stat { 1922 struct isp2x_sihst_win_stat win_stat[ISP2X_SIHIST_WIN_NUM]; 1923 } __attribute__ ((packed)); 1924 1925 struct isp2x_stat { 1926 struct isp2x_siawb_stat siawb; 1927 struct isp2x_rawawb_meas_stat rawawb; 1928 struct isp2x_rawaelite_stat rawae0; 1929 struct isp2x_rawaebig_stat rawae1; 1930 struct isp2x_rawaebig_stat rawae2; 1931 struct isp2x_rawaebig_stat rawae3; 1932 struct isp2x_yuvae_stat yuvae; 1933 struct isp2x_rawaf_stat rawaf; 1934 struct isp2x_siaf_stat siaf; 1935 struct isp2x_rawhistlite_stat rawhist0; 1936 struct isp2x_rawhistbig_stat rawhist1; 1937 struct isp2x_rawhistbig_stat rawhist2; 1938 struct isp2x_rawhistbig_stat rawhist3; 1939 struct isp2x_sihst_stat sihst; 1940 1941 struct isp2x_bls_stat bls; 1942 struct isp2x_hdrtmo_stat hdrtmo; 1943 struct isp2x_dhaz_stat dhaz; 1944 } __attribute__ ((packed)); 1945 1946 /** 1947 * struct rkisp_isp2x_stat_buffer - Rockchip ISP2 Statistics Meta Data 1948 * 1949 * @meas_type: measurement types (CIFISP_STAT_ definitions) 1950 * @frame_id: frame ID for sync 1951 * @params: statistics data 1952 */ 1953 struct rkisp_isp2x_stat_buffer { 1954 unsigned int meas_type; 1955 unsigned int frame_id; 1956 struct isp2x_stat params; 1957 } __attribute__ ((packed)); 1958 1959 /** 1960 * struct rkisp_mipi_luma - statistics mipi y statistic 1961 * 1962 * @exp_mean: Mean luminance value of block xx 1963 * 1964 * Image is divided into 5x5 blocks. 1965 */ 1966 struct rkisp_mipi_luma { 1967 unsigned int exp_mean[ISP2X_MIPI_LUMA_MEAN_MAX]; 1968 } __attribute__ ((packed)); 1969 1970 /** 1971 * struct rkisp_isp2x_luma_buffer - Rockchip ISP1 Statistics Mipi Luma 1972 * 1973 * @meas_type: measurement types (CIFISP_STAT_ definitions) 1974 * @frame_id: frame ID for sync 1975 * @params: statistics data 1976 */ 1977 struct rkisp_isp2x_luma_buffer { 1978 unsigned int meas_type; 1979 unsigned int frame_id; 1980 struct rkisp_mipi_luma luma[ISP2X_MIPI_RAW_MAX]; 1981 } __attribute__ ((packed)); 1982 1983 /** 1984 * struct rkisp_thunderboot_resmem_head 1985 */ 1986 struct rkisp_thunderboot_resmem_head { 1987 u16 enable; 1988 u16 complete; 1989 u16 frm_total; 1990 u16 hdr_mode; 1991 u16 width; 1992 u16 height; 1993 u32 bus_fmt; 1994 1995 u32 exp_time[3]; 1996 u32 exp_gain[3]; 1997 u32 exp_time_reg[3]; 1998 u32 exp_gain_reg[3]; 1999 } __attribute__ ((packed)); 2000 2001 /** 2002 * struct rkisp_thunderboot_resmem - shared buffer for thunderboot with risc-v side 2003 */ 2004 struct rkisp_thunderboot_resmem { 2005 u32 resmem_padr; 2006 u32 resmem_size; 2007 } __attribute__ ((packed)); 2008 2009 /** 2010 * struct rkisp_thunderboot_shmem 2011 */ 2012 struct rkisp_thunderboot_shmem { 2013 u32 shm_start; 2014 u32 shm_size; 2015 s32 shm_fd; 2016 } __attribute__ ((packed)); 2017 2018 #endif /* _UAPI_RKISP2_CONFIG_H */ 2019