1*4882a593SmuzhiyunFrom 5e2ba0042bf530c7c50468eeac24f6c2b71d494a Mon Sep 17 00:00:00 2001 2*4882a593SmuzhiyunFrom: Jeffy Chen <jeffy.chen@rock-chips.com> 3*4882a593SmuzhiyunDate: Mon, 30 May 2022 15:25:32 +0800 4*4882a593SmuzhiyunSubject: [PATCH] arm64 front end: add support for 'ldnp', 'stnp' 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunSigned-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> 7*4882a593Smuzhiyun--- 8*4882a593Smuzhiyun VEX/priv/guest_arm64_toIR.c | 14 +++++++++++--- 9*4882a593Smuzhiyun 1 file changed, 11 insertions(+), 3 deletions(-) 10*4882a593Smuzhiyun 11*4882a593Smuzhiyundiff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c 12*4882a593Smuzhiyunindex 44a1c23..d406fcf 100644 13*4882a593Smuzhiyun--- a/VEX/priv/guest_arm64_toIR.c 14*4882a593Smuzhiyun+++ b/VEX/priv/guest_arm64_toIR.c 15*4882a593Smuzhiyun@@ -5006,13 +5006,16 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn, 16*4882a593Smuzhiyun } 17*4882a593Smuzhiyun } 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun- /* -------- LDP,STP (immediate, simm7) (INT REGS) -------- */ 20*4882a593Smuzhiyun+ /* -------- LDP,STP,LDNP,STNP (immediate, simm7) (INT REGS) -------- */ 21*4882a593Smuzhiyun /* L==1 => mm==LD 22*4882a593Smuzhiyun L==0 => mm==ST 23*4882a593Smuzhiyun x==0 => 32 bit transfers, and zero extended loads 24*4882a593Smuzhiyun x==1 => 64 bit transfers 25*4882a593Smuzhiyun simm7 is scaled by the (single-register) transfer size 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun+ (at-Rn-then-Rn=EA (non-temporal)) 28*4882a593Smuzhiyun+ x0 101 0000 L imm7 Rt2 Rn Rt1 mmP Rt1,Rt2, [Xn|SP], #imm 29*4882a593Smuzhiyun+ 30*4882a593Smuzhiyun (at-Rn-then-Rn=EA) 31*4882a593Smuzhiyun x0 101 0001 L imm7 Rt2 Rn Rt1 mmP Rt1,Rt2, [Xn|SP], #imm 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun@@ -5023,12 +5026,13 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn, 34*4882a593Smuzhiyun x0 101 0010 L imm7 Rt2 Rn Rt1 mmP Rt1,Rt2, [Xn|SP, #imm] 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun UInt insn_30_23 = INSN(30,23); 37*4882a593Smuzhiyun- if (insn_30_23 == BITS8(0,1,0,1,0,0,0,1) 38*4882a593Smuzhiyun+ if (insn_30_23 == BITS8(0,1,0,1,0,0,0,0) 39*4882a593Smuzhiyun+ || insn_30_23 == BITS8(0,1,0,1,0,0,0,1) 40*4882a593Smuzhiyun || insn_30_23 == BITS8(0,1,0,1,0,0,1,1) 41*4882a593Smuzhiyun || insn_30_23 == BITS8(0,1,0,1,0,0,1,0)) { 42*4882a593Smuzhiyun UInt bL = INSN(22,22); 43*4882a593Smuzhiyun UInt bX = INSN(31,31); 44*4882a593Smuzhiyun- UInt bWBack = INSN(23,23); 45*4882a593Smuzhiyun+ UInt bWBack = INSN(24,23) != BITS2(1,0); 46*4882a593Smuzhiyun UInt rT1 = INSN(4,0); 47*4882a593Smuzhiyun UInt rN = INSN(9,5); 48*4882a593Smuzhiyun UInt rT2 = INSN(14,10); 49*4882a593Smuzhiyun@@ -5049,6 +5053,7 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn, 50*4882a593Smuzhiyun IRTemp tTA = newTemp(Ity_I64); 51*4882a593Smuzhiyun IRTemp tWA = newTemp(Ity_I64); 52*4882a593Smuzhiyun switch (INSN(24,23)) { 53*4882a593Smuzhiyun+ case BITS2(0,0): /* fallthru */ 54*4882a593Smuzhiyun case BITS2(0,1): 55*4882a593Smuzhiyun assign(tTA, mkexpr(tRN)); assign(tWA, mkexpr(tEA)); break; 56*4882a593Smuzhiyun case BITS2(1,1): 57*4882a593Smuzhiyun@@ -5109,6 +5114,9 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn, 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun const HChar* fmt_str = NULL; 60*4882a593Smuzhiyun switch (INSN(24,23)) { 61*4882a593Smuzhiyun+ case BITS2(0,0): 62*4882a593Smuzhiyun+ fmt_str = "%snp %s, %s, [%s], #%lld (at-Rn-then-Rn=EA (non-temporal))\n"; 63*4882a593Smuzhiyun+ break; 64*4882a593Smuzhiyun case BITS2(0,1): 65*4882a593Smuzhiyun fmt_str = "%sp %s, %s, [%s], #%lld (at-Rn-then-Rn=EA)\n"; 66*4882a593Smuzhiyun break; 67*4882a593Smuzhiyun-- 68*4882a593Smuzhiyun2.20.1 69*4882a593Smuzhiyun 70