1From 5e2ba0042bf530c7c50468eeac24f6c2b71d494a Mon Sep 17 00:00:00 2001
2From: Jeffy Chen <jeffy.chen@rock-chips.com>
3Date: Mon, 30 May 2022 15:25:32 +0800
4Subject: [PATCH] arm64 front end: add support for 'ldnp', 'stnp'
5
6Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
7---
8 VEX/priv/guest_arm64_toIR.c | 14 +++++++++++---
9 1 file changed, 11 insertions(+), 3 deletions(-)
10
11diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
12index 44a1c23..d406fcf 100644
13--- a/VEX/priv/guest_arm64_toIR.c
14+++ b/VEX/priv/guest_arm64_toIR.c
15@@ -5006,13 +5006,16 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn,
16       }
17    }
18
19-   /* -------- LDP,STP (immediate, simm7) (INT REGS) -------- */
20+   /* -------- LDP,STP,LDNP,STNP (immediate, simm7) (INT REGS) -------- */
21    /* L==1 => mm==LD
22       L==0 => mm==ST
23       x==0 => 32 bit transfers, and zero extended loads
24       x==1 => 64 bit transfers
25       simm7 is scaled by the (single-register) transfer size
26
27+      (at-Rn-then-Rn=EA (non-temporal))
28+      x0 101 0000 L imm7 Rt2 Rn Rt1  mmP Rt1,Rt2, [Xn|SP], #imm
29+
30       (at-Rn-then-Rn=EA)
31       x0 101 0001 L imm7 Rt2 Rn Rt1  mmP Rt1,Rt2, [Xn|SP], #imm
32
33@@ -5023,12 +5026,13 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn,
34       x0 101 0010 L imm7 Rt2 Rn Rt1  mmP Rt1,Rt2, [Xn|SP, #imm]
35    */
36    UInt insn_30_23 = INSN(30,23);
37-   if (insn_30_23 == BITS8(0,1,0,1,0,0,0,1)
38+   if (insn_30_23 == BITS8(0,1,0,1,0,0,0,0)
39+       || insn_30_23 == BITS8(0,1,0,1,0,0,0,1)
40        || insn_30_23 == BITS8(0,1,0,1,0,0,1,1)
41        || insn_30_23 == BITS8(0,1,0,1,0,0,1,0)) {
42       UInt bL     = INSN(22,22);
43       UInt bX     = INSN(31,31);
44-      UInt bWBack = INSN(23,23);
45+      UInt bWBack = INSN(24,23) != BITS2(1,0);
46       UInt rT1    = INSN(4,0);
47       UInt rN     = INSN(9,5);
48       UInt rT2    = INSN(14,10);
49@@ -5049,6 +5053,7 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn,
50          IRTemp tTA = newTemp(Ity_I64);
51          IRTemp tWA = newTemp(Ity_I64);
52          switch (INSN(24,23)) {
53+            case BITS2(0,0): /* fallthru */
54             case BITS2(0,1):
55                assign(tTA, mkexpr(tRN)); assign(tWA, mkexpr(tEA)); break;
56             case BITS2(1,1):
57@@ -5109,6 +5114,9 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn,
58
59          const HChar* fmt_str = NULL;
60          switch (INSN(24,23)) {
61+            case BITS2(0,0):
62+               fmt_str = "%snp %s, %s, [%s], #%lld (at-Rn-then-Rn=EA (non-temporal))\n";
63+               break;
64             case BITS2(0,1):
65                fmt_str = "%sp %s, %s, [%s], #%lld (at-Rn-then-Rn=EA)\n";
66                break;
67--
682.20.1
69
70