1*4882a593SmuzhiyunFrom 7c4d9a6a758200f89a4659673dd43162164ddd0c Mon Sep 17 00:00:00 2001 2*4882a593SmuzhiyunFrom: Kevin Zhao <kevin.zhao@linaro.org> 3*4882a593SmuzhiyunDate: Thu, 22 Jul 2021 16:00:21 +0800 4*4882a593SmuzhiyunSubject: [PATCH] arm64 front end: add support for 'dc cvac', 'dc cvap', 5*4882a593Smuzhiyun handling it the same as 'dc cvau'. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunSigned-off-by: Kevin Zhao <kevin.zhao@linaro.org> 8*4882a593Smuzhiyun--- 9*4882a593Smuzhiyun VEX/priv/guest_arm64_toIR.c | 6 +++++- 10*4882a593Smuzhiyun 1 file changed, 5 insertions(+), 1 deletion(-) 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundiff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c 13*4882a593Smuzhiyunindex 12a1c59..44a1c23 100644 14*4882a593Smuzhiyun--- a/VEX/priv/guest_arm64_toIR.c 15*4882a593Smuzhiyun+++ b/VEX/priv/guest_arm64_toIR.c 16*4882a593Smuzhiyun@@ -7467,9 +7467,13 @@ Bool dis_ARM64_branch_etc(/*MB_OUT*/DisResult* dres, UInt insn, 17*4882a593Smuzhiyun /* ------------------ DC_CVAU ------------------ */ 18*4882a593Smuzhiyun /* D5 0B 7B 001 Rt dc cvau, rT 19*4882a593Smuzhiyun D5 0B 7E 001 Rt dc civac, rT 20*4882a593Smuzhiyun+ D5 0B 7A 001 Rt dc cvac, rT 21*4882a593Smuzhiyun+ D5 0B 7C 001 Rt dc cvap, rT 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun if ( (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7B20 24*4882a593Smuzhiyun- || (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7E20) { 25*4882a593Smuzhiyun+ || (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7E20 26*4882a593Smuzhiyun+ || ((INSN(31,0) & 0xFFFFFFE0) == 0xD50B7A20) 27*4882a593Smuzhiyun+ || ((INSN(31,0) & 0xFFFFFFE0) == 0xD50B7C20)) { 28*4882a593Smuzhiyun /* Exactly the same scheme as for IC IVAU, except we observe the 29*4882a593Smuzhiyun dMinLine size, and request an Ijk_FlushDCache instead of 30*4882a593Smuzhiyun Ijk_InvalICache. */ 31*4882a593Smuzhiyun-- 32*4882a593Smuzhiyun2.20.1 33*4882a593Smuzhiyun 34